VIA 486 bringup
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tiseno100
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195
src/chipset/via_vt82c49x.c
Normal file
195
src/chipset/via_vt82c49x.c
Normal file
@@ -0,0 +1,195 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the VIA VT82C49X chipset.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2020 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct
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{
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uint8_t index,
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regs[256];
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} vt82c49x_t;
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#define ENABLE_VT82C49X_LOG 1
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#ifdef ENABLE_VT82C49X_LOG
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int vt82c49x_do_log = ENABLE_VT82C49X_LOG;
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static void
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vt82c49x_log(const char *fmt, ...)
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{
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va_list ap;
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if (vt82c49x_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define vt82c49x_log(fmt, ...)
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#endif
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static void vt82c49x_shadow_recalc(vt82c49x_t *dev)
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{
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uint32_t wp_c, wp_e, wp_f;
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/* Register 40h */
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wp_c = (dev->regs[0x40] & 0x80) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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wp_f = (dev->regs[0x40] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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wp_e = (dev->regs[0x40] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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/* Register 30h */
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mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0x30] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x01) ? wp_c : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0x30] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x04) ? wp_c : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0x30] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x10) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0x30] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x30] & 0x40) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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/* Register 31h */
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mem_set_mem_state_both(0xd0000, 0x4000, ((dev->regs[0x31] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x01) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xd4000, 0x4000, ((dev->regs[0x31] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xd8000, 0x4000, ((dev->regs[0x31] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x10) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xdc000, 0x4000, ((dev->regs[0x31] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x31] & 0x40) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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/* Register 32h */
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shadowbios = (dev->regs[0x40] & 0x20);
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shadowbios_write = (dev->regs[0x40] & 0x10);
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x32] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x32] & 0x40) ? wp_e : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x32] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x32] & 0x10) ? wp_f : MEM_WRITE_EXTANY));
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}
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static void
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vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
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{
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vt82c49x_t *dev = (vt82c49x_t *) priv;
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switch (addr) {
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case 0xa8:
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dev->index = val;
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break;
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case 0xa9:
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dev->regs[dev->index] = val;
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vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val);
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switch(dev->index){
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/* Wait States */
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case 0x03:
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cpu_update_waitstates();
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break;
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/* Shadow RAM */
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x40:
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vt82c49x_shadow_recalc(dev);
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break;
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/* External Cache Enable(Based on the 486-VC-HD BIOS) */
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case 0x50:
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cpu_cache_ext_enabled = (val & 0x84);
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break;
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/* SMI/SMM(Not at all perfect or even functional :/) */
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case 0x5b:
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if(val & 0x40)
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mem_set_mem_state_smram(1, 0x30000, 0x20000, 0);
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if(val & 0x20)
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smi_line = 1;
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break;
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}
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break;
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}
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}
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static uint8_t
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vt82c49x_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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vt82c49x_t *dev = (vt82c49x_t *) priv;
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switch (addr) {
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case 0xa9:
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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static void
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vt82c49x_close(void *priv)
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{
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vt82c49x_t *dev = (vt82c49x_t *) priv;
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free(dev);
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}
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static void *
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vt82c49x_init(const device_t *info)
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{
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vt82c49x_t *dev = (vt82c49x_t *) malloc(sizeof(vt82c49x_t));
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memset(dev, 0, sizeof(vt82c49x_t));
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device_add(&port_92_device);
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io_sethandler(0x0a8, 0x0001, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
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io_sethandler(0x0a9, 0x0001, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
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dev->regs[0x30] = 0x00;
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dev->regs[0x31] = 0x00;
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dev->regs[0x32] = 0x00;
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vt82c49x_shadow_recalc(dev);
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return dev;
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}
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const device_t via_vt82c49x_device = {
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"VIA VT82C49X",
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0,
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0,
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vt82c49x_init, vt82c49x_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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161
src/chipset/via_vt82c505.c
Normal file
161
src/chipset/via_vt82c505.c
Normal file
@@ -0,0 +1,161 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the VIA VT82C505 VL/PCI Bridge Controller.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2020 Tiseno100
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*
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/chipset.h>
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typedef struct vt82c505_t
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{
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uint8_t pci_conf[256];
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} vt82c505_t;
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static void
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vt82c505_write(int func, int addr, uint8_t val, void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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/* Read-Only Registers */
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switch (addr)
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{
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case 0x00: case 0x01:
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case 0x02: case 0x03:
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return;
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}
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switch(addr)
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{
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case 0x04:
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dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x07) | (val & 0x07);
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break;
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case 0x07:
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dev->pci_conf[0x07] = (dev->pci_conf[0x07] & ~0x90) | (val & 0x90);
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break;
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case 0x90:
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if((dev->pci_conf[0x90] & 0x08) && ((val & 0x07) != 0))
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pci_set_irq_routing(PCI_INTC, val & 0x07);
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else
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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if((dev->pci_conf[0x90] & 0x80) && (((val & 0x07) << 4) != 0))
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pci_set_irq_routing(PCI_INTD, ((val & 0x07) << 4));
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else
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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break;
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case 0x91:
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if((dev->pci_conf[0x91] & 0x08) && ((val & 0x07) != 0))
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pci_set_irq_routing(PCI_INTA, val & 0x07);
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else
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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if((dev->pci_conf[0x91] & 0x80) && (((val & 0x07) << 4) != 0))
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pci_set_irq_routing(PCI_INTB, ((val & 0x07) << 4));
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else
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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break;
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}
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}
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static uint8_t
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vt82c505_read(int func, int addr, void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->pci_conf[addr];
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return ret;
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}
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static void
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vt82c505_reset(void *priv)
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{
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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}
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static void
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vt82c505_close(void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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free(dev);
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}
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static void *
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vt82c505_init(const device_t *info)
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{
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vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
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memset(dev, 0, sizeof(vt82c505_t));
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pci_add_card(0, vt82c505_read, vt82c505_write, dev);
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dev->pci_conf[0x00] = 0x06;
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dev->pci_conf[0x01] = 0x11;
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dev->pci_conf[0x02] = 0x05;
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dev->pci_conf[0x03] = 0x05;
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dev->pci_conf[0x04] = 0x07;
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dev->pci_conf[0x05] = 0x00;
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dev->pci_conf[0x06] = 0x00;
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dev->pci_conf[0x07] = 0x90;
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dev->pci_conf[0x81] = 0x01;
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dev->pci_conf[0x84] = 0x03;
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dev->pci_conf[0x85] = 0x00;
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dev->pci_conf[0x93] = 0x40;
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return dev;
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}
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const device_t via_vt82c505_device = {
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"VIA VT82C505",
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DEVICE_PCI,
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0,
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vt82c505_init,
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vt82c505_close,
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vt82c505_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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