From 17f6ddecb319ae2ea1a4de0e333001b3cce7560b Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 24 Sep 2024 04:41:45 +0200 Subject: [PATCH] More UM888x fixes. --- src/chipset/umc_8886.c | 48 ++++++++++------------ src/chipset/umc_hb4.c | 93 +++++++++++++++++++++++++++++++++++------- 2 files changed, 100 insertions(+), 41 deletions(-) diff --git a/src/chipset/umc_8886.c b/src/chipset/umc_8886.c index 3ec6885b6..4242062c6 100644 --- a/src/chipset/umc_8886.c +++ b/src/chipset/umc_8886.c @@ -126,10 +126,10 @@ umc_8886_ide_handler(umc_8886_t *dev) ide_sec_disable(); if (dev->pci_conf_sb[1][0x04] & 0x01) { - if (dev->pci_conf_sb[1][0x40] & 0x80) + if (dev->pci_conf_sb[1][0x41] & 0x80) ide_pri_enable(); - if (dev->pci_conf_sb[1][0x40] & 0x40) + if (dev->pci_conf_sb[1][0x41] & 0x40) ide_sec_enable(); } } @@ -204,7 +204,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv) case 0x50 ... 0x55: case 0x57: case 0x70 ... 0x76: - case 0x80 ... 0x82: + case 0x80 ... 0x83: case 0x90 ... 0x92: case 0xa0 ... 0xa1: case 0xa5 ... 0xa8: @@ -270,13 +270,13 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv) break; case 0x3c: - case 0x41 ... 0x4b: - case 0x54 ... 0x59: + case 0x40: + case 0x42 ... 0x59: if (dev->ide_id == 0x673a) dev->pci_conf_sb[func][addr] = val; break; - case 0x40: + case 0x41: if (dev->ide_id == 0x673a) { dev->pci_conf_sb[func][addr] = val; umc_8886_ide_handler(dev); @@ -322,25 +322,17 @@ umc_8886_reset(void *priv) dev->pci_conf_sb[0][0x09] = 0x00; dev->pci_conf_sb[0][0x0a] = 0x01; dev->pci_conf_sb[0][0x0b] = 0x06; + dev->pci_conf_sb[0][0x40] = 0x01; - dev->pci_conf_sb[0][0x41] = 0x06; + dev->pci_conf_sb[0][0x41] = 0x04; dev->pci_conf_sb[0][0x42] = 0x08; - dev->pci_conf_sb[0][0x43] = 0x00; - dev->pci_conf_sb[0][0x44] = 0x00; - dev->pci_conf_sb[0][0x45] = 0x04; - dev->pci_conf_sb[0][0x46] = 0x00; - dev->pci_conf_sb[0][0x47] = 0x40; - dev->pci_conf_sb[0][0x50] = 0x01; - dev->pci_conf_sb[0][0x51] = 0x03; - dev->pci_conf_sb[0][0x56] = dev->pci_conf_sb[0][0x57] = 0x00; - dev->pci_conf_sb[0][0x70] = dev->pci_conf_sb[0][0x71] = 0x00; - dev->pci_conf_sb[0][0x72] = dev->pci_conf_sb[0][0x73] = 0x00; - dev->pci_conf_sb[0][0x74] = dev->pci_conf_sb[0][0x76] = 0x00; - dev->pci_conf_sb[0][0x82] = 0x00; - dev->pci_conf_sb[0][0x90] = dev->pci_conf_sb[0][0x91] = 0x00; - dev->pci_conf_sb[0][0xa0] = dev->pci_conf_sb[0][0xa2] = 0x00; - dev->pci_conf_sb[0][0xa4] = 0x00; - dev->pci_conf_sb[0][0xa8] = 0x20; + dev->pci_conf_sb[0][0x43] = 0x9a; + dev->pci_conf_sb[0][0x44] = 0xbc; + dev->pci_conf_sb[0][0x45] = 0x00; + dev->pci_conf_sb[0][0x46] = 0x10; + dev->pci_conf_sb[0][0x47] = 0x30; + + dev->pci_conf_sb[0][0x51] = 0x02; if (dev->has_ide) { dev->pci_conf_sb[1][0x00] = 0x60; /* UMC */ @@ -363,13 +355,15 @@ umc_8886_reset(void *priv) dev->pci_conf_sb[1][0x21] = 0x10; if (dev->ide_id == 0x673a) { - dev->pci_conf_sb[1][0x40] = 0xc0; - dev->pci_conf_sb[1][0x41] = 0x00; + dev->pci_conf_sb[1][0x40] = 0x00; + dev->pci_conf_sb[1][0x41] = 0xc0; dev->pci_conf_sb[1][0x42] = dev->pci_conf_sb[1][0x43] = 0x00; dev->pci_conf_sb[1][0x44] = dev->pci_conf_sb[1][0x45] = 0x00; dev->pci_conf_sb[1][0x46] = dev->pci_conf_sb[1][0x47] = 0x00; - dev->pci_conf_sb[1][0x48] = dev->pci_conf_sb[1][0x49] = 0x00; - dev->pci_conf_sb[1][0x4a] = dev->pci_conf_sb[1][0x4b] = 0x00; + dev->pci_conf_sb[1][0x48] = dev->pci_conf_sb[1][0x49] = 0x55; + dev->pci_conf_sb[1][0x4a] = dev->pci_conf_sb[1][0x4b] = 0x55; + dev->pci_conf_sb[1][0x4c] = dev->pci_conf_sb[1][0x4d] = 0x88; + dev->pci_conf_sb[1][0x4e] = dev->pci_conf_sb[1][0x4f] = 0xaa; dev->pci_conf_sb[1][0x54] = dev->pci_conf_sb[1][0x55] = 0x00; dev->pci_conf_sb[1][0x56] = dev->pci_conf_sb[1][0x57] = 0x00; dev->pci_conf_sb[1][0x58] = dev->pci_conf_sb[1][0x59] = 0x00; diff --git a/src/chipset/umc_hb4.c b/src/chipset/umc_hb4.c index a7ed0b880..707bbdd45 100644 --- a/src/chipset/umc_hb4.c +++ b/src/chipset/umc_hb4.c @@ -136,6 +136,9 @@ hb4_log(const char *fmt, ...) #endif typedef struct hb4_t { + uint8_t idx; + uint8_t access_data; + uint8_t pci_slot; uint8_t pci_conf[256]; /* PCI Registers */ @@ -176,7 +179,10 @@ hb4_shadow_bios_low(hb4_t *dev) int state; /* Erratum in Vogons' datasheet: Register 55h bit 7 in fact controls E0000-FFFFF. */ - state = shadow_bios[dev->pci_conf[0x55] >> 6]; + // state = shadow_bios[dev->pci_conf[0x55] >> 6]; + state = (dev->pci_conf[0x55] & 0x80) ? shadow_read[dev->pci_conf[0x54] & 0x01] : + MEM_READ_EXTANY; + state |= shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; if (state != dev->mem_state[7]) { mem_set_mem_state_both(0xe0000, 0x10000, state); @@ -194,8 +200,9 @@ hb4_shadow_main(hb4_t *dev) int n = 0; for (uint8_t i = 0; i < 6; i++) { - state = shadow_read[(dev->pci_conf[0x54] >> (i + 2)) & 0x01] | - shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; + state = (dev->pci_conf[0x55] & 0x80) ? shadow_read[(dev->pci_conf[0x54] >> (i + 2)) & 0x01] : + MEM_READ_EXTANY; + state |= shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; if (state != dev->mem_state[i + 1]) { n++; @@ -212,8 +219,9 @@ hb4_shadow_video(hb4_t *dev) { int state; - state = shadow_read[(dev->pci_conf[0x54] >> 1) & 0x01] | - shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; + state = (dev->pci_conf[0x55] & 0x80) ? shadow_read[(dev->pci_conf[0x54] >> 1) & 0x01] : + MEM_READ_EXTANY; + state |= shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; if (state != dev->mem_state[0]) { mem_set_mem_state_both(0xc0000, 0x8000, state); @@ -302,7 +310,7 @@ hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv) hb4_shadow(dev); break; - case 0x56 ... 0x5b: + case 0x56 ... 0x5a: case 0x5e ... 0x5f: dev->pci_conf[addr] = val; break; @@ -313,10 +321,14 @@ hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv) hb4_smram(dev); break; - case 0x61 ... 0x62: + case 0x61: dev->pci_conf[addr] = val; break; + case 0x62: + dev->pci_conf[addr] = val & 0x03; + break; + default: break; } @@ -354,14 +366,16 @@ hb4_reset(void *priv) dev->pci_conf[0x52] = 0x01; dev->pci_conf[0x53] = 0x00; dev->pci_conf[0x54] = 0x00; - dev->pci_conf[0x55] = 0x00; - dev->pci_conf[0x56] = 0x00; - dev->pci_conf[0x57] = 0x00; - dev->pci_conf[0x58] = 0x00; - dev->pci_conf[0x59] = 0x00; - dev->pci_conf[0x5a] = 0x04; + dev->pci_conf[0x55] = 0x40; + dev->pci_conf[0x56] = 0xff; + dev->pci_conf[0x57] = 0x0f; + dev->pci_conf[0x58] = 0xff; + dev->pci_conf[0x59] = 0x0f; + dev->pci_conf[0x5a] = 0x00; + dev->pci_conf[0x5b] = 0x2c; dev->pci_conf[0x5c] = 0x00; - dev->pci_conf[0x5d] = 0x20; + dev->pci_conf[0x5d] = 0x0f; + dev->pci_conf[0x5e] = 0x00; dev->pci_conf[0x5f] = 0xff; dev->pci_conf[0x60] = 0x00; dev->pci_conf[0x61] = 0x00; @@ -385,6 +399,55 @@ hb4_close(void *priv) free(dev); } +static void +ims8848_write(uint16_t addr, uint8_t val, void *priv) +{ + hb4_t *dev = (hb4_t *) priv; + + switch (addr) { + case 0x22: + dev->idx = val; + break; + case 0x23: + if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0))) + dev->access_data = 1; + break; + case 0x24: + if (dev->access_data) + dev->access_data = 0; + break; + + default: + break; + } +} + +static uint8_t +ims8848_read(uint16_t addr, void *priv) +{ + uint8_t ret = 0xff; + hb4_t *dev = (hb4_t *) priv; + + switch (addr) { + case 0x22: + ret = dev->idx; + break; + case 0x23: + ret = (dev->idx >> 4) | (dev->idx << 4); + break; + case 0x24: + if (dev->access_data) { + ret = dev->pci_conf[dev->idx]; + dev->access_data = 0; + } + break; + default: + break; + } + + return ret; +} + static void * hb4_init(UNUSED(const device_t *info)) { @@ -402,6 +465,8 @@ hb4_init(UNUSED(const device_t *info)) dev->smram_base = 0x000a0000; hb4_reset(dev); + io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev); + return dev; }