Assorted changes and bugfixes and added the two IMS 8848 machines.
This commit is contained in:
OBattler
411
src/chipset/ims8848.c
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411
src/chipset/ims8848.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the IMS 8848/8849 chipset.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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* Tiseno100,
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*
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* Copyright 2021 Miran Grca.
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* Copyright 2021 Tiseno100.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/smram.h>
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#include <86box/pci.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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/*
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IMS 884x Configuration Registers
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Note: IMS 884x are rebadged ATMEL AT 40411/40412 chipsets
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By: Tiseno100, Miran Grca(OBattler)
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Register 00h:
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Bit 3: F0000-FFFFF Shadow Enable
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Bit 2: E0000-EFFFF Shadow Enable
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Bit 0: ????
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Register 04h:
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Bit 3: Cache Write Hit Wait State
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Bit 2: Cache Read Hit Wait State
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Register 06h:
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Bit 3: System BIOS Cacheable (1: Yes / 0: No)
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Bit 1: Power Management Mode (1: IRQ / 0: SMI#)
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Register 08h:
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Bit 2: System BIOS Shadow Write (1: Enable / 0: Disable)
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Bit 1: System BIOS Shadow Read?
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Register 0Dh:
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Bit 0: IO 100H-3FFH Idle Detect (1: Enable / 0: Disable)
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Register 0Eh:
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Bit 7: DMA & Local Bus Idle Detect (1: Enable / 0: Disable)
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Bit 6: Floppy Disk Idle Detect (1: Enable / 0: Disable)
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Bit 5: IDE Idle Detect (1: Enable / 0: Disable)
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Bit 4: Serial Port Idle Detect (1: Enable / 0: Disable)
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Bit 3: Parallel Port Idle Detect (1: Enable / 0: Disable)
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Bit 2: Keyboard Idle Detect (1: Enable / 0: Disable)
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Bit 1: Video Idle Detect (1: Enable / 0: Disable)
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Register 12h:
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Bits 3-2: Power Saving Timer (00 = 1 MIN, 01 = 3 MIN, 10 = 5 MIN, 11 = 8 MIN)
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Bit 1: Base Memory (1: 512KB / 0: 640KB)
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Register 1Ah:
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Bit 3: Cache Write Hit W/S For PCI (1: Enabled / 0: Disable)
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Bit 2: Cache Read Hit W/S For PCI (1: Enabled / 0: Disable)
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Bit 1: VESA Clock Skew (1: 4ns/6ns, 0: No Delay/2ns)
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Register 1Bh:
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Bit 6: Enable SMRAM (always at 30000-4FFFF) in SMM
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Bit 5: ????
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Bit 4: Software SMI#
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Bit 3: DC000-DFFFF Shadow Enable
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Bit 2: D8000-DBFFF Shadow Enable
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Bit 1: D4000-D7FFF Shadow Enable
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Bit 0: D0000-D3FFF Shadow Enable
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Register 1Ch:
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Bits 7-4: INTA IRQ routing (0 = disabled, 1 to F = IRQ)
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Bit 3: CC000-CFFFF Shadow Enable
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Bit 2: C8000-CBFFF Shadow Enable
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Bit 1: C4000-C7FFF Shadow Enable
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Bit 0: C0000-C3FFF Shadow Enable
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Register 1Dh:
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Bits 7-4: INTB IRQ routing (0 = disabled, 1 to F = IRQ)
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Register 1Eh:
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Bits 7-4: INTC IRQ routing (0 = disabled, 1 to F = IRQ)
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Bit 1: C4000-C7FFF Cacheable
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Bit 0: C0000-C3FFF Cacheable
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Register 21h:
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Bits 7-4: INTD IRQ routing (0 = disabled, 1 to F = IRQ)
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Register 22h:
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Bit 5: Local Bus Master #2 select (0 = VESA, 1 = PCI)
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Bit 4: Local Bus Master #1 select (0 = VESA, 1 = PCI)
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Bits 1-0: Internal HADS# Delay Always (00 = No Delay, 01 = 1 Clk, 10 = 2 Clks)
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Register 23h:
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Bit 7: Seven Bits Tag (1: Enabled / 0: Disable)
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Bit 3: Extend LBRDY#(VL Master) (1: Enabled / 0: Disable)
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Bit 2: Sync LRDY#(VL Slave) (1: Enabled / 0: Disable)
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Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable)
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*/
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typedef struct
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{
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uint8_t idx, access_data,
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regs[256], pci_conf[256];
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smram_t *smram;
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} ims8848_t;
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#ifdef ENABLE_IMS8848_LOG
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int ims8848_do_log = ENABLE_IMS8848_LOG;
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static void
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ims8848_log(const char *fmt, ...)
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{
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va_list ap;
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if (ims8848_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define ims8848_log(fmt, ...)
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#endif
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/* Shadow write always enabled, 1B and 1C control C000-DFFF read. */
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static void
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ims8848_recalc(ims8848_t *dev)
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{
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int i, state_on;
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uint32_t base;
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ims8848_log("SHADOW: 00 = %02X, 08 = %02X, 1B = %02X, 1C = %02X\n",
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dev->regs[0x00], dev->regs[0x08], dev->regs[0x1b], dev->regs[0x1c]);
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state_on = MEM_READ_INTERNAL;
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state_on |= (dev->regs[0x08] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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for (i = 0; i < 2; i++) {
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base = 0xe0000 + (i << 16);
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if (dev->regs[0x00] & (1 << (i + 2)))
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mem_set_mem_state_both(base, 0x10000, state_on);
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else
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mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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}
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for (i = 0; i < 4; i++) {
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base = 0xc0000 + (i << 14);
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if (dev->regs[0x1c] & (1 << i))
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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base = 0xd0000 + (i << 14);
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if (dev->regs[0x1b] & (1 << i))
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mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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}
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flushmmucache_nopc();
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}
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static void
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ims8848_base_memory(ims8848_t *dev)
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{
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/* We can use the proper mem_set_access to handle that. */
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mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x12] & 2) ?
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(MEM_READ_DISABLED | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
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}
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static void
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ims8848_smram(ims8848_t *dev)
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{
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smram_disable_all();
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smram_enable(dev->smram, 0x00030000, 0x00030000, 0x20000, dev->regs[0x1b] & 0x40, 1);
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}
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static void
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ims8848_write(uint16_t addr, uint8_t val, void *priv)
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{
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ims8848_t *dev = (ims8848_t *) priv;
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uint8_t old = dev->regs[dev->idx];
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switch (addr) {
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case 0x22:
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ims8848_log("[W] IDX = %02X\n", val);
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dev->idx = val;
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break;
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case 0x23:
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ims8848_log("[W] IDX IN = %02X\n", val);
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if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0)))
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dev->access_data = 1;
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break;
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case 0x24:
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ims8848_log("[W] [%i] REG %02X = %02X\n", dev->access_data, dev->idx, val);
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if (dev->access_data) {
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dev->regs[dev->idx] = val;
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switch (dev->idx) {
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case 0x00: case 0x08: case 0x1b: case 0x1c:
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/* Shadow RAM */
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ims8848_recalc(dev);
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if (dev->idx == 0x1b) {
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ims8848_smram(dev);
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if (!(old & 0x10) && (val & 0x10))
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smi_line = 1;
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} else if (dev->idx == 0x1c)
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pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
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break;
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case 0x1d: case 0x1e:
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pci_set_irq_routing(PCI_INTB + (dev->idx - 0x1d), (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
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break;
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case 0x21:
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pci_set_irq_routing(PCI_INTD, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
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break;
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case 0x12:
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/* Base Memory */
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ims8848_base_memory(dev);
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break;
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}
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dev->access_data = 0;
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}
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break;
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}
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}
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static uint8_t
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ims8848_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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ims8848_t *dev = (ims8848_t *) priv;
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#ifdef ENABLE_IMS8848_LOG
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uint8_t old_ad = dev->access_data;
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#endif
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switch (addr) {
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case 0x22:
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ims8848_log("[R] IDX = %02X\n", ret);
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ret = dev->idx;
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break;
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case 0x23:
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ims8848_log("[R] IDX IN = %02X\n", ret);
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ret = (dev->idx >> 4) | (dev->idx << 4);
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break;
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case 0x24:
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if (dev->access_data) {
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ret = dev->regs[dev->idx];
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dev->access_data = 0;
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}
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ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret);
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break;
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}
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return ret;
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}
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static void
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ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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ims8848_t *dev = (ims8848_t *)priv;
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ims8848_log("IMS 884x-PCI: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80));
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if (func == 0) switch (addr) {
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case 0x04:
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dev->pci_conf[addr] = val;
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break;
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case 0x05:
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dev->pci_conf[addr] = val & 3;
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break;
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case 0x07:
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dev->pci_conf[addr] &= val & 0xf7;
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break;
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case 0x0c ... 0x0d:
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dev->pci_conf[addr] = val;
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break;
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case 0x52 ... 0x55:
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dev->pci_conf[addr] = val;
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break;
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}
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}
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static uint8_t
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ims8849_pci_read(int func, int addr, void *priv)
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{
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ims8848_t *dev = (ims8848_t *)priv;
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uint8_t ret = 0xff;
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if (func == 0)
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ret = dev->pci_conf[addr];
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return ret;
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}
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static void
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ims8848_reset(void *priv)
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{
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ims8848_t *dev = (ims8848_t *)priv;
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memset(dev->regs, 0x00, sizeof(dev->regs));
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memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
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dev->pci_conf[0x00] = 0xe0; /* Integrated Micro Solutions (IMS) */
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x49; /* 8849 */
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dev->pci_conf[0x03] = 0x88;
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dev->pci_conf[0x04] = 0x07;
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dev->pci_conf[0x07] = 0x02;
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dev->pci_conf[0x0b] = 0x06;
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ims8848_recalc(dev); /* Shadow RAM Setup */
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ims8848_base_memory(dev); /* Base Memory Setup */
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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ims8848_smram(dev);
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}
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static void
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ims8848_close(void *priv)
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{
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ims8848_t *dev = (ims8848_t *) priv;
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smram_del(dev->smram);
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free(dev);
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}
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static void *
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ims8848_init(const device_t *info)
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{
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ims8848_t *dev = (ims8848_t *) malloc(sizeof(ims8848_t));
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memset(dev, 0, sizeof(ims8848_t));
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device_add(&port_92_device);
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/* IMS 8848:
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22h Index
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23h Data Unlock
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24h Data
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IMS 8849:
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PCI Device 0: IMS 8849 Dummy for compatibility reasons
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*/
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io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev);
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pci_add_card(PCI_ADD_NORTHBRIDGE, ims8849_pci_read, ims8849_pci_write, dev);
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dev->smram = smram_add();
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smram_set_separate_smram(1);
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cpu_cache_ext_enabled = 1;
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cpu_update_waitstates();
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ims8848_reset(dev);
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return dev;
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}
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const device_t ims8848_device = {
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"IMS 8848/8849",
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0,
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0,
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ims8848_init, ims8848_close, ims8848_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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Reference in New Issue
Block a user