Assorted changes and bugfixes and added the two IMS 8848 machines.
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@@ -59,6 +59,9 @@ extern const device_t headland_ht18a_device;
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extern const device_t headland_ht18b_device;
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extern const device_t headland_ht18c_device;
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/* IMS */
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extern const device_t ims8848_device;
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/* Intel */
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extern const device_t intel_82335_device;
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extern const device_t i420ex_device;
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@@ -162,7 +165,7 @@ extern const device_t wd76c10_device;
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/* Miscellaneous Hardware */
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extern const device_t phoenix_486_jumper_device;
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extern const device_t vpc2007_device;
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extern const device_t phoenix_486_jumper_pci_device;
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#if defined(DEV_BRANCH) && defined(USE_OLIVETTI)
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extern const device_t olivetti_eva_device;
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@@ -366,6 +366,9 @@ extern int machine_at_ms4145_init(const machine_t *);
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extern int machine_at_sbc_490_init(const machine_t *);
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extern int machine_at_tf_486_init(const machine_t *);
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extern int machine_at_pci400c_b_init(const machine_t *);
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extern int machine_at_g486ip_init(const machine_t *);
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extern int machine_at_itoxstar_init(const machine_t *);
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extern int machine_at_arb1423c_init(const machine_t *);
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extern int machine_at_arb1479_init(const machine_t *);
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@@ -89,6 +89,7 @@
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/* Internal execute access, external read access. */
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#define MEM_READ_EXTERNAL_EX 0
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#define MEM_READ_SMRAM (ACCESS_X_SMRAM | ACCESS_R_SMRAM)
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#define MEM_READ_CACHE (ACCESS_X_CACHE | ACCESS_R_CACHE)
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#define MEM_READ_SMRAM_EX (ACCESS_X_SMRAM)
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#define MEM_EXEC_SMRAM MEM_READ_SMRAM_EX
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#define MEM_READ_SMRAM_2 (ACCESS_R_SMRAM)
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@@ -104,6 +105,7 @@
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#define MEM_WRITE_ROMCS (ACCESS_W_ROMCS)
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#define MEM_WRITE_EXTANY (ACCESS_W_ROMCS)
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#define MEM_WRITE_SMRAM (ACCESS_W_SMRAM)
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#define MEM_WRITE_CACHE (ACCESS_W_CACHE)
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/* Theese two are going to be identical. */
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#define MEM_WRITE_DISABLED_EX MEM_READ_DISABLED
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#define MEM_WRITE_MASK 0x03e0
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@@ -52,6 +52,8 @@ extern void smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, ui
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extern int smram_enabled(smram_t *smr);
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/* Changes the SMRAM state. */
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extern void smram_state_change(smram_t *smr, int smm, int flags);
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/* Enables or disables the use of a separate SMRAM for addresses below A0000. */
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extern void smram_set_separate_smram(uint8_t set);
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#endif /*EMU_SMRAM_H*/
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