diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c
index 81781b57f..1c4200b1a 100644
--- a/src/cpu/386_dynarec.c
+++ b/src/cpu/386_dynarec.c
@@ -18,7 +18,9 @@
 #include "../timer.h"
 #include "../floppy/floppy.h"
 #include "../floppy/fdc.h"
+#ifdef USE_DYNAREC
 #include "codegen.h"
+#endif
 #include "386_common.h"
 
 
@@ -500,6 +502,7 @@ static int cpu_cycle_period(void)
 	}
 }
 
+#ifdef USE_DYNAREC
 static int cycles_main = 0;
 void exec386_dynarec(int cycs)
 {
@@ -950,3 +953,4 @@ inrecomp=0;
                 cycles_main -= (cycles_start - cycles);
         }
 }
+#endif
diff --git a/src/cpu/808x.c b/src/cpu/808x.c
index 2a10834e6..3d77f2018 100644
--- a/src/cpu/808x.c
+++ b/src/cpu/808x.c
@@ -1,4 +1,4 @@
-/*
+/*
  * 86Box	A hypervisor and IBM PC system emulator that specializes in
  *		running old operating systems and software designed for IBM
  *		PC systems and compatibles from 1981 through fairly recent
@@ -613,7 +613,9 @@ void resetx86()
         mmu_perm=4;
         memset(inscounts, 0, sizeof(inscounts));
         x86seg_reset();
+#ifdef USE_DYNAREC
         codegen_reset();
+#endif
         x86_was_reset = 1;
 	port_92_clear_reset();
 	scsi_card_reset();
diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 5cbdfd642..2c2e79773 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -8,7 +8,7 @@
  *
  *		CPU type handler.
  *
- * Version:	@(#)cpu.c	1.0.3	2017/10/12
+ * Version:	@(#)cpu.c	1.0.4	2017/10/14
  *
  * Authors:	Sarah Walker, <http://pcem-emulator.co.uk/>
  *		leilei,
@@ -30,11 +30,14 @@
 #include "x86_ops.h"
 #include "../mem.h"
 #include "../pci.h"
+#ifdef USE_DYNAREC
 #include "codegen.h"
+#endif
 
 int isa_cycles;
 static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
 
+#ifdef USE_DYNAREC
 OpFn *x86_dynarec_opcodes;
 OpFn *x86_dynarec_opcodes_0f;
 OpFn *x86_dynarec_opcodes_d8_a16;
@@ -55,6 +58,7 @@ OpFn *x86_dynarec_opcodes_df_a16;
 OpFn *x86_dynarec_opcodes_df_a32;
 OpFn *x86_dynarec_opcodes_REPE;
 OpFn *x86_dynarec_opcodes_REPNE;
+#endif
 
 OpFn *x86_opcodes;
 OpFn *x86_opcodes_0f;
@@ -688,12 +692,19 @@ void cpu_set()
         pclog("hasfpu - %i\n",hasfpu);
         pclog("is486 - %i  %i\n",is486,cpu_s->cpu_type);
 
+#ifdef USE_DYNAREC
         x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
+#else
+        x86_setopcodes(ops_386, ops_386_0f);
+#endif
         x86_opcodes_REPE = ops_REPE;
         x86_opcodes_REPNE = ops_REPNE;
+#ifdef USE_DYNAREC
         x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
         x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
+#endif
 
+#ifdef USE_DYNAREC
         if (hasfpu)
         {
                 x86_dynarec_opcodes_d8_a16 = dynarec_ops_fpu_d8_a16;
@@ -733,6 +744,7 @@ void cpu_set()
                 x86_dynarec_opcodes_df_a32 = dynarec_ops_nofpu_a32;
         }
         codegen_timing_set(&codegen_timing_486);
+#endif
 
         if (hasfpu)
         {
@@ -785,9 +797,14 @@ void cpu_set()
                 break;
                 
                 case CPU_286:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_286, ops_286_0f, dynarec_ops_286, dynarec_ops_286_0f);
+#else
+                x86_setopcodes(ops_286, ops_286_0f);
+#endif
 		if (enable_external_fpu)
 		{
+#ifdef USE_DYNAREC
                 	x86_dynarec_opcodes_d9_a16 = dynarec_ops_fpu_287_d9_a16;
         	        x86_dynarec_opcodes_d9_a32 = dynarec_ops_fpu_287_d9_a32;
                 	x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_287_da_a16;
@@ -802,6 +819,7 @@ void cpu_set()
         	        x86_dynarec_opcodes_de_a32 = dynarec_ops_fpu_287_de_a32;
 	                x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_287_df_a16;
         	        x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_287_df_a32;
+#endif
 	                x86_opcodes_d9_a16 = ops_fpu_287_d9_a16;
 	                x86_opcodes_d9_a32 = ops_fpu_287_d9_a32;
 	                x86_opcodes_da_a16 = ops_fpu_287_da_a16;
@@ -941,7 +959,11 @@ void cpu_set()
                 break;
                 
                 case CPU_486SLC:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 3; /*register dest - memory src*/
                 timing_mr  = 5; /*memory dest   - register src*/
@@ -975,7 +997,11 @@ void cpu_set()
                 break;
                 
                 case CPU_486DLC:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 3; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1014,7 +1040,11 @@ void cpu_set()
 		cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_VME;
                 case CPU_i486SX:
                 case CPU_i486DX:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1049,7 +1079,11 @@ void cpu_set()
                 case CPU_Am486SX:
                 case CPU_Am486DX:
                 /*AMD timing identical to Intel*/
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1083,7 +1117,11 @@ void cpu_set()
                 
                 case CPU_Cx486S:
                 case CPU_Cx486DX:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 3; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1116,7 +1154,11 @@ void cpu_set()
                 break;
                 
                 case CPU_Cx5x86:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+#else
+                x86_setopcodes(ops_386, ops_486_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 1; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -1150,7 +1192,11 @@ void cpu_set()
                 break;
 
                 case CPU_WINCHIP:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_winchip_0f, dynarec_ops_386, dynarec_ops_winchip_0f);
+#else
+                x86_setopcodes(ops_386, ops_winchip_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -1184,13 +1230,19 @@ void cpu_set()
                 timing_jmp_rm      = 5;
                 timing_jmp_pm      = 7;
                 timing_jmp_pm_gate = 17;
+#ifdef USE_DYNAREC
                 codegen_timing_set(&codegen_timing_winchip);
+#endif
                 timing_misaligned = 2;
                 cpu_cyrix_alignment = 1;
                 break;
 
                 case CPU_PENTIUM:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
+#else
+                x86_setopcodes(ops_386, ops_pentium_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1227,11 +1279,17 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+#ifdef USE_DYNAREC
                 codegen_timing_set(&codegen_timing_pentium);
+#endif
                 break;
 
                 case CPU_PENTIUMMMX:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
+#else
+                x86_setopcodes(ops_386, ops_pentiummmx_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1268,11 +1326,17 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+#ifdef USE_DYNAREC
                 codegen_timing_set(&codegen_timing_pentium);
+#endif
                 break;
 
   		case CPU_Cx6x86:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
+#else
+                x86_setopcodes(ops_386, ops_pentium_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 1; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -1307,12 +1371,18 @@ void cpu_set()
                 cpu_hasMMX = 0;
                 cpu_hasMSR = 0;
                 cpu_hasCR4 = 0;
+#ifdef USE_DYNAREC
   		codegen_timing_set(&codegen_timing_686);
+#endif
   		CPUID = 0; /*Disabled on powerup by default*/
                 break;
 
                 case CPU_Cx6x86L:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
+#else
+                x86_setopcodes(ops_386, ops_pentium_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 1; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -1347,13 +1417,19 @@ void cpu_set()
                 cpu_hasMMX = 0;
                 cpu_hasMSR = 0;
                 cpu_hasCR4 = 0;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
          	ccr4 = 0x80;
                 break;
 
 
                 case CPU_CxGX1:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
+#else
+                x86_setopcodes(ops_386, ops_pentium_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 1; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -1371,11 +1447,14 @@ void cpu_set()
                 cpu_hasMSR = 1;
                 cpu_hasCR4 = 1;
                 cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
                 break;
 
   
                 case CPU_Cx6x86MX:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
                 x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
                 x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
@@ -1383,6 +1462,9 @@ void cpu_set()
                 x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
                 x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
                 x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+#else
+                x86_setopcodes(ops_386, ops_c6x86mx_0f);
+#endif
                 x86_opcodes_da_a16 = ops_fpu_686_da_a16;
                 x86_opcodes_da_a32 = ops_fpu_686_da_a32;
                 x86_opcodes_db_a16 = ops_fpu_686_db_a16;
@@ -1424,13 +1506,19 @@ void cpu_set()
                 cpu_hasMSR = 1;
                 cpu_hasCR4 = 1;
                 cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
          	ccr4 = 0x80;
                 break;
 
                 case CPU_K5:
                 case CPU_5K86:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
+#else
+                x86_setopcodes(ops_386, ops_k6_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1450,7 +1538,11 @@ void cpu_set()
                 break;
 
                 case CPU_K6:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
+#else
+                x86_setopcodes(ops_386, ops_k6_0f);
+#endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
                 timing_mr  = 3; /*memory dest   - register src*/
@@ -1468,10 +1560,13 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+#ifdef USE_DYNAREC
                 codegen_timing_set(&codegen_timing_pentium);
+#endif
                 break;
 
                 case CPU_PENTIUMPRO:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentiumpro_0f, dynarec_ops_386, dynarec_ops_pentiumpro_0f);
                 x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
                 x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
@@ -1479,6 +1574,9 @@ void cpu_set()
                 x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
                 x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
                 x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+#else
+                x86_setopcodes(ops_386, ops_pentiumpro_0f);
+#endif
                 x86_opcodes_da_a16 = ops_fpu_686_da_a16;
                 x86_opcodes_da_a32 = ops_fpu_686_da_a32;
                 x86_opcodes_db_a16 = ops_fpu_686_db_a16;
@@ -1502,11 +1600,14 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
                 break;
 
 #if 0                
 		case CPU_PENTIUM2:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium2_0f, dynarec_ops_386, dynarec_ops_pentium2_0f);
                 x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
                 x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
@@ -1514,6 +1615,9 @@ void cpu_set()
                 x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
                 x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
                 x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+#else
+                x86_setopcodes(ops_386, ops_pentium2_0f);
+#endif
                 x86_opcodes_da_a16 = ops_fpu_686_da_a16;
                 x86_opcodes_da_a32 = ops_fpu_686_da_a32;
                 x86_opcodes_db_a16 = ops_fpu_686_db_a16;
@@ -1537,11 +1641,14 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
                 break;
 #endif
 
                 case CPU_PENTIUM2D:
+#ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium2d_0f, dynarec_ops_386, dynarec_ops_pentium2d_0f);
                 x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
                 x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
@@ -1549,6 +1656,9 @@ void cpu_set()
                 x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
                 x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
                 x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+#else
+                x86_setopcodes(ops_386, ops_pentium2d_0f);
+#endif
                 x86_opcodes_da_a16 = ops_fpu_686_da_a16;
                 x86_opcodes_da_a32 = ops_fpu_686_da_a32;
                 x86_opcodes_db_a16 = ops_fpu_686_db_a16;
@@ -1572,7 +1682,9 @@ void cpu_set()
                 cpu_hasCR4 = 1;
 		cpu_hasVME = 1;
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
+#ifdef USE_DYNAREC
          	codegen_timing_set(&codegen_timing_686);
+#endif
                 break;
 
                 default:
@@ -2464,6 +2576,7 @@ uint8_t cyrix_read(uint16_t addr, void *priv)
         return 0xff;
 }
 
+#ifdef USE_DYNAREC
 void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn *dynarec_opcodes_0f)
 {
         x86_opcodes = opcodes;
@@ -2471,6 +2584,13 @@ void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn
         x86_dynarec_opcodes = dynarec_opcodes;
         x86_dynarec_opcodes_0f = dynarec_opcodes_0f;
 }
+#else
+void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f)
+{
+        x86_opcodes = opcodes;
+        x86_opcodes_0f = opcodes_0f;
+}
+#endif
 
 void cpu_update_waitstates()
 {
diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index 732edb894..793c141f4 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -8,7 +8,7 @@
  *
  *		CPU type handler.
  *
- * Version:	@(#)cpu.h	1.0.1	2017/10/07
+ * Version:	@(#)cpu.h	1.0.2	2017/10/14
  *
  * Authors:	Sarah Walker, <http://pcem-emulator.co.uk/>
  *		leilei,
diff --git a/src/cpu/x86_ops.h b/src/cpu/x86_ops.h
index 3352a2577..e0b981807 100644
--- a/src/cpu/x86_ops.h
+++ b/src/cpu/x86_ops.h
@@ -10,6 +10,7 @@
 
 typedef int (*OpFn)(uint32_t fetchdat);
 
+#ifdef USE_DYNAREC
 void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn *dynarec_opcodes_0f);
 
 extern OpFn *x86_dynarec_opcodes;
@@ -95,6 +96,9 @@ extern OpFn dynarec_ops_fpu_686_df_a32[256];
 
 extern OpFn dynarec_ops_REPE[1024];
 extern OpFn dynarec_ops_REPNE[1024];
+#else
+void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f);
+#endif
 
 extern OpFn *x86_opcodes;
 extern OpFn *x86_opcodes_0f;
diff --git a/src/cpu/x86_ops_flag.h b/src/cpu/x86_ops_flag.h
index 7205af152..59c692c65 100644
--- a/src/cpu/x86_ops_flag.h
+++ b/src/cpu/x86_ops_flag.h
@@ -99,7 +99,9 @@ static int opSAHF(uint32_t fetchdat)
         CLOCK_CYCLES(3);
         PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
         
+#if 0
         codegen_flags_changed = 0;
+#endif
 
         return 0;
 }
@@ -180,7 +182,9 @@ static int opPOPF_286(uint32_t fetchdat)
         CLOCK_CYCLES(5);
         PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
         
+#if 0
         codegen_flags_changed = 0;
+#endif
 
         return 0;
 }
@@ -238,7 +242,9 @@ static int opPOPF(uint32_t fetchdat)
         CLOCK_CYCLES(5);
         PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
         
+#if 0
         codegen_flags_changed = 0;
+#endif
 
         return 0;
 }
@@ -270,7 +276,9 @@ static int opPOPFD(uint32_t fetchdat)
         CLOCK_CYCLES(5);
         PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
         
+#if 0
         codegen_flags_changed = 0;
+#endif
 
         return 0;
 }
diff --git a/src/cpu/x86seg.c b/src/cpu/x86seg.c
index 8fd3cd135..e365488bc 100644
--- a/src/cpu/x86seg.c
+++ b/src/cpu/x86seg.c
@@ -405,10 +405,12 @@ void loadseg(uint16_t seg, x86seg *s)
                 }
 #endif
                 s->checked = 0;
+#ifdef USE_DYNAREC
                 if (s == &_ds)
                         codegen_flat_ds = 0;
                 if (s == &_ss)
                         codegen_flat_ss = 0;
+#endif
         }
         else
         {
@@ -418,10 +420,12 @@ void loadseg(uint16_t seg, x86seg *s)
                 if (s == &_ss)
                         stack32 = 0;
                 s->checked = 1;
+#ifdef USE_DYNAREC
                 if (s == &_ds)
                         codegen_flat_ds = 0;
                 if (s == &_ss)
                         codegen_flat_ss = 0;
+#endif
         }
         
         if (s == &_ds)
diff --git a/src/ibm.h b/src/ibm.h
index a9d8a74c8..d671fff9b 100644
--- a/src/ibm.h
+++ b/src/ibm.h
@@ -380,7 +380,7 @@ extern wchar_t floppyfns[4][512];
 extern int driveempty[4];
 
 #define MDA ((gfxcard==GFX_MDA || gfxcard==GFX_HERCULES || gfxcard==GFX_HERCULESPLUS || gfxcard==GFX_INCOLOR || gfxcard==GFX_GENIUS) && (romset<ROM_TANDY || romset>=ROM_IBMAT))
-#define VGA ((gfxcard>=GFX_TVGA || romset==ROM_ACER386) && gfxcard!=GFX_COLORPLUS && gfxcard!=GFX_INCOLOR && gfxcard!=GFX_WY700 && gfxcard!=GFX_GENIUS && gfxcard!=GFX_COMPAQ_EGA && gfxcard!=GFX_SUPER_EGA && gfxcard!=GFX_HERCULESPLUS && romset!=ROM_PC1640 && romset!=ROM_PC1512 && romset!=ROM_TANDY && romset!=ROM_PC200)
+#define VGA ((gfxcard>=GFX_TVGA) && gfxcard!=GFX_COLORPLUS && gfxcard!=GFX_INCOLOR && gfxcard!=GFX_WY700 && gfxcard!=GFX_GENIUS && gfxcard!=GFX_COMPAQ_EGA && gfxcard!=GFX_SUPER_EGA && gfxcard!=GFX_HERCULESPLUS && romset!=ROM_PC1640 && romset!=ROM_PC1512 && romset!=ROM_TANDY && romset!=ROM_PC200)
 
 int GAMEBLASTER, GUS, SSI2001, voodoo_enabled, buslogic_enabled;
 extern int AMSTRAD, AT, is286, is386, PCI, TANDY;
diff --git a/src/mem.c b/src/mem.c
index 3ad1b5015..5ef9e3c72 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -14,7 +14,14 @@
 #include "io.h"
 #include "mem.h"
 #include "rom.h"
+#ifdef USE_DYNAREC
 #include "cpu/codegen.h"
+#else
+#define PAGE_MASK_INDEX_MASK 3
+#define PAGE_MASK_INDEX_SHIFT 10
+#define PAGE_MASK_MASK 63
+#define PAGE_MASK_SHIFT 4
+#endif
 
 
 static uint8_t         (*_mem_read_b[0x40000])(uint32_t addr, void *priv);
@@ -112,7 +119,9 @@ void flushmmucache(void)
         pccache=(uint32_t)0xFFFFFFFF;
         pccache2=(uint8_t *)0xFFFFFFFF;
         
+#ifdef USE_DYNAREC
         codegen_flush();
+#endif
 }
 
 void flushmmucache_nopc(void)
@@ -365,7 +374,11 @@ void addwritelookup(uint32_t virt, uint32_t phys)
                 writelookup2[writelookup[writelnext]] = -1;
         }
 
+#ifdef USE_DYNAREC
         if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3] || (phys & ~0xfff) == recomp_page)
+#else
+        if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3])
+#endif
                 page_lookup[virt >> 12] = &pages[phys >> 12];
         else
                 writelookup2[virt>>12] = (uintptr_t)&ram[(uintptr_t)(phys & ~0xFFF) - (uintptr_t)(virt & ~0xfff)];
@@ -944,7 +957,11 @@ uint32_t mem_read_raml(uint32_t addr, void *priv)
 
 void mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
 {      
+#ifdef USE_DYNAREC
         if (val != p->mem[addr & 0xfff] || codegen_in_recompile)
+#else
+        if (val != p->mem[addr & 0xfff])
+#endif
         {
                 uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
                 p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask;
@@ -953,7 +970,11 @@ void mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
 }
 void mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
 {
+#ifdef USE_DYNAREC
         if (val != *(uint16_t *)&p->mem[addr & 0xfff] || codegen_in_recompile)
+#else
+        if (val != *(uint16_t *)&p->mem[addr & 0xfff])
+#endif
         {
                 uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
                 if ((addr & 0xf) == 0xf)
@@ -964,7 +985,11 @@ void mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
 }
 void mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p)
 {       
+#ifdef USE_DYNAREC
         if (val != *(uint32_t *)&p->mem[addr & 0xfff] || codegen_in_recompile)
+#else
+        if (val != *(uint32_t *)&p->mem[addr & 0xfff])
+#endif
         {
                 uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
                 if ((addr & 0xf) >= 0xd)
diff --git a/src/pc.c b/src/pc.c
index 55513bf40..1832c56fc 100644
--- a/src/pc.c
+++ b/src/pc.c
@@ -8,7 +8,7 @@
  *
  *		Emulation core dispatcher.
  *
- * Version:	@(#)pc.c	1.0.26	2017/10/14
+ * Version:	@(#)pc.c	1.0.27	2017/10/14
  *
  * Authors:	Sarah Walker, <http://pcem-emulator.co.uk/>
  *		Miran Grca, <mgrca8@gmail.com>
@@ -28,7 +28,9 @@
 #include "config.h"
 #include "ibm.h"
 #include "cpu/cpu.h"
+#ifdef USE_DYNAREC
 #include "cpu/codegen.h"
+#endif
 #include "cpu/x86_ops.h"
 #include "io.h"
 #include "mem.h"
@@ -406,7 +408,9 @@ again2:
 
     mem_init();
 
+#ifdef USE_DYNAREC
     codegen_init();
+#endif
 
     mouse_init();
 #ifdef WALTJE
@@ -685,9 +689,11 @@ pc_run(void)
     clockrate = machines[machine].cpu[cpu_manufacturer].cpus[cpu].rspeed;
         
     if (is386)   {
+#ifdef USE_DYNAREC
 	if (cpu_use_dynarec)
 		exec386_dynarec(machines[machine].cpu[cpu_manufacturer].cpus[cpu].rspeed / 100);
-	  else
+	else
+#endif
 		exec386(machines[machine].cpu[cpu_manufacturer].cpus[cpu].rspeed / 100);
     } else if (AT) {
 	exec386(machines[machine].cpu[cpu_manufacturer].cpus[cpu].rspeed / 100);
@@ -718,6 +724,7 @@ pc_run(void)
 	segawrites = egawrites;
 	scycles_lost = cycles_lost;
 
+#ifdef USE_DYNAREC
 	cpu_recomp_blocks_latched = cpu_recomp_blocks;
 	cpu_recomp_ins_latched = cpu_state.cpu_recomp_ins;
 	cpu_recomp_full_ins_latched = cpu_recomp_full_ins;
@@ -739,6 +746,7 @@ pc_run(void)
 	cpu_recomp_removed = 0;
 	cpu_reps = 0;
 	cpu_notreps = 0;
+#endif
 
 	updatestatus = 1;
 	readlnum = writelnum = 0;
diff --git a/src/rom.h b/src/rom.h
index aa6c33764..21d52a695 100644
--- a/src/rom.h
+++ b/src/rom.h
@@ -47,7 +47,6 @@ enum {
     ROM_AMIXT,		/* XT Clone with AMI BIOS */
     ROM_LTXT,
     ROM_LXT3,
-    ROM_PX386,
     ROM_DTK386,
     ROM_PXXT,
     ROM_JUKOPC,
@@ -57,16 +56,10 @@ enum {
     ROM_CMDPC30,
     ROM_AMI286,
     ROM_AWARD286,
-    ROM_DELL200,
-    ROM_MISC286,
-    ROM_IBMAT386,
-    ROM_ACER386,
     ROM_MEGAPC,
     ROM_AMI386SX,
     ROM_AMI486,
     ROM_WIN486,
-    ROM_PCI486,
-    ROM_SIS496,
     ROM_430VX,
     ROM_ENDEAVOR,
     ROM_REVENGE,
@@ -74,11 +67,6 @@ enum {
     ROM_IBMXT286,
     ROM_DESKPRO_386,
     ROM_PORTABLE,
-#if 0
-    ROM_PORTABLEII,
-    ROM_PORTABLEIII,
-    ROM_PORTABLEIII386,	/* original shipped w/80286, later switched to 386DX */
-#endif
     ROM_IBMPS1_2121,
 
     ROM_AMI386DX_OPTI495,
@@ -90,9 +78,8 @@ enum {
     ROM_IBMPS2_M80,
 
     ROM_DTK486,		/* DTK PKM-0038S E-2/SiS 471/Award/SiS 85C471 */
-    ROM_VLI486SV2G,	/* ASUS VL/I-486SV2G/SiS 471/Award/SiS 85C471 */
+    ROM_VLI486SV2G,	/* ASUS VL/I-486SV2G/SiS 471/Award/SiS 85C471 */	/* 51 */
     ROM_R418,		/* Rise Computer R418/SiS 496/497/Award/SMC FDC37C665 */
-    ROM_586MC1,		/* Micro Star 586MC1 MS-5103/430LX/Award */
     ROM_PLATO,		/* Intel Premiere/PCI II/430NX/AMI/SMC FDC37C665 */
     ROM_MB500N,		/* PC Partner MB500N/430FX/Award/SMC FDC37C665 */
     ROM_P54TP4XE,	/* ASUS P/I-P55TP4XE/430FX/Award/SMC FDC37C665 */
@@ -103,13 +90,11 @@ enum {
     ROM_P55T2P4,	/* ASUS P/I-P55T2P4/430HX/Award/Winbond W8387F*/
     ROM_P55TVP4,	/* ASUS P/I-P55TVP4/430HX/Award/Winbond W8387F*/
     ROM_P55VA,		/* Epox P55-VA/430VX/Award/SMC FDC37C932FR*/
-
-    ROM_440FX,		/* Tyan Titan-Pro AT/440FX/Award BIOS/SMC FDC37C665 */
- 
-    ROM_MARL,		/* Intel Advanced_ML/430HX/AMI/NS PC87306 */
     ROM_THOR,		/* Intel Advanced_ATX/430FX/AMI/NS PC87306 */
     ROM_MRTHOR,		/* Intel Advanced_ATX/430FX/MR.BIOS/NS PC87306 */
-    ROM_POWERMATE_V,	/* NEC PowerMate V/430FX/Phoenix/SMC FDC37C66 5*/
+    ROM_POWERMATE_V,	/* NEC PowerMate V/430FX/Phoenix/SMC FDC37C66 5*/	/* 68 */
+
+    ROM_440FX,		/* Tyan Titan-Pro AT/440FX/Award BIOS/SMC FDC37C665 */
 
     ROM_IBMPS1_2121_ISA,/* IBM PS/1 Model 2121 with ISA expansion bus */
 
@@ -123,8 +108,6 @@ enum {
     ROM_MEGAPCDX,	/* 386DX mdl - Note: documentation (in German) clearly says such a model exists */
     ROM_ZAPPA,		/* Intel Advanced_ZP/430FX/AMI/NS PC87306 */
 
-    ROM_CMDPC60,
-
     ROM_S1668,		/* Tyan Titan-Pro ATX/440FX/AMI/SMC FDC37C669 */
     ROM_IBMPS1_2133,
 
diff --git a/src/scsi/scsi_buslogic.c b/src/scsi/scsi_buslogic.c
index 4363bddbd..a1ddc7daa 100644
--- a/src/scsi/scsi_buslogic.c
+++ b/src/scsi/scsi_buslogic.c
@@ -1285,6 +1285,7 @@ buslogic_init(device_t *info)
     uint16_t scam_rom_size;
     FILE *f;
     buslogic_data_t *bl;
+    uint32_t bios_rom_addr;
 
     /* Call common initializer. */
     dev = x54x_init(info);
@@ -1308,7 +1309,13 @@ buslogic_init(device_t *info)
     bl->chip = info->local;
     bl->PCIBase = 0;
     bl->MMIOBase = 0;
-    bl->has_bios = device_get_config_int("bios");
+    if (info->flags & DEVICE_PCI) {
+	bios_rom_addr = 0xd8000;
+	bl->has_bios = device_get_config_int("bios");
+    } else {
+    	bios_rom_addr = device_get_config_hex20("bios_addr");
+	bl->has_bios = !!bios_rom_addr;
+    }
 
     dev->ven_cmd_phase1 = buslogic_cmd_phase1;
     dev->ven_get_host_id = buslogic_get_host_id;
@@ -1390,7 +1397,7 @@ buslogic_init(device_t *info)
 
 	bl->bios_mask = 0xffffc000;
 
-	rom_init(&bl->bios, bios_rom_name, 0xd8000, bios_rom_size, bios_rom_mask, 0, MEM_MAPPING_EXTERNAL);
+	rom_init(&bl->bios, bios_rom_name, bios_rom_addr, bios_rom_size, bios_rom_mask, 0, MEM_MAPPING_EXTERNAL);
 
 	if (has_autoscsi_rom) {
 		f = rom_fopen(autoscsi_rom_name, L"rb");
@@ -1519,9 +1526,26 @@ static device_config_t BT_ISA_Config[] = {
                         }
                 },
         },
-	{
-		"bios", "Enable BIOS", CONFIG_BINARY, "", 0
-	},
+        {
+                "bios_addr", "BIOS Address", CONFIG_HEX20, "", 0,
+                {
+                        {
+                                "Disabled", 0
+                        },
+                        {
+                                "C800H", 0xc8000
+                        },
+                        {
+                                "D000H", 0xd0000
+                        },
+                        {
+                                "D800H", 0xd8000
+                        },
+                        {
+                                ""
+                        }
+                },
+        },
 	{
 		"", "", -1
 	}
diff --git a/src/video/vid_table.c b/src/video/vid_table.c
index 02b06a201..2e3d69b37 100644
--- a/src/video/vid_table.c
+++ b/src/video/vid_table.c
@@ -187,10 +187,6 @@ video_reset_device(int rs, int gc)
 		device_add(&paradise_wd90c11_megapc_device);
 		return;
 			
-	case ROM_ACER386:
-		device_add(&oti067_device);
-		return;
-		
 	case ROM_IBMPS1_2011:
 	case ROM_IBMPS2_M30_286:
 	case ROM_IBMPS2_M50:
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index b784f3323..07a830da5 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -278,12 +278,14 @@ BEGIN
                     12,12
     LTEXT           "MB",IDT_1705,123,64,10,10
     LTEXT           "Memory:",IDT_1706,7,64,30,10
-    CONTROL         "Dynamic Recompiler",IDC_CHECK_DYNAREC,"Button",
-                    BS_AUTOCHECKBOX | WS_TABSTOP,7,100,94,10
+    CONTROL         "Enable time sync",IDC_CHECK_SYNC,"Button",
+                    BS_AUTOCHECKBOX | WS_TABSTOP,7,100,102,10
     CONTROL         "Enable FPU",IDC_CHECK_FPU,"Button",BS_AUTOCHECKBOX | 
                     WS_TABSTOP,147,100,113,10
-    CONTROL         "Enable time sync",IDC_CHECK_SYNC,"Button",
-                    BS_AUTOCHECKBOX | WS_TABSTOP,7,115,102,10
+#ifdef USE_DYNAREC
+    CONTROL         "Dynamic Recompiler",IDC_CHECK_DYNAREC,"Button",
+                    BS_AUTOCHECKBOX | WS_TABSTOP,7,115,94,10
+#endif
 END
 
 DLG_CFG_VIDEO DIALOG DISCARDABLE  97, 0, 267, 63
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index 65fa7c18b..c16b33be4 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -8,7 +8,7 @@
 #
 #		Makefile for Win32 (MinGW32) environment.
 #
-# Version:	@(#)Makefile.mingw	1.0.62	2017/10/14
+# Version:	@(#)Makefile.mingw	1.0.63	2017/10/14
 #
 # Authors:	Miran Grca, <mgrca8@gmail.com>
 #               Fred N. van Kempen, <decwiz@yahoo.com>
@@ -89,6 +89,9 @@ endif
 ifndef PAS16
 PAS16		= n
 endif
+ifndef DYNAREC
+DYNAREC		:= y
+endif
 ifndef X64
 X64		:= n
 endif
@@ -187,6 +190,17 @@ endif
 
 
 # Optional modules.
+ifeq ($(DYNAREC), y)
+CFLAGS		+= -DUSE_DYNAREC
+RFLAGS		+= -DUSE_DYNAREC
+DYNARECOBJ	:= 386_dynarec_ops.o \
+		    codegen.o \
+		    codegen_ops.o \
+		    codegen_timing_common.o codegen_timing_486.o \
+		    codegen_timing_686.o codegen_timing_pentium.o \
+		    codegen_timing_winchip.o $(PLATCG)
+endif
+
 ifeq ($(FLUIDSYNTH), y)
 CFLAGS		+= -DUSE_FLUIDSYNTH
 FSYNTHOBJ	:= midi_fluidsynth.o
@@ -265,13 +279,9 @@ MAINOBJ		:= pc.o config.o random.o timer.o io.o dma.o nmi.o pic.o \
 		   device.o nvr.o nvr_at.o nvr_ps2.o \
 		   intel.o intel_flash.o intel_sio.o
 
-CPUOBJ		:= cpu.o 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o \
-		   codegen.o \
-		    codegen_ops.o \
-		    codegen_timing_common.o codegen_timing_486.o \
-		    codegen_timing_686.o codegen_timing_pentium.o \
-		    codegen_timing_winchip.o $(PLATCG) \
-		   x86seg.o x87.o
+CPUOBJ		:= cpu.o 386.o 386_dynarec.o 808x.o \
+		   x86seg.o x87.o \
+		   $(DYNARECOBJ)
 
 MCHOBJ		:= machine.o \
 		    machine_common.o \
diff --git a/src/win/resource.h b/src/win/resource.h
index e71fa3532..5e050383c 100644
--- a/src/win/resource.h
+++ b/src/win/resource.h
@@ -100,7 +100,9 @@
 #define IDC_COMBO_CPU		1013
 #define IDC_CHECK_FPU		1014
 #define IDC_COMBO_WS		1015
+#ifdef USE_DYNAREC
 #define IDC_CHECK_DYNAREC	1016
+#endif
 #define IDC_MEMTEXT		1017
 #define IDC_MEMSPIN		1018
 #define IDC_TEXT_MB		IDT_1705
diff --git a/src/win/win_settings.c b/src/win/win_settings.c
index 3f73b2137..15b774d5e 100644
--- a/src/win/win_settings.c
+++ b/src/win/win_settings.c
@@ -57,7 +57,10 @@
 
 
 /* Machine category */
-static int temp_machine, temp_cpu_m, temp_cpu, temp_wait_states, temp_mem_size, temp_dynarec, temp_fpu, temp_sync;
+static int temp_machine, temp_cpu_m, temp_cpu, temp_wait_states, temp_mem_size, temp_fpu, temp_sync;
+#ifdef USE_DYNAREC
+static int temp_dynarec;
+#endif
 
 /* Video category */
 static int temp_gfxcard, temp_video_speed, temp_voodoo;
@@ -135,7 +138,9 @@ static void win_settings_init(void)
 	temp_wait_states = cpu_waitstates;
 	temp_cpu = cpu;
 	temp_mem_size = mem_size;
+#ifdef USE_DYNAREC
 	temp_dynarec = cpu_use_dynarec;
+#endif
 	temp_fpu = enable_external_fpu;
 	temp_sync = enable_sync;
 
@@ -205,7 +210,9 @@ static int win_settings_changed(void)
 	i = i || (cpu_waitstates != temp_wait_states);
 	i = i || (cpu != temp_cpu);
 	i = i || (mem_size != temp_mem_size);
+#ifdef USE_DYNAREC
 	i = i || (temp_dynarec != cpu_use_dynarec);
+#endif
 	i = i || (temp_fpu != enable_external_fpu);
 	i = i || (temp_sync != enable_sync);
 
@@ -300,7 +307,9 @@ static void win_settings_save(void)
 	cpu_waitstates = temp_wait_states;
 	cpu = temp_cpu;
 	mem_size = temp_mem_size;
+#ifdef USE_DYNAREC
 	cpu_use_dynarec = temp_dynarec;
+#endif
 	enable_external_fpu = temp_fpu;
 	enable_sync = temp_sync;
 
@@ -382,7 +391,9 @@ static void win_settings_machine_recalc_cpu(HWND hdlg)
 {
 	HWND h;
 	int temp_romset = 0;
+#ifdef USE_DYNAREC
         int cpu_flags;
+#endif
         int cpu_type;
 
 	temp_romset = machine_getromset_ex(temp_machine);
@@ -398,6 +409,7 @@ static void win_settings_machine_recalc_cpu(HWND hdlg)
 		EnableWindow(h, FALSE);
 	}
 
+#ifdef USE_DYNAREC
 	h=GetDlgItem(hdlg, IDC_CHECK_DYNAREC);
 	cpu_flags = machines[romstomachine[temp_romset]].cpu[temp_cpu_m].cpus[temp_cpu].cpu_flags;
 	if (!(cpu_flags & CPU_SUPPORTS_DYNAREC) && (cpu_flags & CPU_REQUIRES_DYNAREC))
@@ -421,6 +433,7 @@ static void win_settings_machine_recalc_cpu(HWND hdlg)
 	{
 		EnableWindow(h, TRUE);
 	}
+#endif
 
 	h = GetDlgItem(hdlg, IDC_CHECK_FPU);
 	cpu_type = machines[romstomachine[temp_romset]].cpu[temp_cpu_m].cpus[temp_cpu].cpu_type;
@@ -594,8 +607,10 @@ static BOOL CALLBACK win_settings_machine_proc(HWND hdlg, UINT message, WPARAM w
 
 			SendMessage(h, CB_SETCURSEL, temp_wait_states, 0);
 
+#ifdef USE_DYNAREC
         	        h=GetDlgItem(hdlg, IDC_CHECK_DYNAREC);
 	                SendMessage(h, BM_SETCHECK, temp_dynarec, 0);
+#endif
 
 			h = GetDlgItem(hdlg, IDC_MEMSPIN);
 			SendMessage(h, UDM_SETBUDDY, (WPARAM)GetDlgItem(hdlg, IDC_MEMTEXT), 0);
@@ -654,8 +669,10 @@ static BOOL CALLBACK win_settings_machine_proc(HWND hdlg, UINT message, WPARAM w
 			lptsTemp = (LPTSTR) malloc(512);
 			stransi = (char *) malloc(512);
 
+#ifdef USE_DYNAREC
         	        h=GetDlgItem(hdlg, IDC_CHECK_DYNAREC);
 			temp_dynarec = SendMessage(h, BM_GETCHECK, 0, 0);
+#endif
 
         	        h=GetDlgItem(hdlg, IDC_CHECK_SYNC);
 			temp_sync = SendMessage(h, BM_GETCHECK, 0, 0);
diff --git a/src/win/win_status.c b/src/win/win_status.c
index 786809174..86565f865 100644
--- a/src/win/win_status.c
+++ b/src/win/win_status.c
@@ -12,7 +12,9 @@
 #include "../ibm.h"
 #include "../mem.h"
 #include "../cpu/x86_ops.h"
+#ifdef USE_DYNAREC
 #include "../cpu/codegen.h"
+#endif
 #include "../device.h"
 #include "win.h"
 
@@ -52,8 +54,10 @@ StatusWindowProcedure(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
 			"Timer 0 frequency : %fHz\n\n"
 			"CPU time : %f%% (%f%%)\n"
 
+#ifdef USE_DYNAREC
 			"New blocks : %i\nOld blocks : %i\nRecompiled speed : %f MIPS\nAverage size : %f\n"
-			"Flushes : %i\nEvicted : %i\nReused : %i\nRemoved : %i\nReal speed : %f MIPS"
+			"Flushes : %i\nEvicted : %i\nReused : %i\nRemoved : %i"
+#endif
 			,mips,
 			flops,
 			segareads,
@@ -61,13 +65,13 @@ StatusWindowProcedure(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
 			clockrate - scycles_lost,
 			pit_timer0_freq(),
 			((double)main_time * 100.0) / status_diff,
-			((double)main_time * 100.0) / timer_freq
+                        ((double)main_time * 100.0) / timer_freq
 
+#ifdef USE_DYNAREC
 			, cpu_new_blocks_latched, cpu_recomp_blocks_latched, (double)cpu_recomp_ins_latched / 1000000.0, (double)cpu_recomp_ins_latched/cpu_recomp_blocks_latched,
 			cpu_recomp_flushes_latched, cpu_recomp_evicted_latched,
-			cpu_recomp_reuse_latched, cpu_recomp_removed_latched,
-			
-			((double)cpu_recomp_ins_latched / 1000000.0) / ((double)main_time / timer_freq)
+			cpu_recomp_reuse_latched, cpu_recomp_removed_latched
+#endif
 		);
 		main_time = 0;
 		SendDlgItemMessage(hdlg, IDT_SDEVICE, WM_SETTEXT,