Added support for the D86F floppy image format I invented that allows things not possible with IMG images;
Applied all mainline PCem commits; Settings dialog now says 86Box instead of PCem; Manifest renamed from PCem to 86Box.
This commit is contained in:
OBattler
@@ -1,6 +1,3 @@
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/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#define OP_ARITH(name, operation, setflags, flagops, gettempc) \
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static int op ## name ## _b_rmw_a16(uint32_t fetchdat) \
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{ \
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@@ -16,9 +13,9 @@
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} \
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else \
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{ \
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uint8_t dst = geteab(); if (abrt) return 1; \
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uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
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uint8_t src = getr8(cpu_reg); \
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seteab(operation); if (abrt) return 1; \
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seteab(operation); if (cpu_state.abrt) return 1; \
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setflags ## 8 flagops; \
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CLOCK_CYCLES(timing_mr); \
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} \
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@@ -38,9 +35,9 @@
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} \
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else \
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{ \
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uint8_t dst = geteab(); if (abrt) return 1; \
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uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
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uint8_t src = getr8(cpu_reg); \
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seteab(operation); if (abrt) return 1; \
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seteab(operation); if (cpu_state.abrt) return 1; \
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setflags ## 8 flagops; \
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CLOCK_CYCLES(timing_mr); \
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} \
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@@ -61,9 +58,9 @@
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} \
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else \
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{ \
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uint16_t dst = geteaw(); if (abrt) return 1; \
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uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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seteaw(operation); if (abrt) return 1; \
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seteaw(operation); if (cpu_state.abrt) return 1; \
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setflags ## 16 flagops; \
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CLOCK_CYCLES(timing_mr); \
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} \
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@@ -83,9 +80,9 @@
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} \
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else \
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{ \
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uint16_t dst = geteaw(); if (abrt) return 1; \
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uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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seteaw(operation); if (abrt) return 1; \
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seteaw(operation); if (cpu_state.abrt) return 1; \
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setflags ## 16 flagops; \
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CLOCK_CYCLES(timing_mr); \
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} \
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@@ -106,9 +103,9 @@
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} \
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else \
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{ \
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uint32_t dst = geteal(); if (abrt) return 1; \
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uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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seteal(operation); if (abrt) return 1; \
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seteal(operation); if (cpu_state.abrt) return 1; \
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setflags ## 32 flagops; \
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CLOCK_CYCLES(timing_mrl); \
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} \
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@@ -128,9 +125,9 @@
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} \
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else \
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{ \
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uint32_t dst = geteal(); if (abrt) return 1; \
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uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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seteal(operation); if (abrt) return 1; \
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seteal(operation); if (cpu_state.abrt) return 1; \
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setflags ## 32 flagops; \
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CLOCK_CYCLES(timing_mrl); \
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} \
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@@ -143,7 +140,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = getr8(cpu_reg); \
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src = geteab(); if (abrt) return 1; \
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src = geteab(); if (cpu_state.abrt) return 1; \
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setflags ## 8 flagops; \
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setr8(cpu_reg, operation); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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@@ -155,7 +152,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = getr8(cpu_reg); \
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src = geteab(); if (abrt) return 1; \
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src = geteab(); if (cpu_state.abrt) return 1; \
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setflags ## 8 flagops; \
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setr8(cpu_reg, operation); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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@@ -168,7 +165,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = cpu_state.regs[cpu_reg].w; \
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src = geteaw(); if (abrt) return 1; \
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src = geteaw(); if (cpu_state.abrt) return 1; \
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setflags ## 16 flagops; \
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cpu_state.regs[cpu_reg].w = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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@@ -180,7 +177,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = cpu_state.regs[cpu_reg].w; \
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src = geteaw(); if (abrt) return 1; \
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src = geteaw(); if (cpu_state.abrt) return 1; \
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setflags ## 16 flagops; \
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cpu_state.regs[cpu_reg].w = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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@@ -193,7 +190,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = cpu_state.regs[cpu_reg].l; \
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src = geteal(); if (abrt) return 1; \
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src = geteal(); if (cpu_state.abrt) return 1; \
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setflags ## 32 flagops; \
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cpu_state.regs[cpu_reg].l = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
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@@ -205,7 +202,7 @@
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = cpu_state.regs[cpu_reg].l; \
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src = geteal(); if (abrt) return 1; \
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src = geteal(); if (cpu_state.abrt) return 1; \
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setflags ## 32 flagops; \
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cpu_state.regs[cpu_reg].l = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
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@@ -237,7 +234,7 @@
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static int op ## name ## _EAX_imm(uint32_t fetchdat) \
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{ \
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uint32_t dst = EAX; \
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uint32_t src = getlong(); if (abrt) return 1; \
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uint32_t src = getlong(); if (cpu_state.abrt) return 1; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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setflags ## 32 flagops; \
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EAX = operation; \
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@@ -257,7 +254,7 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
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{
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uint8_t dst;
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fetch_ea_16(fetchdat);
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dst = geteab(); if (abrt) return 1;
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dst = geteab(); if (cpu_state.abrt) return 1;
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setsub8(dst, getr8(cpu_reg));
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -267,7 +264,7 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
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{
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uint8_t dst;
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fetch_ea_32(fetchdat);
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dst = geteab(); if (abrt) return 1;
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dst = geteab(); if (cpu_state.abrt) return 1;
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setsub8(dst, getr8(cpu_reg));
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -278,7 +275,7 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
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{
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uint16_t dst;
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fetch_ea_16(fetchdat);
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dst = geteaw(); if (abrt) return 1;
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dst = geteaw(); if (cpu_state.abrt) return 1;
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setsub16(dst, cpu_state.regs[cpu_reg].w);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -288,7 +285,7 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
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{
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uint16_t dst;
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fetch_ea_32(fetchdat);
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dst = geteaw(); if (abrt) return 1;
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dst = geteaw(); if (cpu_state.abrt) return 1;
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setsub16(dst, cpu_state.regs[cpu_reg].w);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -299,7 +296,7 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
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{
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uint32_t dst;
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fetch_ea_16(fetchdat);
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dst = geteal(); if (abrt) return 1;
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dst = geteal(); if (cpu_state.abrt) return 1;
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setsub32(dst, cpu_state.regs[cpu_reg].l);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -309,7 +306,7 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
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{
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uint32_t dst;
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fetch_ea_32(fetchdat);
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dst = geteal(); if (abrt) return 1;
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dst = geteal(); if (cpu_state.abrt) return 1;
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setsub32(dst, cpu_state.regs[cpu_reg].l);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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@@ -320,7 +317,7 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
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{
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uint8_t src;
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fetch_ea_16(fetchdat);
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src = geteab(); if (abrt) return 1;
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src = geteab(); if (cpu_state.abrt) return 1;
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setsub8(getr8(cpu_reg), src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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@@ -329,7 +326,7 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
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{
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uint8_t src;
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fetch_ea_32(fetchdat);
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src = geteab(); if (abrt) return 1;
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src = geteab(); if (cpu_state.abrt) return 1;
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setsub8(getr8(cpu_reg), src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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@@ -339,7 +336,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
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{
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uint16_t src;
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fetch_ea_16(fetchdat);
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src = geteaw(); if (abrt) return 1;
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src = geteaw(); if (cpu_state.abrt) return 1;
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setsub16(cpu_state.regs[cpu_reg].w, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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@@ -348,7 +345,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
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{
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uint16_t src;
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fetch_ea_32(fetchdat);
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src = geteaw(); if (abrt) return 1;
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src = geteaw(); if (cpu_state.abrt) return 1;
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setsub16(cpu_state.regs[cpu_reg].w, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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@@ -358,7 +355,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
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{
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uint32_t src;
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fetch_ea_16(fetchdat);
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src = geteal(); if (abrt) return 1;
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src = geteal(); if (cpu_state.abrt) return 1;
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setsub32(cpu_state.regs[cpu_reg].l, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
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return 0;
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@@ -367,7 +364,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
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{
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uint32_t src;
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fetch_ea_32(fetchdat);
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src = geteal(); if (abrt) return 1;
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src = geteal(); if (cpu_state.abrt) return 1;
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setsub32(cpu_state.regs[cpu_reg].l, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
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return 0;
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@@ -391,7 +388,7 @@ static int opCMP_AX_imm(uint32_t fetchdat)
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static int opCMP_EAX_imm(uint32_t fetchdat)
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{
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uint32_t src = getlong(); if (abrt) return 1;
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uint32_t src = getlong(); if (cpu_state.abrt) return 1;
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setsub32(EAX, src);
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CLOCK_CYCLES(timing_rr);
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return 0;
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@@ -401,7 +398,7 @@ static int opTEST_b_a16(uint32_t fetchdat)
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{
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uint8_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 1;
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temp = geteab(); if (cpu_state.abrt) return 1;
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temp2 = getr8(cpu_reg);
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setznp8(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -412,7 +409,7 @@ static int opTEST_b_a32(uint32_t fetchdat)
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{
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uint8_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 1;
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temp = geteab(); if (cpu_state.abrt) return 1;
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temp2 = getr8(cpu_reg);
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setznp8(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -424,7 +421,7 @@ static int opTEST_w_a16(uint32_t fetchdat)
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{
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uint16_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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temp = geteaw(); if (cpu_state.abrt) return 1;
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temp2 = cpu_state.regs[cpu_reg].w;
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setznp16(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -435,7 +432,7 @@ static int opTEST_w_a32(uint32_t fetchdat)
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{
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uint16_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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temp = geteaw(); if (cpu_state.abrt) return 1;
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temp2 = cpu_state.regs[cpu_reg].w;
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setznp16(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -447,7 +444,7 @@ static int opTEST_l_a16(uint32_t fetchdat)
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{
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uint32_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteal(); if (abrt) return 1;
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temp = geteal(); if (cpu_state.abrt) return 1;
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temp2 = cpu_state.regs[cpu_reg].l;
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setznp32(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -458,7 +455,7 @@ static int opTEST_l_a32(uint32_t fetchdat)
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{
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uint32_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteal(); if (abrt) return 1;
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temp = geteal(); if (cpu_state.abrt) return 1;
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temp2 = cpu_state.regs[cpu_reg].l;
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setznp32(temp & temp2);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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@@ -482,7 +479,7 @@ static int opTEST_AX(uint32_t fetchdat)
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}
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static int opTEST_EAX(uint32_t fetchdat)
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{
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uint32_t temp = getlong(); if (abrt) return 1;
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uint32_t temp = getlong(); if (cpu_state.abrt) return 1;
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setznp32(EAX & temp);
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CLOCK_CYCLES(timing_rr);
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return 0;
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@@ -490,46 +487,46 @@ static int opTEST_EAX(uint32_t fetchdat)
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#define ARITH_MULTI(ea_width, flag_width) \
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dst = getea ## ea_width(); if (abrt) return 1; \
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dst = getea ## ea_width(); if (cpu_state.abrt) return 1; \
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switch (rmdat&0x38) \
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{ \
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case 0x00: /*ADD ea, #*/ \
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setea ## ea_width(dst + src); if (abrt) return 1; \
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setea ## ea_width(dst + src); if (cpu_state.abrt) return 1; \
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setadd ## flag_width(dst, src); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
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break; \
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case 0x08: /*OR ea, #*/ \
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dst |= src; \
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setea ## ea_width(dst); if (abrt) return 1; \
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setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
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setznp ## flag_width(dst); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
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break; \
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case 0x10: /*ADC ea, #*/ \
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tempc = CF_SET() ? 1 : 0; \
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setea ## ea_width(dst + src + tempc); if (abrt) return 1; \
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setea ## ea_width(dst + src + tempc); if (cpu_state.abrt) return 1; \
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setadc ## flag_width(dst, src); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
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break; \
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case 0x18: /*SBB ea, #*/ \
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tempc = CF_SET() ? 1 : 0; \
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setea ## ea_width(dst - (src + tempc)); if (abrt) return 1; \
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setea ## ea_width(dst - (src + tempc)); if (cpu_state.abrt) return 1; \
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setsbc ## flag_width(dst, src); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
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break; \
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case 0x20: /*AND ea, #*/ \
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dst &= src; \
|
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setea ## ea_width(dst); if (abrt) return 1; \
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||||
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 1; \
|
||||
setea ## ea_width(dst - src); if (cpu_state.abrt) return 1; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
@@ -546,7 +543,7 @@ static int op80_a16(uint32_t fetchdat)
|
||||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
@@ -556,7 +553,7 @@ static int op80_a32(uint32_t fetchdat)
|
||||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
@@ -566,7 +563,7 @@ static int op81_w_a16(uint32_t fetchdat)
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
@@ -576,7 +573,7 @@ static int op81_w_a32(uint32_t fetchdat)
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
@@ -586,7 +583,7 @@ static int op81_l_a16(uint32_t fetchdat)
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
@@ -596,7 +593,7 @@ static int op81_l_a32(uint32_t fetchdat)
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
@@ -607,7 +604,7 @@ static int op83_w_a16(uint32_t fetchdat)
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
@@ -618,7 +615,7 @@ static int op83_w_a32(uint32_t fetchdat)
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
@@ -630,7 +627,7 @@ static int op83_l_a16(uint32_t fetchdat)
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
@@ -641,7 +638,7 @@ static int op83_l_a32(uint32_t fetchdat)
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user