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Split off the AMD SYSCALL and SYSRET instructions to x86_ops_amd.h;

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Moved the two 440FX board along with the Pentium Pro and Pentium II CPU's to the Dev branch;
Applied the PCem commit that fixed PIIX IDE Bus Master initialization.
This commit is contained in:
OBattler
2018-01-01 02:57:39 +01:00
parent a8be9c22e9
commit 23c536f5dd
12 changed files with 336 additions and 219 deletions
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184
src/cpu/x86_ops_i686.h
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@@ -8,18 +8,20 @@
*
* x86 i686 (Pentium Pro/Pentium II) CPU Instructions.
*
* Version: @(#)x86_ops_i686.h 1.0.0 2017/05/30
* Version: @(#)x86_ops_i686.h 1.0.1 2018/01/01
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2017 Miran Grca.
* Copyright 2016-2018 Miran Grca.
*/
#ifndef internal_illegal
static int internal_illegal(char *s)
{
cpu_state.pc = cpu_state.oldpc;
x86gpf(s, 0);
return cpu_state.abrt;
}
#endif
/* 0 = Limit 0-15
1 = Base 0-15
@@ -513,181 +515,3 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
return cpu_state.abrt;
}
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
/* 0F 05 */
static int opSYSCALL(uint32_t fetchdat)
{
uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
if (!(cr0 & 1)) return internal_illegal("SYSCALL: CPU not in protected mode");
if (!AMD_SYSCALL_SB) return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
/* Set VM, IF, RF to 0. */
/* eflags &= ~0x00030200;
flags &= ~0x0200; */
/* Let's do this by the AMD spec. */
ECX = cpu_state.pc;
cpu_state.pc = AMD_SYSCALL_EIP;
eflags &= ~0x0002;
flags &= ~0x0200;
/* CS */
_cs.seg = AMD_SYSCALL_SB & ~7;
if (cs_msr & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",cs_msr,ldt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",cs_msr,gdt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
syscall_cs_seg_data[0] = 0xFFFF;
syscall_cs_seg_data[1] = 0;
syscall_cs_seg_data[2] = 0x9B00;
syscall_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSCALL_SB & ~3) | 0;
do_seg_load(&_cs, syscall_cs_seg_data);
use32 = 0x300;
CS = (CS & 0xFFFC) | 0;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
syscall_ss_seg_data[0] = 0xFFFF;
syscall_ss_seg_data[1] = 0;
syscall_ss_seg_data[2] = 0x9300;
syscall_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, syscall_ss_seg_data);
_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
cpu_state.pc = eip_msr;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
/* pclog("SYSCALL completed:\n");
pclog("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, _cs.base, _cs.limit, _cs.access, _cs.seg, _cs.limit_low, _cs.limit_high, _cs.checked);
pclog("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, _ss.base, _ss.limit, _ss.access, _ss.seg, _ss.limit_low, _ss.limit_high, _ss.checked);
pclog("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
pclog("Other information: eflags=%04X flags=%04X use32=%04X stack32=%i\n", eflags, flags, use32, stack32); */
return 0;
}
/* 0F 07 */
static int opSYSRET(uint32_t fetchdat)
{
uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
if (!cs_msr) return internal_illegal("SYSRET: CS MSR is zero");
if (!(cr0 & 1)) return internal_illegal("SYSRET: CPU not in protected mode");
cpu_state.pc = ECX;
eflags |= (1 << 1);
/* CS */
_cs.seg = AMD_SYSRET_SB & ~7;
if (cs_msr & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",cs_msr,ldt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",cs_msr,gdt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
sysret_cs_seg_data[0] = 0xFFFF;
sysret_cs_seg_data[1] = 0;
sysret_cs_seg_data[2] = 0xFB00;
sysret_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSRET_SB & ~3) | 3;
do_seg_load(&_cs, sysret_cs_seg_data);
flushmmucache_cr3();
use32 = 0x300;
CS = (CS & 0xFFFC) | 3;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
sysret_ss_seg_data[0] = 0xFFFF;
sysret_ss_seg_data[1] = 0;
sysret_ss_seg_data[2] = 0xF300;
sysret_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, sysret_ss_seg_data);
_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
/* pclog("SYSRET completed:\n");
pclog("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, _cs.base, _cs.limit, _cs.access, _cs.seg, _cs.limit_low, _cs.limit_high, _cs.checked);
pclog("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, _ss.base, _ss.limit, _ss.access, _ss.seg, _ss.limit_low, _ss.limit_high, _ss.checked);
pclog("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
pclog("Other information: eflags=%04X flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", eflags, flags, use32, stack32, ECX, EDX); */
return 0;
}