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Split off the AMD SYSCALL and SYSRET instructions to x86_ops_amd.h;

Browse Source 
Moved the two 440FX board along with the Pentium Pro and Pentium II CPU's to the Dev branch;
Applied the PCem commit that fixed PIIX IDE Bus Master initialization.
This commit is contained in:
OBattler
2018-01-01 02:57:39 +01:00
parent a8be9c22e9
commit 23c536f5dd
12 changed files with 336 additions and 219 deletions
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17
src/cpu/386_ops.h
View File

@@ -8,14 +8,14 @@
*
* 286/386+ instruction handlers list.
*
* Version: @(#)386_ops.h 1.0.0 2017/05/30
* Version: @(#)386_ops.h 1.0.1 2018/01/01
*
* Author: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 leilei.
* Copyright 2016-2017 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 leilei.
* Copyright 2016-2018 Miran Grca.
*/
#include "x86_ops.h"
@@ -148,6 +148,7 @@ static int ILLEGAL(uint32_t fetchdat)
}
#include "x86seg.h"
#include "x86_ops_amd.h"
#include "x86_ops_arith.h"
#include "x86_ops_atomic.h"
#include "x86_ops_bcd.h"
@@ -162,7 +163,11 @@ static int ILLEGAL(uint32_t fetchdat)
#include "x86_ops_jump.h"
#include "x86_ops_misc.h"
#include "x87_ops.h"
#ifdef DEV_BRANCH
#ifdef USE_I686
#include "x86_ops_i686.h"
#endif
#endif
#include "x86_ops_mmx.h"
#include "x86_ops_mmx_arith.h"
#include "x86_ops_mmx_cmp.h"
@@ -955,6 +960,8 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
/*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL,
};
#ifdef DEV_BRANCH
#ifdef USE_I686
OpFn OP_TABLE(pentiumpro_0f)[1024] =
{
/*16-bit data, 16-bit addr*/
@@ -1229,6 +1236,8 @@ OpFn OP_TABLE(pentium2d_0f)[1024] =
/*e0*/ ILLEGAL, opPSRAW_a32, opPSRAD_a32, ILLEGAL, ILLEGAL, opPMULHW_a32, ILLEGAL, ILLEGAL, opPSUBSB_a32, opPSUBSW_a32, NULL, opPOR_a32, opPADDSB_a32, opPADDSW_a32, NULL, opPXOR_a32,
/*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL,
};
#endif
#endif
OpFn OP_TABLE(286)[1024] =
{

28
src/cpu/cpu.c
View File

@@ -8,15 +8,15 @@
*
* CPU type handler.
*
* Version: @(#)cpu.c 1.0.8 2017/11/27
* Version: @(#)cpu.c 1.0.9 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 leilei.
* Copyright 2016,2017 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 leilei.
* Copyright 2016,2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
@@ -127,6 +127,8 @@ uint64_t pmc[2] = {0, 0};
uint16_t temp_seg_data[4] = {0, 0, 0, 0};
#ifdef DEV_BRANCH
#ifdef USE_I686
uint16_t cs_msr = 0;
uint32_t esp_msr = 0;
uint32_t eip_msr = 0;
@@ -151,6 +153,8 @@ uint64_t ecx186_msr = 0;
uint64_t ecx187_msr = 0;
uint64_t ecx1e0_msr = 0;
uint64_t ecx570_msr = 0;
#endif
#endif
/* AMD K5 and K6 MSR's. */
uint64_t ecx83_msr = 0;
@@ -1117,6 +1121,8 @@ void cpu_set()
#endif
break;
#ifdef DEV_BRANCH
#ifdef USE_I686
case CPU_PENTIUMPRO:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentiumpro_0f, dynarec_ops_386, dynarec_ops_pentiumpro_0f);
@@ -1238,6 +1244,8 @@ void cpu_set()
codegen_timing_set(&codegen_timing_686);
#endif
break;
#endif
#endif
default:
fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
@@ -1610,6 +1618,8 @@ void cpu_CPUID()
EAX = 0;
break;
#ifdef DEV_BRANCH
#ifdef USE_I686
case CPU_PENTIUMPRO:
if (!EAX)
{
@@ -1678,6 +1688,8 @@ void cpu_CPUID()
else
EAX = 0;
break;
#endif
#endif
}
}
@@ -1774,6 +1786,8 @@ void cpu_RDMSR()
}
break;
#ifdef DEV_BRANCH
#ifdef USE_I686
case CPU_PENTIUMPRO:
case CPU_PENTIUM2D:
EAX = EDX = 0;
@@ -1899,6 +1913,8 @@ i686_invalid_rdmsr:
break;
}
break;
#endif
#endif
}
}
@@ -1981,6 +1997,8 @@ void cpu_WRMSR()
}
break;
#ifdef DEV_BRANCH
#ifdef USE_I686
case CPU_PENTIUMPRO:
case CPU_PENTIUM2D:
switch (ECX)
@@ -2074,6 +2092,8 @@ i686_invalid_wrmsr:
break;
}
break;
#endif
#endif
}
}

16
src/cpu/cpu.h
View File

@@ -8,15 +8,15 @@
*
* CPU type handler.
*
* Version: @(#)cpu.h 1.0.4 2017/11/27
* Version: @(#)cpu.h 1.0.5 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 leilei.
* Copyright 2016,2017 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 leilei.
* Copyright 2016,2018 Miran Grca.
*/
#ifndef EMU_CPU_H
# define EMU_CPU_H
@@ -48,6 +48,8 @@
#define CPU_K5 23
#define CPU_5K86 24
#define CPU_K6 25
#ifdef DEV_BRANCH
#ifdef USE_I686
#define CPU_PENTIUMPRO 26 /* 686 class CPUs */
#if 0
# define CPU_PENTIUM2 27
@@ -55,6 +57,8 @@
#else
# define CPU_PENTIUM2D 27
#endif
#endif
#endif
#define MANU_INTEL 0
#define MANU_AMD 1
@@ -100,9 +104,13 @@ extern CPU cpus_K5[];
extern CPU cpus_K56[];
extern CPU cpus_Pentium[];
extern CPU cpus_6x86[];
#ifdef DEV_BRANCH
#ifdef USE_I686
extern CPU cpus_PentiumPro[];
extern CPU cpus_Pentium2[];
extern CPU cpus_Pentium2D[];
#endif
#endif
#define C_FLAG 0x0001

8
src/cpu/x86_ops.h
View File

@@ -50,8 +50,12 @@ extern OpFn dynarec_ops_c6x86mx_0f[1024];
extern OpFn dynarec_ops_k6_0f[1024];
#ifdef DEV_BRANCH
#ifdef USE_I686
extern OpFn dynarec_ops_pentiumpro_0f[1024];
extern OpFn dynarec_ops_pentium2d_0f[1024];
#endif
#endif
extern OpFn dynarec_ops_fpu_287_d9_a16[256];
extern OpFn dynarec_ops_fpu_287_d9_a32[256];
@@ -138,8 +142,12 @@ extern OpFn ops_c6x86mx_0f[1024];
extern OpFn ops_k6_0f[1024];
#ifdef DEV_BRANCH
#ifdef USE_I686
extern OpFn ops_pentiumpro_0f[1024];
extern OpFn ops_pentium2d_0f[1024];
#endif
#endif
extern OpFn ops_fpu_287_d9_a16[256];
extern OpFn ops_fpu_287_d9_a32[256];

201
src/cpu/x86_ops_amd.h Normal file
View File

@@ -0,0 +1,201 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* AMD SYSCALL and SYSRET CPU Instructions.
*
* Version: @(#)x86_ops_amd.h 1.0.0 2018/01/01
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2018 Miran Grca.
*/
#ifndef internal_illegal
static int internal_illegal(char *s)
{
cpu_state.pc = cpu_state.oldpc;
x86gpf(s, 0);
return cpu_state.abrt;
}
#endif
/* 0 = Limit 0-15
1 = Base 0-15
2 = Base 16-23 (bits 0-7), Access rights
8-11 Type
12 S
13, 14 DPL
15 P
3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
4 A
6 DB
7 G */
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
/* 0F 05 */
static int opSYSCALL(uint32_t fetchdat)
{
uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
if (!(cr0 & 1)) return internal_illegal("SYSCALL: CPU not in protected mode");
if (!AMD_SYSCALL_SB) return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
/* Set VM, IF, RF to 0. */
/* eflags &= ~0x00030200;
flags &= ~0x0200; */
/* Let's do this by the AMD spec. */
ECX = cpu_state.pc;
eflags &= ~0x0002;
flags &= ~0x0200;
/* CS */
_cs.seg = AMD_SYSCALL_SB & ~7;
if (AMD_SYSCALL_SB & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",AMD_SYSCALL_SB,ldt.limit);
x86gpf(NULL, AMD_SYSCALL_SB & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",AMD_SYSCALL_SB,gdt.limit);
x86gpf(NULL, AMD_SYSCALL_SB & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
syscall_cs_seg_data[0] = 0xFFFF;
syscall_cs_seg_data[1] = 0;
syscall_cs_seg_data[2] = 0x9B00;
syscall_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSCALL_SB & ~3) | 0;
do_seg_load(&_cs, syscall_cs_seg_data);
use32 = 0x300;
CS = (CS & 0xFFFC) | 0;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
syscall_ss_seg_data[0] = 0xFFFF;
syscall_ss_seg_data[1] = 0;
syscall_ss_seg_data[2] = 0x9300;
syscall_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, syscall_ss_seg_data);
_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
cpu_state.pc = AMD_SYSCALL_EIP;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
return 0;
}
/* 0F 07 */
static int opSYSRET(uint32_t fetchdat)
{
uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
if (!AMD_SYSRET_SB) return internal_illegal("SYSRET: CS MSR is zero");
if (!(cr0 & 1)) return internal_illegal("SYSRET: CPU not in protected mode");
cpu_state.pc = ECX;
eflags |= (1 << 1);
/* CS */
_cs.seg = AMD_SYSRET_SB & ~7;
if (AMD_SYSRET_SB & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",AMD_SYSRET_SB,ldt.limit);
x86gpf(NULL, AMD_SYSRET_SB & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",AMD_SYSRET_SB,gdt.limit);
x86gpf(NULL, AMD_SYSRET_SB & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
sysret_cs_seg_data[0] = 0xFFFF;
sysret_cs_seg_data[1] = 0;
sysret_cs_seg_data[2] = 0xFB00;
sysret_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSRET_SB & ~3) | 3;
do_seg_load(&_cs, sysret_cs_seg_data);
flushmmucache_cr3();
use32 = 0x300;
CS = (CS & 0xFFFC) | 3;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
sysret_ss_seg_data[0] = 0xFFFF;
sysret_ss_seg_data[1] = 0;
sysret_ss_seg_data[2] = 0xF300;
sysret_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, sysret_ss_seg_data);
_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
return 0;
}

184
src/cpu/x86_ops_i686.h
View File

@@ -8,18 +8,20 @@
*
* x86 i686 (Pentium Pro/Pentium II) CPU Instructions.
*
* Version: @(#)x86_ops_i686.h 1.0.0 2017/05/30
* Version: @(#)x86_ops_i686.h 1.0.1 2018/01/01
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2017 Miran Grca.
* Copyright 2016-2018 Miran Grca.
*/
#ifndef internal_illegal
static int internal_illegal(char *s)
{
cpu_state.pc = cpu_state.oldpc;
x86gpf(s, 0);
return cpu_state.abrt;
}
#endif
/* 0 = Limit 0-15
1 = Base 0-15
@@ -513,181 +515,3 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
return cpu_state.abrt;
}
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
/* 0F 05 */
static int opSYSCALL(uint32_t fetchdat)
{
uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
if (!(cr0 & 1)) return internal_illegal("SYSCALL: CPU not in protected mode");
if (!AMD_SYSCALL_SB) return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
/* Set VM, IF, RF to 0. */
/* eflags &= ~0x00030200;
flags &= ~0x0200; */
/* Let's do this by the AMD spec. */
ECX = cpu_state.pc;
cpu_state.pc = AMD_SYSCALL_EIP;
eflags &= ~0x0002;
flags &= ~0x0200;
/* CS */
_cs.seg = AMD_SYSCALL_SB & ~7;
if (cs_msr & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",cs_msr,ldt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",cs_msr,gdt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
syscall_cs_seg_data[0] = 0xFFFF;
syscall_cs_seg_data[1] = 0;
syscall_cs_seg_data[2] = 0x9B00;
syscall_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSCALL_SB & ~3) | 0;
do_seg_load(&_cs, syscall_cs_seg_data);
use32 = 0x300;
CS = (CS & 0xFFFC) | 0;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
syscall_ss_seg_data[0] = 0xFFFF;
syscall_ss_seg_data[1] = 0;
syscall_ss_seg_data[2] = 0x9300;
syscall_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, syscall_ss_seg_data);
_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
cpu_state.pc = eip_msr;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
/* pclog("SYSCALL completed:\n");
pclog("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, _cs.base, _cs.limit, _cs.access, _cs.seg, _cs.limit_low, _cs.limit_high, _cs.checked);
pclog("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, _ss.base, _ss.limit, _ss.access, _ss.seg, _ss.limit_low, _ss.limit_high, _ss.checked);
pclog("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
pclog("Other information: eflags=%04X flags=%04X use32=%04X stack32=%i\n", eflags, flags, use32, stack32); */
return 0;
}
/* 0F 07 */
static int opSYSRET(uint32_t fetchdat)
{
uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
if (!cs_msr) return internal_illegal("SYSRET: CS MSR is zero");
if (!(cr0 & 1)) return internal_illegal("SYSRET: CPU not in protected mode");
cpu_state.pc = ECX;
eflags |= (1 << 1);
/* CS */
_cs.seg = AMD_SYSRET_SB & ~7;
if (cs_msr & 4)
{
if (_cs.seg >= ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X CS\n",cs_msr,ldt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg +=ldt.base;
}
else
{
if (_cs.seg >= gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X CS\n",cs_msr,gdt.limit);
x86gpf(NULL, cs_msr & ~3);
return 1;
}
_cs.seg += gdt.base;
}
cpl_override = 1;
sysret_cs_seg_data[0] = 0xFFFF;
sysret_cs_seg_data[1] = 0;
sysret_cs_seg_data[2] = 0xFB00;
sysret_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSRET_SB & ~3) | 3;
do_seg_load(&_cs, sysret_cs_seg_data);
flushmmucache_cr3();
use32 = 0x300;
CS = (CS & 0xFFFC) | 3;
_cs.limit = 0xFFFFFFFF;
_cs.limit_high = 0xFFFFFFFF;
/* SS */
sysret_ss_seg_data[0] = 0xFFFF;
sysret_ss_seg_data[1] = 0;
sysret_ss_seg_data[2] = 0xF300;
sysret_ss_seg_data[3] = 0xC0;
do_seg_load(&_ss, sysret_ss_seg_data);
_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
stack32 = 1;
_ss.limit = 0xFFFFFFFF;
_ss.limit_high = 0xFFFFFFFF;
_ss.checked = 0;
CLOCK_CYCLES(20);
CPU_BLOCK_END();
/* pclog("SYSRET completed:\n");
pclog("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, _cs.base, _cs.limit, _cs.access, _cs.seg, _cs.limit_low, _cs.limit_high, _cs.checked);
pclog("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, _ss.base, _ss.limit, _ss.access, _ss.seg, _ss.limit_low, _ss.limit_high, _ss.checked);
pclog("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
pclog("Other information: eflags=%04X flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", eflags, flags, use32, stack32, ECX, EDX); */
return 0;
}

7
src/disk/hdc_ide.c
View File

@@ -9,13 +9,13 @@
* Implementation of the IDE emulation for hard disks and ATAPI
* CD-ROM devices.
*
* Version: @(#)hdc_ide.c 1.0.22 2017/12/15
* Version: @(#)hdc_ide.c 1.0.23 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016,2018 Miran Grca.
*/
#define __USE_LARGEFILE64
#define _LARGEFILE_SOURCE
@@ -2391,7 +2391,6 @@ void ide_init(void)
{
ide_pri_enable();
ide_sec_enable();
ide_bus_master_read = ide_bus_master_write = NULL;
timer_add(ide_callback_pri, &idecallback[0], &idecallback[0], NULL);
timer_add(ide_callback_sec, &idecallback[1], &idecallback[1], NULL);

13
src/machine/machine.c
View File

@@ -8,21 +8,22 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.c 1.0.27 2017/11/08
* Version: @(#)machine.c 1.0.28 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
* Copyright 2017 Fred N. van Kempen.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016,2018 Miran Grca.
* Copyright 2018 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../dma.h"
#include "../pic.h"
#include "../pit.h"
@@ -33,6 +34,8 @@
#include "../floppy/floppy.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "machine.h"
@@ -46,6 +49,8 @@ machine_init(void)
{
pclog("Initializing as \"%s\"\n", machine_getname());
ide_set_bus_master(NULL, NULL, NULL);
/* Set up the architecture flags. */
AT = IS_ARCH(machine, MACHINE_AT);
PCI = IS_ARCH(machine, MACHINE_PCI);

26
src/machine/machine_table.c
View File

@@ -11,15 +11,15 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.9 2017/12/31
* Version: @(#)machine_table.c 1.0.10 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
* Copyright 2017 Fred N. van Kempen.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016,2018 Miran Grca.
* Copyright 2018 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdint.h>
@@ -62,8 +62,10 @@ machine_t machines[] = {
{ "[286 ISA] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL, nvr_at_close },
{ "[286 ISA] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL, nvr_at_close },
{ "[286 ISA] Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_compaq_init, NULL, nvr_at_close },
#ifdef PORTABLE3
#ifdef DEV_BRANCH
#ifdef USE_PORTABLE3
{ "[286 ISA] Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_compaq_init, NULL, nvr_at_close },
#endif
#endif
{ "[286 ISA] Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL, nvr_at_close },
{ "[286 ISA] IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_top_remap_init, NULL, nvr_at_close },
@@ -91,8 +93,10 @@ machine_t machines[] = {
{ "[386DX ISA] Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 16, 1, 127, machine_at_wd76c10_init, NULL, nvr_at_close },
{ "[386DX ISA] Award 386DX clone", ROM_AWARD386DX_OPTI495, "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL, nvr_at_close },
{ "[386DX ISA] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL, nvr_at_close },
#ifdef PORTABLE3
#ifdef DEV_BRANCH
#ifdef USE_PORTABLE3
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_compaq_init, NULL, nvr_at_close },
#endif
#endif
{ "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 12, 1, 63, machine_ps2_model_80_init, NULL, nvr_at_close },
@@ -109,10 +113,12 @@ machine_t machines[] = {
{ "[486 PCI] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL, nvr_at_close },
#ifdef GREENB
#ifdef DEV_BRANCH
#ifdef USE_GREENB
{ "[486 VLB] Green-B 4GP V3.1", ROM_4GPV31, "4gpv31", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 128, 1, 127, machine_at_4gpv31_init, NULL, nvr_at_close },
#endif
#endif
{ "[Socket 4 LX] Intel Premiere/PCI", ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL, nvr_at_close },
{ "[Socket 5 NX] Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL, nvr_at_close },
@@ -136,8 +142,12 @@ machine_t machines[] = {
{ "[Socket 7 VX] Award 430VX PCI", ROM_430VX, "430vx", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL, nvr_at_close },
{ "[Socket 7 VX] Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL, nvr_at_close },
#ifdef DEV_BRANCH
#ifdef USE_I686
{ "[Socket 8 FX] Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL, nvr_at_close },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL, nvr_at_close },
#endif
#endif
{ "", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0,0, 0 }
};

12
src/rom.c
View File

@@ -13,15 +13,15 @@
* - c386sx16 BIOS fails checksum
* - the loadfont() calls should be done elsewhere
*
* Version: @(#)rom.c 1.0.24 2017/12/31
* Version: @(#)rom.c 1.0.25 2018/01/01
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
* Copyright 2017 Fred N. van Kempen.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
* Copyright 2018 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdint.h>
@@ -741,6 +741,8 @@ rom_load_bios(int rom_id)
biosmask = 0x1ffff;
return(1);
#ifdef DEV_BRANCH
#ifdef USE_I686
case ROM_440FX: /* working Tyan BIOS */
if (! rom_load_linear(
L"roms/machines/440fx/ntmaw501.bin",
@@ -754,6 +756,8 @@ rom_load_bios(int rom_id)
0x000000, 131072, 0, rom)) break;
biosmask = 0x1ffff;
return(1);
#endif
#endif
case ROM_THOR:
if (! rom_load_linear(

24
src/rom.h
View File

@@ -8,10 +8,10 @@
*
* Definitions for the ROM image handler.
*
* Version: @(#)rom.h 1.0.10 2017/12/31
* Version: @(#)rom.h 1.0.11 2018/01/01
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
* Copyright 2017 Fred N. van Kempen.
* Copyright 2018 Fred N. van Kempen.
*/
#ifndef EMU_ROM_H
# define EMU_ROM_H
@@ -72,14 +72,18 @@ enum {
ROM_REVENGE,
ROM_IBMPS1_2011,
ROM_IBMXT286,
#ifdef PORTABLE3
#ifdef DEV_BRANCH
#ifdef USE_PORTABLE3
ROM_DESKPRO_386,
#endif
#endif
ROM_PORTABLE,
ROM_PORTABLEII,
#ifdef PORTABLE3
#ifdef DEV_BRANCH
#ifdef USE_PORTABLE3
ROM_PORTABLEIII,
ROM_PORTABLEIII386,
#endif
#endif
ROM_IBMPS1_2121,
@@ -112,7 +116,11 @@ enum {
ROM_POWERMATE_V, /* NEC PowerMate V/430FX/Phoenix/SMC FDC37C66 5*/ /* 68 */
#endif
#ifdef DEV_BRANCH
#ifdef USE_I686
ROM_440FX, /* Tyan Titan-Pro AT/440FX/Award BIOS/SMC FDC37C665 */
#endif
#endif
ROM_IBMPS1_2121_ISA,/* IBM PS/1 Model 2121 with ISA expansion bus */
@@ -126,7 +134,11 @@ enum {
ROM_MEGAPCDX, /* 386DX mdl - Note: documentation (in German) clearly says such a model exists */
ROM_ZAPPA, /* Intel Advanced_ZP/430FX/AMI/NS PC87306 */
#ifdef DEV_BRANCH
#ifdef USE_I686
ROM_S1668, /* Tyan Titan-Pro ATX/440FX/AMI/SMC FDC37C669 */
#endif
#endif
ROM_IBMPS1_2133,
ROM_PRESIDENT, /* President Award 430FX PCI/430FX/Award/Unknown SIO */
@@ -134,9 +146,11 @@ enum {
ROM_IBMPS2_M80_486,
#endif
#ifdef GREENB
#ifdef DEV_BRANCH
#ifdef USE_GREENB
ROM_4GPV31, /* Green-B 4GPV3.1 ISA/VLB 486/Pentium, AMI */
#endif
#endif
#ifdef WALTJE
ROM_OPENAT, /* PC/AT clone with Open BIOS */

19
src/win/Makefile.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Win32 (MinGW32) environment.
#
# Version: @(#)Makefile.mingw 1.0.86 2017/12/29
# Version: @(#)Makefile.mingw 1.0.87 2018/01/01
#
# Authors: Miran Grca, <mgrca8@gmail.com>
# Fred N. van Kempen, <decwiz@yahoo.com>
@@ -68,6 +68,9 @@ endif
ifndef GREENB
GREENB := n
endif
ifndef I686
I686 := n
endif
ifndef NE1000
NE1000 := n
endif
@@ -304,6 +307,15 @@ OPTS += -DUSE_CIRRUS
DEVBROBJ += vid_cl_gd.o vid_cl_gd_blit.o vid_cl_ramdac.o
endif
ifeq ($(GREENB), y)
OPTS += -DUSE_GREENB
endif
ifeq ($(I686), y)
OPTS += -DUSE_I686
DEVBROBJ += m_at_440fx.o
endif
ifeq ($(NE1000), y)
OPTS += -DUSE_NE1000
endif
@@ -318,6 +330,10 @@ OPTS += -DUSE_PAS16
DEVBROBJ += snd_pas16.o
endif
ifeq ($(PORTABLE3), y)
OPTS += -DUSE_PORTABLE3
endif
endif
@@ -361,7 +377,6 @@ MCHOBJ := machine.o machine_table.o \
m_at_sis_85c471.o m_at_sis_85c496.o \
m_at_430lx_nx.o m_at_430fx.o \
m_at_430hx.o m_at_430vx.o \
m_at_440fx.o \
m_at_4gpv31.o \
m_pcjr.o m_ps1.o m_ps2_isa.o m_ps2_mca.o