Applied mainline PCem commit: Added code generation for RMW versions of ADD/SUB/OR/XOR/AND.
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@@ -1,6 +1,3 @@
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/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#define SHIFT(size, size2, count, res_store) \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \
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reg = LOAD_REG_ ## size(fetchdat & 7); \
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