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Applied mainline PCem commit: Added code generation for RMW versions of ADD/SUB/OR/XOR/AND.

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OBattler
2016-11-13 16:44:42 +01:00
parent 66ed552b16
commit 26a6b910db
18 changed files with 2136 additions and 212 deletions
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11
src/codegen_ops_xchg.h
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@@ -1,6 +1,3 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#define OP_XCHG_AX_(reg) \
static uint32_t ropXCHG_AX_ ## reg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
@@ -47,9 +44,9 @@ OP_XCHG_EAX_(EBP)
static uint32_t ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
// #ifdef __amd64__
// return 0;
// #else
#ifdef __amd64__
return 0;
#else
int src_reg, dst_reg, temp_reg;
if ((fetchdat & 0xc0) != 0xc0)
@@ -62,7 +59,7 @@ static uint32_t ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_REG_TARGET_B_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
// #endif
#endif
}
static uint32_t ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{