ACPI, SMM, and PIIX fixes, fixes quite a few boards, also fixed the Via Apollo series northbridge ID's, some CPU instructions on both 808x and 286+, and added SMM to 486's (Intel and AMD), WinChip and WinChip 2, and VIA Cyrix III, also removed the TC430HX and the Toshiba machine from the Dev branch.
This commit is contained in:
OBattler
139
src/acpi.c
139
src/acpi.c
@@ -61,16 +61,16 @@ acpi_update_irq(void *priv)
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acpi_t *dev = (acpi_t *) priv;
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int sci_level;
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sci_level = (dev->pmsts & dev->pmen) & (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN);
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sci_level = (dev->regs.pmsts & dev->regs.pmen) & (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN);
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if (sci_level) {
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if (dev->irq_mode == 1)
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pci_set_irq(dev->slot, dev->irq_pin);
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if (dev->regs.irq_mode == 1)
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pci_set_irq(dev->regs.slot, dev->regs.irq_pin);
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else
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picintlevel(1 << 9);
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} else {
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if (dev->irq_mode == 1)
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pci_clear_irq(dev->slot, dev->irq_pin);
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if (dev->regs.irq_mode == 1)
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pci_clear_irq(dev->regs.slot, dev->regs.irq_pin);
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else
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picintc(1 << 9);
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}
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@@ -91,82 +91,80 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
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switch (addr) {
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case 0x00: case 0x01:
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/* PMSTS - Power Management Status Register (IO) */
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ret = (dev->pmsts >> shift16) & 0xff;
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ret = (dev->regs.pmsts >> shift16) & 0xff;
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break;
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case 0x02: case 0x03:
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/* PMEN - Power Management Resume Enable Register (IO) */
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ret = (dev->pmen >> shift16) & 0xff;
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ret = (dev->regs.pmen >> shift16) & 0xff;
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break;
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case 0x04: case 0x05:
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/* PMCNTRL - Power Management Control Register (IO) */
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ret = (dev->pmcntrl >> shift16) & 0xff;
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ret = (dev->regs.pmcntrl >> shift16) & 0xff;
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break;
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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/* PMTMR - Power Management Timer Register (IO) */
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ret = (dev->timer_val >> shift32) & 0xff;
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ret = (dev->regs.timer_val >> shift32) & 0xff;
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break;
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case 0x0c: case 0x0d:
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/* GPSTS - General Purpose Status Register (IO) */
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ret = (dev->gpsts >> shift16) & 0xff;
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ret = (dev->regs.gpsts >> shift16) & 0xff;
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break;
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case 0x0e: case 0x0f:
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/* GPEN - General Purpose Enable Register (IO) */
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ret = (dev->gpen >> shift16) & 0xff;
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ret = (dev->regs.gpen >> shift16) & 0xff;
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break;
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case 0x10: case 0x11: case 0x12: case 0x13:
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/* PCNTRL - Processor Control Register (IO) */
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ret = (dev->pcntrl >> shift32) & 0xff;
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ret = (dev->regs.pcntrl >> shift32) & 0xff;
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break;
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case 0x14:
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/* PLVL2 - Processor Level 2 Register (IO) */
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if (size == 1)
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ret = dev->plvl2;
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ret = dev->regs.plvl2;
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break;
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case 0x15:
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/* PLVL3 - Processor Level 3 Register (IO) */
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if (size == 1)
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ret = dev->plvl3;
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ret = dev->regs.plvl3;
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break;
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case 0x18: case 0x19:
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/* GLBSTS - Global Status Register (IO) */
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ret = (dev->glbsts >> shift16) & 0xff;
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ret = (dev->regs.glbsts >> shift16) & 0xff;
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if (addr == 0x18) {
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ret &= 0x05;
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if (dev->gpsts != 0x0000)
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ret &= 0x25;
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if (dev->regs.gpsts != 0x0000)
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ret |= 0x80;
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if (dev->pmsts != 0x0000)
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if (dev->regs.pmsts != 0x0000)
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ret |= 0x40;
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if (in_smm)
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ret |= 0x20;
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if (dev->devsts != 0x00000000)
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if (dev->regs.devsts != 0x00000000)
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ret |= 0x10;
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}
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break;
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case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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/* DEVSTS - Device Status Register (IO) */
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ret = ((dev->devsts | 0x10000000) >> shift32) & 0xff;
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ret = (dev->regs.devsts >> shift32) & 0xff;
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break;
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case 0x20: case 0x21:
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/* GLBEN - Global Enable Register (IO) */
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ret = (dev->glben >> shift16) & 0xff;
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ret = (dev->regs.glben >> shift16) & 0xff;
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break;
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case 0x28: case 0x29: case 0x2a: case 0x2b:
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/* GLBCTL - Global Control Register (IO) */
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ret = (dev->glbctl >> shift32) & 0xff;
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ret = (dev->regs.glbctl >> shift32) & 0xff;
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break;
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case 0x2c: case 0x2d: case 0x2e: case 0x2f:
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/* DEVCTL - Device Control Register (IO) */
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ret = (dev->devctl >> shift32) & 0xff;
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ret = (dev->regs.devctl >> shift32) & 0xff;
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break;
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case 0x30: case 0x31: case 0x32:
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/* GPIREG - General Purpose Input Register (IO) */
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if (size == 1)
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ret = dev->gpireg[addr & 3];
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ret = dev->regs.gpireg[addr & 3];
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break;
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case 0x34: case 0x35: case 0x36: case 0x37:
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/* GPOREG - General Purpose Output Register (IO) */
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if (size == 1)
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ret = dev->gporeg[addr & 3];
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ret = dev->regs.gporeg[addr & 3];
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break;
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}
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@@ -190,19 +188,19 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
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switch (addr) {
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case 0x00: case 0x01:
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/* PMSTS - Power Management Status Register (IO) */
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dev->pmsts &= ~((val << shift16) & 0x8d31);
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dev->regs.pmsts &= ~((val << shift16) & 0x8d31);
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acpi_update_irq(dev);
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break;
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case 0x02: case 0x03:
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/* PMEN - Power Management Resume Enable Register (IO) */
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dev->pmen = ((dev->pmen & ~(0xff << shift16)) | (val << shift16)) & 0x0521;
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dev->regs.pmen = ((dev->regs.pmen & ~(0xff << shift16)) | (val << shift16)) & 0x0521;
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acpi_update_irq(dev);
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break;
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case 0x04: case 0x05:
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/* PMCNTRL - Power Management Control Register (IO) */
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dev->pmcntrl = ((dev->pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
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if (dev->pmcntrl & 0x2000) {
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sus_typ = (dev->pmcntrl >> 10) & 7;
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dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
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if (dev->regs.pmcntrl & 0x2000) {
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sus_typ = (dev->regs.pmcntrl >> 10) & 7;
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switch (sus_typ) {
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case 0:
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/* Soft power off. */
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@@ -232,51 +230,51 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
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break;
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case 0x0c: case 0x0d:
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/* GPSTS - General Purpose Status Register (IO) */
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dev->gpsts &= ~((val << shift16) & 0x0f81);
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dev->regs.gpsts &= ~((val << shift16) & 0x0f81);
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break;
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case 0x0e: case 0x0f:
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/* GPEN - General Purpose Enable Register (IO) */
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dev->gpen = ((dev->gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0f01;
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dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0f01;
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break;
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case 0x10: case 0x11: case 0x12: case 0x13:
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/* PCNTRL - Processor Control Register (IO) */
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dev->pcntrl = ((dev->pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00023e1e;
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dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00023e1e;
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break;
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case 0x14:
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/* PLVL2 - Processor Level 2 Register (IO) */
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if (size == 1)
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dev->plvl2 = val;
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dev->regs.plvl2 = val;
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break;
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case 0x15:
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/* PLVL3 - Processor Level 3 Register (IO) */
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if (size == 1)
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dev->plvl3 = val;
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dev->regs.plvl3 = val;
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break;
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case 0x18: case 0x19:
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/* GLBSTS - Global Status Register (IO) */
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dev->glbsts &= ~((val << shift16) & 0x0df7);
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dev->regs.glbsts &= ~((val << shift16) & 0x0df7);
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break;
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case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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/* DEVSTS - Device Status Register (IO) */
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dev->devsts &= ~((val << shift32) & 0x3fff0fff);
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dev->regs.devsts &= ~((val << shift32) & 0x3fff0fff);
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break;
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case 0x20: case 0x21:
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/* GLBEN - Global Enable Register (IO) */
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dev->glben = ((dev->glben & ~(0xff << shift16)) | (val << shift16)) & 0x8d1f;
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dev->regs.glben = ((dev->regs.glben & ~(0xff << shift16)) | (val << shift16)) & 0x8d1f;
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break;
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case 0x28: case 0x29: case 0x2a: case 0x2b:
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/* GLBCTL - Global Control Register (IO) */
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// dev->glbctl = ((dev->glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
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dev->glbctl = ((dev->glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0700ff07;
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// dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
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dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0700ff07;
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break;
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case 0x2c: case 0x2d: case 0x2e: case 0x2f:
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/* DEVCTL - Device Control Register (IO) */
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dev->devctl = ((dev->devctl & ~(0xff << shift32)) | (val << shift32)) & 0x0fffffff;
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dev->regs.devctl = ((dev->regs.devctl & ~(0xff << shift32)) | (val << shift32)) & 0x0fffffff;
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break;
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case 0x34: case 0x35: case 0x36: case 0x37:
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/* GPOREG - General Purpose Output Register (IO) */
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if (size == 1)
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dev->gporeg[addr & 3] = val;
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dev->regs.gporeg[addr & 3] = val;
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break;
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}
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}
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@@ -351,16 +349,16 @@ acpi_reg_write(uint16_t addr, uint8_t val, void *p)
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void
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acpi_update_io_mapping(acpi_t *dev, uint32_t base, int chipset_en)
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{
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if (dev->io_base != 0x0000) {
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io_removehandler(dev->io_base, 0x40,
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if (dev->regs.io_base != 0x0000) {
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io_removehandler(dev->regs.io_base, 0x40,
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acpi_reg_read, acpi_reg_readw, acpi_reg_readl,
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acpi_reg_write, acpi_reg_writew, acpi_reg_writel, dev);
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}
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dev->io_base = base;
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dev->regs.io_base = base;
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if (chipset_en && (dev->io_base != 0x0000)) {
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io_sethandler(dev->io_base, 0x40,
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if (chipset_en && (dev->regs.io_base != 0x0000)) {
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io_sethandler(dev->regs.io_base, 0x40,
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acpi_reg_read, acpi_reg_readw, acpi_reg_readl,
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acpi_reg_write, acpi_reg_writew, acpi_reg_writel, dev);
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}
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@@ -374,18 +372,18 @@ acpi_timer_count(void *priv)
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int overflow;
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uint32_t old;
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old = dev->timer_val;
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dev->timer_val++;
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old = dev->regs.timer_val;
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dev->regs.timer_val++;
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if (dev->timer32)
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overflow = (old ^ dev->timer_val) & 0x80000000;
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if (dev->regs.timer32)
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overflow = (old ^ dev->regs.timer_val) & 0x80000000;
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else {
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dev->timer_val &= 0x00ffffff;
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overflow = (old ^ dev->timer_val) & 0x00800000;
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dev->regs.timer_val &= 0x00ffffff;
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overflow = (old ^ dev->regs.timer_val) & 0x00800000;
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}
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if (overflow) {
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dev->pmsts |= TMROF_EN;
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dev->regs.pmsts |= TMROF_EN;
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acpi_update_irq(dev);
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}
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@@ -396,42 +394,42 @@ acpi_timer_count(void *priv)
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void
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acpi_init_gporeg(acpi_t *dev, uint8_t val0, uint8_t val1, uint8_t val2, uint8_t val3)
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{
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dev->gporeg[0] = val0;
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dev->gporeg[1] = val1;
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dev->gporeg[2] = val2;
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dev->gporeg[3] = val3;
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acpi_log("acpi_init_gporeg(): %02X %02X %02X %02X\n", dev->gporeg[0], dev->gporeg[1], dev->gporeg[2], dev->gporeg[3]);
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dev->regs.gporeg[0] = dev->gporeg_default[0] = val0;
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dev->regs.gporeg[1] = dev->gporeg_default[1] = val1;
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dev->regs.gporeg[2] = dev->gporeg_default[2] = val2;
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dev->regs.gporeg[3] = dev->gporeg_default[3] = val3;
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acpi_log("acpi_init_gporeg(): %02X %02X %02X %02X\n", dev->regs.gporeg[0], dev->regs.gporeg[1], dev->regs.gporeg[2], dev->regs.gporeg[3]);
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}
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void
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acpi_set_timer32(acpi_t *dev, uint8_t timer32)
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{
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dev->timer32 = timer32;
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dev->regs.timer32 = timer32;
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if (!dev->timer32)
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dev->timer_val &= 0x00ffffff;
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if (!dev->regs.timer32)
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dev->regs.timer_val &= 0x00ffffff;
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}
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void
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acpi_set_slot(acpi_t *dev, int slot)
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{
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dev->slot = slot;
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dev->regs.slot = slot;
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}
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void
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acpi_set_irq_mode(acpi_t *dev, int irq_mode)
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{
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dev->irq_mode = irq_mode;
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dev->regs.irq_mode = irq_mode;
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}
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void
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acpi_set_irq_pin(acpi_t *dev, int irq_pin)
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{
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dev->irq_pin = irq_pin;
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dev->regs.irq_pin = irq_pin;
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}
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@@ -446,8 +444,11 @@ static void
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acpi_reset(void *priv)
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{
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acpi_t *dev = (acpi_t *) priv;
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int i;
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dev->timer_val = 0;
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memset(&dev->regs, 0x00, sizeof(acpi_regs_t));
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for (i = 0; i < 4; i++)
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dev->regs.gporeg[i] = dev->gporeg_default[i];
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}
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@@ -484,8 +485,6 @@ acpi_init(const device_t *info)
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timer_add(&dev->timer, acpi_timer_count, dev, 0);
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timer_set_delay_u64(&dev->timer, ACPICONST);
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dev->pmsts |= 0x0100;
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return dev;
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}
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Reference in New Issue
Block a user