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ACPI, SMM, and PIIX fixes, fixes quite a few boards, also fixed the Via Apollo series northbridge ID's, some CPU instructions on both 808x and 286+, and added SMM to 486's (Intel and AMD), WinChip and WinChip 2, and VIA Cyrix III, also removed the TC430HX and the Toshiba machine from the Dev branch.

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This commit is contained in:
OBattler
2020-04-16 21:56:19 +02:00
parent 08f52c5a29
commit 275dd5a2f7
36 changed files with 862 additions and 429 deletions
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42
src/cpu_common/x86_ops_atomic.h
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@@ -134,75 +134,81 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
static int opXADD_b_a16(uint32_t fetchdat)
{
uint8_t temp;
uint8_t temp, temp2;
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteab(); if (cpu_state.abrt) return 1;
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setadd8(temp, getr8(cpu_reg));
temp2 = getr8(cpu_reg);
setr8(cpu_reg, temp);
seteab(temp + temp2); if (cpu_state.abrt) return 1;
setadd8(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}
static int opXADD_b_a32(uint32_t fetchdat)
{
uint8_t temp;
uint8_t temp, temp2;
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteab(); if (cpu_state.abrt) return 1;
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setadd8(temp, getr8(cpu_reg));
temp2 = getr8(cpu_reg);
setr8(cpu_reg, temp);
seteab(temp + temp2); if (cpu_state.abrt) return 1;
setadd8(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}
static int opXADD_w_a16(uint32_t fetchdat)
{
uint16_t temp;
uint16_t temp, temp2;
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteaw(); if (cpu_state.abrt) return 1;
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
setadd16(temp, cpu_state.regs[cpu_reg].w);
temp2 = cpu_state.regs[cpu_reg].w;
cpu_state.regs[cpu_reg].w = temp;
seteaw(temp + temp2); if (cpu_state.abrt) return 1;
setadd16(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}
static int opXADD_w_a32(uint32_t fetchdat)
{
uint16_t temp;
uint16_t temp, temp2;
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteaw(); if (cpu_state.abrt) return 1;
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
setadd16(temp, cpu_state.regs[cpu_reg].w);
temp2 = cpu_state.regs[cpu_reg].w;
cpu_state.regs[cpu_reg].w = temp;
seteaw(temp + temp2); if (cpu_state.abrt) return 1;
setadd16(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}
static int opXADD_l_a16(uint32_t fetchdat)
{
uint32_t temp;
uint32_t temp, temp2;
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteal(); if (cpu_state.abrt) return 1;
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
setadd32(temp, cpu_state.regs[cpu_reg].l);
temp2 = cpu_state.regs[cpu_reg].l;
cpu_state.regs[cpu_reg].l = temp;
seteal(temp + temp2); if (cpu_state.abrt) return 1;
setadd32(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}
static int opXADD_l_a32(uint32_t fetchdat)
{
uint32_t temp;
uint32_t temp, temp2;
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
temp = geteal(); if (cpu_state.abrt) return 1;
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
setadd32(temp, cpu_state.regs[cpu_reg].l);
temp2 = cpu_state.regs[cpu_reg].l;
cpu_state.regs[cpu_reg].l = temp;
seteal(temp + temp2); if (cpu_state.abrt) return 1;
setadd32(temp, temp2);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
return 0;
}