diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index e70d57973..996cfc536 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -192,9 +192,15 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
 	if (base[0] != 0x00000000) {
 		/* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */
 		i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x38) == 0x20) || s);
+		/* If base is on top of memory, this mapping will point to RAM.
+		   TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */
+		/* If we are open, not closed, and not locked, point to RAM. */
 
 		/* If the register is set accordingly, disable the mapping also in SMM. */
 		i4x0_smram_map(0, base[0], size[0], !(regs[0x72] & 0x10) || s);
+		/* If base is on top of memory, this mapping will point to RAM.
+		   TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */
+		/* If we are not closed, point to RAM. */
 	}
     }
 }
@@ -1359,6 +1365,7 @@ static void
     i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
     i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
     i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
+    i4x0_write(regs[0x72], 0x72, 0x00, dev);
 
     // smbase = 0xa0000;
 
diff --git a/src/config.c b/src/config.c
index 7b352d876..0cc5d35a1 100644
--- a/src/config.c
+++ b/src/config.c
@@ -282,8 +282,10 @@ config_read(wchar_t *fn)
 	if (feof(f)) break;
 
 	/* Make sure there are no stray newlines or hard-returns in there. */
-	if (buff[wcslen(buff)-1] == L'\n') buff[wcslen(buff)-1] = L'\0';
-	if (buff[wcslen(buff)-1] == L'\r') buff[wcslen(buff)-1] = L'\0';
+	if (wcslen(buff) > 0)
+		if (buff[wcslen(buff)-1] == L'\n') buff[wcslen(buff)-1] = L'\0';
+	if (wcslen(buff) > 0)
+		if (buff[wcslen(buff)-1] == L'\r') buff[wcslen(buff)-1] = L'\0';
 
 	/* Skip any leading whitespace. */
 	c = 0;
@@ -2292,7 +2294,10 @@ config_set_string(char *head, char *name, char *val)
     if (ent == NULL)
 	ent = create_entry(section, name);
 
-    memcpy(ent->data, val, sizeof(ent->data));
+    if ((strlen(val) + 1) <= sizeof(ent->data))
+	memcpy(ent->data, val, strlen(val) + 1);
+    else
+	memcpy(ent->data, val, sizeof(ent->data));
     mbstowcs(ent->wdata, ent->data, sizeof_w(ent->wdata));
 }
 
diff --git a/src/cpu/codegen.c b/src/cpu/codegen.c
index 3949b8e98..cd12b43bc 100644
--- a/src/cpu/codegen.c
+++ b/src/cpu/codegen.c
@@ -11,9 +11,10 @@
 
 void (*codegen_timing_start)();
 void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
-void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
+void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
 void (*codegen_timing_block_start)();
 void (*codegen_timing_block_end)();
+int (*codegen_timing_jump_cycles)();
 
 void codegen_timing_set(codegen_timing_t *timing)
 {
@@ -22,6 +23,7 @@ void codegen_timing_set(codegen_timing_t *timing)
         codegen_timing_opcode = timing->opcode;
         codegen_timing_block_start = timing->block_start;
         codegen_timing_block_end = timing->block_end;
+        codegen_timing_jump_cycles = timing->jump_cycles;
 }
 
 int codegen_in_recompile;
diff --git a/src/cpu/codegen.h b/src/cpu/codegen.h
index c092c445c..24cb20de6 100644
--- a/src/cpu/codegen.h
+++ b/src/cpu/codegen.h
@@ -319,23 +319,28 @@ extern int codegen_block_cycles;
 
 extern void (*codegen_timing_start)();
 extern void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
-extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
+extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
 extern void (*codegen_timing_block_start)();
 extern void (*codegen_timing_block_end)();
+extern int (*codegen_timing_jump_cycles)();
 
 typedef struct codegen_timing_t
 {
         void (*start)();
         void (*prefix)(uint8_t prefix, uint32_t fetchdat);
-        void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
+        void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
         void (*block_start)();
         void (*block_end)();
+        int (*jump_cycles)();
 } codegen_timing_t;
 
 extern codegen_timing_t codegen_timing_pentium;
 extern codegen_timing_t codegen_timing_686;
 extern codegen_timing_t codegen_timing_486;
 extern codegen_timing_t codegen_timing_winchip;
+extern codegen_timing_t codegen_timing_winchip2;
+extern codegen_timing_t codegen_timing_k6;
+extern codegen_timing_t codegen_timing_p6;
 
 void codegen_timing_set(codegen_timing_t *timing);
 
diff --git a/src/cpu/codegen_ops_x86-64.h b/src/cpu/codegen_ops_x86-64.h
index 9508a83bd..6d1fc188c 100644
--- a/src/cpu/codegen_ops_x86-64.h
+++ b/src/cpu/codegen_ops_x86-64.h
@@ -5359,7 +5359,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
         load_param_1_reg_32(REG_EDI);
         load_param_2_32(&codeblock[block_current], 1);
 
-        call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
+        call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
         addbyte(0x80); /*CMP abrt, 0*/
         addbyte(0x7d);
         addbyte((uint8_t)cpu_state_offset(abrt));
@@ -5498,7 +5498,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
         jump_pos = block_pos;
         load_param_1_reg_32(REG_EBX);
         load_param_2_32(&codeblock[block_current], 1);
-        call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
+        call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
         addbyte(0x83); /*ADD EBX, 1*/
         addbyte(0xc3);
         addbyte(1);
@@ -5647,7 +5647,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
         jump_pos = block_pos;
         load_param_1_reg_32(REG_EBX);
         load_param_2_32(&codeblock[block_current], 1);
-        call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
+        call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
         addbyte(0x83); /*ADD EBX, 3*/
         addbyte(0xc3);
         addbyte(3);
diff --git a/src/cpu/codegen_timing_486.c b/src/cpu/codegen_timing_486.c
index 0b0ab9c15..a3859ecce 100644
--- a/src/cpu/codegen_timing_486.c
+++ b/src/cpu/codegen_timing_486.c
@@ -300,7 +300,7 @@ void codegen_timing_486_prefix(uint8_t prefix, uint32_t fetchdat)
         last_prefix = prefix;
 }
 
-void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
+void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
 {
         int **timings;
         uint64_t *deps;
@@ -360,7 +360,7 @@ void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
                 {
                         case 0x80: case 0x82: case 0x83:
                         timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
-                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
                         opcode = (fetchdat >> 3) & 7;
                         break;
                         case 0x81:
@@ -416,5 +416,6 @@ codegen_timing_t codegen_timing_486 =
         codegen_timing_486_prefix,
         codegen_timing_486_opcode,
         codegen_timing_486_block_start,
-        codegen_timing_486_block_end
+        codegen_timing_486_block_end,
+        NULL
 };
diff --git a/src/cpu/codegen_timing_686.c b/src/cpu/codegen_timing_686.c
index 3563d38d9..ff7ff54d2 100644
--- a/src/cpu/codegen_timing_686.c
+++ b/src/cpu/codegen_timing_686.c
@@ -826,7 +826,7 @@ static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_3
         return 0;
 }
 
-void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
+void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
 {
         uint32_t *timings;
         uint64_t *deps;
@@ -886,7 +886,7 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
                 {
                         case 0x80: case 0x82: case 0x83:
                         timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
-                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
                         opcode = (fetchdat >> 3) & 7;
                         break;
                         case 0x81:
@@ -1052,5 +1052,6 @@ codegen_timing_t codegen_timing_686 =
         codegen_timing_686_prefix,
         codegen_timing_686_opcode,
         codegen_timing_686_block_start,
-        codegen_timing_686_block_end
+        codegen_timing_686_block_end,
+        NULL
 };
diff --git a/src/cpu/codegen_timing_common.c b/src/cpu/codegen_timing_common.c
index a0e0c8787..7d4a37453 100644
--- a/src/cpu/codegen_timing_common.c
+++ b/src/cpu/codegen_timing_common.c
@@ -4,8 +4,9 @@
 #include <wchar.h>
 #include <86box/86box.h>
 #include "cpu.h"
-#include "codegen_timing_common.h"
+#include <86box/mem.h>
 
+#include "codegen_timing_common.h"
 
 uint64_t opcode_deps[256] =
 {
@@ -280,7 +281,7 @@ uint64_t opcode_deps_0f[256] =
 /*00*/  MODRM,  MODRM,   MODRM,   MODRM,
         0,      0,       0,       0,
         0,      0,       0,       0,
-        0,      0,       0,       0,
+        0,      MODRM,   0,       MODRM,
 
 /*10*/  0,      0,       0,       0,
         0,      0,       0,       0,
@@ -362,7 +363,7 @@ uint64_t opcode_deps_0f_mod3[256] =
 /*00*/  MODRM,  MODRM,   MODRM,   MODRM,
         0,      0,       0,       0,
         0,      0,       0,       0,
-        0,      0,       0,       0,
+        0,      MODRM,   0,       MODRM,
 
 /*10*/  0,      0,       0,       0,
         0,      0,       0,       0,
@@ -440,6 +441,171 @@ uint64_t opcode_deps_0f_mod3[256] =
         MODRM,  MODRM,                  MODRM,                   0,
 };
 
+uint64_t opcode_deps_0f0f[256] =
+{
+/*00*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      MODRM,   0,       0,
+
+/*10*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      MODRM,   0,       0,
+
+/*20*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*30*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*40*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*50*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*60*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*70*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*80*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*90*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       MODRM,   0,
+        0,      0,       MODRM,   0,
+
+/*a0*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*b0*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       0,       0,
+        0,      0,       0,       MODRM,
+
+/*c0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*d0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*e0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*f0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+};
+uint64_t opcode_deps_0f0f_mod3[256] =
+{
+/*00*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      MODRM,   0,       0,
+
+/*10*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      MODRM,   0,       0,
+
+/*20*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*30*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*40*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*50*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*60*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*70*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*80*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*90*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       MODRM,   0,
+        0,      0,       MODRM,   0,
+
+/*a0*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*b0*/  MODRM,  0,       0,       0,
+        MODRM,  0,       MODRM,   MODRM,
+        0,      0,       0,       0,
+        0,      0,       0,       MODRM,
+
+/*c0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*d0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*e0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+
+/*f0*/  0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+        0,      0,       0,       0,
+};
+
 uint64_t opcode_deps_shift[8] =
 {
         MODRM,    MODRM,    MODRM,    MODRM,
@@ -664,21 +830,21 @@ uint64_t opcode_deps_df_mod3[8] =
 
 uint64_t opcode_deps_81[8] =
 {
-        MODRM,  MODRM,  MODRM,  MODRM,
-        MODRM,  MODRM,  MODRM,  MODRM
+        MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632,
+        MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632,  MODRM | HAS_IMM1632
 };
 uint64_t opcode_deps_81_mod3[8] =
 {
-        SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,
-        SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | MODRM
+        SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,
+        SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,  SRCDEP_RM | MODRM | HAS_IMM1632
 };
 uint64_t opcode_deps_8x[8] =
 {
-        MODRM,  MODRM,  MODRM,  MODRM,
-        MODRM,  MODRM,  MODRM,  MODRM
+        MODRM | HAS_IMM8,  MODRM | HAS_IMM8,  MODRM | HAS_IMM8,  MODRM | HAS_IMM8,
+        MODRM | HAS_IMM8,  MODRM | HAS_IMM8,  MODRM | HAS_IMM8,  MODRM | HAS_IMM8
 };
 uint64_t opcode_deps_8x_mod3[8] =
 {
-        SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,
-        SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_RM | MODRM
+        SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,
+        SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,  SRCDEP_RM | MODRM | HAS_IMM8
 };
diff --git a/src/cpu/codegen_timing_common.h b/src/cpu/codegen_timing_common.h
index 19856ed99..0ec5adcac 100644
--- a/src/cpu/codegen_timing_common.h
+++ b/src/cpu/codegen_timing_common.h
@@ -73,6 +73,10 @@
 #define FPU_FXCH (1ull << 33)
 
 
+#define HAS_IMM8    (1ull << 34)
+#define HAS_IMM1632 (1ull << 35)
+
+
 #define REGMASK_IMPL_ESP (1 << 8)
 #define REGMASK_SHIFTPACK (1 << 9)
 #define REGMASK_MULTIPLY  (1 << 9)
@@ -82,6 +86,8 @@ extern uint64_t opcode_deps[256];
 extern uint64_t opcode_deps_mod3[256];
 extern uint64_t opcode_deps_0f[256];
 extern uint64_t opcode_deps_0f_mod3[256];
+extern uint64_t opcode_deps_0f0f[256];
+extern uint64_t opcode_deps_0f0f_mod3[256];
 extern uint64_t opcode_deps_shift[8];
 extern uint64_t opcode_deps_shift_mod3[8];
 extern uint64_t opcode_deps_shift_cl[8];
diff --git a/src/cpu/codegen_timing_k6.c b/src/cpu/codegen_timing_k6.c
new file mode 100644
index 000000000..a9b1aca13
--- /dev/null
+++ b/src/cpu/codegen_timing_k6.c
@@ -0,0 +1,2353 @@
+/*Most of the vector instructions here are a total guess.
+  Some of the timings are based on http://users.atw.hu/instlatx64/AuthenticAMD0000562_K6_InstLatX86.txt*/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <wchar.h>
+#include <86box/86box.h>
+#include "cpu.h"
+#include <86box/mem.h>
+#include <86box/machine.h>
+
+#include "x86.h"
+#include "x86_ops.h"
+#include "x87.h"
+#include "386_common.h"
+#include "codegen.h"
+#include "codegen_ops.h"
+#include "codegen_timing_common.h"
+
+typedef enum uop_type_t
+{
+        UOP_ALU = 0,   /*Executes in Integer X or Y units*/
+        UOP_ALUX,      /*Executes in Integer X unit*/
+        UOP_LOAD,      /*Executes in Load unit*/
+        UOP_STORE,     /*Executes in Store unit*/
+        UOP_FLOAD,     /*Executes in Load unit*/
+        UOP_FSTORE,    /*Executes in Store unit*/
+        UOP_MLOAD,     /*Executes in Load unit*/
+        UOP_MSTORE,    /*Executes in Store unit*/
+        UOP_FLOAT,     /*Executes in Floating Point unit*/
+        UOP_MEU,       /*Executes in Multimedia unit*/
+        UOP_MEU_SHIFT, /*Executes in Multimedia unit or ALU X/Y. Uses MMX shifter*/
+        UOP_MEU_MUL,   /*Executes in Multimedia unit or ALU X/Y. Uses MMX/3DNow multiplier*/
+        UOP_MEU_3DN,   /*Executes in Multimedia unit or ALU X/Y. Uses 3DNow ALU*/
+        UOP_BRANCH,    /*Executes in Branch unit*/
+        UOP_LIMM       /*Does not require an execution unit*/
+} uop_type_t;
+
+typedef enum decode_type_t
+{
+        DECODE_SHORT,
+        DECODE_LONG,
+        DECODE_VECTOR
+} decode_type_t;
+
+#define MAX_UOPS 10
+
+typedef struct risc86_uop_t
+{
+        uop_type_t type;
+        int throughput;
+        int latency;
+} risc86_uop_t;
+
+typedef struct risc86_instruction_t
+{
+        int nr_uops;
+        decode_type_t decode_type;
+        risc86_uop_t uop[MAX_UOPS];
+} risc86_instruction_t;
+
+static const risc86_instruction_t alu_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alux_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alu_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alux_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t branch_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t limm_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LIMM, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t load_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t store_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+
+
+static const risc86_instruction_t bswap_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t leave_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t lods_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t mov_reg_seg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+};
+static const risc86_instruction_t movs_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pop_reg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pop_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t push_imm_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_STORE,  .throughput = 1, .latency = 2},
+};
+static const risc86_instruction_t push_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t push_seg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t stos_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_reg_b_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_mem_imm_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_mem_imm_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t xchg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t m3dn_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_3DN, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t mmx_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t mmx_mul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t mmx_shift_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_SHIFT, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_3dn_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,     .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_3DN,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_mmx_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_mmx_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t load_mmx_shift_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,      .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_SHIFT, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t mload_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MLOAD, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t mstore_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MSTORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pmul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t pmul_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t float_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
+};
+static const risc86_instruction_t load_float_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
+};
+static const risc86_instruction_t fstore_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t fdiv_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 40, .latency = 40}
+};
+static const risc86_instruction_t fdiv_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .throughput = 40, .latency = 40}
+};
+static const risc86_instruction_t fsin_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 62, .latency = 62}
+};
+static const risc86_instruction_t fsqrt_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 41, .latency = 41}
+};
+
+static const risc86_instruction_t vector_fldcw_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 8, .latency = 8}
+};
+static const risc86_instruction_t vector_float_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
+};
+static const risc86_instruction_t vector_float_l_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 50, .latency = 50}
+};
+static const risc86_instruction_t vector_flde_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
+};
+static const risc86_instruction_t vector_fste_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2},
+        .uop[1] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t vector_alu1_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu2_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu3_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu6_op =
+{
+        .nr_uops = 6,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux1_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux3_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux6_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_arpl_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_bound_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_bsx_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_call_far_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_STORE,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cli_sti_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 7, .latency = 7}
+};
+static const risc86_instruction_t vector_cmps_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cmpsb_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cmpxchg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+};
+static const risc86_instruction_t vector_cmpxchg_b_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+};
+static const risc86_instruction_t vector_cpuid_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 22, .latency = 22}
+};
+static const risc86_instruction_t vector_div16_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_div16_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_div32_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
+};
+static const risc86_instruction_t vector_div32_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
+};
+static const risc86_instruction_t vector_emms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 25, .latency = 25}
+};
+static const risc86_instruction_t vector_enter_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE,  .throughput =  1, .latency =  2},
+        .uop[1] = {.type = UOP_ALU,    .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_femms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 6, .latency = 6}
+};
+static const risc86_instruction_t vector_in_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 10, .latency = 11}
+};
+static const risc86_instruction_t vector_ins_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 10, .latency = 11},
+        .uop[1] = {.type = UOP_STORE, .throughput =  1, .latency =  1},
+        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_int_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
+        .uop[1] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[2] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[3] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_iret_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[1] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[2] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[3] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
+        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_invd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1000, .latency = 1000}
+};
+static const risc86_instruction_t vector_jmp_far_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_lss_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mov_mem_seg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mov_seg_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mov_seg_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul64_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul64_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_out_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_outs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput =  1, .latency =  1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 10, .latency = 10},
+        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_pusha_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[6] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[7] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_popa_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[6] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[7] = {.type = UOP_LOAD, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_popf_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput =  1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 17, .latency = 17}
+};
+static const risc86_instruction_t vector_push_mem_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_pushf_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_ret_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_retf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_scas_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_scasb_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_setcc_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_setcc_reg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_test_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_test_mem_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_xchg_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_xlat_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t vector_wbinvd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 10000, .latency = 10000}
+};
+
+#define INVALID NULL
+
+static const risc86_instruction_t *opcode_timings[256] =
+{
+/*      ADD                    ADD                    ADD                   ADD*/
+/*00*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      ADD                    ADD                    PUSH ES               POP ES*/
+        &alux_op,              &alu_op,               &push_seg_op,         &vector_mov_seg_mem_op,
+/*      OR                     OR                     OR                    OR*/
+        &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      OR                     OR                     PUSH CS               */
+        &alux_op,              &alu_op,               &push_seg_op,         INVALID,
+
+/*      ADC                    ADC                    ADC                   ADC*/
+/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*      ADC                    ADC                    PUSH SS               POP SS*/
+        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+/*      SBB                    SBB                    SBB                   SBB*/
+/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*      SBB                    SBB                    PUSH DS               POP DS*/
+        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+
+/*      AND                    AND                    AND                   AND*/
+/*20*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      AND                    AND                                          DAA*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+/*      SUB                    SUB                    SUB                   SUB*/
+        &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      SUB                    SUB                                          DAS*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+
+/*      XOR                    XOR                    XOR                   XOR*/
+/*30*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      XOR                    XOR                                          AAA*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+/*      CMP                    CMP                    CMP                   CMP*/
+        &load_alux_op,         &load_alu_op,          &load_alux_op,        &load_alu_op,
+/*      CMP                    CMP                                          AAS*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+
+/*      INC EAX                INC ECX                INC EDX                INC EBX*/
+/*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      INC ESP                INC EBP                INC ESI                INC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC EAX                DEC ECX                DEC EDX                DEC EBX*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC ESP                DEC EBP                DEC ESI                DEC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+
+/*      PUSH EAX               PUSH ECX               PUSH EDX               PUSH EBX*/
+/*50*/  &store_op,             &store_op,             &store_op,             &store_op,
+/*      PUSH ESP               PUSH EBP               PUSH ESI               PUSH EDI*/
+        &store_op,             &store_op,             &store_op,             &store_op,
+/*      POP EAX                POP ECX                POP EDX                POP EBX*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+/*      POP ESP                POP EBP                POP ESI                POP EDI*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+
+/*      PUSHA                  POPA                   BOUND                  ARPL*/
+/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+        INVALID,               INVALID,               INVALID,               INVALID,
+/*      PUSH imm               IMUL                   PUSH imm               IMUL*/
+        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+/*      INSB                   INSW                   OUTSB                  OUTSW*/
+        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+
+/*      Jxx*/
+/*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      TEST                       TEST                       XCHG                       XCHG*/
+        &vector_test_mem_b_op,     &vector_test_mem_op,       &vector_xchg_mem_op,       &vector_xchg_mem_op,
+/*      MOV                        MOV                        MOV                        MOV*/
+        &store_op,                 &store_op,                 &load_op,                  &load_op,
+/*      MOV from seg               LEA                        MOV to seg                 POP*/
+        &vector_mov_mem_seg_op,    &store_op,                 &vector_mov_seg_mem_op,    &pop_mem_op,
+
+/*      NOP                        XCHG                       XCHG                       XCHG*/
+/*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      XCHG                       XCHG                       XCHG                       XCHG*/
+        &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      CBW                        CWD                        CALL far                   WAIT*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+/*      PUSHF                      POPF                       SAHF                       LAHF*/
+        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+
+/*      MOV                        MOV                        MOV                        MOV*/
+/*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
+/*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
+        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+/*      TEST                       TEST                       STOSB                      STOSW*/
+        &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
+/*      LODSB                      LODSW                      SCASB                      SCASW*/
+        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+
+/*      MOV*/
+/*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+
+/*                                                            RET imm                    RET*/
+/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*      LES                        LDS                        MOV                        MOV*/
+        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+/*      ENTER                      LEAVE                      RETF                       RETF*/
+        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+/*      INT3                       INT                        INTO                       IRET*/
+        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+
+
+/*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      AAM                        AAD                        SETALC                     XLAT*/
+        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
+/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+/*      CALL                       JMP                        JMP                        JMP*/
+        &store_op,                 &branch_op,                &vector_jmp_far_op,           &branch_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+
+/*                                                            REPNE                      REPE*/
+/*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      HLT                        CMC*/
+        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+/*      CLC                        STC                        CLI                        STI*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+/*      CLD                        STD                        INCDEC*/
+        &vector_alu1_op,           &vector_alu1_op,           &alux_store_op,            INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_mod3[256] =
+{
+/*      ADD                       ADD                       ADD                       ADD*/
+/*00*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      ADD                       ADD                       PUSH ES                   POP ES*/
+        &alux_op,                 &alu_op,                  &push_seg_op,             &vector_mov_seg_mem_op,
+/*      OR                        OR                        OR                        OR*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      OR                        OR                        PUSH CS                   */
+        &alux_op,                 &alu_op,                  &push_seg_op,             INVALID,
+
+/*      ADC                       ADC                       ADC                       ADC*/
+/*10*/  &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*      ADC                       ADC                       PUSH SS                   POP SS*/
+        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+/*      SBB                       SBB                       SBB                       SBB*/
+        &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*      SBB                       SBB                       PUSH DS                   POP DS*/
+        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+
+/*      AND                       AND                       AND                       AND*/
+/*20*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      AND                       AND                                                 DAA*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+/*      SUB                       SUB                       SUB                       SUB*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      SUB                       SUB                                                 DAS*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+
+/*      XOR                       XOR                       XOR                       XOR*/
+/*30*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      XOR                       XOR                                                 AAA*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+/*      CMP                       CMP                       CMP                       CMP*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      CMP                       CMP                                                 AAS*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+
+/*      INC EAX                INC ECX                INC EDX                INC EBX*/
+/*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      INC ESP                INC EBP                INC ESI                INC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC EAX                DEC ECX                DEC EDX                DEC EBX*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC ESP                DEC EBP                DEC ESI                DEC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+
+/*      PUSH EAX               PUSH ECX               PUSH EDX               PUSH EBX*/
+/*50*/  &store_op,             &store_op,             &store_op,             &store_op,
+/*      PUSH ESP               PUSH EBP               PUSH ESI               PUSH EDI*/
+        &store_op,             &store_op,             &store_op,             &store_op,
+/*      POP EAX                POP ECX                POP EDX                POP EBX*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+/*      POP ESP                POP EBP                POP ESI                POP EDI*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+
+/*      PUSHA                  POPA                   BOUND                  ARPL*/
+/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+        INVALID,               INVALID,               INVALID,               INVALID,
+/*      PUSH imm               IMUL                   PUSH imm               IMUL*/
+        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+/*      INSB                   INSW                   OUTSB                  OUTSW*/
+        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+
+/*      Jxx*/
+/*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      TEST                       TEST                       XCHG                       XCHG*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_alu3_op,           &vector_alu3_op,
+/*      MOV                        MOV                        MOV                        MOV*/
+        &store_op,                 &store_op,                 &load_op,                  &load_op,
+/*      MOV from seg               LEA                        MOV to seg                 POP*/
+        &mov_reg_seg_op,           &store_op,                 &vector_mov_seg_reg_op,    &pop_reg_op,
+
+/*      NOP                        XCHG                       XCHG                       XCHG*/
+/*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      XCHG                       XCHG                       XCHG                       XCHG*/
+        &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      CBW                        CWD                        CALL far                   WAIT*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+/*      PUSHF                      POPF                       SAHF                       LAHF*/
+        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+
+/*      MOV                        MOV                        MOV                        MOV*/
+/*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
+/*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
+        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+/*      TEST                       TEST                       STOSB                      STOSW*/
+        &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
+/*      LODSB                      LODSW                      SCASB                      SCASW*/
+        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+
+/*      MOV*/
+/*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+
+/*                                                            RET imm                    RET*/
+/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*      LES                        LDS                        MOV                        MOV*/
+        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+/*      ENTER                      LEAVE                      RETF                       RETF*/
+        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+/*      INT3                       INT                        INTO                       IRET*/
+        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+
+
+/*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      AAM                        AAD                        SETALC                     XLAT*/
+        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
+/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+/*      CALL                       JMP                        JMP                        JMP*/
+        &store_op,                 &branch_op,                &vector_jmp_far_op,        &branch_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+
+/*                                                            REPNE                      REPE*/
+/*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      HLT                        CMC*/
+        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+/*      CLC                        STC                        CLI                        STI*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+/*      CLD                        STD                        INCDEC*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_alux1_op,          INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_0f[256] =
+{
+/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
+        INVALID,                &load_op,               &vector_femms_op,       &load_3dn_op,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        INVALID,                INVALID,                &mload_op,              &mload_op,
+
+/*70*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &vector_emms_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                &mstore_op,             &mstore_op,
+
+/*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*90*/  &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+
+/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_load_alu_op,
+        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                INVALID,
+        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_load_alu_op,
+        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                &vector_mul_op,
+
+/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_load_alu_op,
+        &vector_lss_op,         &vector_lss_op,         &load_alux_op,          &load_alu_op,
+        INVALID,                INVALID,                &vector_load_alu_op,    &vector_load_alu_op,
+        &vector_bsx_op,         &vector_bsx_op,         &load_alux_op,          &load_alu_op,
+
+/*c0*/  &vector_alux_store_op,  &vector_alu_store_op,   INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &vector_cmpxchg_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+
+/*d0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                &load_mmx_mul_op,       INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+
+/*e0*/  &load_mmx_op,           &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
+        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+
+/*f0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+};
+static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
+{
+/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
+        INVALID,                INVALID,                &vector_femms_op,       &m3dn_op,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+
+/*70*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &vector_emms_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+
+/*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*90*/  &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+
+/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_alu1_op,
+        &vector_alu1_op,      &vector_alu1_op,          INVALID,                INVALID,
+        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_alu1_op,
+        &vector_alu1_op,      &vector_alu1_op,          INVALID,                &vector_mul_op,
+
+/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_alu1_op,
+        &vector_lss_op,         &vector_lss_op,         &alux_op,               &alu_op,
+        INVALID,                INVALID,                &vector_alu1_op,        &vector_alu1_op,
+        &vector_bsx_op,         &vector_bsx_op,         &alux_op,               &alu_op,
+
+/*c0*/  &vector_alux1_op,       &vector_alu1_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+
+/*d0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        INVALID,                &mmx_mul_op,            INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+
+/*e0*/  &mmx_op,                &mmx_shift_op,          &mmx_shift_op,          INVALID,
+        INVALID,                &pmul_op,               INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+
+/*f0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        INVALID,                &pmul_op,               INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+};
+
+static const risc86_instruction_t *opcode_timings_0f0f[256] =
+{
+/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                &load_3dn_op,           INVALID,                INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                &load_3dn_op,           INVALID,                INVALID,
+
+/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*90*/  &load_3dn_op,           INVALID,                INVALID,                INVALID,
+        &load_3dn_op,           INVALID,                &load_3dn_op,           &load_3dn_op,
+        INVALID,                INVALID,                &load_3dn_op,           INVALID,
+        INVALID,                INVALID,                &load_3dn_op,           INVALID,
+
+/*a0*/  &load_3dn_op,           INVALID,                INVALID,                INVALID,
+        &load_3dn_op,           INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
+        INVALID,                INVALID,                &load_3dn_op,           INVALID,
+        INVALID,                INVALID,                &load_3dn_op,           INVALID,
+
+/*b0*/  &load_3dn_op,           INVALID,                INVALID,                INVALID,
+        &load_mmx_mul_op,       INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &load_mmx_op,
+
+/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+};
+static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
+{
+/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                &m3dn_op,               INVALID,                INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                &m3dn_op,               INVALID,                INVALID,
+
+/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*90*/  &m3dn_op,               INVALID,                INVALID,                INVALID,
+        &m3dn_op,               INVALID,                &m3dn_op,               &m3dn_op,
+        INVALID,                INVALID,                &m3dn_op,               INVALID,
+        INVALID,                INVALID,                &m3dn_op,               INVALID,
+
+/*a0*/  &m3dn_op,               INVALID,                INVALID,                INVALID,
+        &m3dn_op,               INVALID,                &mmx_mul_op,            &mmx_mul_op,
+        INVALID,                INVALID,                &m3dn_op,               INVALID,
+        INVALID,                INVALID,                &m3dn_op,               INVALID,
+
+/*b0*/  &m3dn_op,               INVALID,                INVALID,                INVALID,
+        &mmx_mul_op,            INVALID,                &mmx_mul_op,            &mmx_mul_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &mmx_op,
+
+/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+};
+
+static const risc86_instruction_t *opcode_timings_shift[8] =
+{
+        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,
+        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op
+};
+static const risc86_instruction_t *opcode_timings_shift_b[8] =
+{
+        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,
+        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op
+};
+static const risc86_instruction_t *opcode_timings_shift_mod3[8] =
+{
+        &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,
+        &alu_op,           &alu_op,           &alu_op,           &alu_op
+};
+static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] =
+{
+        &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,
+        &alux_op,          &alux_op,          &alux_op,          &alux_op
+};
+
+static const risc86_instruction_t *opcode_timings_80[8] =
+{
+        &alux_store_op, &alux_store_op, &vector_alux_store_op,  &vector_alux_store_op,
+        &alux_store_op, &alux_store_op, &alux_store_op,         &alux_store_op,
+};
+static const risc86_instruction_t *opcode_timings_80_mod3[8] =
+{
+        &alux_op,       &alux_op,       &alux_store_op,         &alux_store_op,
+        &alux_op,       &alux_op,       &alux_op,               &alux_op,
+};
+static const risc86_instruction_t *opcode_timings_8x[8] =
+{
+        &alu_store_op,  &alu_store_op,  &vector_alu_store_op,   &vector_alu_store_op,
+        &alu_store_op,  &alu_store_op,  &alu_store_op,          &alu_store_op,
+};
+static const risc86_instruction_t *opcode_timings_8x_mod3[8] =
+{
+        &alu_op,        &alu_op,        &alu_store_op,          &alu_store_op,
+        &alu_op,        &alu_op,        &alu_op,                &alu_op,
+};
+
+static const risc86_instruction_t *opcode_timings_f6[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_mem_imm_b_op,     INVALID,                &vector_alux_store_op,  &vector_alux_store_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul_mem_op,     &vector_mul_mem_op,     &vector_div16_mem_op,   &vector_div16_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_f6_mod3[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_reg_b_op,         INVALID,                &alux_op,               &alux_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul_op,         &vector_mul_op,         &vector_div16_op,       &vector_div16_op,
+};
+static const risc86_instruction_t *opcode_timings_f7[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_mem_imm_op,       INVALID,                &vector_alu_store_op,   &vector_alu_store_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul64_mem_op,   &vector_mul64_mem_op,   &vector_div32_mem_op,   &vector_div32_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_f7_mod3[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_reg_op,           INVALID,                &alu_op,                &alu_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul64_op,       &vector_mul64_op,       &vector_div32_op,       &vector_div32_op,
+};
+static const risc86_instruction_t *opcode_timings_ff[8] =
+{
+/*      INC                     DEC                     CALL                    CALL far*/
+        &alu_store_op,          &alu_store_op,          &store_op,              &vector_call_far_op,
+/*      JMP                     JMP far                 PUSH*/
+        &branch_op,             &vector_jmp_far_op,     &push_mem_op,           INVALID
+};
+static const risc86_instruction_t *opcode_timings_ff_mod3[8] =
+{
+/*      INC                     DEC                     CALL                    CALL far*/
+        &vector_alu1_op,        &vector_alu1_op,        &store_op,              &vector_call_far_op,
+/*      JMP                     JMP far                 PUSH*/
+        &branch_op,             &vector_jmp_far_op,     &vector_push_mem_op,    INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_d8[8] =
+{
+/*      FADDs            FMULs            FCOMs            FCOMPs*/
+        &load_float_op,  &load_float_op,  &load_float_op,  &load_float_op,
+/*      FSUBs            FSUBRs           FDIVs            FDIVRs*/
+        &load_float_op,  &load_float_op,  &fdiv_mem_op,    &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_d8_mod3[8] =
+{
+/*      FADD             FMUL             FCOM             FCOMP*/
+        &float_op,       &float_op,       &float_op,       &float_op,
+/*      FSUB             FSUBR            FDIV             FDIVR*/
+        &float_op,       &float_op,       &fdiv_op,        &fdiv_op,
+};
+
+static const risc86_instruction_t *opcode_timings_d9[8] =
+{
+/*      FLDs                                    FSTs                 FSTPs*/
+        &load_float_op,      INVALID,           &fstore_op,          &fstore_op,
+/*      FLDENV               FLDCW              FSTENV               FSTCW*/
+        &vector_float_l_op,  &vector_fldcw_op,  &vector_float_l_op,  &vector_float_op
+};
+static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
+{
+        /*FLD*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+        /*FXCH*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+        /*FNOP*/
+        &float_op,    INVALID,      INVALID,      INVALID,
+        INVALID,      INVALID,      INVALID,      INVALID,
+        /*FSTP*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+/*      opFCHS        opFABS*/
+        &float_op,    &float_op,    INVALID,      INVALID,
+/*      opFTST        opFXAM*/
+        &float_op,    &float_op,    INVALID,      INVALID,
+/*      opFLD1        opFLDL2T      opFLDL2E      opFLDPI*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+/*      opFLDEG2      opFLDLN2      opFLDZ*/
+        &float_op,    &float_op,    &float_op,    INVALID,
+/*      opF2XM1       opFYL2X       opFPTAN       opFPATAN*/
+        &fsin_op,     &fsin_op,     &fsin_op,     &fsin_op,
+/*                                  opFDECSTP     opFINCSTP,*/
+        INVALID,      INVALID,      &float_op,    &float_op,
+/*      opFPREM                     opFSQRT       opFSINCOS*/
+        &fdiv_op,     INVALID,      &fsqrt_op,    &fsin_op,
+/*      opFRNDINT     opFSCALE      opFSIN        opFCOS*/
+        &float_op,    &fdiv_op,     &fsin_op,     &fsin_op
+};
+
+static const risc86_instruction_t *opcode_timings_da[8] =
+{
+/*      FIADDl            FIMULl            FICOMl            FICOMPl*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FISUBl            FISUBRl           FIDIVl            FIDIVRl*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_da_mod3[8] =
+{
+        INVALID,          INVALID,          INVALID,          INVALID,
+/*                        FCOMPP*/
+        INVALID,          &float_op,        INVALID,          INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_db[8] =
+{
+/*      FLDil                               FSTil         FSTPil*/
+        &load_float_op,   INVALID,          &fstore_op,   &fstore_op,
+/*                        FLDe                            FSTPe*/
+        INVALID,          &vector_flde_op,  INVALID,      &vector_fste_op
+};
+static const risc86_instruction_t *opcode_timings_db_mod3[64] =
+{
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+/*                        opFNOP            opFCLEX       opFINIT*/
+        INVALID,          &float_op,        &float_op,    &float_op,
+/*      opFNOP            opFNOP*/
+        &float_op,        &float_op,        INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+};
+
+static const risc86_instruction_t *opcode_timings_dc[8] =
+{
+/*      FADDd             FMULd             FCOMd             FCOMPd*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FSUBd             FSUBRd            FDIVd             FDIVRd*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_dc_mod3[8] =
+{
+/*      opFADDr           opFMULr*/
+        &float_op,        &float_op,        INVALID,          INVALID,
+/*      opFSUBRr          opFSUBr           opFDIVRr          opFDIVr*/
+        &float_op,        &float_op,        &fdiv_op,         &fdiv_op
+};
+
+static const risc86_instruction_t *opcode_timings_dd[8] =
+{
+/*      FLDd                                    FSTd                 FSTPd*/
+        &load_float_op,     INVALID,            &fstore_op,          &fstore_op,
+/*      FRSTOR                                  FSAVE                FSTSW*/
+        &vector_float_l_op, INVALID,            &vector_float_l_op,  &vector_float_l_op
+};
+static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
+{
+/*      FFFREE                            FST                FSTP*/
+        &float_op,       INVALID,         &float_op,         &float_op,
+/*      FUCOM            FUCOMP*/
+        &float_op,       &float_op,       INVALID,           INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_de[8] =
+{
+/*      FIADDw            FIMULw            FICOMw            FICOMPw*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FISUBw            FISUBRw           FIDIVw            FIDIVRw*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_de_mod3[8] =
+{
+/*      FADDP            FMULP                          FCOMPP*/
+        &float_op,       &float_op,       INVALID,      &float_op,
+/*      FSUBP            FSUBRP           FDIVP         FDIVRP*/
+        &float_op,       &float_op,       &fdiv_op,     &fdiv_op,
+};
+
+static const risc86_instruction_t *opcode_timings_df[8] =
+{
+/*      FILDiw                              FISTiw               FISTPiw*/
+        &load_float_op,   INVALID,          &fstore_op,          &fstore_op,
+/*                        FILDiq            FBSTP                FISTPiq*/
+        INVALID,          &load_float_op,   &vector_float_l_op,  &fstore_op,
+};
+static const risc86_instruction_t *opcode_timings_df_mod3[8] =
+{
+        INVALID,      INVALID,      INVALID,      INVALID,
+/*      FSTSW AX*/
+        &float_op,    INVALID,      INVALID,      INVALID
+};
+
+
+static uint8_t last_prefix;
+static int prefixes;
+
+static int decode_timestamp;
+static int last_complete_timestamp;
+
+typedef struct k6_unit_t
+{
+        uint32_t uop_mask;
+        int first_available_cycle;
+} k6_unit_t;
+
+static int nr_units;
+static k6_unit_t *units;
+
+/*K6 has dedicated MMX unit*/
+static k6_unit_t k6_units[] =
+{
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX)},                                 /*Integer X*/
+        {.uop_mask = (1 << UOP_ALU)},                                                   /*Integer Y*/
+        {.uop_mask = (1 << UOP_MEU) | (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},       /*Multimedia*/
+        {.uop_mask = (1 << UOP_FLOAT)},                                                 /*Floating point*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},          /*Load*/
+        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)},         /*Store*/
+        {.uop_mask = (1 << UOP_BRANCH)}                                                 /*Branch*/
+};
+#define NR_K6_UNITS (sizeof(k6_units) / sizeof(k6_unit_t))
+
+/*K6-2 and later integrate MMX into ALU X & Y, sharing multiplier, shifter and
+  3DNow ALU between two execution units*/
+static k6_unit_t k6_2_units[] =
+{
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_MEU) |        /*Integer X*/
+                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL) | (1 << UOP_MEU_3DN)},
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_MEU) |                          /*Integer Y*/
+                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL) | (1 << UOP_MEU_3DN)},
+        {.uop_mask = (1 << UOP_FLOAT)},                                         /*Floating point*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},  /*Load*/
+        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)}, /*Store*/
+        {.uop_mask = (1 << UOP_BRANCH)}                                         /*Branch*/
+};
+#define NR_K6_2_UNITS (sizeof(k6_2_units) / sizeof(k6_unit_t))
+
+/*First available cycles of shared execution units. Each of these can be submitted
+  to by ALU X and Y*/
+static int mul_first_available_cycle;
+static int shift_first_available_cycle;
+static int m3dnow_first_available_cycle;
+
+static int uop_run(const risc86_uop_t *uop, int decode_time)
+{
+        int c;
+        k6_unit_t *best_unit = NULL;
+        int best_start_cycle = 99999;
+        
+        /*UOP_LIMM does not require execution*/
+        if (uop->type == UOP_LIMM)
+                return decode_time;
+
+        /*Handle shared units on K6-2 and later*/
+        if (units == k6_2_units)
+        {
+                if (uop->type == UOP_MEU_MUL && decode_time < mul_first_available_cycle)
+                        decode_time = mul_first_available_cycle;
+                else if (uop->type == UOP_MEU_SHIFT && decode_time < mul_first_available_cycle)
+                        decode_time = shift_first_available_cycle;
+                else if (uop->type == UOP_MEU_3DN && decode_time < mul_first_available_cycle)
+                        decode_time = m3dnow_first_available_cycle;
+        }
+
+        /*Find execution unit for this uOP*/
+        for (c = 0; c < nr_units; c++)
+        {
+                if (units[c].uop_mask & (1 << uop->type))
+                {
+                        if (units[c].first_available_cycle < best_start_cycle)
+                        {
+                                best_unit = &units[c];
+                                best_start_cycle = units[c].first_available_cycle;
+                        }
+                }
+        }
+        if (!best_unit)
+                fatal("uop_run: can not find execution unit\n");
+
+        if (best_start_cycle < decode_time)
+                best_start_cycle = decode_time;
+        best_unit->first_available_cycle = best_start_cycle + uop->throughput;
+
+        if (units == k6_2_units)
+        {
+                if (uop->type == UOP_MEU_MUL)
+                        mul_first_available_cycle = best_start_cycle + uop->throughput;
+                else if (uop->type == UOP_MEU_SHIFT)
+                        shift_first_available_cycle = best_start_cycle + uop->throughput;
+                else if (uop->type == UOP_MEU_3DN)
+                        m3dnow_first_available_cycle = best_start_cycle + uop->throughput;
+        }
+
+        return best_start_cycle + uop->throughput;
+}
+
+/*The K6 decoder can decode, per clock :
+  - 1 or 2 'short' instructions, each up to 2 uOPs and 7 bytes long
+  - 1 'long' instruction, up to 4 uOPs
+  - 1 'vector' instruction, up to 4 uOPs per cycle, plus (I think) 1 cycle startup delay)
+*/
+static struct
+{
+        int nr_uops;
+        const risc86_uop_t *uops[4];
+        /*Earliest time a uop can start. If the timestamp is -1, then the uop is
+          part of a dependency chain and the start time is the completion time of
+          the previous uop*/
+        int earliest_start[4];
+} decode_buffer;
+
+#define NR_OPQUADS 6
+/*Timestamps of when the last six opquads completed. The K6 scheduler retires
+  opquads in order, so this is needed to determine when the next can be scheduled*/
+static int opquad_completion_timestamp[NR_OPQUADS];
+static int next_opquad = 0;
+
+#define NR_REGS 8
+/*Timestamp of when last operation on an integer register completed*/
+static int reg_available_timestamp[NR_REGS];
+/*Timestamp of when last operation on an FPU register completed*/
+static int fpu_st_timestamp[8];
+/*Completion time of the last uop to be processed. Used to calculate timing of
+  dependent uop chains*/
+static int last_uop_timestamp = 0;
+
+void decode_flush()
+{
+        int c;
+        int uop_timestamp = 0;
+
+        /*Decoded opquad can not be submitted if there are no free spaces in the
+          opquad buffer*/
+        if (decode_timestamp < opquad_completion_timestamp[next_opquad])
+                decode_timestamp = opquad_completion_timestamp[next_opquad];
+
+        /*Ensure that uops can not be submitted before they have been decoded*/
+        if (decode_timestamp > last_uop_timestamp)
+                last_uop_timestamp = decode_timestamp;
+
+        /*Submit uops to execution units, and determine the latest completion time*/
+        for (c = 0; c < decode_buffer.nr_uops; c++)
+        {
+                int start_timestamp;
+                
+                if (decode_buffer.earliest_start[c] == -1)
+                        start_timestamp = last_uop_timestamp;
+                else
+                        start_timestamp = decode_buffer.earliest_start[c];
+                
+                last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
+                if (last_uop_timestamp > uop_timestamp)
+                        uop_timestamp = last_uop_timestamp;
+        }
+
+        /*Calculate opquad completion time. Since opquads complete in order, it
+          must be after the last completion.*/
+        if (uop_timestamp <= last_complete_timestamp)
+                last_complete_timestamp = last_complete_timestamp + 1;
+        else
+                last_complete_timestamp = uop_timestamp;
+
+        /*Advance to next opquad in buffer*/
+        opquad_completion_timestamp[next_opquad] = last_complete_timestamp;
+        next_opquad++;
+        if (next_opquad == NR_OPQUADS)
+                next_opquad = 0;
+
+        decode_timestamp++;
+        decode_buffer.nr_uops = 0;
+}
+
+/*The instruction is only of interest here if it's longer than 7 bytes, as that's the
+  limit on K6 short decoding*/
+static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_32)
+{
+        int len = prefixes + 1; /*Opcode*/
+        if (deps & MODRM)
+        {
+                len++; /*ModR/M*/
+                if (deps & HAS_IMM8)
+                        len++;
+                if (deps & HAS_IMM1632)
+                        len += (op_32 & 0x100) ? 4 : 2;
+
+                if (op_32 & 0x200)
+                {
+                        if ((fetchdat & 7) == 4 && (fetchdat & 0xc0) != 0xc0)
+                        {
+                                /* Has SIB*/
+                                len++;
+                                if ((fetchdat & 0xc0) == 0x40)
+                                        len++;
+                                else if ((fetchdat & 0xc0) == 0x80)
+                                        len += 4;
+                                else if ((fetchdat & 0x700) == 0x500)
+                                        len += 4;
+                        }
+                        else
+                        {
+                                if ((fetchdat & 0xc0) == 0x40)
+                                        len++;
+                                else if ((fetchdat & 0xc0) == 0x80)
+                                        len += 4;
+                                else if ((fetchdat & 0xc7) == 0x05)
+                                        len += 4;
+                        }
+                }
+                else
+                {
+                        if ((fetchdat & 0xc0) == 0x40)
+                                len++;
+                        else if ((fetchdat & 0xc0) == 0x80)
+                                len += 2;
+                        else if ((fetchdat & 0xc7) == 0x06)
+                                len += 2;
+                }
+        }
+
+        return len;
+}
+
+static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8)
+{
+        uint32_t regmask_required;
+        uint32_t regmask_modified;
+        int c, d;
+        int earliest_start = 0;
+        decode_type_t decode_type = ins->decode_type;
+        int instr_length = codegen_timing_instr_length(deps, fetchdat, op_32);
+
+        /*Generate input register mask, and determine the earliest time this
+          instruction can start. This is not accurate, as this is calculated per
+          x86 instruction when it should be handled per uop*/
+        regmask_required = get_dstdep_mask(deps, fetchdat, bit8);
+        regmask_required |= get_addr_regmask(deps, fetchdat, op_32);
+        for (c = 0; c < 8; c++)
+        {
+                if (regmask_required & (1 << c))
+                {
+                        if (reg_available_timestamp[c] > decode_timestamp)
+                                earliest_start = reg_available_timestamp[c];
+                }
+        }
+        if ((deps & FPU_RW_ST0) && fpu_st_timestamp[0] > decode_timestamp)
+                earliest_start = fpu_st_timestamp[0];
+        if ((deps & FPU_RW_ST1) && fpu_st_timestamp[1] > decode_timestamp)
+                earliest_start = fpu_st_timestamp[1];
+        if ((deps & FPU_RW_STREG))
+        {
+                int reg = fetchdat & 7;
+
+                if (fpu_st_timestamp[reg] > decode_timestamp)
+                        earliest_start = fpu_st_timestamp[reg];
+        }
+
+        /*Short decoders are limited to 7 bytes*/
+        if (decode_type == DECODE_SHORT && instr_length > 7)
+                decode_type = DECODE_LONG;
+        /*Long decoder is limited to 11 bytes*/
+        else if (instr_length > 11)
+                decode_type = DECODE_VECTOR;
+
+        switch (decode_type)
+        {
+                case DECODE_SHORT:
+                if (decode_buffer.nr_uops)
+                {
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        if (ins->nr_uops > 1)
+                        {
+                                decode_buffer.uops[decode_buffer.nr_uops+1] = &ins->uop[1];
+                                decode_buffer.earliest_start[decode_buffer.nr_uops+1] = -1;
+                        }
+                        decode_buffer.nr_uops += ins->nr_uops;
+
+                        decode_flush();
+                }
+                else
+                {
+                        decode_buffer.nr_uops = ins->nr_uops;
+                        decode_buffer.uops[0] = &ins->uop[0];
+                        decode_buffer.earliest_start[0] = earliest_start;
+                        if (ins->nr_uops > 1)
+                        {
+                                decode_buffer.uops[1] = &ins->uop[1];
+                                decode_buffer.earliest_start[1] = -1;
+                        }
+                }
+                break;
+                
+                case DECODE_LONG:
+                if (decode_buffer.nr_uops)
+                        decode_flush();
+                        
+                decode_buffer.nr_uops = ins->nr_uops;
+                for (c = 0; c < ins->nr_uops; c++)
+                {
+                        decode_buffer.uops[c] = &ins->uop[c];
+                        if (c == 0)
+                                decode_buffer.earliest_start[c] = earliest_start;
+                        else
+                                decode_buffer.earliest_start[c] = -1;
+                }
+                decode_flush();
+                break;
+                
+                case DECODE_VECTOR:
+                if (decode_buffer.nr_uops)
+                        decode_flush();
+                        
+                decode_timestamp++;
+                d = 0;
+
+                for (c = 0; c < ins->nr_uops; c++)
+                {
+                        decode_buffer.uops[d] = &ins->uop[c];
+                        if (c == 0)
+                                decode_buffer.earliest_start[d] = earliest_start;
+                        else
+                                decode_buffer.earliest_start[d] = -1;
+                        d++;
+                                
+                        if (d == 4)
+                        {
+                                d = 0;
+                                decode_buffer.nr_uops = 4;
+                                decode_flush();
+                        }
+                }
+                if (d)
+                {
+                        decode_buffer.nr_uops = d;
+                        decode_flush();
+                }
+                break;
+        }
+
+        /*Update write timestamps for any output registers*/
+        regmask_modified = get_dstdep_mask(deps, fetchdat, bit8);
+        for (c = 0; c < 8; c++)
+        {
+                if (regmask_modified & (1 << c))
+                        reg_available_timestamp[c] = last_complete_timestamp;
+        }
+        if (deps & FPU_POP)
+        {
+                for (c = 0; c < 7; c++)
+                        fpu_st_timestamp[c] = fpu_st_timestamp[c+1];
+                fpu_st_timestamp[7] = 0;
+        }
+        if (deps & FPU_POP2)
+        {
+                for (c = 0; c < 6; c++)
+                        fpu_st_timestamp[c] = fpu_st_timestamp[c+2];
+                fpu_st_timestamp[6] = fpu_st_timestamp[7] = 0;
+        }
+        if (deps & FPU_PUSH)
+        {
+                for (c = 0; c < 7; c++)
+                        fpu_st_timestamp[c+1] = fpu_st_timestamp[c];
+                fpu_st_timestamp[0] = 0;
+        }
+        if (deps & FPU_WRITE_ST0)
+                fpu_st_timestamp[0] = last_complete_timestamp;
+        if (deps & FPU_WRITE_ST1)
+                fpu_st_timestamp[1] = last_complete_timestamp;
+        if (deps & FPU_WRITE_STREG)
+        {
+                int reg = fetchdat & 7;
+                if (deps & FPU_POP)
+                        reg--;
+                if (reg >= 0 &&
+                        !(reg == 0 && (deps & FPU_WRITE_ST0)) &&
+                        !(reg == 1 && (deps & FPU_WRITE_ST1)))
+                        fpu_st_timestamp[reg] = last_complete_timestamp;
+        }
+}
+
+void codegen_timing_k6_block_start()
+{
+        int c;
+
+        for (c = 0; c < nr_units; c++)
+                units[c].first_available_cycle = 0;
+
+        mul_first_available_cycle = 0;
+        shift_first_available_cycle = 0;
+        m3dnow_first_available_cycle = 0;
+
+        decode_timestamp = 0;
+        last_complete_timestamp = 0;
+        
+        for (c = 0; c < NR_OPQUADS; c++)
+                opquad_completion_timestamp[c] = 0;
+        next_opquad = 0;
+        
+        for (c = 0; c < NR_REGS; c++)
+                reg_available_timestamp[c] = 0;
+        for (c = 0; c < 8; c++)
+                fpu_st_timestamp[c] = 0;
+}
+
+void codegen_timing_k6_start()
+{
+        if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_K6)
+        {
+                units = k6_units;
+                nr_units = NR_K6_UNITS;
+        }
+        else
+        {
+                units = k6_2_units;
+                nr_units = NR_K6_2_UNITS;
+        }
+        last_prefix = 0;
+        prefixes = 0;
+}
+
+void codegen_timing_k6_prefix(uint8_t prefix, uint32_t fetchdat)
+{
+        if (prefix != 0x0f)
+                decode_timestamp++;
+
+        last_prefix = prefix;
+        prefixes++;
+}
+
+void codegen_timing_k6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
+{
+        const risc86_instruction_t **ins_table;
+        uint64_t *deps;
+        int mod3 = ((fetchdat & 0xc0) == 0xc0);
+        int old_last_complete_timestamp = last_complete_timestamp;
+        int bit8 = !(opcode & 1);
+
+        switch (last_prefix)
+        {
+                case 0x0f:
+                if (opcode == 0x0f)
+                {
+                        /*3DNow has the actual opcode after ModR/M, SIB and any offset*/
+                        uint32_t opcode_pc = op_pc + 1; /*Byte after ModR/M*/
+                        uint8_t modrm = fetchdat & 0xff;
+                        uint8_t sib = (fetchdat >> 8) & 0xff;
+
+                        if ((modrm & 0xc0) != 0xc0)
+                        {
+                                if (op_32 & 0x200)
+                                {
+                                        if ((modrm & 7) == 4)
+                                        {
+                                                /* Has SIB*/
+                                                opcode_pc++;
+                                                if ((modrm & 0xc0) == 0x40)
+                                                        opcode_pc++;
+                                                else if ((modrm & 0xc0) == 0x80)
+                                                        opcode_pc += 4;
+                                                else if ((sib & 0x07) == 0x05)
+                                                        opcode_pc += 4;
+                                        }
+                                        else
+                                        {
+                                                if ((modrm & 0xc0) == 0x40)
+                                                        opcode_pc++;
+                                                else if ((modrm & 0xc0) == 0x80)
+                                                        opcode_pc += 4;
+                                                else if ((modrm & 0xc7) == 0x05)
+                                                        opcode_pc += 4;
+                                        }
+                                }
+                                else
+                                {
+                                        if ((modrm & 0xc0) == 0x40)
+                                                opcode_pc++;
+                                        else if ((modrm & 0xc0) == 0x80)
+                                                opcode_pc += 2;
+                                        else if ((modrm & 0xc7) == 0x06)
+                                                opcode_pc += 2;
+                                }
+                        }
+                        
+                        opcode = fastreadb(cs + opcode_pc);
+
+                        ins_table = mod3 ? opcode_timings_0f0f_mod3 : opcode_timings_0f0f;
+                        deps = mod3 ? opcode_deps_0f0f_mod3 : opcode_deps_0f0f;
+                }
+                else
+                {
+                        ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+                        deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
+                }
+                break;
+
+                case 0xd8:
+                ins_table = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
+                deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xd9:
+                ins_table = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
+                deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xda:
+                ins_table = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
+                deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdb:
+                ins_table = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
+                deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xdc:
+                ins_table = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
+                deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdd:
+                ins_table = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
+                deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xde:
+                ins_table = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
+                deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdf:
+                ins_table = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
+                deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
+                opcode = (opcode >> 3) & 7;
+                break;
+
+                default:
+                switch (opcode)
+                {
+                        case 0x80: case 0x82:
+                        ins_table = mod3 ? opcode_timings_80_mod3 : opcode_timings_80;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0x81: case 0x83:
+                        ins_table = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        case 0xc0: case 0xd0: case 0xd2:
+                        ins_table = mod3 ? opcode_timings_shift_b_mod3 : opcode_timings_shift_b;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        
+                        case 0xc1: case 0xd1: case 0xd3:
+                        ins_table = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        case 0xf6:
+                        ins_table = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
+                        deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xf7:
+                        ins_table = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
+                        deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xff:
+                        ins_table = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
+                        deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        default:
+                        ins_table = mod3 ? opcode_timings_mod3 : opcode_timings;
+                        deps = mod3 ? opcode_deps_mod3 : opcode_deps;
+                        break;
+                }
+        }
+
+        if (ins_table[opcode])
+                decode_instruction(ins_table[opcode], deps[opcode], fetchdat, op_32, bit8);
+        else
+                decode_instruction(&vector_alu1_op, 0, fetchdat, op_32, bit8);
+        codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
+}
+
+void codegen_timing_k6_block_end()
+{
+        if (decode_buffer.nr_uops)
+        {
+                int old_last_complete_timestamp = last_complete_timestamp;
+                decode_flush();
+                codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
+        }
+}
+
+int codegen_timing_k6_jump_cycles()
+{
+        if (decode_buffer.nr_uops)
+                return 1;
+        return 0;
+}
+
+codegen_timing_t codegen_timing_k6 =
+{
+        codegen_timing_k6_start,
+        codegen_timing_k6_prefix,
+        codegen_timing_k6_opcode,
+        codegen_timing_k6_block_start,
+        codegen_timing_k6_block_end,
+        codegen_timing_k6_jump_cycles
+};
diff --git a/src/cpu/codegen_timing_p6.c b/src/cpu/codegen_timing_p6.c
new file mode 100644
index 000000000..0cddde494
--- /dev/null
+++ b/src/cpu/codegen_timing_p6.c
@@ -0,0 +1,2330 @@
+/*Hacky P6 timings based on K6 timings*/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <wchar.h>
+#include <86box/86box.h>
+#include "cpu.h"
+#include <86box/mem.h>
+#include <86box/machine.h>
+
+#include "x86.h"
+#include "x86_ops.h"
+#include "x87.h"
+#include "386_common.h"
+#include "codegen.h"
+#include "codegen_ops.h"
+#include "codegen_timing_common.h"
+
+typedef enum uop_type_t
+{
+        UOP_ALU = 0,   /*Executes in Integer X or Y units*/
+        UOP_ALUX,      /*Executes in Integer X unit*/
+        UOP_LOAD,      /*Executes in Load unit*/
+        UOP_STORE,     /*Executes in Store unit*/
+        UOP_FLOAD,     /*Executes in Load unit*/
+        UOP_FSTORE,    /*Executes in Store unit*/
+        UOP_MLOAD,     /*Executes in Load unit*/
+        UOP_MSTORE,    /*Executes in Store unit*/
+        UOP_FLOAT,     /*Executes in Floating Point unit*/
+        UOP_MEU,       /*Executes in Multimedia unit*/
+        UOP_MEU_SHIFT, /*Executes in Multimedia unit or ALU X/Y. Uses MMX shifter*/
+        UOP_MEU_MUL,   /*Executes in Multimedia unit or ALU X/Y. Uses MMX multiplier*/
+        UOP_BRANCH,    /*Executes in Branch unit*/
+        UOP_LIMM       /*Does not require an execution unit*/
+} uop_type_t;
+
+typedef enum decode_type_t
+{
+        DECODE_SHORT,
+        DECODE_LONG,
+        DECODE_VECTOR
+} decode_type_t;
+
+#define MAX_UOPS 10
+
+typedef struct risc86_uop_t
+{
+        uop_type_t type;
+        double throughput;
+        double latency;
+} risc86_uop_t;
+
+typedef struct risc86_instruction_t
+{
+        int nr_uops;
+        decode_type_t decode_type;
+        risc86_uop_t uop[MAX_UOPS];
+} risc86_instruction_t;
+
+static const risc86_instruction_t alu_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alux_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alu_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t alux_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t branch_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t limm_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LIMM, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t load_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t store_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+
+
+static const risc86_instruction_t bswap_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t leave_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t lods_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t mov_reg_seg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+};
+static const risc86_instruction_t movs_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pop_reg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pop_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t push_imm_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_STORE,  .throughput = 1, .latency = 2},
+};
+static const risc86_instruction_t push_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t push_seg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t stos_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_reg_b_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_mem_imm_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t test_mem_imm_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t xchg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_LONG,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+
+
+static const risc86_instruction_t mmx_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t mmx_mul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 3}
+};
+static const risc86_instruction_t mmx_shift_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t load_mmx_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU,  .throughput = 1.5, .latency = 3}
+};
+static const risc86_instruction_t load_mmx_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t load_mmx_shift_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,      .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_SHIFT, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t mload_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MLOAD, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t mstore_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MSTORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t pmul_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t pmul_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_LOAD,    .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_MEU_MUL, .throughput = 1, .latency = 2}
+};
+
+static const risc86_instruction_t float_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t load_float_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .throughput = 1.5, .latency = 1.5}
+};
+static const risc86_instruction_t fstore_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t fdiv_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+};
+static const risc86_instruction_t fdiv_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAT, .throughput = 38, .latency = 38}
+};
+static const risc86_instruction_t fsin_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 62, .latency = 62}
+};
+static const risc86_instruction_t fsqrt_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_SHORT,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 49, .latency = 49}
+};
+
+static const risc86_instruction_t vector_fldcw_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 8, .latency = 8}
+};
+static const risc86_instruction_t vector_float_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_float_l_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 50, .latency = 50}
+};
+static const risc86_instruction_t vector_flde_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_FLOAD, .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2}
+};
+static const risc86_instruction_t vector_fste_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_FLOAT, .throughput = 2, .latency = 2},
+        .uop[1] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+
+static const risc86_instruction_t vector_alu1_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu2_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu3_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu6_op =
+{
+        .nr_uops = 6,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux1_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux3_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux6_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alu_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_alux_store_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_arpl_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_bound_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_bsx_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_call_far_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_STORE,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cli_sti_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 7, .latency = 7}
+};
+static const risc86_instruction_t vector_cmps_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cmpsb_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_cmpxchg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+};
+static const risc86_instruction_t vector_cmpxchg_b_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+};
+static const risc86_instruction_t vector_cpuid_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 22, .latency = 22}
+};
+static const risc86_instruction_t vector_div16_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_div16_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_div32_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
+};
+static const risc86_instruction_t vector_div32_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 18, .latency = 18}
+};
+static const risc86_instruction_t vector_emms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 25, .latency = 25}
+};
+static const risc86_instruction_t vector_enter_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE,  .throughput =  1, .latency =  2},
+        .uop[1] = {.type = UOP_ALU,    .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_femms_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 6, .latency = 6}
+};
+static const risc86_instruction_t vector_in_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 10, .latency = 11}
+};
+static const risc86_instruction_t vector_ins_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 10, .latency = 11},
+        .uop[1] = {.type = UOP_STORE, .throughput =  1, .latency =  1},
+        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_int_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
+        .uop[1] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[2] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[3] = {.type = UOP_STORE,  .throughput =  1, .latency =  1},
+        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_iret_op =
+{
+        .nr_uops = 5,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[1] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[2] = {.type = UOP_LOAD,   .throughput =  1, .latency =  2},
+        .uop[3] = {.type = UOP_ALU,    .throughput = 20, .latency = 20},
+        .uop[4] = {.type = UOP_BRANCH, .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_invd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 1000, .latency = 1000}
+};
+static const risc86_instruction_t vector_jmp_far_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_load_alu_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_load_alux_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_loop_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_lss_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mov_mem_seg_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mov_seg_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mov_seg_reg_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 3, .latency = 3}
+};
+static const risc86_instruction_t vector_mul_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul64_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_mul64_mem_op =
+{
+        .nr_uops = 4,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALUX, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_out_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 10, .latency = 10}
+};
+static const risc86_instruction_t vector_outs_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput =  1, .latency =  1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 10, .latency = 10},
+        .uop[2] = {.type = UOP_ALU,   .throughput =  1, .latency =  1}
+};
+static const risc86_instruction_t vector_pusha_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[6] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[7] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_popa_op =
+{
+        .nr_uops = 8,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[3] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[4] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[5] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[6] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[7] = {.type = UOP_LOAD, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_popf_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput =  1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 17, .latency = 17}
+};
+static const risc86_instruction_t vector_push_mem_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_pushf_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_ret_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_retf_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,   .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,    .throughput = 3, .latency = 3},
+        .uop[2] = {.type = UOP_BRANCH, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_scas_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_scasb_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_setcc_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,   .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_FSTORE, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_setcc_reg_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_ALUX,  .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU,   .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_test_mem_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALU,  .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_test_mem_b_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 2},
+        .uop[1] = {.type = UOP_ALUX, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_xchg_mem_op =
+{
+        .nr_uops = 3,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_LOAD, .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_STORE, .throughput = 1, .latency = 1},
+        .uop[2] = {.type = UOP_ALU, .throughput = 1, .latency = 1}
+};
+static const risc86_instruction_t vector_xlat_op =
+{
+        .nr_uops = 2,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU,   .throughput = 1, .latency = 1},
+        .uop[1] = {.type = UOP_LOAD,  .throughput = 1, .latency = 2}
+};
+static const risc86_instruction_t vector_wbinvd_op =
+{
+        .nr_uops = 1,
+        .decode_type = DECODE_VECTOR,
+        .uop[0] = {.type = UOP_ALU, .throughput = 10000, .latency = 10000}
+};
+
+#define INVALID NULL
+
+static const risc86_instruction_t *opcode_timings[256] =
+{
+/*      ADD                    ADD                    ADD                   ADD*/
+/*00*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      ADD                    ADD                    PUSH ES               POP ES*/
+        &alux_op,              &alu_op,               &push_seg_op,         &vector_mov_seg_mem_op,
+/*      OR                     OR                     OR                    OR*/
+        &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      OR                     OR                     PUSH CS               */
+        &alux_op,              &alu_op,               &push_seg_op,         INVALID,
+
+/*      ADC                    ADC                    ADC                   ADC*/
+/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*      ADC                    ADC                    PUSH SS               POP SS*/
+        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+/*      SBB                    SBB                    SBB                   SBB*/
+/*10*/  &vector_alux_store_op, &vector_alu_store_op,  &vector_load_alux_op, &vector_load_alu_op,
+/*      SBB                    SBB                    PUSH DS               POP DS*/
+        &vector_alux1_op,      &vector_alu1_op,       &push_seg_op,         &vector_mov_seg_mem_op,
+
+/*      AND                    AND                    AND                   AND*/
+/*20*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      AND                    AND                                          DAA*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+/*      SUB                    SUB                    SUB                   SUB*/
+        &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      SUB                    SUB                                          DAS*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux1_op,
+
+/*      XOR                    XOR                    XOR                   XOR*/
+/*30*/  &alux_store_op,        &alu_store_op,         &load_alux_op,        &load_alu_op,
+/*      XOR                    XOR                                          AAA*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+/*      CMP                    CMP                    CMP                   CMP*/
+        &load_alux_op,         &load_alu_op,          &load_alux_op,        &load_alu_op,
+/*      CMP                    CMP                                          AAS*/
+        &alux_op,              &alu_op,               INVALID,              &vector_alux6_op,
+
+/*      INC EAX                INC ECX                INC EDX                INC EBX*/
+/*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      INC ESP                INC EBP                INC ESI                INC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC EAX                DEC ECX                DEC EDX                DEC EBX*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC ESP                DEC EBP                DEC ESI                DEC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+
+/*      PUSH EAX               PUSH ECX               PUSH EDX               PUSH EBX*/
+/*50*/  &store_op,             &store_op,             &store_op,             &store_op,
+/*      PUSH ESP               PUSH EBP               PUSH ESI               PUSH EDI*/
+        &store_op,             &store_op,             &store_op,             &store_op,
+/*      POP EAX                POP ECX                POP EDX                POP EBX*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+/*      POP ESP                POP EBP                POP ESI                POP EDI*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+
+/*      PUSHA                  POPA                   BOUND                  ARPL*/
+/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+        INVALID,               INVALID,               INVALID,               INVALID,
+/*      PUSH imm               IMUL                   PUSH imm               IMUL*/
+        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+/*      INSB                   INSW                   OUTSB                  OUTSW*/
+        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+
+/*      Jxx*/
+/*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      TEST                       TEST                       XCHG                       XCHG*/
+        &vector_test_mem_b_op,     &vector_test_mem_op,       &vector_xchg_mem_op,       &vector_xchg_mem_op,
+/*      MOV                        MOV                        MOV                        MOV*/
+        &store_op,                 &store_op,                 &load_op,                  &load_op,
+/*      MOV from seg               LEA                        MOV to seg                 POP*/
+        &vector_mov_mem_seg_op,    &store_op,                 &vector_mov_seg_mem_op,    &pop_mem_op,
+
+/*      NOP                        XCHG                       XCHG                       XCHG*/
+/*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      XCHG                       XCHG                       XCHG                       XCHG*/
+        &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      CBW                        CWD                        CALL far                   WAIT*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+/*      PUSHF                      POPF                       SAHF                       LAHF*/
+        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+
+/*      MOV                        MOV                        MOV                        MOV*/
+/*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
+/*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
+        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+/*      TEST                       TEST                       STOSB                      STOSW*/
+        &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
+/*      LODSB                      LODSW                      SCASB                      SCASW*/
+        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+
+/*      MOV*/
+/*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+
+/*                                                            RET imm                    RET*/
+/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*      LES                        LDS                        MOV                        MOV*/
+        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+/*      ENTER                      LEAVE                      RETF                       RETF*/
+        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+/*      INT3                       INT                        INTO                       IRET*/
+        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+
+
+/*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      AAM                        AAD                        SETALC                     XLAT*/
+        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
+/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+/*      CALL                       JMP                        JMP                        JMP*/
+        &store_op,                 &branch_op,                &vector_jmp_far_op,           &branch_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+
+/*                                                            REPNE                      REPE*/
+/*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      HLT                        CMC*/
+        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+/*      CLC                        STC                        CLI                        STI*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+/*      CLD                        STD                        INCDEC*/
+        &vector_alu1_op,           &vector_alu1_op,           &alux_store_op,            INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_mod3[256] =
+{
+/*      ADD                       ADD                       ADD                       ADD*/
+/*00*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      ADD                       ADD                       PUSH ES                   POP ES*/
+        &alux_op,                 &alu_op,                  &push_seg_op,             &vector_mov_seg_mem_op,
+/*      OR                        OR                        OR                        OR*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      OR                        OR                        PUSH CS                   */
+        &alux_op,                 &alu_op,                  &push_seg_op,             INVALID,
+
+/*      ADC                       ADC                       ADC                       ADC*/
+/*10*/  &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*      ADC                       ADC                       PUSH SS                   POP SS*/
+        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+/*      SBB                       SBB                       SBB                       SBB*/
+        &vector_alux1_op,         &vector_alu1_op,          &vector_alux1_op,         &vector_alu1_op,
+/*      SBB                       SBB                       PUSH DS                   POP DS*/
+        &vector_alux1_op,         &vector_alu1_op,          &push_seg_op,             &vector_mov_seg_mem_op,
+
+/*      AND                       AND                       AND                       AND*/
+/*20*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      AND                       AND                                                 DAA*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+/*      SUB                       SUB                       SUB                       SUB*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      SUB                       SUB                                                 DAS*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux1_op,
+
+/*      XOR                       XOR                       XOR                       XOR*/
+/*30*/  &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      XOR                       XOR                                                 AAA*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+/*      CMP                       CMP                       CMP                       CMP*/
+        &alux_op,                 &alu_op,                  &alux_op,                 &alu_op,
+/*      CMP                       CMP                                                 AAS*/
+        &alux_op,                 &alu_op,                  INVALID,                  &vector_alux6_op,
+
+/*      INC EAX                INC ECX                INC EDX                INC EBX*/
+/*40*/  &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      INC ESP                INC EBP                INC ESI                INC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC EAX                DEC ECX                DEC EDX                DEC EBX*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+/*      DEC ESP                DEC EBP                DEC ESI                DEC EDI*/
+        &alu_op,               &alu_op,               &alu_op,               &alu_op,
+
+/*      PUSH EAX               PUSH ECX               PUSH EDX               PUSH EBX*/
+/*50*/  &store_op,             &store_op,             &store_op,             &store_op,
+/*      PUSH ESP               PUSH EBP               PUSH ESI               PUSH EDI*/
+        &store_op,             &store_op,             &store_op,             &store_op,
+/*      POP EAX                POP ECX                POP EDX                POP EBX*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+/*      POP ESP                POP EBP                POP ESI                POP EDI*/
+        &pop_reg_op,           &pop_reg_op,           &pop_reg_op,           &pop_reg_op,
+
+/*      PUSHA                  POPA                   BOUND                  ARPL*/
+/*60*/  &vector_pusha_op,      &vector_popa_op,       &vector_bound_op,      &vector_arpl_op,
+        INVALID,               INVALID,               INVALID,               INVALID,
+/*      PUSH imm               IMUL                   PUSH imm               IMUL*/
+        &push_imm_op,          &vector_mul_op,        &push_imm_op,          &vector_mul_op,
+/*      INSB                   INSW                   OUTSB                  OUTSW*/
+        &vector_ins_op,        &vector_ins_op,        &vector_outs_op,       &vector_outs_op,
+
+/*      Jxx*/
+/*70*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*80*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      TEST                       TEST                       XCHG                       XCHG*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_alu3_op,           &vector_alu3_op,
+/*      MOV                        MOV                        MOV                        MOV*/
+        &store_op,                 &store_op,                 &load_op,                  &load_op,
+/*      MOV from seg               LEA                        MOV to seg                 POP*/
+        &mov_reg_seg_op,           &store_op,                 &vector_mov_seg_reg_op,    &pop_reg_op,
+
+/*      NOP                        XCHG                       XCHG                       XCHG*/
+/*90*/  &limm_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      XCHG                       XCHG                       XCHG                       XCHG*/
+        &xchg_op,                  &xchg_op,                  &xchg_op,                  &xchg_op,
+/*      CBW                        CWD                        CALL far                   WAIT*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_call_far_op,       &limm_op,
+/*      PUSHF                      POPF                       SAHF                       LAHF*/
+        &vector_pushf_op,          &vector_popf_op,           &vector_alux1_op,          &vector_alux1_op,
+
+/*      MOV                        MOV                        MOV                        MOV*/
+/*a0*/  &load_op,                  &load_op,                  &store_op,                 &store_op,
+/*      MOVSB                      MOVSW                      CMPSB                      CMPSW*/
+        &movs_op,                  &movs_op,                  &vector_cmpsb_op,          &vector_cmps_op,
+/*      TEST                       TEST                       STOSB                      STOSW*/
+        &test_reg_b_op,            &test_reg_op,              &stos_op,                  &stos_op,
+/*      LODSB                      LODSW                      SCASB                      SCASW*/
+        &lods_op,                  &lods_op,                  &vector_scasb_op,          &vector_scas_op,
+
+/*      MOV*/
+/*b0*/  &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+        &limm_op,       &limm_op,       &limm_op,       &limm_op,
+
+/*                                                            RET imm                    RET*/
+/*c0*/  INVALID,                   INVALID,                   &vector_ret_op,            &vector_ret_op,
+/*      LES                        LDS                        MOV                        MOV*/
+        &vector_lss_op,            &vector_lss_op,            &store_op,                 &store_op,
+/*      ENTER                      LEAVE                      RETF                       RETF*/
+        &vector_enter_op,          &leave_op,                 &vector_retf_op,           &vector_retf_op,
+/*      INT3                       INT                        INTO                       IRET*/
+        &vector_int_op,            &vector_int_op,            &vector_int_op,            &vector_iret_op,
+
+
+/*d0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      AAM                        AAD                        SETALC                     XLAT*/
+        &vector_alux6_op,          &vector_alux3_op,          &vector_alux1_op,          &vector_xlat_op,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+        INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      LOOPNE                     LOOPE                      LOOP                       JCXZ*/
+/*e0*/  &vector_loop_op,           &vector_loop_op,           &loop_op,                  &vector_loop_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+/*      CALL                       JMP                        JMP                        JMP*/
+        &store_op,                 &branch_op,                &vector_jmp_far_op,        &branch_op,
+/*      IN AL                      IN AX                      OUT_AL                     OUT_AX*/
+        &vector_in_op,             &vector_in_op,             &vector_out_op,            &vector_out_op,
+
+/*                                                            REPNE                      REPE*/
+/*f0*/  INVALID,                   INVALID,                   INVALID,                   INVALID,
+/*      HLT                        CMC*/
+        &vector_alux1_op,          &vector_alu2_op,           INVALID,                   INVALID,
+/*      CLC                        STC                        CLI                        STI*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_cli_sti_op,        &vector_cli_sti_op,
+/*      CLD                        STD                        INCDEC*/
+        &vector_alu1_op,           &vector_alu1_op,           &vector_alux1_op,          INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_0f[256] =
+{
+/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
+        INVALID,                &load_op,               &vector_femms_op,       INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &load_mmx_op,
+        INVALID,                INVALID,                &mload_op,              &mload_op,
+
+/*70*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           &vector_emms_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                &mstore_op,             &mstore_op,
+
+/*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*90*/  &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+        &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op, &vector_setcc_reg_op,
+
+/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_load_alu_op,
+        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                INVALID,
+        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_load_alu_op,
+        &vector_alu_store_op, &vector_alu_store_op,     INVALID,                &vector_mul_op,
+
+/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_load_alu_op,
+        &vector_lss_op,         &vector_lss_op,         &load_alux_op,          &load_alu_op,
+        INVALID,                INVALID,                &vector_load_alu_op,    &vector_load_alu_op,
+        &vector_bsx_op,         &vector_bsx_op,         &load_alux_op,          &load_alu_op,
+
+/*c0*/  &vector_alux_store_op,  &vector_alu_store_op,   INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &vector_cmpxchg_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+
+/*d0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                &load_mmx_mul_op,       INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+
+/*e0*/  &load_mmx_op,           &load_mmx_shift_op,     &load_mmx_shift_op,     INVALID,
+        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+        &load_mmx_op,           &load_mmx_op,           INVALID,                &load_mmx_op,
+
+/*f0*/  INVALID,                &load_mmx_shift_op,     &load_mmx_shift_op,     &load_mmx_shift_op,
+        INVALID,                &pmul_mem_op,           INVALID,                INVALID,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+        &load_mmx_op,           &load_mmx_op,           &load_mmx_op,           INVALID,
+};
+static const risc86_instruction_t *opcode_timings_0f_mod3[256] =
+{
+/*00*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        INVALID,                &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        &vector_invd_op,        &vector_wbinvd_op,      INVALID,                INVALID,
+        INVALID,                INVALID,                &vector_femms_op,       INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*20*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,
+        &vector_alu6_op,        &vector_alu6_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  &vector_alu6_op,        &vector_alu6_op,        &vector_alu6_op,        INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &mmx_op,
+        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+
+/*70*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        &mmx_op,                &mmx_op,                &mmx_op,                &vector_emms_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                &mmx_op,                &mmx_op,
+
+/*80*/  &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+        &branch_op,     &branch_op,     &branch_op,     &branch_op,
+
+/*90*/  &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+        &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op, &vector_setcc_mem_op,
+
+/*a0*/  &push_seg_op,         &vector_mov_seg_mem_op,   &vector_cpuid_op,       &vector_alu1_op,
+        &vector_alu1_op,      &vector_alu1_op,          INVALID,                INVALID,
+        &push_seg_op,         &vector_mov_seg_mem_op,   INVALID,                &vector_alu1_op,
+        &vector_alu1_op,      &vector_alu1_op,          INVALID,                &vector_mul_op,
+
+/*b0*/  &vector_cmpxchg_b_op,   &vector_cmpxchg_op,     &vector_lss_op,         &vector_alu1_op,
+        &vector_lss_op,         &vector_lss_op,         &alux_op,               &alu_op,
+        INVALID,                INVALID,                &vector_alu1_op,        &vector_alu1_op,
+        &vector_bsx_op,         &vector_bsx_op,         &alux_op,               &alu_op,
+
+/*c0*/  &vector_alux1_op,       &vector_alu1_op,        INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+        &bswap_op,              &bswap_op,              &bswap_op,              &bswap_op,
+
+/*d0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        INVALID,                &mmx_mul_op,            INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+
+/*e0*/  &mmx_op,                &mmx_shift_op,          &mmx_shift_op,          INVALID,
+        INVALID,                &pmul_op,               INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+        &mmx_op,                &mmx_op,                INVALID,                &mmx_op,
+
+/*f0*/  INVALID,                &mmx_shift_op,          &mmx_shift_op,          &mmx_shift_op,
+        INVALID,                &pmul_op,               INVALID,                INVALID,
+        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+        &mmx_op,                &mmx_op,                &mmx_op,                INVALID,
+};
+
+static const risc86_instruction_t *opcode_timings_0f0f[256] =
+{
+/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,           	INVALID,                INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,           	INVALID,                INVALID,
+
+/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*90*/  INVALID,          	INVALID,                INVALID,           	INVALID,
+        INVALID,          	INVALID,                INVALID,           	INVALID,
+        INVALID,                INVALID,                INVALID,           	INVALID,
+        INVALID,                INVALID,                INVALID,           	INVALID,
+
+/*a0*/  INVALID,           	INVALID,                INVALID,                INVALID,
+        INVALID,           	INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
+        INVALID,                INVALID,               	INVALID,          	INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*b0*/  INVALID,           	INVALID,                INVALID,                INVALID,
+        &load_mmx_mul_op,       INVALID,                &load_mmx_mul_op,       &load_mmx_mul_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &load_mmx_op,
+
+/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+};
+static const risc86_instruction_t *opcode_timings_0f0f_mod3[256] =
+{
+/*00*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*10*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*20*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*30*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*40*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*50*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*60*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*70*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*80*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*90*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,               INVALID,
+        INVALID,                INVALID,                INVALID,               INVALID,
+        INVALID,                INVALID,                INVALID,               INVALID,
+
+/*a0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                &mmx_mul_op,            &mmx_mul_op,
+        INVALID,                INVALID,                INVALID,               INVALID,
+        INVALID,                INVALID,                INVALID,               INVALID,
+
+/*b0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        &mmx_mul_op,            INVALID,                &mmx_mul_op,            &mmx_mul_op,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                &mmx_op,
+
+/*c0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*d0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*e0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+/*f0*/  INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+        INVALID,                INVALID,                INVALID,                INVALID,
+
+};
+
+static const risc86_instruction_t *opcode_timings_shift[8] =
+{
+        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,
+        &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op,   &vector_alu_store_op
+};
+static const risc86_instruction_t *opcode_timings_shift_b[8] =
+{
+        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,
+        &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op,  &vector_alux_store_op
+};
+static const risc86_instruction_t *opcode_timings_shift_mod3[8] =
+{
+        &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,   &vector_alu1_op,
+        &alu_op,           &alu_op,           &alu_op,           &alu_op
+};
+static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] =
+{
+        &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,  &vector_alux1_op,
+        &alux_op,          &alux_op,          &alux_op,          &alux_op
+};
+
+static const risc86_instruction_t *opcode_timings_80[8] =
+{
+        &alux_store_op, &alux_store_op, &vector_alux_store_op,  &vector_alux_store_op,
+        &alux_store_op, &alux_store_op, &alux_store_op,         &alux_store_op,
+};
+static const risc86_instruction_t *opcode_timings_80_mod3[8] =
+{
+        &alux_op,       &alux_op,       &alux_store_op,         &alux_store_op,
+        &alux_op,       &alux_op,       &alux_op,               &alux_op,
+};
+static const risc86_instruction_t *opcode_timings_8x[8] =
+{
+        &alu_store_op,  &alu_store_op,  &vector_alu_store_op,   &vector_alu_store_op,
+        &alu_store_op,  &alu_store_op,  &alu_store_op,          &alu_store_op,
+};
+static const risc86_instruction_t *opcode_timings_8x_mod3[8] =
+{
+        &alu_op,        &alu_op,        &alu_store_op,          &alu_store_op,
+        &alu_op,        &alu_op,        &alu_op,                &alu_op,
+};
+
+static const risc86_instruction_t *opcode_timings_f6[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_mem_imm_b_op,     INVALID,                &vector_alux_store_op,  &vector_alux_store_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul_mem_op,     &vector_mul_mem_op,     &vector_div16_mem_op,   &vector_div16_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_f6_mod3[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_reg_b_op,         INVALID,                &alux_op,               &alux_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul_op,         &vector_mul_op,         &vector_div16_op,       &vector_div16_op,
+};
+static const risc86_instruction_t *opcode_timings_f7[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_mem_imm_op,       INVALID,                &vector_alu_store_op,   &vector_alu_store_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul64_mem_op,   &vector_mul64_mem_op,   &vector_div32_mem_op,   &vector_div32_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_f7_mod3[8] =
+{
+/*      TST                                             NOT                     NEG*/
+        &test_reg_op,           INVALID,                &alu_op,                &alu_op,
+/*      MUL                     IMUL                    DIV                     IDIV*/
+        &vector_mul64_op,       &vector_mul64_op,       &vector_div32_op,       &vector_div32_op,
+};
+static const risc86_instruction_t *opcode_timings_ff[8] =
+{
+/*      INC                     DEC                     CALL                    CALL far*/
+        &alu_store_op,          &alu_store_op,          &store_op,              &vector_call_far_op,
+/*      JMP                     JMP far                 PUSH*/
+        &branch_op,             &vector_jmp_far_op,     &push_mem_op,           INVALID
+};
+static const risc86_instruction_t *opcode_timings_ff_mod3[8] =
+{
+/*      INC                     DEC                     CALL                    CALL far*/
+        &vector_alu1_op,        &vector_alu1_op,        &store_op,              &vector_call_far_op,
+/*      JMP                     JMP far                 PUSH*/
+        &branch_op,             &vector_jmp_far_op,     &vector_push_mem_op,    INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_d8[8] =
+{
+/*      FADDs            FMULs            FCOMs            FCOMPs*/
+        &load_float_op,  &load_float_op,  &load_float_op,  &load_float_op,
+/*      FSUBs            FSUBRs           FDIVs            FDIVRs*/
+        &load_float_op,  &load_float_op,  &fdiv_mem_op,    &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_d8_mod3[8] =
+{
+/*      FADD             FMUL             FCOM             FCOMP*/
+        &float_op,       &float_op,       &float_op,       &float_op,
+/*      FSUB             FSUBR            FDIV             FDIVR*/
+        &float_op,       &float_op,       &fdiv_op,        &fdiv_op,
+};
+
+static const risc86_instruction_t *opcode_timings_d9[8] =
+{
+/*      FLDs                                    FSTs                 FSTPs*/
+        &load_float_op,      INVALID,           &fstore_op,          &fstore_op,
+/*      FLDENV               FLDCW              FSTENV               FSTCW*/
+        &vector_float_l_op,  &vector_fldcw_op,  &vector_float_l_op,  &vector_float_op
+};
+static const risc86_instruction_t *opcode_timings_d9_mod3[64] =
+{
+        /*FLD*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+        /*FXCH*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+        /*FNOP*/
+        &float_op,    INVALID,      INVALID,      INVALID,
+        INVALID,      INVALID,      INVALID,      INVALID,
+        /*FSTP*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+        &float_op,    &float_op,    &float_op,    &float_op,
+/*      opFCHS        opFABS*/
+        &float_op,    &float_op,    INVALID,      INVALID,
+/*      opFTST        opFXAM*/
+        &float_op,    &float_op,    INVALID,      INVALID,
+/*      opFLD1        opFLDL2T      opFLDL2E      opFLDPI*/
+        &float_op,    &float_op,    &float_op,    &float_op,
+/*      opFLDEG2      opFLDLN2      opFLDZ*/
+        &float_op,    &float_op,    &float_op,    INVALID,
+/*      opF2XM1       opFYL2X       opFPTAN       opFPATAN*/
+        &fsin_op,     &fsin_op,     &fsin_op,     &fsin_op,
+/*                                  opFDECSTP     opFINCSTP,*/
+        INVALID,      INVALID,      &float_op,    &float_op,
+/*      opFPREM                     opFSQRT       opFSINCOS*/
+        &fdiv_op,     INVALID,      &fsqrt_op,    &fsin_op,
+/*      opFRNDINT     opFSCALE      opFSIN        opFCOS*/
+        &float_op,    &fdiv_op,     &fsin_op,     &fsin_op
+};
+
+static const risc86_instruction_t *opcode_timings_da[8] =
+{
+/*      FIADDl            FIMULl            FICOMl            FICOMPl*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FISUBl            FISUBRl           FIDIVl            FIDIVRl*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_da_mod3[8] =
+{
+        INVALID,          INVALID,          INVALID,          INVALID,
+/*                        FCOMPP*/
+        INVALID,          &float_op,        INVALID,          INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_db[8] =
+{
+/*      FLDil                               FSTil         FSTPil*/
+        &load_float_op,   INVALID,          &fstore_op,   &fstore_op,
+/*                        FLDe                            FSTPe*/
+        INVALID,          &vector_flde_op,  INVALID,      &vector_fste_op
+};
+static const risc86_instruction_t *opcode_timings_db_mod3[64] =
+{
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+/*                        opFNOP            opFCLEX       opFINIT*/
+        INVALID,          &float_op,        &float_op,    &float_op,
+/*      opFNOP            opFNOP*/
+        &float_op,        &float_op,        INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+
+        INVALID,          INVALID,          INVALID,      INVALID,
+        INVALID,          INVALID,          INVALID,      INVALID,
+};
+
+static const risc86_instruction_t *opcode_timings_dc[8] =
+{
+/*      FADDd             FMULd             FCOMd             FCOMPd*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FSUBd             FSUBRd            FDIVd             FDIVRd*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_dc_mod3[8] =
+{
+/*      opFADDr           opFMULr*/
+        &float_op,        &float_op,        INVALID,          INVALID,
+/*      opFSUBRr          opFSUBr           opFDIVRr          opFDIVr*/
+        &float_op,        &float_op,        &fdiv_op,         &fdiv_op
+};
+
+static const risc86_instruction_t *opcode_timings_dd[8] =
+{
+/*      FLDd                                    FSTd                 FSTPd*/
+        &load_float_op,     INVALID,            &fstore_op,          &fstore_op,
+/*      FRSTOR                                  FSAVE                FSTSW*/
+        &vector_float_l_op, INVALID,            &vector_float_l_op,  &vector_float_l_op
+};
+static const risc86_instruction_t *opcode_timings_dd_mod3[8] =
+{
+/*      FFFREE                            FST                FSTP*/
+        &float_op,       INVALID,         &float_op,         &float_op,
+/*      FUCOM            FUCOMP*/
+        &float_op,       &float_op,       INVALID,           INVALID
+};
+
+static const risc86_instruction_t *opcode_timings_de[8] =
+{
+/*      FIADDw            FIMULw            FICOMw            FICOMPw*/
+        &load_float_op,   &load_float_op,   &load_float_op,   &load_float_op,
+/*      FISUBw            FISUBRw           FIDIVw            FIDIVRw*/
+        &load_float_op,   &load_float_op,   &fdiv_mem_op,     &fdiv_mem_op,
+};
+static const risc86_instruction_t *opcode_timings_de_mod3[8] =
+{
+/*      FADDP            FMULP                          FCOMPP*/
+        &float_op,       &float_op,       INVALID,      &float_op,
+/*      FSUBP            FSUBRP           FDIVP         FDIVRP*/
+        &float_op,       &float_op,       &fdiv_op,     &fdiv_op,
+};
+
+static const risc86_instruction_t *opcode_timings_df[8] =
+{
+/*      FILDiw                              FISTiw               FISTPiw*/
+        &load_float_op,   INVALID,          &fstore_op,          &fstore_op,
+/*                        FILDiq            FBSTP                FISTPiq*/
+        INVALID,          &load_float_op,   &vector_float_l_op,  &fstore_op,
+};
+static const risc86_instruction_t *opcode_timings_df_mod3[8] =
+{
+        INVALID,      INVALID,      INVALID,      INVALID,
+/*      FSTSW AX*/
+        &float_op,    INVALID,      INVALID,      INVALID
+};
+
+
+static uint8_t last_prefix;
+static int prefixes;
+
+static int decode_timestamp;
+static int last_complete_timestamp;
+
+typedef struct p6_unit_t
+{
+        uint32_t uop_mask;
+        double first_available_cycle;
+} p6_unit_t;
+
+static int nr_units;
+static p6_unit_t *units;
+
+/*Pentium Pro has no MMX*/
+static p6_unit_t ppro_units[] =
+{
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX)},                                 /*Integer X*/
+        {.uop_mask = (1 << UOP_ALU)},                                                   /*Integer Y*/
+        {.uop_mask = (1 << UOP_FLOAT)},                                                 /*Floating point*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},          /*Load*/
+        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)},         /*Store*/
+        {.uop_mask = (1 << UOP_BRANCH)}                                                 /*Branch*/
+};
+#define NR_PPRO_UNITS (sizeof(ppro_units) / sizeof(p6_unit_t))
+
+/*Well, it works I guess*/
+static p6_unit_t p2_units[] =
+{
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_MEU) |        /*Integer X*/
+                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
+        {.uop_mask = (1 << UOP_ALU) | (1 << UOP_MEU) |                          /*Integer Y*/
+                        (1 << UOP_MEU_SHIFT) | (1 << UOP_MEU_MUL)},
+        {.uop_mask = (1 << UOP_FLOAT)},                                         	/*Floating point*/
+        {.uop_mask = (1 << UOP_LOAD)  | (1 << UOP_FLOAD)  | (1 << UOP_MLOAD)},  	/*Load*/
+        {.uop_mask = (1 << UOP_STORE) | (1 << UOP_FSTORE) | (1 << UOP_MSTORE)}, 	/*Store*/
+        {.uop_mask = (1 << UOP_BRANCH)}                                         	/*Branch*/
+};
+#define NR_P2_UNITS (sizeof(p2_units) / sizeof(p6_unit_t))
+
+/*First available cycles of shared execution units. Each of these can be submitted
+  to by ALU X and Y*/
+static int mul_first_available_cycle;
+static int shift_first_available_cycle;
+
+static int uop_run(const risc86_uop_t *uop, int decode_time)
+{
+        int c;
+        p6_unit_t *best_unit = NULL;
+        double best_start_cycle = 99999;
+        
+        /*UOP_LIMM does not require execution*/
+        if (uop->type == UOP_LIMM)
+                return decode_time;
+	
+        if (units == p2_units) /*More hackyness*/
+        {
+                if (uop->type == UOP_MEU_MUL && decode_time < mul_first_available_cycle)
+                        decode_time = mul_first_available_cycle;
+                else if (uop->type == UOP_MEU_SHIFT && decode_time < mul_first_available_cycle)
+                        decode_time = shift_first_available_cycle;
+        }
+
+        /*Find execution unit for this uOP*/
+        for (c = 0; c < nr_units; c++)
+        {
+                if (units[c].uop_mask & (1 << uop->type))
+                {
+                        if (units[c].first_available_cycle < best_start_cycle)
+                        {
+                                best_unit = &units[c];
+                                best_start_cycle = units[c].first_available_cycle;
+                        }
+                }
+        }
+        if (!best_unit)
+                fatal("uop_run: can not find execution unit\n");
+
+        if (best_start_cycle < decode_time)
+                best_start_cycle = decode_time;
+        best_unit->first_available_cycle = best_start_cycle + uop->throughput;
+	
+        if (units == p2_units) /*More hackyness*/
+        {
+                if (uop->type == UOP_MEU_MUL)
+                        mul_first_available_cycle = best_start_cycle + uop->throughput;
+                else if (uop->type == UOP_MEU_SHIFT)
+                        shift_first_available_cycle = best_start_cycle + uop->throughput;
+        }
+
+        return best_start_cycle + uop->throughput;
+}
+
+/*The K6 decoder can decode, per clock :
+  - 1 or 2 'short' instructions, each up to 2 uOPs and 7 bytes long
+  - 1 'long' instruction, up to 4 uOPs
+  - 1 'vector' instruction, up to 4 uOPs per cycle, plus (I think) 1 cycle startup delay)
+*/
+static struct
+{
+        int nr_uops;
+        const risc86_uop_t *uops[4];
+        /*Earliest time a uop can start. If the timestamp is -1, then the uop is
+          part of a dependency chain and the start time is the completion time of
+          the previous uop*/
+        int earliest_start[4];
+} decode_buffer;
+
+#define NR_OPQUADS 6
+/*Timestamps of when the last six opquads completed. The K6 scheduler retires
+  opquads in order, so this is needed to determine when the next can be scheduled*/
+static int opquad_completion_timestamp[NR_OPQUADS];
+static int next_opquad = 0;
+
+#define NR_REGS 8
+/*Timestamp of when last operation on an integer register completed*/
+static int reg_available_timestamp[NR_REGS];
+/*Timestamp of when last operation on an FPU register completed*/
+static int fpu_st_timestamp[8];
+/*Completion time of the last uop to be processed. Used to calculate timing of
+  dependent uop chains*/
+static int last_uop_timestamp = 0;
+
+void decode_flush_p6()
+{
+        int c;
+        int uop_timestamp = 0;
+
+        /*Decoded opquad can not be submitted if there are no free spaces in the
+          opquad buffer*/
+        if (decode_timestamp < opquad_completion_timestamp[next_opquad])
+                decode_timestamp = opquad_completion_timestamp[next_opquad];
+
+        /*Ensure that uops can not be submitted before they have been decoded*/
+        if (decode_timestamp > last_uop_timestamp)
+                last_uop_timestamp = decode_timestamp;
+
+        /*Submit uops to execution units, and determine the latest completion time*/
+        for (c = 0; c < decode_buffer.nr_uops; c++)
+        {
+                int start_timestamp;
+                
+                if (decode_buffer.earliest_start[c] == -1)
+                        start_timestamp = last_uop_timestamp;
+                else
+                        start_timestamp = decode_buffer.earliest_start[c];
+                
+                last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp);
+                if (last_uop_timestamp > uop_timestamp)
+                        uop_timestamp = last_uop_timestamp;
+        }
+
+        /*Calculate opquad completion time. Since opquads complete in order, it
+          must be after the last completion.*/
+        if (uop_timestamp <= last_complete_timestamp)
+                last_complete_timestamp = last_complete_timestamp + 1;
+        else
+                last_complete_timestamp = uop_timestamp;
+
+        /*Advance to next opquad in buffer*/
+        opquad_completion_timestamp[next_opquad] = last_complete_timestamp;
+        next_opquad++;
+        if (next_opquad == NR_OPQUADS)
+                next_opquad = 0;
+
+        decode_timestamp++;
+        decode_buffer.nr_uops = 0;
+}
+
+/*The instruction is only of interest here if it's longer than 7 bytes, as that's the
+  limit on K6 short decoding*/
+static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_32)
+{
+        int len = prefixes + 1; /*Opcode*/
+        if (deps & MODRM)
+        {
+                len++; /*ModR/M*/
+                if (deps & HAS_IMM8)
+                        len++;
+                if (deps & HAS_IMM1632)
+                        len += (op_32 & 0x100) ? 4 : 2;
+
+                if (op_32 & 0x200)
+                {
+                        if ((fetchdat & 7) == 4 && (fetchdat & 0xc0) != 0xc0)
+                        {
+                                /* Has SIB*/
+                                len++;
+                                if ((fetchdat & 0xc0) == 0x40)
+                                        len++;
+                                else if ((fetchdat & 0xc0) == 0x80)
+                                        len += 4;
+                                else if ((fetchdat & 0x700) == 0x500)
+                                        len += 4;
+                        }
+                        else
+                        {
+                                if ((fetchdat & 0xc0) == 0x40)
+                                        len++;
+                                else if ((fetchdat & 0xc0) == 0x80)
+                                        len += 4;
+                                else if ((fetchdat & 0xc7) == 0x05)
+                                        len += 4;
+                        }
+                }
+                else
+                {
+                        if ((fetchdat & 0xc0) == 0x40)
+                                len++;
+                        else if ((fetchdat & 0xc0) == 0x80)
+                                len += 2;
+                        else if ((fetchdat & 0xc7) == 0x06)
+                                len += 2;
+                }
+        }
+
+        return len;
+}
+
+static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8)
+{
+        uint32_t regmask_required;
+        uint32_t regmask_modified;
+        int c, d;
+        int earliest_start = 0;
+        decode_type_t decode_type = ins->decode_type;
+        int instr_length = codegen_timing_instr_length(deps, fetchdat, op_32);
+
+        /*Generate input register mask, and determine the earliest time this
+          instruction can start. This is not accurate, as this is calculated per
+          x86 instruction when it should be handled per uop*/
+        regmask_required = get_dstdep_mask(deps, fetchdat, bit8);
+        regmask_required |= get_addr_regmask(deps, fetchdat, op_32);
+        for (c = 0; c < 8; c++)
+        {
+                if (regmask_required & (1 << c))
+                {
+                        if (reg_available_timestamp[c] > decode_timestamp)
+                                earliest_start = reg_available_timestamp[c];
+                }
+        }
+        if ((deps & FPU_RW_ST0) && fpu_st_timestamp[0] > decode_timestamp)
+                earliest_start = fpu_st_timestamp[0];
+        if ((deps & FPU_RW_ST1) && fpu_st_timestamp[1] > decode_timestamp)
+                earliest_start = fpu_st_timestamp[1];
+        if ((deps & FPU_RW_STREG))
+        {
+                int reg = fetchdat & 7;
+
+                if (fpu_st_timestamp[reg] > decode_timestamp)
+                        earliest_start = fpu_st_timestamp[reg];
+        }
+
+        /*Short decoders are limited to 7 bytes*/
+        if (decode_type == DECODE_SHORT && instr_length > 7)
+                decode_type = DECODE_LONG;
+        /*Long decoder is limited to 11 bytes*/
+        else if (instr_length > 11)
+                decode_type = DECODE_VECTOR;
+
+        switch (decode_type)
+        {
+                case DECODE_SHORT:
+                if (decode_buffer.nr_uops)
+                {
+                        decode_buffer.uops[decode_buffer.nr_uops] = &ins->uop[0];
+                        decode_buffer.earliest_start[decode_buffer.nr_uops] = earliest_start;
+                        if (ins->nr_uops > 1)
+                        {
+                                decode_buffer.uops[decode_buffer.nr_uops+1] = &ins->uop[1];
+                                decode_buffer.earliest_start[decode_buffer.nr_uops+1] = -1;
+                        }
+                        decode_buffer.nr_uops += ins->nr_uops;
+
+                        decode_flush_p6();
+                }
+                else
+                {
+                        decode_buffer.nr_uops = ins->nr_uops;
+                        decode_buffer.uops[0] = &ins->uop[0];
+                        decode_buffer.earliest_start[0] = earliest_start;
+                        if (ins->nr_uops > 1)
+                        {
+                                decode_buffer.uops[1] = &ins->uop[1];
+                                decode_buffer.earliest_start[1] = -1;
+                        }
+                }
+                break;
+                
+                case DECODE_LONG:
+                if (decode_buffer.nr_uops)
+                        decode_flush_p6();
+                        
+                decode_buffer.nr_uops = ins->nr_uops;
+                for (c = 0; c < ins->nr_uops; c++)
+                {
+                        decode_buffer.uops[c] = &ins->uop[c];
+                        if (c == 0)
+                                decode_buffer.earliest_start[c] = earliest_start;
+                        else
+                                decode_buffer.earliest_start[c] = -1;
+                }
+                decode_flush_p6();
+                break;
+                
+                case DECODE_VECTOR:
+                if (decode_buffer.nr_uops)
+                        decode_flush_p6();
+                        
+                decode_timestamp++;
+                d = 0;
+
+                for (c = 0; c < ins->nr_uops; c++)
+                {
+                        decode_buffer.uops[d] = &ins->uop[c];
+                        if (c == 0)
+                                decode_buffer.earliest_start[d] = earliest_start;
+                        else
+                                decode_buffer.earliest_start[d] = -1;
+                        d++;
+                                
+                        if (d == 4)
+                        {
+                                d = 0;
+                                decode_buffer.nr_uops = 4;
+                                decode_flush_p6();
+                        }
+                }
+                if (d)
+                {
+                        decode_buffer.nr_uops = d;
+                        decode_flush_p6();
+                }
+                break;
+        }
+
+        /*Update write timestamps for any output registers*/
+        regmask_modified = get_dstdep_mask(deps, fetchdat, bit8);
+        for (c = 0; c < 8; c++)
+        {
+                if (regmask_modified & (1 << c))
+                        reg_available_timestamp[c] = last_complete_timestamp;
+        }
+        if (deps & FPU_POP)
+        {
+                for (c = 0; c < 7; c++)
+                        fpu_st_timestamp[c] = fpu_st_timestamp[c+1];
+                fpu_st_timestamp[7] = 0;
+        }
+        if (deps & FPU_POP2)
+        {
+                for (c = 0; c < 6; c++)
+                        fpu_st_timestamp[c] = fpu_st_timestamp[c+2];
+                fpu_st_timestamp[6] = fpu_st_timestamp[7] = 0;
+        }
+        if (deps & FPU_PUSH)
+        {
+                for (c = 0; c < 7; c++)
+                        fpu_st_timestamp[c+1] = fpu_st_timestamp[c];
+                fpu_st_timestamp[0] = 0;
+        }
+        if (deps & FPU_WRITE_ST0)
+                fpu_st_timestamp[0] = last_complete_timestamp;
+        if (deps & FPU_WRITE_ST1)
+                fpu_st_timestamp[1] = last_complete_timestamp;
+        if (deps & FPU_WRITE_STREG)
+        {
+                int reg = fetchdat & 7;
+                if (deps & FPU_POP)
+                        reg--;
+                if (reg >= 0 &&
+                        !(reg == 0 && (deps & FPU_WRITE_ST0)) &&
+                        !(reg == 1 && (deps & FPU_WRITE_ST1)))
+                        fpu_st_timestamp[reg] = last_complete_timestamp;
+        }
+}
+
+void codegen_timing_p6_block_start()
+{
+        int c;
+
+        for (c = 0; c < nr_units; c++)
+                units[c].first_available_cycle = 0;
+
+        mul_first_available_cycle = 0;
+        shift_first_available_cycle = 0;
+
+        decode_timestamp = 0;
+        last_complete_timestamp = 0;
+        
+        for (c = 0; c < NR_OPQUADS; c++)
+                opquad_completion_timestamp[c] = 0;
+        next_opquad = 0;
+        
+        for (c = 0; c < NR_REGS; c++)
+                reg_available_timestamp[c] = 0;
+        for (c = 0; c < 8; c++)
+                fpu_st_timestamp[c] = 0;
+}
+
+void codegen_timing_p6_start()
+{
+        if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUMPRO)
+        {
+                units = ppro_units;
+                nr_units = NR_PPRO_UNITS;
+        }
+        else
+        {
+                units = p2_units;
+                nr_units = NR_P2_UNITS;
+        }
+        last_prefix = 0;
+        prefixes = 0;
+}
+
+void codegen_timing_p6_prefix(uint8_t prefix, uint32_t fetchdat)
+{
+        if (prefix != 0x0f)
+                decode_timestamp++;
+
+        last_prefix = prefix;
+        prefixes++;
+}
+
+void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
+{
+        const risc86_instruction_t **ins_table;
+        uint64_t *deps;
+        int mod3 = ((fetchdat & 0xc0) == 0xc0);
+        int old_last_complete_timestamp = last_complete_timestamp;
+        int bit8 = !(opcode & 1);
+
+        switch (last_prefix)
+        {
+                case 0x0f:
+                if (opcode == 0x0f)
+                {
+                        /*3DNow has the actual opcode after ModR/M, SIB and any offset*/
+                        uint32_t opcode_pc = op_pc + 1; /*Byte after ModR/M*/
+                        uint8_t modrm = fetchdat & 0xff;
+                        uint8_t sib = (fetchdat >> 8) & 0xff;
+
+                        if ((modrm & 0xc0) != 0xc0)
+                        {
+                                if (op_32 & 0x200)
+                                {
+                                        if ((modrm & 7) == 4)
+                                        {
+                                                /* Has SIB*/
+                                                opcode_pc++;
+                                                if ((modrm & 0xc0) == 0x40)
+                                                        opcode_pc++;
+                                                else if ((modrm & 0xc0) == 0x80)
+                                                        opcode_pc += 4;
+                                                else if ((sib & 0x07) == 0x05)
+                                                        opcode_pc += 4;
+                                        }
+                                        else
+                                        {
+                                                if ((modrm & 0xc0) == 0x40)
+                                                        opcode_pc++;
+                                                else if ((modrm & 0xc0) == 0x80)
+                                                        opcode_pc += 4;
+                                                else if ((modrm & 0xc7) == 0x05)
+                                                        opcode_pc += 4;
+                                        }
+                                }
+                                else
+                                {
+                                        if ((modrm & 0xc0) == 0x40)
+                                                opcode_pc++;
+                                        else if ((modrm & 0xc0) == 0x80)
+                                                opcode_pc += 2;
+                                        else if ((modrm & 0xc7) == 0x06)
+                                                opcode_pc += 2;
+                                }
+                        }
+                        
+                        opcode = fastreadb(cs + opcode_pc);
+
+                        ins_table = mod3 ? opcode_timings_0f0f_mod3 : opcode_timings_0f0f;
+                        deps = mod3 ? opcode_deps_0f0f_mod3 : opcode_deps_0f0f;
+                }
+                else
+                {
+                        ins_table = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+                        deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
+                }
+                break;
+
+                case 0xd8:
+                ins_table = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
+                deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xd9:
+                ins_table = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
+                deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xda:
+                ins_table = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
+                deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdb:
+                ins_table = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
+                deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xdc:
+                ins_table = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
+                deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdd:
+                ins_table = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
+                deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xde:
+                ins_table = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
+                deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdf:
+                ins_table = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
+                deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
+                opcode = (opcode >> 3) & 7;
+                break;
+
+                default:
+                switch (opcode)
+                {
+                        case 0x80: case 0x82:
+                        ins_table = mod3 ? opcode_timings_80_mod3 : opcode_timings_80;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0x81: case 0x83:
+                        ins_table = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        case 0xc0: case 0xd0: case 0xd2:
+                        ins_table = mod3 ? opcode_timings_shift_b_mod3 : opcode_timings_shift_b;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        
+                        case 0xc1: case 0xd1: case 0xd3:
+                        ins_table = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        case 0xf6:
+                        ins_table = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
+                        deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xf7:
+                        ins_table = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
+                        deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xff:
+                        ins_table = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
+                        deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        default:
+                        ins_table = mod3 ? opcode_timings_mod3 : opcode_timings;
+                        deps = mod3 ? opcode_deps_mod3 : opcode_deps;
+                        break;
+                }
+        }
+
+        if (ins_table[opcode])
+                decode_instruction(ins_table[opcode], deps[opcode], fetchdat, op_32, bit8);
+        else
+                decode_instruction(&vector_alu1_op, 0, fetchdat, op_32, bit8);
+        codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
+}
+
+void codegen_timing_p6_block_end()
+{
+        if (decode_buffer.nr_uops)
+        {
+                int old_last_complete_timestamp = last_complete_timestamp;
+                decode_flush_p6();
+                codegen_block_cycles += (last_complete_timestamp - old_last_complete_timestamp);
+        }
+}
+
+int codegen_timing_p6_jump_cycles()
+{
+        if (decode_buffer.nr_uops)
+                return 1;
+        return 0;
+}
+
+codegen_timing_t codegen_timing_p6 =
+{
+        codegen_timing_p6_start,
+        codegen_timing_p6_prefix,
+        codegen_timing_p6_opcode,
+        codegen_timing_p6_block_start,
+        codegen_timing_p6_block_end,
+        codegen_timing_p6_jump_cycles
+};
diff --git a/src/cpu/codegen_timing_pentium.c b/src/cpu/codegen_timing_pentium.c
index 01dca954f..c95821df9 100644
--- a/src/cpu/codegen_timing_pentium.c
+++ b/src/cpu/codegen_timing_pentium.c
@@ -1076,7 +1076,7 @@ static void codegen_instruction(uint64_t *timings, uint64_t *deps, uint8_t opcod
         }
 }
 
-void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
+void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
 {
         uint64_t *timings;
         uint64_t *deps;
@@ -1137,7 +1137,7 @@ void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
                 {
                         case 0x80: case 0x82: case 0x83:
                         timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
-                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
                         opcode = (fetchdat >> 3) & 7;
                         break;
                         case 0x81:
@@ -1318,5 +1318,6 @@ codegen_timing_t codegen_timing_pentium =
         codegen_timing_pentium_prefix,
         codegen_timing_pentium_opcode,
         codegen_timing_pentium_block_start,
-        codegen_timing_pentium_block_end
+        codegen_timing_pentium_block_end,
+        NULL
 };
diff --git a/src/cpu/codegen_timing_winchip.c b/src/cpu/codegen_timing_winchip.c
index c05f7c28f..dd2123f49 100644
--- a/src/cpu/codegen_timing_winchip.c
+++ b/src/cpu/codegen_timing_winchip.c
@@ -300,7 +300,7 @@ void codegen_timing_winchip_prefix(uint8_t prefix, uint32_t fetchdat)
         last_prefix = prefix;
 }
 
-void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
+void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
 {
         int **timings;
         uint64_t *deps;
@@ -360,7 +360,7 @@ void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
                 {
                         case 0x80: case 0x82: case 0x83:
                         timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
-                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
                         opcode = (fetchdat >> 3) & 7;
                         break;
                         case 0x81:
@@ -416,5 +416,6 @@ codegen_timing_t codegen_timing_winchip =
         codegen_timing_winchip_prefix,
         codegen_timing_winchip_opcode,
         codegen_timing_winchip_block_start,
-        codegen_timing_winchip_block_end
+        codegen_timing_winchip_block_end,
+        NULL
 };
diff --git a/src/cpu/codegen_timing_winchip2.c b/src/cpu/codegen_timing_winchip2.c
new file mode 100644
index 000000000..06cc06697
--- /dev/null
+++ b/src/cpu/codegen_timing_winchip2.c
@@ -0,0 +1,743 @@
+/*Since IDT/Centaur didn't document cycle timings in the WinChip datasheets, and
+  I don't currently own a WinChip 2 to test against, most of the timing here is
+  a guess. This code makes the current (probably wrong) assumptions :
+  - FPU uses same timings as a Pentium, except for FXCH (which doesn't pair)
+  - 3DNow! instructions perfectly pair
+  - MMX follows mostly Pentium rules - one pipeline has shift/pack, one has
+    multiply, and other instructions can execute in either pipeline
+  - Instructions with prefixes can pair if both instructions are fully decoded
+    when the first instruction starts execution.*/
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <wchar.h>
+#include <86box/86box.h>
+#include "cpu.h"
+#include <86box/mem.h>
+
+#include "x86.h"
+#include "x86_ops.h"
+#include "x87.h"
+#include "codegen.h"
+#include "codegen_ops.h"
+#include "codegen_timing_common.h"
+
+/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
+#define CYCLES_HAS_MULTI (1 << 31)
+
+#define CYCLES_FPU (1 << 30)
+
+#define CYCLES_IS_MMX_MUL   (1 << 29)
+#define CYCLES_IS_MMX_SHIFT (1 << 28)
+#define CYCLES_IS_MMX_ANY   (1 << 27)
+#define CYCLES_IS_3DNOW     (1 << 26)
+
+#define CYCLES_MMX_MUL(c)   (CYCLES_IS_MMX_MUL   | c)
+#define CYCLES_MMX_SHIFT(c) (CYCLES_IS_MMX_SHIFT | c)
+#define CYCLES_MMX_ANY(c)   (CYCLES_IS_MMX_ANY   | c)
+#define CYCLES_3DNOW(c)     (CYCLES_IS_3DNOW     | c)
+
+#define CYCLES_IS_MMX (CYCLES_IS_MMX_MUL | CYCLES_IS_MMX_SHIFT | CYCLES_IS_MMX_ANY | CYCLES_IS_3DNOW)
+
+#define GET_CYCLES(c) (c & ~(CYCLES_HAS_MULTI | CYCLES_FPU | CYCLES_IS_MMX))
+
+#define CYCLES(c) c
+#define CYCLES2(c16, c32) (CYCLES_HAS_MULTI | c16 | (c32 << 8))
+
+/*comp_time = cycles until instruction complete
+  i_overlap = cycles that overlap with integer
+  f_overlap = cycles that overlap with subsequent FPU*/
+#define FPU_CYCLES(comp_time, i_overlap, f_overlap) (comp_time) | (i_overlap << 8) | (f_overlap << 16) | CYCLES_FPU
+
+#define FPU_COMP_TIME(timing) (timing & 0xff)
+#define FPU_I_OVERLAP(timing) ((timing >> 8) & 0xff)
+#define FPU_F_OVERLAP(timing) ((timing >> 16) & 0xff)
+
+#define FPU_I_LATENCY(timing) (FPU_COMP_TIME(timing) - FPU_I_OVERLAP(timing))
+
+#define FPU_F_LATENCY(timing) (FPU_I_OVERLAP(timing) - FPU_F_OVERLAP(timing))
+
+#define FPU_RESULT_LATENCY(timing) ((timing >> 8) & 0xff)
+
+#define INVALID 0
+
+static uint32_t opcode_timings[256] =
+{
+/*00*/  CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(2),      INVALID,
+/*10*/  CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),
+/*20*/  CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),
+/*30*/  CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),
+
+/*40*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*50*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*60*/  CYCLES(11),     CYCLES(9),      CYCLES(7),      CYCLES(9),      CYCLES(4),      CYCLES(4),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES2(17,25), CYCLES(1),      CYCLES2(17,20), CYCLES(17),     CYCLES(17),     CYCLES(17),     CYCLES(17),
+/*70*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*80*/  CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(5),      CYCLES(5),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(1),      CYCLES(5),      CYCLES(6),
+/*90*/  CYCLES(1),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(0),      CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(2),      CYCLES(3),
+/*a0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(7),      CYCLES(7),      CYCLES(8),      CYCLES(8),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),
+/*b0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*c0*/  CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),      CYCLES(1),      CYCLES(1),      CYCLES(14),     CYCLES(5),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(3),      CYCLES(0),
+/*d0*/  CYCLES(4),      CYCLES(4),      CYCLES(4),      CYCLES(4),      CYCLES(15),     CYCLES(14),     CYCLES(2),      CYCLES(4),      INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,
+/*e0*/  CYCLES(6),      CYCLES(6),      CYCLES(6),      CYCLES(5),      CYCLES(14),     CYCLES(14),     CYCLES(16),     CYCLES(16),     CYCLES(3),      CYCLES(3),      CYCLES(17),     CYCLES(3),      CYCLES(14),     CYCLES(14),     CYCLES(14),     CYCLES(14),
+/*f0*/  CYCLES(4),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(4),      CYCLES(2),      INVALID,        INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(3),      INVALID
+};
+
+static uint32_t opcode_timings_mod3[256] =
+{
+/*00*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      INVALID,
+/*10*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),
+/*20*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),
+/*30*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),
+
+/*40*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*50*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*60*/  CYCLES(11),     CYCLES(9),      CYCLES(7),      CYCLES(9),      CYCLES(4),      CYCLES(4),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES2(14,25), CYCLES(1),      CYCLES2(17,20), CYCLES(17),     CYCLES(17),     CYCLES(17),     CYCLES(17),
+/*70*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*80*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(1),      CYCLES(2),      CYCLES(1),
+/*90*/  CYCLES(1),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(0),      CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(2),      CYCLES(3),
+/*a0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(7),      CYCLES(7),      CYCLES(8),      CYCLES(8),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),
+/*b0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*c0*/  CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),      CYCLES(1),      CYCLES(1),      CYCLES(14),     CYCLES(5),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(3),      CYCLES(0),
+/*d0*/  CYCLES(4),      CYCLES(4),      CYCLES(4),      CYCLES(4),      CYCLES(15),     CYCLES(14),     CYCLES(2),      CYCLES(4),      INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,
+/*e0*/  CYCLES(6),      CYCLES(6),      CYCLES(6),      CYCLES(5),      CYCLES(14),     CYCLES(14),     CYCLES(16),     CYCLES(16),     CYCLES(3),      CYCLES(3),      CYCLES(17),     CYCLES(3),      CYCLES(14),     CYCLES(14),     CYCLES(14),     CYCLES(14),
+/*f0*/  CYCLES(4),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(4),      CYCLES(2),      INVALID,        INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(3),      INVALID,
+};
+
+static uint32_t opcode_timings_0f[256] =
+{
+/*00*/  CYCLES(20),          CYCLES(11),          CYCLES(11),          CYCLES(10),          INVALID,           CYCLES(195),       CYCLES(7),         INVALID,             CYCLES(1000),        CYCLES(10000),       INVALID,             INVALID,             INVALID,           CYCLES_3DNOW(1),   CYCLES(1),         CYCLES_3DNOW(1),
+/*10*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*20*/  CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),         CYCLES(6),         INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*30*/  CYCLES(9),           CYCLES(1),           CYCLES(9),           INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+
+/*40*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*50*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*60*/  CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID,           INVALID,           CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2),
+/*70*/  INVALID,             CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES(100),         INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2),
+
+/*80*/  CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*90*/  CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),
+/*a0*/  CYCLES(3),           CYCLES(3),           CYCLES(14),          CYCLES(8),           CYCLES(3),         CYCLES(4),         INVALID,           INVALID,             CYCLES(3),           CYCLES(3),           INVALID,             CYCLES(13),          CYCLES(3),         CYCLES(3),         INVALID,           CYCLES2(18,30),
+/*b0*/  CYCLES(10),          CYCLES(10),          CYCLES(6),           CYCLES(13),          CYCLES(6),         CYCLES(6),         CYCLES(3),         CYCLES(3),           INVALID,             INVALID,             CYCLES(6),           CYCLES(13),          CYCLES(7),         CYCLES(7),         CYCLES(3),         CYCLES(3),
+
+/*c0*/  CYCLES(4),           CYCLES(4),           INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           CYCLES(3),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*d0*/  INVALID,             CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID,           CYCLES_MMX_MUL(2), INVALID,           INVALID,             CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2),   INVALID,             CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID,           CYCLES_MMX_ANY(2),
+/*e0*/  INVALID,             CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID,             INVALID,           CYCLES_MMX_MUL(2), INVALID,           INVALID,             CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2),   INVALID,             CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID,           CYCLES_MMX_ANY(2),
+/*f0*/  INVALID,             CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID,           CYCLES_MMX_MUL(2), INVALID,           INVALID,             CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2),   CYCLES_MMX_ANY(2),   INVALID,             CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID,
+};
+static uint32_t opcode_timings_0f_mod3[256] =
+{
+/*00*/  CYCLES(20),          CYCLES(11),          CYCLES(11),          CYCLES(10),          INVALID,           CYCLES(195),       CYCLES(7),         INVALID,             CYCLES(1000),        CYCLES(10000),       INVALID,             INVALID,             INVALID,           CYCLES_3DNOW(1),   CYCLES(1),         CYCLES_3DNOW(1),
+/*10*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*20*/  CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),         CYCLES(6),         INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*30*/  CYCLES(9),           CYCLES(1),           CYCLES(9),           INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+
+/*40*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*50*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*60*/  CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+/*70*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES(100),         INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+
+/*80*/  CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*90*/  CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),
+/*a0*/  CYCLES(3),           CYCLES(3),           CYCLES(14),          CYCLES(8),           CYCLES(3),         CYCLES(4),         INVALID,           INVALID,             CYCLES(3),           CYCLES(3),           INVALID,             CYCLES(13),          CYCLES(3),         CYCLES(3),         INVALID,           CYCLES2(18,30),
+/*b0*/  CYCLES(10),          CYCLES(10),          CYCLES(6),           CYCLES(13),          CYCLES(6),         CYCLES(6),         CYCLES(3),         CYCLES(3),           INVALID,             INVALID,             CYCLES(6),           CYCLES(13),          CYCLES(7),         CYCLES(7),         CYCLES(3),         CYCLES(3),
+
+/*c0*/  CYCLES(4),           CYCLES(4),           INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           CYCLES(3),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*d0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*e0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,             INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*f0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,
+};
+
+static uint32_t opcode_timings_shift[8] =
+{
+        CYCLES(7),      CYCLES(7),      CYCLES(10),     CYCLES(10),     CYCLES(7),      CYCLES(7),      CYCLES(7),      CYCLES(7)
+};
+static uint32_t opcode_timings_shift_mod3[8] =
+{
+        CYCLES(3),      CYCLES(3),      CYCLES(9),      CYCLES(9),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3)
+};
+
+static uint32_t opcode_timings_f6[8] =
+{
+        CYCLES(2),      INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(13),     CYCLES(14),     CYCLES(16),     CYCLES(19)
+};
+static uint32_t opcode_timings_f6_mod3[8] =
+{
+        CYCLES(1),      INVALID,        CYCLES(1),      CYCLES(1),      CYCLES(13),     CYCLES(14),     CYCLES(16),     CYCLES(19)
+};
+static uint32_t opcode_timings_f7[8] =
+{
+        CYCLES(2),      INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(21),     CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
+};
+static uint32_t opcode_timings_f7_mod3[8] =
+{
+        CYCLES(1),      INVALID,        CYCLES(1),      CYCLES(1),      CYCLES(21),     CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
+};
+static uint32_t opcode_timings_ff[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(5),      CYCLES(0),      CYCLES(5),      CYCLES(0),      CYCLES(5),      INVALID
+};
+static uint32_t opcode_timings_ff_mod3[8] =
+{
+        CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(0),      CYCLES(5),      CYCLES(0),      CYCLES(5),      INVALID
+};
+
+static uint32_t opcode_timings_d8[8] =
+{
+/*      FADDs               FMULs               FCOMs                 FCOMPs*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  FPU_CYCLES(1,0,0),    FPU_CYCLES(1,0,0),
+/*      FSUBs               FSUBRs              FDIVs                 FDIVRs*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+static uint32_t opcode_timings_d8_mod3[8] =
+{
+/*      FADD                  FMUL                  FCOM                  FCOMP*/
+        FPU_CYCLES(3,2,2),    FPU_CYCLES(3,2,2),    FPU_CYCLES(1,0,0),    FPU_CYCLES(1,0,0),
+/*      FSUB                  FSUBR                 FDIV                  FDIVR*/
+        FPU_CYCLES(3,2,2),    FPU_CYCLES(3,2,2),    FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_d9[8] =
+{
+/*      FLDs                                     FSTs                 FSTPs*/
+        FPU_CYCLES(1,0,0),   INVALID,            FPU_CYCLES(2,0,0),   FPU_CYCLES(2,0,0),
+/*      FLDENV               FLDCW               FSTENV               FSTCW*/
+        FPU_CYCLES(32,0,0),  FPU_CYCLES(8,0,0),  FPU_CYCLES(48,0,0),  FPU_CYCLES(2,0,0)
+};
+static uint32_t opcode_timings_d9_mod3[64] =
+{
+        /*FLD*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+        /*FXCH*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+        /*FNOP*/
+        FPU_CYCLES(3,0,0),  INVALID,            INVALID,            INVALID,
+        INVALID,            INVALID,            INVALID,            INVALID,
+        /*FSTP*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),
+/*      opFCHS              opFABS*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  INVALID,            INVALID,
+/*      opFTST              opFXAM*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(21,4,0), INVALID,            INVALID,
+/*      opFLD1              opFLDL2T            opFLDL2E            opFLDPI*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),
+/*      opFLDEG2            opFLDLN2            opFLDZ*/
+        FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),  FPU_CYCLES(2,0,0),  INVALID,
+/*      opF2XM1             opFYL2X             opFPTAN             opFPATAN*/
+        FPU_CYCLES(53,2,2), FPU_CYCLES(103,2,2),FPU_CYCLES(120,36,0),FPU_CYCLES(112,2,2),
+/*                                              opFDECSTP           opFINCSTP,*/
+        INVALID,            INVALID,            FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+/*      opFPREM                                 opFSQRT             opFSINCOS*/
+        FPU_CYCLES(64,2,2), INVALID,            FPU_CYCLES(70,69,2),FPU_CYCLES(89,2,2),
+/*      opFRNDINT           opFSCALE            opFSIN              opFCOS*/
+        FPU_CYCLES(9,0,0),  FPU_CYCLES(20,5,0), FPU_CYCLES(65,2,2), FPU_CYCLES(65,2,2)
+};
+
+static uint32_t opcode_timings_da[8] =
+{
+/*      FIADDl              FIMULl              FICOMl                FICOMPl*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(4,0,0),    FPU_CYCLES(4,0,0),
+/*      FISUBl              FISUBRl             FIDIVl                FIDIVRl*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(42,38,2),  FPU_CYCLES(42,38,2)
+};
+static uint32_t opcode_timings_da_mod3[8] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+/*                          FCOMPP*/
+        INVALID,            FPU_CYCLES(1,0,0),  INVALID,              INVALID
+};
+
+
+static uint32_t opcode_timings_db[8] =
+{
+/*      FLDil                                   FSTil                 FSTPil*/
+        FPU_CYCLES(3,2,2),  INVALID,            FPU_CYCLES(6,0,0),    FPU_CYCLES(6,0,0),
+/*                          FLDe                                      FSTPe*/
+        INVALID,            FPU_CYCLES(3,0,0),  INVALID,              FPU_CYCLES(3,0,0)
+};
+static uint32_t opcode_timings_db_mod3[64] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+/*                          opFNOP              opFCLEX               opFINIT*/
+        INVALID,            FPU_CYCLES(1,0,0),  FPU_CYCLES(7,0,0),    FPU_CYCLES(17,0,0),
+/*      opFNOP              opFNOP*/
+        FPU_CYCLES(1,0,0),  FPU_CYCLES(1,0,0),  INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+};
+
+static uint32_t opcode_timings_dc[8] =
+{
+/*      FADDd               FMULd               FCOMd                 FCOMPd*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  FPU_CYCLES(1,0,0),    FPU_CYCLES(1,0,0),
+/*      FSUBd               FSUBRd              FDIVd                 FDIVRd*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+static uint32_t opcode_timings_dc_mod3[8] =
+{
+/*      opFADDr               opFMULr*/
+        FPU_CYCLES(3,2,2),    FPU_CYCLES(3,2,2),INVALID,              INVALID,
+/*      opFSUBRr              opFSUBr           opFDIVRr              opFDIVr*/
+        FPU_CYCLES(3,2,2),    FPU_CYCLES(3,2,2),FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_dd[8] =
+{
+/*      FLDd                                    FSTd                  FSTPd*/
+        FPU_CYCLES(1,0,0),    INVALID,          FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FRSTOR                                  FSAVE                 FSTSW*/
+        FPU_CYCLES(70,0,0),   INVALID,          FPU_CYCLES(127,0,0),  FPU_CYCLES(6,0,0)
+};
+static uint32_t opcode_timings_dd_mod3[8] =
+{
+/*      FFFREE                                  FST                   FSTP*/
+        FPU_CYCLES(2,0,0),    INVALID,          FPU_CYCLES(1,0,0),    FPU_CYCLES(1,0,0),
+/*      FUCOM                 FUCOMP*/
+        FPU_CYCLES(1,0,0),    FPU_CYCLES(1,0,0),INVALID,              INVALID
+};
+
+static uint32_t opcode_timings_de[8] =
+{
+/*      FIADDw              FIMULw              FICOMw                FICOMPw*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(4,0,0),    FPU_CYCLES(4,0,0),
+/*      FISUBw              FISUBRw             FIDIVw                FIDIVRw*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(42,38,2),  FPU_CYCLES(42,38,2)
+};
+static uint32_t opcode_timings_de_mod3[8] =
+{
+/*      FADDP               FMULP                                     FCOMPP*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  INVALID,              FPU_CYCLES(1,0,0),
+/*      FSUBP               FSUBRP              FDIVP                 FDIVRP*/
+        FPU_CYCLES(3,2,2),  FPU_CYCLES(3,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_df[8] =
+{
+/*      FILDiw                                  FISTiw                FISTPiw*/
+        FPU_CYCLES(3,2,2),  INVALID,            FPU_CYCLES(6,0,0),    FPU_CYCLES(6,0,0),
+/*                          FILDiq              FBSTP                 FISTPiq*/
+        INVALID,            FPU_CYCLES(3,2,2),  FPU_CYCLES(148,0,0),  FPU_CYCLES(6,0,0)
+};
+static uint32_t opcode_timings_df_mod3[8] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+/*      FSTSW AX*/
+        FPU_CYCLES(6,0,0),  INVALID,            INVALID,              INVALID
+};
+
+static uint32_t opcode_timings_8x[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_8x_mod3[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_81[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_81_mod3[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+
+static int timing_count;
+static uint8_t last_prefix;
+static uint32_t regmask_modified;
+static int decode_delay, decode_delay_offset;
+static int fpu_latency;
+static int fpu_st_latency[8];
+
+static int u_pipe_full;
+static uint32_t u_pipe_opcode;
+static uint32_t *u_pipe_timings;
+static uint32_t u_pipe_op_32;
+static uint32_t u_pipe_regmask;
+static uint32_t u_pipe_fetchdat;
+static int u_pipe_decode_delay_offset;
+static uint64_t *u_pipe_deps;
+
+int can_pair(uint32_t timing_a, uint32_t timing_b, uint8_t regmask_b)
+{
+        /*Only MMX/3DNow instructions can pair*/
+        if (!(timing_b & CYCLES_IS_MMX))
+                return 0;
+        /*Only one MMX multiply per cycle*/
+        if ((timing_a & CYCLES_IS_MMX_MUL) && (timing_b & CYCLES_IS_MMX_MUL))
+                return 0;
+        /*Only one MMX shift/pack per cycle*/
+        if ((timing_a & CYCLES_IS_MMX_SHIFT) && (timing_b & CYCLES_IS_MMX_SHIFT))
+                return 0;
+        /*Second instruction can not access registers written by first*/
+        if (u_pipe_regmask & regmask_b)
+                return 0;
+        /*Must have had enough time to decode prefixes*/
+        if ((decode_delay+decode_delay_offset+u_pipe_decode_delay_offset) > 0)
+                return 0;
+
+        return 1;
+}
+
+static inline int COUNT(uint32_t c, int op_32)
+{
+        if (c & CYCLES_FPU)
+                return FPU_I_LATENCY(c);
+        if (c & CYCLES_HAS_MULTI)
+        {
+                if (op_32 & 0x100)
+                        return (c >> 8) & 0xff;
+                return c & 0xff;
+        }
+        return GET_CYCLES(c);
+}
+
+static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_32)
+{
+        uint32_t addr_regmask = get_addr_regmask(deps[opcode], fetchdat, op_32);
+
+        /*Instructions that use ESP implicitly (eg PUSH, POP, CALL etc) do not
+          cause AGIs with each other, but do with instructions that use it explicitly*/
+        if ((addr_regmask & REGMASK_IMPL_ESP) && (regmask_modified & (1 << REG_ESP)) && !(regmask_modified & REGMASK_IMPL_ESP))
+                addr_regmask |= (1 << REG_ESP);
+
+        return (regmask_modified & addr_regmask) & ~REGMASK_IMPL_ESP;
+}
+
+static int codegen_fpu_latencies(uint64_t deps, int reg)
+{
+        int latency = fpu_latency;
+
+        if ((deps & FPU_RW_ST0) && fpu_st_latency[0] && fpu_st_latency[0] > latency)
+                latency = fpu_st_latency[0];
+        if ((deps & FPU_RW_ST1) && fpu_st_latency[1] && fpu_st_latency[1] > latency)
+                latency = fpu_st_latency[1];
+        if ((deps & FPU_RW_STREG) && fpu_st_latency[reg] && fpu_st_latency[reg] > latency)
+                latency = fpu_st_latency[reg];
+
+        return latency;
+}
+
+#define SUB_AND_CLAMP(latency, count)  \
+        latency -= count;              \
+        if (latency < 0)               \
+                latency = 0
+
+static void codegen_fpu_latency_clock(int count)
+{
+        SUB_AND_CLAMP(fpu_latency, count);
+        SUB_AND_CLAMP(fpu_st_latency[0], count);
+        SUB_AND_CLAMP(fpu_st_latency[1], count);
+        SUB_AND_CLAMP(fpu_st_latency[2], count);
+        SUB_AND_CLAMP(fpu_st_latency[3], count);
+        SUB_AND_CLAMP(fpu_st_latency[4], count);
+        SUB_AND_CLAMP(fpu_st_latency[5], count);
+        SUB_AND_CLAMP(fpu_st_latency[6], count);
+        SUB_AND_CLAMP(fpu_st_latency[7], count);
+}
+
+static void codegen_instruction(uint32_t *timings, uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int decode_delay_offset, int op_32, int exec_delay)
+{
+        int instr_cycles, latency = 0;
+
+        if ((timings[opcode] & CYCLES_FPU) && !(deps[opcode] & FPU_FXCH))
+                instr_cycles = latency = codegen_fpu_latencies(deps[opcode], fetchdat & 7);
+        else
+                instr_cycles = 0;
+
+        if ((decode_delay + decode_delay_offset) > 0)
+                codegen_fpu_latency_clock(decode_delay + decode_delay_offset + instr_cycles);
+        else
+                codegen_fpu_latency_clock(instr_cycles);
+        instr_cycles += COUNT(timings[opcode], op_32);
+        instr_cycles += exec_delay;
+        if ((decode_delay + decode_delay_offset) > 0)
+                codegen_block_cycles += instr_cycles + decode_delay + decode_delay_offset;
+        else
+                codegen_block_cycles += instr_cycles;
+        decode_delay = (-instr_cycles) + 1;
+
+        if (deps[opcode] & FPU_POP)
+        {
+                int c;
+
+                for (c = 0; c < 7; c++)
+                        fpu_st_latency[c] = fpu_st_latency[c+1];
+                fpu_st_latency[7] = 0;
+        }
+        if (deps[opcode] & FPU_POP2)
+        {
+                int c;
+
+                for (c = 0; c < 6; c++)
+                        fpu_st_latency[c] = fpu_st_latency[c+2];
+                fpu_st_latency[6] = fpu_st_latency[7] = 0;
+        }
+        if (timings[opcode] & CYCLES_FPU)
+        {
+  /*              if (fpu_latency)
+                        fatal("Bad latency FPU\n");*/
+                fpu_latency = FPU_F_LATENCY(timings[opcode]);
+        }
+
+        if (deps[opcode] & FPU_PUSH)
+        {
+                int c;
+
+                for (c = 0; c < 7; c++)
+                        fpu_st_latency[c+1] = fpu_st_latency[c];
+                fpu_st_latency[0] = 0;
+        }
+        if (deps[opcode] & FPU_WRITE_ST0)
+        {
+/*                if (fpu_st_latency[0])
+                        fatal("Bad latency ST0\n");*/
+                fpu_st_latency[0] = FPU_RESULT_LATENCY(timings[opcode]);
+        }
+        if (deps[opcode] & FPU_WRITE_ST1)
+        {
+/*                if (fpu_st_latency[1])
+                        fatal("Bad latency ST1\n");*/
+                fpu_st_latency[1] = FPU_RESULT_LATENCY(timings[opcode]);
+        }
+        if (deps[opcode] & FPU_WRITE_STREG)
+        {
+                int reg = fetchdat & 7;
+                if (deps[opcode] & FPU_POP)
+                        reg--;
+                if (reg >= 0 &&
+                        !(reg == 0 && (deps[opcode] & FPU_WRITE_ST0)) &&
+                        !(reg == 1 && (deps[opcode] & FPU_WRITE_ST1)))
+                {
+/*                        if (fpu_st_latency[reg])
+                                fatal("Bad latency STREG %i %08x %i %016llx %02x\n",fpu_st_latency[reg], fetchdat, reg, timings[opcode], opcode);*/
+                        fpu_st_latency[reg] = FPU_RESULT_LATENCY(timings[opcode]);
+                }
+        }
+}
+
+static void codegen_timing_winchip2_block_start()
+{
+        regmask_modified = 0;
+        decode_delay = decode_delay_offset = 0;
+        u_pipe_full = 0;
+}
+
+static void codegen_timing_winchip2_start()
+{
+        timing_count = 0;
+        last_prefix = 0;
+}
+
+static void codegen_timing_winchip2_prefix(uint8_t prefix, uint32_t fetchdat)
+{
+        if (prefix == 0x0f)
+        {
+                /*0fh prefix is 'free'*/
+                last_prefix = prefix;
+                return;
+        }
+        /*On WinChip all prefixes take 1 cycle to decode. Decode may be shadowed
+          by execution of previous instructions*/
+        decode_delay_offset++;
+        last_prefix = prefix;
+}
+
+static void codegen_timing_winchip2_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
+{
+        uint32_t *timings;
+        uint64_t *deps;
+        int mod3 = ((fetchdat & 0xc0) == 0xc0);
+        int bit8 = !(opcode & 1);
+        int agi_stall = 0;
+
+        switch (last_prefix)
+        {
+                case 0x0f:
+                timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+                deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
+                break;
+                
+                case 0xd8:
+                timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
+                deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xd9:
+                timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
+                deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xda:
+                timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
+                deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdb:
+                timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
+                deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+                break;
+                case 0xdc:
+                timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
+                deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdd:
+                timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
+                deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xde:
+                timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
+                deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
+                opcode = (opcode >> 3) & 7;
+                break;
+                case 0xdf:
+                timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
+                deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
+                opcode = (opcode >> 3) & 7;
+                break;
+
+                default:
+                switch (opcode)
+                {
+                        case 0x80: case 0x82: case 0x83:
+                        timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0x81:
+                        timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
+                        deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                                
+                        case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
+                        timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        
+                        case 0xf6:
+                        timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
+                        deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xf7:
+                        timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
+                        deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+                        case 0xff:
+                        timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
+                        deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
+                        opcode = (fetchdat >> 3) & 7;
+                        break;
+
+                        default:
+                        timings = mod3 ? opcode_timings_mod3 : opcode_timings;
+                        deps = mod3 ? opcode_deps_mod3 : opcode_deps;
+                        break;
+                }
+        }
+        
+        if (u_pipe_full)
+        {
+                uint8_t regmask = get_srcdep_mask(deps[opcode], fetchdat, bit8, u_pipe_op_32);
+                
+                if (can_pair(u_pipe_timings[u_pipe_opcode], timings[opcode], regmask))
+                {
+                        int cycles_a = u_pipe_timings[u_pipe_opcode] & 0xff;
+                        int cycles_b = timings[opcode] & 0xff;
+                        uint32_t timing = (cycles_a > cycles_b) ? u_pipe_timings[u_pipe_opcode] : timings[opcode];
+                        uint64_t temp_deps = 0;
+
+                        if (check_agi(deps, opcode, fetchdat, op_32) || check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
+                                agi_stall = 1;
+
+                        codegen_instruction(&timing, &temp_deps, 0, 0, 0, 0, agi_stall);
+                        u_pipe_full = 0;
+                        decode_delay_offset = 0;
+                        regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8) | u_pipe_regmask;
+                        return;
+                }
+                else
+                {
+                        /*No pairing, run first instruction now*/
+                        if (check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
+                                agi_stall = 1;
+                        codegen_instruction(u_pipe_timings, u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_decode_delay_offset, u_pipe_op_32, agi_stall);
+                        u_pipe_full = 0;
+                        regmask_modified = u_pipe_regmask;
+                }
+        }
+        if (timings[opcode] & CYCLES_IS_MMX)
+        {
+                /*Might pair with next instruction*/
+                u_pipe_full = 1;
+                u_pipe_opcode = opcode;
+                u_pipe_timings = timings;
+                u_pipe_op_32 = op_32;
+                u_pipe_regmask = get_dstdep_mask(deps[opcode], fetchdat, bit8);
+                u_pipe_fetchdat = fetchdat;
+                u_pipe_decode_delay_offset = decode_delay_offset;
+                u_pipe_deps = deps;
+                decode_delay_offset = 0;
+                return;
+        }
+        
+        if (check_agi(deps, opcode, fetchdat, op_32))
+                agi_stall = 1;
+        codegen_instruction(timings, deps, opcode, fetchdat, decode_delay_offset, op_32, agi_stall);
+        decode_delay_offset = 0;
+        regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
+}
+
+static void codegen_timing_winchip2_block_end()
+{
+        if (u_pipe_full)
+        {
+                int agi_stall = 0;
+                
+                if (check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
+                        agi_stall = 1;
+                codegen_instruction(u_pipe_timings, u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_decode_delay_offset, u_pipe_op_32, agi_stall);
+                u_pipe_full = 0;
+        }
+}
+
+codegen_timing_t codegen_timing_winchip2 =
+{
+        codegen_timing_winchip2_start,
+        codegen_timing_winchip2_prefix,
+        codegen_timing_winchip2_opcode,
+        codegen_timing_winchip2_block_start,
+        codegen_timing_winchip2_block_end,
+        NULL
+};
diff --git a/src/cpu/codegen_x86-64.c b/src/cpu/codegen_x86-64.c
index 7c1a9c394..a396e0008 100644
--- a/src/cpu/codegen_x86-64.c
+++ b/src/cpu/codegen_x86-64.c
@@ -1067,7 +1067,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
         }
         
 generate_call:
-        codegen_timing_opcode(opcode, fetchdat, op_32);
+        codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
         
         if ((op_table == x86_dynarec_opcodes &&
               ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
@@ -1075,6 +1075,24 @@ generate_call:
               (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
             (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
         {
+                /*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
+                  subsequent instructions, so no cycles may have been deducted for it yet.
+                  To prevent having zero cycle blocks (eg with a jump instruction pointing
+                  to itself), apply the cycles that would be taken if this jump is taken,
+                  then reverse it for subsequent instructions if the jump is not taken*/
+                int jump_cycles = 0;
+
+		if (codegen_timing_jump_cycles != NULL)
+			codegen_timing_jump_cycles();
+
+                if (jump_cycles)
+                {
+                        addbyte(0x81); /*SUB $jump_cycles, cyclcs*/
+                        addbyte(0x6d);
+                        addbyte((uint8_t)cpu_state_offset(_cycles));
+                        addlong((uint32_t)jump_cycles);
+                }
+
                 /*Opcode is likely to cause block to exit, update cycle count*/
                 if (codegen_block_cycles)
                 {
@@ -1092,6 +1110,15 @@ generate_call:
                         addlong(codegen_block_ins);
                         codegen_block_ins = 0;
                 }
+
+                if (jump_cycles)
+                {
+                        addbyte(0x81); /*SUB $jump_cycles, cyclcs*/
+                        addbyte(0x6d);
+                        addbyte((uint8_t)cpu_state_offset(_cycles));
+                        addlong((uint32_t)jump_cycles);
+                        jump_cycles = 0;
+                }
         }
 
         if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32])
diff --git a/src/cpu/codegen_x86.c b/src/cpu/codegen_x86.c
index 590e530af..91e3b9655 100644
--- a/src/cpu/codegen_x86.c
+++ b/src/cpu/codegen_x86.c
@@ -977,8 +977,8 @@ static uint32_t gen_MEM_CHECK_WRITE()
         addbyte(0x6a); /*PUSH 1*/
         addbyte(1);
         addbyte(0x57); /*PUSH EDI*/
-        addbyte(0xe8); /*CALL mmutranslatereal*/
-        addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
+        addbyte(0xe8); /*CALL mmutranslatereal32*/
+        addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
         addbyte(0x83); /*ADD ESP, 8*/
         addbyte(0xc4);
         addbyte(8);
@@ -1049,8 +1049,8 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
         addbyte(0x6a); /*PUSH 1*/
         addbyte(1);
         addbyte(0x57); /*PUSH EDI*/
-        addbyte(0xe8); /*CALL mmutranslatereal*/
-        addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
+        addbyte(0xe8); /*CALL mmutranslatereal32*/
+        addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
         addbyte(0x5f); /*POP EDI*/
         addbyte(0x83); /*ADD ESP, 4*/
         addbyte(0xc4);
@@ -1131,8 +1131,8 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
         addbyte(0x6a); /*PUSH 1*/
         addbyte(1);
         addbyte(0x57); /*PUSH EDI*/
-        addbyte(0xe8); /*CALL mmutranslatereal*/
-        addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
+        addbyte(0xe8); /*CALL mmutranslatereal32*/
+        addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
         addbyte(0x5f); /*POP EDI*/
         addbyte(0x83); /*ADD ESP, 4*/
         addbyte(0xc4);
@@ -1874,7 +1874,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
         int pc_off = 0;
         int test_modrm = 1;
         int c;
-        
+
         op_ea_seg = &cpu_state.seg_ds;
         op_ssegs = 0;
         op_old_pc = old_pc;
@@ -2031,7 +2031,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
         }
         
 generate_call:
-        codegen_timing_opcode(opcode, fetchdat, op_32);
+        codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
 
         if ((op_table == x86_dynarec_opcodes &&
               ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
@@ -2039,10 +2039,28 @@ generate_call:
               (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
             (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
         {
+                /*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
+                  subsequent instructions, so no cycles may have been deducted for it yet.
+                  To prevent having zero cycle blocks (eg with a jump instruction pointing
+                  to itself), apply the cycles that would be taken if this jump is taken,
+                  then reverse it for subsequent instructions if the jump is not taken*/
+                int jump_cycles = 0;
+
+		if (codegen_timing_jump_cycles != NULL)
+			codegen_timing_jump_cycles();
+
+                if (jump_cycles)
+                {
+                        addbyte(0x81); /*SUB $jump_cycles, cycles*/
+                        addbyte(0x6d);
+                        addbyte((uint8_t)cpu_state_offset(_cycles));
+                        addlong(jump_cycles);
+                }
+
                 /*Opcode is likely to cause block to exit, update cycle count*/
                 if (codegen_block_cycles)
                 {
-                        addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
+                        addbyte(0x81); /*SUB $codegen_block_cycles, cycles*/
                         addbyte(0x6d);
                         addbyte((uint8_t)cpu_state_offset(_cycles));
                         addlong(codegen_block_cycles);
@@ -2066,6 +2084,15 @@ generate_call:
                         codegen_block_full_ins = 0;
                 }
 #endif
+
+                if (jump_cycles)
+                {
+                        addbyte(0x81); /*SUB $jump_cycles, cycles*/
+                        addbyte(0x6d);
+                        addbyte((uint8_t)cpu_state_offset(_cycles));
+                        addlong(jump_cycles);
+                        jump_cycles = 0;
+                }
         }
 
         if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32])
@@ -2099,7 +2126,7 @@ generate_call:
                 addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
                 addbyte(0x45);
                 addbyte((uint8_t)cpu_state_offset(ssegs));
-                addbyte(op_pc + pc_off);
+               	addbyte(op_pc + pc_off);
         }
 
         if (!test_modrm ||
@@ -2140,7 +2167,7 @@ generate_call:
         addbyte(0xC7); /*MOVL pc,new_pc*/
         addbyte(0x45);
         addbyte((uint8_t)cpu_state_offset(pc));
-        addlong(op_pc + pc_off);
+	addlong(op_pc + pc_off);
 
         addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
         addbyte(0x45);
diff --git a/src/cpu/x86seg.c b/src/cpu/x86seg.c
index 286f20817..c903fbb79 100644
--- a/src/cpu/x86seg.c
+++ b/src/cpu/x86seg.c
@@ -391,12 +391,17 @@ void loadseg(uint16_t seg, x86seg *s)
                 {
                         if (!(seg&~3))
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Stack segment is zero",seg&~3);
                                 return;
                         }
-                        if ((seg&3)!=CPL || dpl!=CPL)
+                        if ((seg&3)!=CPL)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
+                                return;
+                        }
+                        if (dpl!=CPL)
+                        {
+                                x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
                                 return;
                         }
                         switch ((segdat[2]>>8)&0x1F)
@@ -404,7 +409,7 @@ void loadseg(uint16_t seg, x86seg *s)
                                 case 0x12: case 0x13: case 0x16: case 0x17: /*r/w*/
                                 break;
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Unknown stack segment type",seg&~3);
                                 return;
                         }
                         if (!(segdat[2]&0x8000))
@@ -423,16 +428,21 @@ void loadseg(uint16_t seg, x86seg *s)
                                 case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
                                 case 0x14: case 0x15: case 0x16: case 0x17:
                                 case 0x1A: case 0x1B: /*Readable non-conforming code*/
-                                if ((seg&3)>dpl || (CPL)>dpl)
+                                if ((seg&3)>dpl)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("loadseg(): Normal segment is zero",seg&~3);
+                                        return;
+                                }
+                                if ((CPL)>dpl)
+                                {
+                                        x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
                                         return;
                                 }
                                 break;
                                 case 0x1E: case 0x1F: /*Readable conforming code*/
                                 break;
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Unknown normal segment type",seg&~3);
                                 return;
                         }
                 }
@@ -519,7 +529,7 @@ void loadcs(uint16_t seg)
                 {
                         if (addr>=ldt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcs(): Protected mode selector > LDT limit",seg&~3);
                                 return;
                         }
                         addr+=ldt.base;
@@ -528,7 +538,7 @@ void loadcs(uint16_t seg)
                 {
                         if (addr>=gdt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcs(): Protected mode selector > GDT limit",seg&~3);
                                 return;
                         }
                         addr+=gdt.base;
@@ -544,12 +554,12 @@ void loadcs(uint16_t seg)
                         {
                                 if ((seg&3)>CPL)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("loadcs(): Non-conforming RPL > CPL",seg&~3);
                                         return;
                                 }
                                 if (CPL != DPL)
                                 {
-                                        x86gpf("loadcs(): CPL != DPL",seg&~3);
+                                        x86gpf("loadcs(): Non-conforming CPL != DPL",seg&~3);
                                         return;
                                 }
                         }
@@ -579,13 +589,13 @@ void loadcs(uint16_t seg)
                 {
                         if (!(segdat[2]&0x8000))
                         {
-                                x86np("Load CS system seg not present\n", seg & 0xfffc);
+                                x86np("Load CS system seg not present", seg & 0xfffc);
                                 return;
                         }
                         switch (segdat[2]&0xF00)
                         {
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("Load CS system segment has bits 0-3 of access rights set",seg&~3);
                                 return;
                         }
                 }
@@ -614,7 +624,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
         {
                 if (!(seg&~3))
                 {
-                        x86gpf(NULL,0);
+                        x86gpf("loadcsjmp(): Selector is zero",0);
                         return;
                 }
                 addr=seg&~7;
@@ -622,7 +632,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                 {
                         if (addr>=ldt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loacsjmp(): Selector > LDT limit",seg&~3);
                                 return;
                         }
                         addr+=ldt.base;
@@ -631,7 +641,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                 {
                         if (addr>=gdt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loacsjmp(): Selector > GDT limit",seg&~3);
                                 return;
                         }
                         addr+=gdt.base;
@@ -700,9 +710,14 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                                 cgate16=!cgate32;
                                 oldcs=CS;
                                 cpu_state.oldpc = cpu_state.pc;
-                                if ((DPL < CPL) || (DPL < (seg&3)))
+                                if (DPL < CPL)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("loadcsjmp(): Call gate DPL < CPL",seg&~3);
+                                        return;
+                                }
+                                if (DPL < (seg&3))
+                                {
+                                        x86gpf("loadcsjmp(): Call gate DPL< RPL",seg&~3);
                                         return;
                                 }
                                 if (DPL < CPL)
@@ -732,7 +747,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                                 {
                                         if (addr>=ldt.limit)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcsjmp(): Call gate selector > LDT limit",seg2&~3);
                                                 return;
                                         }
                                         addr+=ldt.base;
@@ -741,7 +756,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                                 {
                                         if (addr>=gdt.limit)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcsjmp(): Call gate selector > GDT limit",seg2&~3);
                                                 return;
                                         }
                                         addr+=gdt.base;
@@ -769,7 +784,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                                         case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
                                         if (DPL > CPL)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcsjmp(): Non-conforming DPL > CPL",seg2&~3);
                                                 return;
                                         }
 					/*FALLTHROUGH*/
@@ -789,7 +804,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
                                         break;
 
                                         default:
-                                        x86gpf(NULL,seg2&~3);
+                                        x86gpf("loadcsjmp(): Unknown type",seg2&~3);
                                         return;
                                 }
                                 cycles -= timing_jmp_pm_gate;
@@ -910,7 +925,7 @@ void loadcscall(uint16_t seg)
                 if (csout) x86seg_log("Protected mode CS load! %04X\n",seg);
                 if (!(seg&~3))
                 {
-                        x86gpf(NULL,0);
+                        x86gpf("loadcscall(): Protected mode selector is zero",0);
                         return;
                 }
                 addr=seg&~7;
@@ -918,7 +933,7 @@ void loadcscall(uint16_t seg)
                 {
                         if (addr>=ldt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcscall(): Selector > LDT limit",seg&~3);
                                 return;
                         }
                         addr+=ldt.base;
@@ -927,7 +942,7 @@ void loadcscall(uint16_t seg)
                 {
                         if (addr>=gdt.limit)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcscall(): Selector > GDT limit",seg&~3);
                                 return;
                         }
                         addr+=gdt.base;
@@ -948,18 +963,18 @@ void loadcscall(uint16_t seg)
                         {
                                 if ((seg&3)>CPL)
                                 {
-                                        x86gpf("loadcscall(): segment > CPL",seg&~3);
+                                        x86gpf("loadcscall(): Non-conforming RPL > CPL",seg&~3);
                                         return;
                                 }
                                 if (CPL != DPL)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("loadcscall(): Non-conforming CPL != DPL",seg&~3);
                                         return;
                                 }
                         }
                         if (CPL < DPL)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcscall(): CPL < DPL",seg&~3);
                                 return;
                         }
                         if (!(segdat[2]&0x8000))
@@ -1033,7 +1048,7 @@ void loadcscall(uint16_t seg)
                                 {
                                         if (addr>=ldt.limit)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcscall(): ex Selector > LDT limit",seg2&~3);
                                                 return;
                                         }
                                         addr+=ldt.base;
@@ -1042,7 +1057,7 @@ void loadcscall(uint16_t seg)
                                 {
                                         if (addr>=gdt.limit)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcscall(): ex Selector > GDT limit",seg2&~3);
                                                 return;
                                         }
                                         addr+=gdt.base;
@@ -1241,7 +1256,7 @@ void loadcscall(uint16_t seg)
                                         }
                                         else if (DPL > CPL)
                                         {
-                                                x86gpf(NULL,seg2&~3);
+                                                x86gpf("loadcscall(): Call PM Gate Inner DPL > CPL",seg2&~3);
                                                 return;
                                         }
 					/*FALLTHROUGH*/
@@ -1261,7 +1276,7 @@ void loadcscall(uint16_t seg)
                                         break;
                                         
                                         default:
-                                        x86gpf(NULL,seg2&~3);
+                                        x86gpf("loadcscall(): Unknown subtype",seg2&~3);
                                         return;
                                 }
                                 break;
@@ -1275,7 +1290,7 @@ void loadcscall(uint16_t seg)
                                 break;
 
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadcscall(): Unknown type",seg&~3);
                                 return;
                         }
                 }
@@ -1331,7 +1346,7 @@ void pmoderetf(int is32, uint16_t off)
         {
                 if (addr>=ldt.limit)
                 {
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmoderetf(): Selector > LDT limit",seg&~3);
                         return;
                 }
                 addr+=ldt.base;
@@ -1340,7 +1355,7 @@ void pmoderetf(int is32, uint16_t off)
         {
                 if (addr>=gdt.limit)
                 {
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmoderetf(): Selector > GDT limit",seg&~3);
                         return;
                 }
                 addr+=gdt.base;
@@ -1366,7 +1381,7 @@ void pmoderetf(int is32, uint16_t off)
                         if (CPL != DPL)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmoderetf(): Non-conforming CPL != DPL",seg&~3);
                                 return;
                         }
                         break;
@@ -1374,12 +1389,12 @@ void pmoderetf(int is32, uint16_t off)
                         if (CPL < DPL)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmoderetf(): Conforming CPL < DPL",seg&~3);
                                 return;
                         }
                         break;
                         default:
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmoderetf(): Unknown type",seg&~3);
                         return;
                 }
                 if (!(segdat[2]&0x8000))
@@ -1414,7 +1429,7 @@ void pmoderetf(int is32, uint16_t off)
                         if ((seg&3) != DPL)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmoderetf(): Non-conforming RPL != DPL",seg&~3);
                                 return;
                         }
                          x86seg_log("RETF non-conforming, %i %i\n",seg&3, DPL);
@@ -1423,14 +1438,14 @@ void pmoderetf(int is32, uint16_t off)
                         if ((seg&3) < DPL)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmoderetf(): Conforming RPL < DPL",seg&~3);
                                 return;
                         }
                          x86seg_log("RETF conforming, %i %i\n",seg&3, DPL);
                         break;
                         default:
                         ESP=oldsp;
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmoderetf(): Unknown type",seg&~3);
                         return;
                 }
                 if (!(segdat[2]&0x8000))
@@ -1455,7 +1470,7 @@ void pmoderetf(int is32, uint16_t off)
                 if (!(newss&~3))
                 {
                         ESP=oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmoderetf(): New SS selector is zero",newss&~3);
                         return;
                 }
                 addr=newss&~7;
@@ -1464,7 +1479,7 @@ void pmoderetf(int is32, uint16_t off)
                         if (addr>=ldt.limit)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,newss&~3);
+                                x86gpf("pmoderetf(): New SS selector > LDT limit",newss&~3);
                                 return;
                         }
                         addr+=ldt.base;
@@ -1474,7 +1489,7 @@ void pmoderetf(int is32, uint16_t off)
                         if (addr>=gdt.limit)
                         {
                                 ESP=oldsp;
-                                x86gpf(NULL,newss&~3);
+                                x86gpf("pmoderetf(): New SS selector > GDT limit",newss&~3);
                                 return;
                         }
                         addr+=gdt.base;
@@ -1488,13 +1503,13 @@ void pmoderetf(int is32, uint16_t off)
                 if ((newss & 3) != (seg & 3))
                 {
                         ESP=oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmoderetf(): New SS RPL > CS RPL",newss&~3);
                         return;
                 }
                 if ((segdat2[2]&0x1A00)!=0x1200)
                 {
                         ESP=oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmoderetf(): New SS unknown type",newss&~3);
                         return;
                 }
                 if (!(segdat2[2]&0x8000))
@@ -1506,7 +1521,7 @@ void pmoderetf(int is32, uint16_t off)
                 if (DPL2 != (seg & 3))
                 {
                         ESP=oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmoderetf(): New SS DPL != CS RPL",newss&~3);
                         return;
                 }
                 SS=newss;
@@ -1564,7 +1579,7 @@ void pmodeint(int num, int soft)
         if (cpu_state.eflags&VM_FLAG && IOPL!=3 && soft)
         {
                  x86seg_log("V86 banned int\n");
-                x86gpf(NULL,0);
+                x86gpf("pmodeint(): V86 banned int",0);
                 return;
         }
         addr=(num<<3);
@@ -1582,9 +1597,9 @@ void pmodeint(int num, int soft)
                 }
                 else
                 {
-                        x86gpf(NULL,(num*8)+2+((soft)?0:1));
+                        x86gpf("pmodeint(): Vector > IDT limit",(num*8)+2+((soft)?0:1));
                 }
-                 x86seg_log("addr >= IDT.limit\n");
+                x86seg_log("addr >= IDT.limit\n");
                 return;
         }
         addr+=idt.base;
@@ -1598,12 +1613,12 @@ void pmodeint(int num, int soft)
          x86seg_log("Addr %08X seg %04X %04X %04X %04X\n",addr,segdat[0],segdat[1],segdat[2],segdat[3]);
         if (!(segdat[2]&0x1F00))
         {
-                x86gpf(NULL,(num*8)+2);
+                x86gpf("pmodeint(): Vector descriptor with bad type",(num*8)+2);
                 return;
         }
         if (DPL<CPL && soft)
         {
-                x86gpf(NULL,(num*8)+2);
+                x86gpf("pmodeint(): Vector DPL < CPL",(num*8)+2);
                 return;
         }
         type=segdat[2]&0x1F00;
@@ -1624,7 +1639,7 @@ void pmodeint(int num, int soft)
                         {
                                 if (addr>=ldt.limit)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): Interrupt or trap gate selector > LDT limit",seg&~3);
                                         return;
                                 }
                                 addr+=ldt.base;
@@ -1633,7 +1648,7 @@ void pmodeint(int num, int soft)
                         {
                                 if (addr>=gdt.limit)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): Interrupt or trap gate selector > GDT limit", seg&~3);
                                         return;
                                 }
                                 addr+=gdt.base;
@@ -1647,7 +1662,7 @@ void pmodeint(int num, int soft)
                         
                         if (DPL2 > CPL)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmodeint(): Interrupt or trap gate DPL > CPL",seg&~3);
                                 return;
                         }
                         switch (segdat2[2]&0x1F00)
@@ -1662,7 +1677,7 @@ void pmodeint(int num, int soft)
                                         }
                                         if ((cpu_state.eflags&VM_FLAG) && DPL2)
                                         {
-                                                x86gpf(NULL,segdat[1]&0xFFFC);
+                                                x86gpf("pmodeint(): Interrupt or trap gate non-zero DPL in V86 mode",segdat[1]&0xFFFC);
                                                 return;
                                         }
                                         /*Load new stack*/
@@ -1774,7 +1789,7 @@ void pmodeint(int num, int soft)
                                 }
                                 else if (DPL2!=CPL)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): DPL != CPL",seg&~3);
                                         return;
                                 }
 				/*FALLTHROUGH*/
@@ -1786,7 +1801,7 @@ void pmodeint(int num, int soft)
                                 }
                                 if ((cpu_state.eflags & VM_FLAG) && DPL2<CPL)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): DPL < CPL in V86 mode",seg&~3);
                                         return;
                                 }
                                 if (type>0x800)
@@ -1804,7 +1819,7 @@ void pmodeint(int num, int soft)
                                 new_cpl = CS & 3;
                                 break;
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("pmodeint(): Unknown type",seg&~3);
                                 return;
                         }
                 do_seg_load(&cpu_state.seg_cs, segdat2);
@@ -1838,7 +1853,7 @@ void pmodeint(int num, int soft)
                         {
                                 if (addr>=ldt.limit)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): Task gate selector > LDT limit",seg&~3);
                                         return;
                                 }
                                 addr+=ldt.base;
@@ -1847,7 +1862,7 @@ void pmodeint(int num, int soft)
                         {
                                 if (addr>=gdt.limit)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("pmodeint(): Task gate selector > GDT limit",seg&~3);
                                         return;
                                 }
                                 addr+=gdt.base;
@@ -1926,7 +1941,7 @@ void pmodeiret(int is32)
                 if (seg&4)
                 {
                         x86seg_log("TS LDT %04X %04X IRET\n",seg,gdt.limit);
-                        x86ts(NULL,seg&~3);
+                        x86ts("pmodeiret(): Selector points to LDT",seg&~3);
                         return;
                 }
                 else
@@ -2016,7 +2031,7 @@ void pmodeiret(int is32)
                 if (addr>=ldt.limit)
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmodeiret(): Selector > LDT limit",seg&~3);
                         return;
                 }
                 addr+=ldt.base;
@@ -2026,7 +2041,7 @@ void pmodeiret(int is32)
                 if (addr>=gdt.limit)
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmodeiret(): Selector > GDT limit",seg&~3);
                         return;
                 }
                 addr+=gdt.base;
@@ -2034,7 +2049,7 @@ void pmodeiret(int is32)
         if ((seg&3) < CPL)
         {
                 ESP = oldsp;
-                x86gpf(NULL,seg&~3);
+                x86gpf("pmodeiret(): RPL < CPL",seg&~3);
                 return;
         }
         cpl_override=1;
@@ -2049,7 +2064,7 @@ void pmodeiret(int is32)
                 if ((seg&3) != DPL)
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmodeiret(): Non-conforming RPL != DPL",seg&~3);
                         return;
                 }
                 break;
@@ -2057,7 +2072,7 @@ void pmodeiret(int is32)
                 if ((seg&3) < DPL)
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,seg&~3);
+                        x86gpf("pmodeiret(): Conforming RPL < DPL",seg&~3);
                         return;
                 }
                 break;
@@ -2107,7 +2122,7 @@ void pmodeiret(int is32)
                 if (!(newss&~3))
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmodeiret(): New SS selector is zero",newss&~3);
                         return;
                 }
                 addr=newss&~7;
@@ -2116,7 +2131,7 @@ void pmodeiret(int is32)
                         if (addr>=ldt.limit)
                         {
                                 ESP = oldsp;
-                                x86gpf(NULL,newss&~3);
+                                x86gpf("pmodeiret(): New SS selector > LDT limit",newss&~3);
                                 return;
                         }
                         addr+=ldt.base;
@@ -2126,7 +2141,7 @@ void pmodeiret(int is32)
                         if (addr>=gdt.limit)
                         {
                                 ESP = oldsp;
-                                x86gpf(NULL,newss&~3);
+                                x86gpf("pmodeiret(): New SS selector > GDT limit",newss&~3);
                                 return;
                         }
                         addr+=gdt.base;
@@ -2139,19 +2154,19 @@ void pmodeiret(int is32)
                 if ((newss & 3) != (seg & 3))
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmodeiret(): New SS RPL > CS RPL",newss&~3);
                         return;
                 }
                 if ((segdat2[2]&0x1A00)!=0x1200)
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmodeiret(): New SS bad type",newss&~3);
                         return;
                 }
                 if (DPL2 != (seg & 3))
                 {
                         ESP = oldsp;
-                        x86gpf(NULL,newss&~3);
+                        x86gpf("pmodeiret(): New SS DPL != CS RPL",newss&~3);
                         return;
                 }
                 if (!(segdat2[2]&0x8000))
diff --git a/src/cpu_common/386.c b/src/cpu_common/386.c
index d9c6e2567..91670745f 100644
--- a/src/cpu_common/386.c
+++ b/src/cpu_common/386.c
@@ -280,33 +280,14 @@ exec386(int cycs)
 			}
 		}
 
-		if ((in_smm == 0) && smi_line) {
-#ifdef ENABLE_386_LOG
-			x386_log("SMI while not in SMM\n");
-#endif
-			enter_smm();
-			smi_line = 0;
-		} else if ((in_smm == 1) && smi_line) {
-			/* Mark this so that we don't latch more than one SMI. */
-#ifdef ENABLE_386_LOG
-			x386_log("SMI while in unlatched SMM\n");
-#endif
-			smi_latched = 1;
-			smi_line = 0;
-		} else if ((in_smm == 2) && smi_line) {
-			/* Mark this so that we don't latch more than one SMI. */
-#ifdef ENABLE_386_LOG
-			x386_log("SMI while in latched SMM\n");
-#endif
-			smi_line = 0;
-		}
-
 		ins_cycles -= cycles;
 		tsc += ins_cycles;
 
 		cycdiff = oldcyc - cycles;
 
-		if (trap) {
+		if (smi_line)
+			enter_smm_check(0);
+		else if (trap) {
 			flags_rebuild();
 			if (msw&1)
 				pmodeint(1,0);
diff --git a/src/cpu_common/386_common.c b/src/cpu_common/386_common.c
index cacaf8811..888d24fd5 100644
--- a/src/cpu_common/386_common.c
+++ b/src/cpu_common/386_common.c
@@ -20,10 +20,16 @@
 #include <86box/pit.h>
 #include <86box/fdd.h>
 #include <86box/fdc.h>
+#include <86box/keyboard.h>
 #include "386_common.h"
 #include "x86_flags.h"
+#include "x86seg.h"
 #include "codegen.h"
 
+
+#define CPU_BLOCK_END() cpu_block_end = 1
+
+
 x86seg gdt, ldt, idt, tr;
 
 uint32_t cr2, cr3, cr4;
@@ -55,6 +61,236 @@ uint32_t pccache;
 uint8_t *pccache2;
 
 
+int in_sys = 0;
+
+
+#define AMD_SYSCALL_EIP	(star & 0xFFFFFFFF)
+#define AMD_SYSCALL_SB	((star >> 32) & 0xFFFF)
+#define AMD_SYSRET_SB	((star >> 48) & 0xFFFF)
+
+
+/* These #define's and enum have been borrowed from Bochs. */
+/* SMM feature masks */
+#define SMM_IO_INSTRUCTION_RESTART  (0x00010000)
+#define SMM_SMBASE_RELOCATION       (0x00020000)
+
+/* TODO: Which CPU added SMBASE relocation? */
+#define SMM_REVISION_ID SMM_SMBASE_RELOCATION
+
+#define SMM_SAVE_STATE_MAP_SIZE 128
+
+
+enum SMMRAM_Fields_386_To_P5 {
+    SMRAM_FIELD_P5_CR0 = 0,		/* 1FC */
+    SMRAM_FIELD_P5_CR3,			/* 1F8 */
+    SMRAM_FIELD_P5_EFLAGS,		/* 1F4 */
+    SMRAM_FIELD_P5_EIP,			/* 1F0 */
+    SMRAM_FIELD_P5_EDI,			/* 1EC */
+    SMRAM_FIELD_P5_ESI,			/* 1E8 */
+    SMRAM_FIELD_P5_EBP,			/* 1E4 */
+    SMRAM_FIELD_P5_ESP,			/* 1E0 */
+    SMRAM_FIELD_P5_EBX,			/* 1DC */
+    SMRAM_FIELD_P5_EDX,			/* 1D8 */
+    SMRAM_FIELD_P5_ECX,			/* 1D4 */
+    SMRAM_FIELD_P5_EAX,			/* 1D0 */
+    SMRAM_FIELD_P5_DR6,			/* 1CC */
+    SMRAM_FIELD_P5_DR7,			/* 1C8 */
+    SMRAM_FIELD_P5_TR_SELECTOR,		/* 1C4 */
+    SMRAM_FIELD_P5_LDTR_SELECTOR,	/* 1C0 */
+    SMRAM_FIELD_P5_GS_SELECTOR,		/* 1BC */
+    SMRAM_FIELD_P5_FS_SELECTOR,		/* 1B8 */
+    SMRAM_FIELD_P5_DS_SELECTOR,		/* 1B4 */
+    SMRAM_FIELD_P5_SS_SELECTOR,		/* 1B0 */
+    SMRAM_FIELD_P5_CS_SELECTOR,		/* 1AC */
+    SMRAM_FIELD_P5_ES_SELECTOR,		/* 1A8 */
+    SMRAM_FIELD_P5_TR_ACCESS,		/* 1A4 */
+    SMRAM_FIELD_P5_TR_BASE,		/* 1A0 */
+    SMRAM_FIELD_P5_TR_LIMIT,		/* 19C */
+    SMRAM_FIELD_P5_IDTR_ACCESS,		/* 198 */
+    SMRAM_FIELD_P5_IDTR_BASE,		/* 194 */
+    SMRAM_FIELD_P5_IDTR_LIMIT,		/* 190 */
+    SMRAM_FIELD_P5_GDTR_ACCESS,		/* 18C */
+    SMRAM_FIELD_P5_GDTR_BASE,		/* 188 */
+    SMRAM_FIELD_P5_GDTR_LIMIT,		/* 184 */
+    SMRAM_FIELD_P5_LDTR_ACCESS,		/* 180 */
+    SMRAM_FIELD_P5_LDTR_BASE,		/* 17C */
+    SMRAM_FIELD_P5_LDTR_LIMIT,		/* 178 */
+    SMRAM_FIELD_P5_GS_ACCESS,		/* 174 */
+    SMRAM_FIELD_P5_GS_BASE,		/* 170 */
+    SMRAM_FIELD_P5_GS_LIMIT,		/* 16C */
+    SMRAM_FIELD_P5_FS_ACCESS,		/* 168 */
+    SMRAM_FIELD_P5_FS_BASE,		/* 164 */
+    SMRAM_FIELD_P5_FS_LIMIT,		/* 160 */
+    SMRAM_FIELD_P5_DS_ACCESS,		/* 15C */
+    SMRAM_FIELD_P5_DS_BASE,		/* 158 */
+    SMRAM_FIELD_P5_DS_LIMIT,		/* 154 */
+    SMRAM_FIELD_P5_SS_ACCESS,		/* 150 */
+    SMRAM_FIELD_P5_SS_BASE,		/* 14C */
+    SMRAM_FIELD_P5_SS_LIMIT,		/* 148 */
+    SMRAM_FIELD_P5_CS_ACCESS,		/* 144 */
+    SMRAM_FIELD_P5_CS_BASE,		/* 140 */
+    SMRAM_FIELD_P5_CS_LIMIT,		/* 13C */
+    SMRAM_FIELD_P5_ES_ACCESS,		/* 138 */
+    SMRAM_FIELD_P5_ES_BASE,		/* 134 */
+    SMRAM_FIELD_P5_ES_LIMIT,		/* 130 */
+    SMRAM_FIELD_P5_UNWRITTEN_1,		/* 12C */
+    SMRAM_FIELD_P5_CR4,			/* 128 */
+    SMRAM_FIELD_P5_ALTERNATE_DR6,	/* 124 */
+    SMRAM_FIELD_P5_RESERVED_1,		/* 120 */
+    SMRAM_FIELD_P5_RESERVED_2,		/* 11C */
+    SMRAM_FIELD_P5_RESERVED_3,		/* 118 */
+    SMRAM_FIELD_P5_RESERVED_4,		/* 114 */
+    SMRAM_FIELD_P5_IO_RESTART_EIP,	/* 110 */
+    SMRAM_FIELD_P5_IO_RESTART_ESI,	/* 10C */
+    SMRAM_FIELD_P5_IO_RESTART_ECX,	/* 108 */
+    SMRAM_FIELD_P5_IO_RESTART_EDI,	/* 104 */
+    SMRAM_FIELD_P5_AUTOHALT_RESTART,	/* 100 */
+    SMRAM_FIELD_P5_SMM_REVISION_ID,	/* 0FC */
+    SMRAM_FIELD_P5_SMBASE_OFFSET,	/* 0F8 */
+    SMRAM_FIELD_P5_LAST
+};
+
+enum SMMRAM_Fields_P6 {
+    SMRAM_FIELD_P6_CR0 = 0,		/* 1FC */
+    SMRAM_FIELD_P6_CR3,			/* 1F8 */
+    SMRAM_FIELD_P6_EFLAGS,		/* 1F4 */
+    SMRAM_FIELD_P6_EIP,			/* 1F0 */
+    SMRAM_FIELD_P6_EDI,			/* 1EC */
+    SMRAM_FIELD_P6_ESI,			/* 1E8 */
+    SMRAM_FIELD_P6_EBP,			/* 1E4 */
+    SMRAM_FIELD_P6_ESP,			/* 1E0 */
+    SMRAM_FIELD_P6_EBX,			/* 1DC */
+    SMRAM_FIELD_P6_EDX,			/* 1D8 */
+    SMRAM_FIELD_P6_ECX,			/* 1D4 */
+    SMRAM_FIELD_P6_EAX,			/* 1D0 */
+    SMRAM_FIELD_P6_DR6,			/* 1CC */
+    SMRAM_FIELD_P6_DR7,			/* 1C8 */
+    SMRAM_FIELD_P6_TR_SELECTOR,		/* 1C4 */
+    SMRAM_FIELD_P6_LDTR_SELECTOR,	/* 1C0 */
+    SMRAM_FIELD_P6_GS_SELECTOR,		/* 1BC */
+    SMRAM_FIELD_P6_FS_SELECTOR,		/* 1B8 */
+    SMRAM_FIELD_P6_DS_SELECTOR,		/* 1B4 */
+    SMRAM_FIELD_P6_SS_SELECTOR,		/* 1B0 */
+    SMRAM_FIELD_P6_CS_SELECTOR,		/* 1AC */
+    SMRAM_FIELD_P6_ES_SELECTOR,		/* 1A8 */
+    SMRAM_FIELD_P6_SS_BASE,		/* 1A4 */
+    SMRAM_FIELD_P6_SS_LIMIT,		/* 1A0 */
+    SMRAM_FIELD_P6_SS_SELECTOR_AR,	/* 19C */
+    SMRAM_FIELD_P6_CS_BASE,		/* 198 */
+    SMRAM_FIELD_P6_CS_LIMIT,		/* 194 */
+    SMRAM_FIELD_P6_CS_SELECTOR_AR,	/* 190 */
+    SMRAM_FIELD_P6_ES_BASE,		/* 18C */
+    SMRAM_FIELD_P6_ES_LIMIT,		/* 188 */
+    SMRAM_FIELD_P6_ES_SELECTOR_AR,	/* 184 */
+    SMRAM_FIELD_P6_LDTR_BASE,		/* 180 */
+    SMRAM_FIELD_P6_LDTR_LIMIT,		/* 17C */
+    SMRAM_FIELD_P6_LDTR_SELECTOR_AR,	/* 178 */
+    SMRAM_FIELD_P6_GDTR_BASE,		/* 174 */
+    SMRAM_FIELD_P6_GDTR_LIMIT,		/* 170 */
+    SMRAM_FIELD_P6_GDTR_SELECTOR_AR,	/* 16C */
+    SMRAM_FIELD_P6_SREG_STATUS1,	/* 168 */
+    SMRAM_FIELD_P6_TR_BASE,		/* 164 */
+    SMRAM_FIELD_P6_TR_LIMIT,		/* 160 */
+    SMRAM_FIELD_P6_TR_SELECTOR_AR,	/* 15C */
+    SMRAM_FIELD_P6_IDTR_BASE,		/* 158 */
+    SMRAM_FIELD_P6_IDTR_LIMIT,		/* 154 */
+    SMRAM_FIELD_P6_IDTR_SELECTOR_AR,	/* 150 */
+    SMRAM_FIELD_P6_GS_BASE,		/* 14C */
+    SMRAM_FIELD_P6_GS_LIMIT,		/* 148 */
+    SMRAM_FIELD_P6_GS_SELECTOR_AR,	/* 144 */
+    SMRAM_FIELD_P6_FS_BASE,		/* 140 */
+    SMRAM_FIELD_P6_FS_LIMIT,		/* 13C */
+    SMRAM_FIELD_P6_FS_SELECTOR_AR,	/* 138 */
+    SMRAM_FIELD_P6_DS_BASE,		/* 134 */
+    SMRAM_FIELD_P6_DS_LIMIT,		/* 130 */
+    SMRAM_FIELD_P6_DS_SELECTOR_AR,	/* 12C */
+    SMRAM_FIELD_P6_SREG_STATUS0,	/* 128 */
+    SMRAM_FIELD_P6_ALTERNATIVE_DR6,	/* 124 */
+    SMRAM_FIELD_P6_CPL,			/* 120 */
+    SMRAM_FIELD_P6_SMM_STATUS,		/* 11C */
+    SMRAM_FIELD_P6_A20M,		/* 118 */
+    SMRAM_FIELD_P6_CR4,			/* 114 */
+    SMRAM_FIELD_P6_IO_RESTART_EIP,	/* 110 */
+    SMRAM_FIELD_P6_IO_RESTART_ESI,	/* 10C */
+    SMRAM_FIELD_P6_IO_RESTART_ECX,	/* 108 */
+    SMRAM_FIELD_P6_IO_RESTART_EDI,	/* 104 */
+    SMRAM_FIELD_P6_AUTOHALT_RESTART,	/* 100 */
+    SMRAM_FIELD_P6_SMM_REVISION_ID,	/* 0FC */
+    SMRAM_FIELD_P6_SMBASE_OFFSET,	/* 0F8 */
+    SMRAM_FIELD_P6_LAST
+};
+
+enum SMMRAM_Fields_AMD_K {
+    SMRAM_FIELD_AMD_K_CR0 = 0,		/* 1FC */
+    SMRAM_FIELD_AMD_K_CR3,		/* 1F8 */
+    SMRAM_FIELD_AMD_K_EFLAGS,		/* 1F4 */
+    SMRAM_FIELD_AMD_K_EIP,		/* 1F0 */
+    SMRAM_FIELD_AMD_K_EDI,		/* 1EC */
+    SMRAM_FIELD_AMD_K_ESI,		/* 1E8 */
+    SMRAM_FIELD_AMD_K_EBP,		/* 1E4 */
+    SMRAM_FIELD_AMD_K_ESP,		/* 1E0 */
+    SMRAM_FIELD_AMD_K_EBX,		/* 1DC */
+    SMRAM_FIELD_AMD_K_EDX,		/* 1D8 */
+    SMRAM_FIELD_AMD_K_ECX,		/* 1D4 */
+    SMRAM_FIELD_AMD_K_EAX,		/* 1D0 */
+    SMRAM_FIELD_AMD_K_DR6,		/* 1CC */
+    SMRAM_FIELD_AMD_K_DR7,		/* 1C8 */
+    SMRAM_FIELD_AMD_K_TR_SELECTOR,	/* 1C4 */
+    SMRAM_FIELD_AMD_K_LDTR_SELECTOR,	/* 1C0 */
+    SMRAM_FIELD_AMD_K_GS_SELECTOR,	/* 1BC */
+    SMRAM_FIELD_AMD_K_FS_SELECTOR,	/* 1B8 */
+    SMRAM_FIELD_AMD_K_DS_SELECTOR,	/* 1B4 */
+    SMRAM_FIELD_AMD_K_SS_SELECTOR,	/* 1B0 */
+    SMRAM_FIELD_AMD_K_CS_SELECTOR,	/* 1AC */
+    SMRAM_FIELD_AMD_K_ES_SELECTOR,	/* 1A8 */
+    SMRAM_FIELD_AMD_K_IO_RESTART_DWORD,	/* 1A4 */
+    SMRAM_FIELD_AMD_K_RESERVED_1,	/* 1A0 */
+    SMRAM_FIELD_AMD_K_IO_RESTART_EIP,	/* 19C */
+    SMRAM_FIELD_AMD_K_RESERVED_2,	/* 198 */
+    SMRAM_FIELD_AMD_K_RESERVED_3,	/* 194 */
+    SMRAM_FIELD_AMD_K_IDTR_BASE,	/* 190 */
+    SMRAM_FIELD_AMD_K_IDTR_LIMIT,	/* 18C */
+    SMRAM_FIELD_AMD_K_GDTR_BASE,	/* 188 */
+    SMRAM_FIELD_AMD_K_GDTR_LIMIT,	/* 184 */
+    SMRAM_FIELD_AMD_K_TR_ACCESS,	/* 180 */
+    SMRAM_FIELD_AMD_K_TR_BASE,		/* 17C */
+    SMRAM_FIELD_AMD_K_TR_LIMIT,		/* 178 */
+    SMRAM_FIELD_AMD_K_LDTR_ACCESS,	/* 174 - reserved on K6 */
+    SMRAM_FIELD_AMD_K_LDTR_BASE,	/* 170 */
+    SMRAM_FIELD_AMD_K_LDTR_LIMIT,	/* 16C */
+    SMRAM_FIELD_AMD_K_GS_ACCESS,	/* 168 */
+    SMRAM_FIELD_AMD_K_GS_BASE,		/* 164 */
+    SMRAM_FIELD_AMD_K_GS_LIMIT,		/* 160 */
+    SMRAM_FIELD_AMD_K_FS_ACCESS,	/* 15C */
+    SMRAM_FIELD_AMD_K_FS_BASE,		/* 158 */
+    SMRAM_FIELD_AMD_K_FS_LIMIT,		/* 154 */
+    SMRAM_FIELD_AMD_K_DS_ACCESS,	/* 150 */
+    SMRAM_FIELD_AMD_K_DS_BASE,		/* 14C */
+    SMRAM_FIELD_AMD_K_DS_LIMIT,		/* 148 */
+    SMRAM_FIELD_AMD_K_SS_ACCESS,	/* 144 */
+    SMRAM_FIELD_AMD_K_SS_BASE,		/* 140 */
+    SMRAM_FIELD_AMD_K_SS_LIMIT,		/* 13C */
+    SMRAM_FIELD_AMD_K_CS_ACCESS,	/* 138 */
+    SMRAM_FIELD_AMD_K_CS_BASE,		/* 134 */
+    SMRAM_FIELD_AMD_K_CS_LIMIT,		/* 130 */
+    SMRAM_FIELD_AMD_K_ES_ACCESS,	/* 12C */
+    SMRAM_FIELD_AMD_K_ES_BASE,		/* 128 */
+    SMRAM_FIELD_AMD_K_ES_LIMIT,		/* 124 */
+    SMRAM_FIELD_AMD_K_RESERVED_4,	/* 120 */
+    SMRAM_FIELD_AMD_K_RESERVED_5,	/* 11C */
+    SMRAM_FIELD_AMD_K_RESERVED_6,	/* 118 */
+    SMRAM_FIELD_AMD_K_CR2,		/* 114 */
+    SMRAM_FIELD_AMD_K_CR4,		/* 110 */
+    SMRAM_FIELD_AMD_K_IO_RESTART_ESI,	/* 10C */
+    SMRAM_FIELD_AMD_K_IO_RESTART_ECX,	/* 108 */
+    SMRAM_FIELD_AMD_K_IO_RESTART_EDI,	/* 104 */
+    SMRAM_FIELD_AMD_K_AUTOHALT_RESTART,	/* 100 */
+    SMRAM_FIELD_AMD_K_SMM_REVISION_ID,	/* 0FC */
+    SMRAM_FIELD_AMD_K_SMBASE_OFFSET,	/* 0F8 */
+    SMRAM_FIELD_AMD_K_LAST
+};
+
+
 #ifdef ENABLE_386_COMMON_LOG
 int x386_common_do_log = ENABLE_386_COMMON_LOG;
 
@@ -75,235 +311,1465 @@ x386_common_log(const char *fmt, ...)
 #endif
 
 
-void x86_int(int num)
+static __inline void
+set_stack32(int s)
 {
-        uint32_t addr;
-        flags_rebuild();
-        cpu_state.pc=cpu_state.oldpc;
-        if (msw&1)
-        {
-                pmodeint(num,0);
-        }
-        else
-        {
-                addr = (num << 2) + idt.base;
+    stack32 = s;
 
-                if ((num << 2) + 3 > idt.limit)
-                {
-                        if (idt.limit < 35)
-                        {
-                                cpu_state.abrt = 0;
-                                softresetx86();
-                                cpu_set_edx();
+    if (stack32)
+	cpu_cur_status |= CPU_STATUS_STACK32;
+    else
+	cpu_cur_status &= ~CPU_STATUS_STACK32;
+}
+
+
+static __inline void
+set_use32(int u)
+{
+    if (u) {
+	use32 = 0x300;
+	cpu_cur_status |= CPU_STATUS_USE32;
+    } else {
+	use32 = 0;
+	cpu_cur_status &= ~CPU_STATUS_USE32;
+    }
+}
+
+
+static void
+smm_seg_load(x86seg *s)
+{
+    if (!is386)
+	s->base &= 0x00ffffff;
+
+    if ((s->access & 0x18) != 0x10 || !(s->access & (1 << 2))) {
+	/* Expand down. */
+	s->limit_high = s->limit;
+	s->limit_low = 0;
+    } else {
+	s->limit_high = (s->ar_high & 0x40) ? 0xffffffff : 0xffff;
+	s->limit_low = s->limit + 1;
+    }
+
+    if ((cr0 & 1) && !(cpu_state.eflags & VM_FLAG))
+	s->checked = s->seg ? 1 : 0;
+    else
+	s->checked = 1;
+
+    if (s == &cpu_state.seg_cs)
+	set_use32(s->ar_high & 0x40);
+
+    if (s == &cpu_state.seg_ds) {
+	if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
+		cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
+	else
+		cpu_cur_status |= CPU_STATUS_NOTFLATDS;
+    }
+
+    if (s == &cpu_state.seg_ss) {
+	if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
+		cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
+	else
+		cpu_cur_status |= CPU_STATUS_NOTFLATSS;
+	set_stack32((s->ar_high & 0x40) ? 1 : 0);
+    }
+}
+
+
+static void
+smram_save_state_p5(uint32_t *saved_state, int in_hlt)
+{
+    int n = 0;
+
+    saved_state[SMRAM_FIELD_P5_SMM_REVISION_ID] = SMM_REVISION_ID;
+    saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET] = smbase;
+
+    for (n = 0; n < 8; n++)
+	saved_state[SMRAM_FIELD_P5_EAX - n] = cpu_state.regs[n].l;
+
+    if (in_hlt)
+	saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] = 1;
+    else
+	saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] = 0;
+
+    saved_state[SMRAM_FIELD_P5_EIP] = cpu_state.pc;
+
+    saved_state[SMRAM_FIELD_P5_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
+
+    saved_state[SMRAM_FIELD_P5_CR0] = cr0;
+    saved_state[SMRAM_FIELD_P5_CR3] = cr3;
+    saved_state[SMRAM_FIELD_P5_CR4] = cr4;
+    saved_state[SMRAM_FIELD_P5_DR6] = dr[6];
+    saved_state[SMRAM_FIELD_P5_DR7] = dr[7];
+
+    /* TR */
+    saved_state[SMRAM_FIELD_P5_TR_SELECTOR] = tr.seg;
+    saved_state[SMRAM_FIELD_P5_TR_BASE] = tr.base;
+    saved_state[SMRAM_FIELD_P5_TR_LIMIT] = tr.limit;
+    saved_state[SMRAM_FIELD_P5_TR_ACCESS] = (tr.ar_high << 16) | (tr.access << 8);
+
+    /* LDTR */
+    saved_state[SMRAM_FIELD_P5_LDTR_SELECTOR] = ldt.seg;
+    saved_state[SMRAM_FIELD_P5_LDTR_BASE] = ldt.base;
+    saved_state[SMRAM_FIELD_P5_LDTR_LIMIT] = ldt.limit;
+    saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] = (ldt.ar_high << 16) | (ldt.access << 8);
+
+    /* IDTR */
+    saved_state[SMRAM_FIELD_P5_IDTR_BASE] = idt.base;
+    saved_state[SMRAM_FIELD_P5_IDTR_LIMIT] = idt.limit;
+    saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] = (idt.ar_high << 16) | (idt.access << 8);
+
+    /* GDTR */
+    saved_state[SMRAM_FIELD_P5_GDTR_BASE] = gdt.base;
+    saved_state[SMRAM_FIELD_P5_GDTR_LIMIT] = gdt.limit;
+    saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] = (gdt.ar_high << 16) | (gdt.access << 8);
+
+    /* ES */
+    saved_state[SMRAM_FIELD_P5_ES_SELECTOR] = cpu_state.seg_es.seg;
+    saved_state[SMRAM_FIELD_P5_ES_BASE] = cpu_state.seg_es.base;
+    saved_state[SMRAM_FIELD_P5_ES_LIMIT] = cpu_state.seg_es.limit;
+    saved_state[SMRAM_FIELD_P5_ES_ACCESS] = (cpu_state.seg_es.ar_high << 16) | (cpu_state.seg_es.access << 8);
+
+    /* CS */
+    saved_state[SMRAM_FIELD_P5_CS_SELECTOR] = cpu_state.seg_cs.seg;
+    saved_state[SMRAM_FIELD_P5_CS_BASE] = cpu_state.seg_cs.base;
+    saved_state[SMRAM_FIELD_P5_CS_LIMIT] = cpu_state.seg_cs.limit;
+    saved_state[SMRAM_FIELD_P5_CS_ACCESS] = (cpu_state.seg_cs.ar_high << 16) | (cpu_state.seg_cs.access << 8);
+
+    /* DS */
+    saved_state[SMRAM_FIELD_P5_DS_SELECTOR] = cpu_state.seg_ds.seg;
+    saved_state[SMRAM_FIELD_P5_DS_BASE] = cpu_state.seg_ds.base;
+    saved_state[SMRAM_FIELD_P5_DS_LIMIT] = cpu_state.seg_ds.limit;
+    saved_state[SMRAM_FIELD_P5_DS_ACCESS] = (cpu_state.seg_ds.ar_high << 16) | (cpu_state.seg_ds.access << 8);
+
+    /* SS */
+    saved_state[SMRAM_FIELD_P5_SS_SELECTOR] = cpu_state.seg_ss.seg;
+    saved_state[SMRAM_FIELD_P5_SS_BASE] = cpu_state.seg_ss.base;
+    saved_state[SMRAM_FIELD_P5_SS_LIMIT] = cpu_state.seg_ss.limit;
+    saved_state[SMRAM_FIELD_P5_SS_ACCESS] = (cpu_state.seg_ss.ar_high << 16) | (cpu_state.seg_ss.access << 8);
+
+    /* FS */
+    saved_state[SMRAM_FIELD_P5_FS_SELECTOR] = cpu_state.seg_fs.seg;
+    saved_state[SMRAM_FIELD_P5_FS_BASE] = cpu_state.seg_fs.base;
+    saved_state[SMRAM_FIELD_P5_FS_LIMIT] = cpu_state.seg_fs.limit;
+    saved_state[SMRAM_FIELD_P5_FS_ACCESS] = (cpu_state.seg_fs.ar_high << 16) | (cpu_state.seg_fs.access << 8);
+
+    /* GS */
+    saved_state[SMRAM_FIELD_P5_GS_SELECTOR] = cpu_state.seg_gs.seg;
+    saved_state[SMRAM_FIELD_P5_GS_BASE] = cpu_state.seg_gs.base;
+    saved_state[SMRAM_FIELD_P5_GS_LIMIT] = cpu_state.seg_gs.limit;
+    saved_state[SMRAM_FIELD_P5_GS_ACCESS] = (cpu_state.seg_gs.ar_high << 16) | (cpu_state.seg_gs.access << 8);
+}
+
+
+static void
+smram_restore_state_p5(uint32_t *saved_state)
+{
+    int n = 0;
+
+    for (n = 0; n < 8; n++)
+	cpu_state.regs[n].l = saved_state[SMRAM_FIELD_P5_EAX - n];
+
+    if (saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] & 0xffff)
+	cpu_state.pc = saved_state[SMRAM_FIELD_P5_EIP] - 1;
+    else
+	cpu_state.pc = saved_state[SMRAM_FIELD_P5_EIP];
+
+    cpu_state.eflags = saved_state[SMRAM_FIELD_P5_EFLAGS] >> 16;
+    cpu_state.flags = saved_state[SMRAM_FIELD_P5_EFLAGS] & 0xffff;
+
+    cr0 = saved_state[SMRAM_FIELD_P5_CR0];
+    cr3 = saved_state[SMRAM_FIELD_P5_CR3];
+    cr4 = saved_state[SMRAM_FIELD_P5_CR4];
+    dr[6] = saved_state[SMRAM_FIELD_P5_DR6];
+    dr[7] = saved_state[SMRAM_FIELD_P5_DR7];
+
+    /* TR */
+    tr.seg = saved_state[SMRAM_FIELD_P5_TR_SELECTOR];
+    tr.base = saved_state[SMRAM_FIELD_P5_TR_BASE];
+    tr.limit = saved_state[SMRAM_FIELD_P5_TR_LIMIT];
+    tr.access = (saved_state[SMRAM_FIELD_P5_TR_ACCESS] >> 8) & 0xff;
+    tr.ar_high = (saved_state[SMRAM_FIELD_P5_TR_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&tr);
+
+    /* LDTR */
+    ldt.seg = saved_state[SMRAM_FIELD_P5_LDTR_SELECTOR];
+    ldt.base = saved_state[SMRAM_FIELD_P5_LDTR_BASE];
+    ldt.limit = saved_state[SMRAM_FIELD_P5_LDTR_LIMIT];
+    ldt.access = (saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] >> 8) & 0xff;
+    ldt.ar_high = (saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&ldt);
+
+    /* IDTR */
+    idt.base = saved_state[SMRAM_FIELD_P5_IDTR_BASE];
+    idt.limit = saved_state[SMRAM_FIELD_P5_IDTR_LIMIT];
+    idt.access = (saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] >> 8) & 0xff;
+    idt.ar_high = (saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] >> 16) & 0xff;
+
+    /* GDTR */
+    gdt.base = saved_state[SMRAM_FIELD_P5_GDTR_BASE];
+    gdt.limit = saved_state[SMRAM_FIELD_P5_GDTR_LIMIT];
+    gdt.access = (saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] >> 8) & 0xff;
+    gdt.ar_high = (saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] >> 16) & 0xff;
+
+    /* ES */
+    cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_P5_ES_SELECTOR];
+    cpu_state.seg_es.base = saved_state[SMRAM_FIELD_P5_ES_BASE];
+    cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_P5_ES_LIMIT];
+    cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_P5_ES_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_P5_ES_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_es);
+
+    /* CS */
+    cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_P5_CS_SELECTOR];
+    cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_P5_CS_BASE];
+    cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_P5_CS_LIMIT];
+    cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_P5_CS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_P5_CS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_cs);
+
+    /* DS */
+    cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_P5_DS_SELECTOR];
+    cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_P5_DS_BASE];
+    cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_P5_DS_LIMIT];
+    cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_P5_DS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_P5_DS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_ds);
+
+    /* SS */
+    cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_P5_SS_SELECTOR];
+    cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_P5_SS_BASE];
+    cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_P5_SS_LIMIT];
+    cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_P5_SS_ACCESS] >> 8) & 0xff;
+    /* The actual CPL (DPL of CS) is overwritten with DPL of SS. */
+    cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | (cpu_state.seg_ss.access & 0x60);
+    cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_P5_SS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_ss);
+
+    /* FS */
+    cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_P5_FS_SELECTOR];
+    cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_P5_FS_BASE];
+    cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_P5_FS_LIMIT];
+    cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_P5_FS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_P5_FS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_fs);
+
+    /* GS */
+    cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_P5_GS_SELECTOR];
+    cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_P5_GS_BASE];
+    cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_P5_GS_LIMIT];
+    cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_P5_GS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_P5_GS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_gs);
+
+    if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
+	smbase = saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET];
+}
+
+
+static void
+smram_save_state_p6(uint32_t *saved_state, int in_hlt)
+{
+    int n = 0;
+
+    saved_state[SMRAM_FIELD_P6_SMM_REVISION_ID] = SMM_REVISION_ID;
+    saved_state[SMRAM_FIELD_P6_SMBASE_OFFSET] = smbase;
+
+    for (n = 0; n < 8; n++)
+	saved_state[SMRAM_FIELD_P6_EAX - n] = cpu_state.regs[n].l;
+
+    if (in_hlt)
+	saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] = 1;
+    else
+	saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] = 0;
+    saved_state[SMRAM_FIELD_P6_EIP] = cpu_state.pc;
+
+    saved_state[SMRAM_FIELD_P6_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
+
+    saved_state[SMRAM_FIELD_P6_CR0] = cr0;
+    saved_state[SMRAM_FIELD_P6_CR3] = cr3;
+    saved_state[SMRAM_FIELD_P6_CR4] = cr4;
+    saved_state[SMRAM_FIELD_P6_DR6] = dr[6];
+    saved_state[SMRAM_FIELD_P6_DR7] = dr[7];
+    saved_state[SMRAM_FIELD_P6_CPL] = CPL;
+    saved_state[SMRAM_FIELD_P6_A20M] = !mem_a20_state;
+
+    /* TR */
+    saved_state[SMRAM_FIELD_P6_TR_SELECTOR] = tr.seg;
+    saved_state[SMRAM_FIELD_P6_TR_BASE] = tr.base;
+    saved_state[SMRAM_FIELD_P6_TR_LIMIT] = tr.limit;
+    saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] = (tr.ar_high << 24) | (tr.access << 16) | tr.seg;
+
+    /* LDTR */
+    saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR] = ldt.seg;
+    saved_state[SMRAM_FIELD_P6_LDTR_BASE] = ldt.base;
+    saved_state[SMRAM_FIELD_P6_LDTR_LIMIT] = ldt.limit;
+    saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] = (ldt.ar_high << 24) | (ldt.access << 16) | ldt.seg;
+
+    /* IDTR */
+    saved_state[SMRAM_FIELD_P6_IDTR_BASE] = idt.base;
+    saved_state[SMRAM_FIELD_P6_IDTR_LIMIT] = idt.limit;
+    saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] = (idt.ar_high << 24) | (idt.access << 16) | idt.seg;
+
+    /* GDTR */
+    saved_state[SMRAM_FIELD_P6_GDTR_BASE] = gdt.base;
+    saved_state[SMRAM_FIELD_P6_GDTR_LIMIT] = gdt.limit;
+    saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] = (gdt.ar_high << 24) | (gdt.access << 16) | gdt.seg;
+
+    /* ES */
+    saved_state[SMRAM_FIELD_P6_ES_SELECTOR] = cpu_state.seg_es.seg;
+    saved_state[SMRAM_FIELD_P6_ES_BASE] = cpu_state.seg_es.base;
+    saved_state[SMRAM_FIELD_P6_ES_LIMIT] = cpu_state.seg_es.limit;
+    saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] =
+	(cpu_state.seg_es.ar_high << 24) | (cpu_state.seg_es.access << 16) | cpu_state.seg_es.seg;
+
+    /* CS */
+    saved_state[SMRAM_FIELD_P6_CS_SELECTOR] = cpu_state.seg_cs.seg;
+    saved_state[SMRAM_FIELD_P6_CS_BASE] = cpu_state.seg_cs.base;
+    saved_state[SMRAM_FIELD_P6_CS_LIMIT] = cpu_state.seg_cs.limit;
+    saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] =
+	(cpu_state.seg_cs.ar_high << 24) | (cpu_state.seg_cs.access << 16) | cpu_state.seg_cs.seg;
+
+    /* DS */
+    saved_state[SMRAM_FIELD_P6_DS_SELECTOR] = cpu_state.seg_ds.seg;
+    saved_state[SMRAM_FIELD_P6_DS_BASE] = cpu_state.seg_ds.base;
+    saved_state[SMRAM_FIELD_P6_DS_LIMIT] = cpu_state.seg_ds.limit;
+    saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] =
+	(cpu_state.seg_ds.ar_high << 24) | (cpu_state.seg_ds.access << 16) | cpu_state.seg_ds.seg;
+
+    /* SS */
+    saved_state[SMRAM_FIELD_P6_SS_SELECTOR] = cpu_state.seg_ss.seg;
+    saved_state[SMRAM_FIELD_P6_SS_BASE] = cpu_state.seg_ss.base;
+    saved_state[SMRAM_FIELD_P6_SS_LIMIT] = cpu_state.seg_ss.limit;
+    saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] =
+	(cpu_state.seg_ss.ar_high << 24) | (cpu_state.seg_ss.access << 16) | cpu_state.seg_ss.seg;
+
+    /* FS */
+    saved_state[SMRAM_FIELD_P6_FS_SELECTOR] = cpu_state.seg_fs.seg;
+    saved_state[SMRAM_FIELD_P6_FS_BASE] = cpu_state.seg_fs.base;
+    saved_state[SMRAM_FIELD_P6_FS_LIMIT] = cpu_state.seg_fs.limit;
+    saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] =
+	(cpu_state.seg_fs.ar_high << 24) | (cpu_state.seg_fs.access << 16) | cpu_state.seg_fs.seg;
+
+    /* GS */
+    saved_state[SMRAM_FIELD_P6_GS_SELECTOR] = cpu_state.seg_gs.seg;
+    saved_state[SMRAM_FIELD_P6_GS_BASE] = cpu_state.seg_gs.base;
+    saved_state[SMRAM_FIELD_P6_GS_LIMIT] = cpu_state.seg_gs.limit;
+    saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] =
+	(cpu_state.seg_gs.ar_high << 24) | (cpu_state.seg_gs.access << 16) | cpu_state.seg_gs.seg;
+}
+
+
+static void
+smram_restore_state_p6(uint32_t *saved_state)
+{
+    int n = 0;
+
+    for (n = 0; n < 8; n++)
+	cpu_state.regs[n].l = saved_state[SMRAM_FIELD_P6_EAX - n];
+
+    if (saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] & 0xffff)
+	cpu_state.pc = saved_state[SMRAM_FIELD_P6_EIP] - 1;
+    else
+	cpu_state.pc = saved_state[SMRAM_FIELD_P6_EIP];
+
+    cpu_state.eflags = saved_state[SMRAM_FIELD_P6_EFLAGS] >> 16;
+    cpu_state.flags = saved_state[SMRAM_FIELD_P6_EFLAGS] & 0xffff;
+
+    cr0 = saved_state[SMRAM_FIELD_P6_CR0];
+    cr3 = saved_state[SMRAM_FIELD_P6_CR3];
+    cr4 = saved_state[SMRAM_FIELD_P6_CR4];
+    dr[6] = saved_state[SMRAM_FIELD_P6_DR6];
+    dr[7] = saved_state[SMRAM_FIELD_P6_DR7];
+
+    /* TR */
+    tr.seg = saved_state[SMRAM_FIELD_P6_TR_SELECTOR];
+    tr.base = saved_state[SMRAM_FIELD_P6_TR_BASE];
+    tr.limit = saved_state[SMRAM_FIELD_P6_TR_LIMIT];
+    tr.access = (saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] >> 16) & 0xff;
+    tr.ar_high = (saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&tr);
+
+    /* LDTR */
+    ldt.seg = saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR];
+    ldt.base = saved_state[SMRAM_FIELD_P6_LDTR_BASE];
+    ldt.limit = saved_state[SMRAM_FIELD_P6_LDTR_LIMIT];
+    ldt.access = (saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] >> 16) & 0xff;
+    ldt.ar_high = (saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&ldt);
+
+    /* IDTR */
+    idt.base = saved_state[SMRAM_FIELD_P6_IDTR_BASE];
+    idt.limit = saved_state[SMRAM_FIELD_P6_IDTR_LIMIT];
+    idt.access = (saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] >> 16) & 0xff;
+    idt.ar_high = (saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] >> 24) & 0xff;
+
+    /* GDTR */
+    gdt.base = saved_state[SMRAM_FIELD_P6_GDTR_BASE];
+    gdt.limit = saved_state[SMRAM_FIELD_P6_GDTR_LIMIT];
+    gdt.access = (saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] >> 16) & 0xff;
+    gdt.ar_high = (saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] >> 24) & 0xff;
+
+    /* ES */
+    cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_P6_ES_SELECTOR];
+    cpu_state.seg_es.base = saved_state[SMRAM_FIELD_P6_ES_BASE];
+    cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_P6_ES_LIMIT];
+    cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_es);
+
+    /* CS */
+    cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_P6_CS_SELECTOR];
+    cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_P6_CS_BASE];
+    cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_P6_CS_LIMIT];
+    cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_cs);
+    cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | ((saved_state[SMRAM_FIELD_P6_CPL] & 0x03) << 5);
+
+    /* DS */
+    cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_P6_DS_SELECTOR];
+    cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_P6_DS_BASE];
+    cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_P6_DS_LIMIT];
+    cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_ds);
+
+    /* SS */
+    cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_P6_SS_SELECTOR];
+    cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_P6_SS_BASE];
+    cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_P6_SS_LIMIT];
+    cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_ss);
+
+    /* FS */
+    cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_P6_FS_SELECTOR];
+    cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_P6_FS_BASE];
+    cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_P6_FS_LIMIT];
+    cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_fs);
+
+    /* GS */
+    cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_P6_GS_SELECTOR];
+    cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_P6_GS_BASE];
+    cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_P6_GS_LIMIT];
+    cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] >> 16) & 0xff;
+    cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] >> 24) & 0xff;
+    smm_seg_load(&cpu_state.seg_gs);
+
+    mem_a20_alt = 0;
+    keyboard_at_set_a20_key(!saved_state[SMRAM_FIELD_P6_A20M]);
+    mem_a20_recalc();
+
+    if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
+	smbase = saved_state[SMRAM_FIELD_P6_SMBASE_OFFSET];
+}
+
+
+static void
+smram_save_state_amd_k(uint32_t *saved_state, int in_hlt)
+{
+    int n = 0;
+
+    saved_state[SMRAM_FIELD_AMD_K_SMM_REVISION_ID] = SMM_REVISION_ID;
+    saved_state[SMRAM_FIELD_AMD_K_SMBASE_OFFSET] = smbase;
+
+    for (n = 0; n < 8; n++)
+	saved_state[SMRAM_FIELD_AMD_K_EAX - n] = cpu_state.regs[n].l;
+
+    if (in_hlt)
+	saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] = 1;
+    else
+	saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] = 0;
+
+    saved_state[SMRAM_FIELD_AMD_K_EIP] = cpu_state.pc;
+
+    saved_state[SMRAM_FIELD_AMD_K_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
+
+    saved_state[SMRAM_FIELD_AMD_K_CR0] = cr0;
+    saved_state[SMRAM_FIELD_AMD_K_CR2] = cr2;
+    saved_state[SMRAM_FIELD_AMD_K_CR3] = cr3;
+    saved_state[SMRAM_FIELD_AMD_K_CR4] = cr4;
+    saved_state[SMRAM_FIELD_AMD_K_DR6] = dr[6];
+    saved_state[SMRAM_FIELD_AMD_K_DR7] = dr[7];
+
+    /* TR */
+    saved_state[SMRAM_FIELD_AMD_K_TR_SELECTOR] = tr.seg;
+    saved_state[SMRAM_FIELD_AMD_K_TR_BASE] = tr.base;
+    saved_state[SMRAM_FIELD_AMD_K_TR_LIMIT] = tr.limit;
+    saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] = (tr.ar_high << 16) | (tr.access << 8);
+
+    /* LDTR */
+    saved_state[SMRAM_FIELD_AMD_K_LDTR_SELECTOR] = ldt.seg;
+    saved_state[SMRAM_FIELD_AMD_K_LDTR_BASE] = ldt.base;
+    saved_state[SMRAM_FIELD_AMD_K_LDTR_LIMIT] = ldt.limit;
+    if (!is_k6)
+	saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] = (ldt.ar_high << 16) | (ldt.access << 8);
+
+    /* IDTR */
+    saved_state[SMRAM_FIELD_AMD_K_IDTR_BASE] = idt.base;
+    saved_state[SMRAM_FIELD_AMD_K_IDTR_LIMIT] = idt.limit;
+
+    /* GDTR */
+    saved_state[SMRAM_FIELD_AMD_K_GDTR_BASE] = gdt.base;
+    saved_state[SMRAM_FIELD_AMD_K_GDTR_LIMIT] = gdt.limit;
+
+    /* ES */
+    saved_state[SMRAM_FIELD_AMD_K_ES_SELECTOR] = cpu_state.seg_es.seg;
+    saved_state[SMRAM_FIELD_AMD_K_ES_BASE] = cpu_state.seg_es.base;
+    saved_state[SMRAM_FIELD_AMD_K_ES_LIMIT] = cpu_state.seg_es.limit;
+    saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] = (cpu_state.seg_es.ar_high << 16) | (cpu_state.seg_es.access << 8);
+
+    /* CS */
+    saved_state[SMRAM_FIELD_AMD_K_CS_SELECTOR] = cpu_state.seg_cs.seg;
+    saved_state[SMRAM_FIELD_AMD_K_CS_BASE] = cpu_state.seg_cs.base;
+    saved_state[SMRAM_FIELD_AMD_K_CS_LIMIT] = cpu_state.seg_cs.limit;
+    saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] = (cpu_state.seg_cs.ar_high << 16) | (cpu_state.seg_cs.access << 8);
+
+    /* DS */
+    saved_state[SMRAM_FIELD_AMD_K_DS_SELECTOR] = cpu_state.seg_ds.seg;
+    saved_state[SMRAM_FIELD_AMD_K_DS_BASE] = cpu_state.seg_ds.base;
+    saved_state[SMRAM_FIELD_AMD_K_DS_LIMIT] = cpu_state.seg_ds.limit;
+    saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] = (cpu_state.seg_ds.ar_high << 16) | (cpu_state.seg_ds.access << 8);
+
+    /* SS */
+    saved_state[SMRAM_FIELD_AMD_K_SS_SELECTOR] = cpu_state.seg_ss.seg;
+    saved_state[SMRAM_FIELD_AMD_K_SS_BASE] = cpu_state.seg_ss.base;
+    saved_state[SMRAM_FIELD_AMD_K_SS_LIMIT] = cpu_state.seg_ss.limit;
+    saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] = (cpu_state.seg_ss.ar_high << 16) | (cpu_state.seg_ss.access << 8);
+
+    /* FS */
+    saved_state[SMRAM_FIELD_AMD_K_FS_SELECTOR] = cpu_state.seg_fs.seg;
+    saved_state[SMRAM_FIELD_AMD_K_FS_BASE] = cpu_state.seg_fs.base;
+    saved_state[SMRAM_FIELD_AMD_K_FS_LIMIT] = cpu_state.seg_fs.limit;
+    saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] = (cpu_state.seg_fs.ar_high << 16) | (cpu_state.seg_fs.access << 8);
+
+    /* GS */
+    saved_state[SMRAM_FIELD_AMD_K_GS_SELECTOR] = cpu_state.seg_gs.seg;
+    saved_state[SMRAM_FIELD_AMD_K_GS_BASE] = cpu_state.seg_gs.base;
+    saved_state[SMRAM_FIELD_AMD_K_GS_LIMIT] = cpu_state.seg_gs.limit;
+    saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] = (cpu_state.seg_gs.ar_high << 16) | (cpu_state.seg_gs.access << 8);
+}
+
+
+static void
+smram_restore_state_amd_k(uint32_t *saved_state)
+{
+    int n = 0;
+
+    for (n = 0; n < 8; n++)
+	cpu_state.regs[n].l = saved_state[SMRAM_FIELD_AMD_K_EAX - n];
+
+    if (saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] & 0xffff)
+	cpu_state.pc = saved_state[SMRAM_FIELD_AMD_K_EIP] - 1;
+    else
+	cpu_state.pc = saved_state[SMRAM_FIELD_AMD_K_EIP];
+
+    cpu_state.eflags = saved_state[SMRAM_FIELD_AMD_K_EFLAGS] >> 16;
+    cpu_state.flags = saved_state[SMRAM_FIELD_AMD_K_EFLAGS] & 0xffff;
+
+    cr0 = saved_state[SMRAM_FIELD_AMD_K_CR0];
+    cr2 = saved_state[SMRAM_FIELD_AMD_K_CR2];
+    cr3 = saved_state[SMRAM_FIELD_AMD_K_CR3];
+    cr4 = saved_state[SMRAM_FIELD_AMD_K_CR4];
+    dr[6] = saved_state[SMRAM_FIELD_AMD_K_DR6];
+    dr[7] = saved_state[SMRAM_FIELD_AMD_K_DR7];
+
+    /* TR */
+    tr.seg = saved_state[SMRAM_FIELD_AMD_K_TR_SELECTOR];
+    tr.base = saved_state[SMRAM_FIELD_AMD_K_TR_BASE];
+    tr.limit = saved_state[SMRAM_FIELD_AMD_K_TR_LIMIT];
+    tr.access = (saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] >> 8) & 0xff;
+    tr.ar_high = (saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&tr);
+
+    /* LDTR */
+    ldt.seg = saved_state[SMRAM_FIELD_AMD_K_LDTR_SELECTOR];
+    ldt.base = saved_state[SMRAM_FIELD_AMD_K_LDTR_BASE];
+    ldt.limit = saved_state[SMRAM_FIELD_AMD_K_LDTR_LIMIT];
+    if (!is_k6) {
+	ldt.access = (saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] >> 8) & 0xff;
+	ldt.ar_high = (saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] >> 16) & 0xff;
+    }
+    smm_seg_load(&ldt);
+
+    /* IDTR */
+    idt.base = saved_state[SMRAM_FIELD_AMD_K_IDTR_BASE];
+    idt.limit = saved_state[SMRAM_FIELD_AMD_K_IDTR_LIMIT];
+
+    /* GDTR */
+    gdt.base = saved_state[SMRAM_FIELD_AMD_K_GDTR_BASE];
+    gdt.limit = saved_state[SMRAM_FIELD_AMD_K_GDTR_LIMIT];
+
+    /* ES */
+    cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_AMD_K_ES_SELECTOR];
+    cpu_state.seg_es.base = saved_state[SMRAM_FIELD_AMD_K_ES_BASE];
+    cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_AMD_K_ES_LIMIT];
+    cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_es);
+
+    /* CS */
+    cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_AMD_K_CS_SELECTOR];
+    cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_AMD_K_CS_BASE];
+    cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_AMD_K_CS_LIMIT];
+    cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_cs);
+
+    /* DS */
+    cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_AMD_K_DS_SELECTOR];
+    cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_AMD_K_DS_BASE];
+    cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_AMD_K_DS_LIMIT];
+    cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_ds);
+
+    /* SS */
+    cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_AMD_K_SS_SELECTOR];
+    cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_AMD_K_SS_BASE];
+    cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_AMD_K_SS_LIMIT];
+    cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] >> 8) & 0xff;
+    /* The actual CPL (DPL of CS) is overwritten with DPL of SS. */
+    cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | (cpu_state.seg_ss.access & 0x60);
+    cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_ss);
+
+    /* FS */
+    cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_AMD_K_FS_SELECTOR];
+    cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_AMD_K_FS_BASE];
+    cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_AMD_K_FS_LIMIT];
+    cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_fs);
+
+    /* GS */
+    cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_AMD_K_GS_SELECTOR];
+    cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_AMD_K_GS_BASE];
+    cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_AMD_K_GS_LIMIT];
+    cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] >> 8) & 0xff;
+    cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] >> 16) & 0xff;
+    smm_seg_load(&cpu_state.seg_gs);
+
+    if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
+	smbase = saved_state[SMRAM_FIELD_AMD_K_SMBASE_OFFSET];
+}
+
+
+void
+enter_smm(int in_hlt)
+{
+    uint32_t saved_state[SMM_SAVE_STATE_MAP_SIZE], n;
+    uint32_t smram_state = smbase + 0x10000;
+
+    /* If it's a CPU on which SMM is not supporter, do nothing. */
+    if (!is_pentium && !is_k5 && !is_k6 && !is_p6)
+	return;
+
+    x386_common_log("enter_smm(): smbase = %08X\n", smbase);
+    x386_common_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,
+		    cpu_state.seg_cs.limit_high, cpu_state.seg_cs.access, cpu_state.seg_cs.ar_high);
+    x386_common_log("DS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_ds.seg, cpu_state.seg_ds.base, cpu_state.seg_ds.limit, cpu_state.seg_ds.limit_low,
+		    cpu_state.seg_ds.limit_high, cpu_state.seg_ds.access, cpu_state.seg_ds.ar_high);
+    x386_common_log("ES : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_es.seg, cpu_state.seg_es.base, cpu_state.seg_es.limit, cpu_state.seg_es.limit_low,
+		    cpu_state.seg_es.limit_high, cpu_state.seg_es.access, cpu_state.seg_es.ar_high);
+    x386_common_log("FS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_fs.seg, cpu_state.seg_fs.base, cpu_state.seg_fs.limit, cpu_state.seg_fs.limit_low,
+		    cpu_state.seg_fs.limit_high, cpu_state.seg_fs.access, cpu_state.seg_fs.ar_high);
+    x386_common_log("GS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_gs.seg, cpu_state.seg_gs.base, cpu_state.seg_gs.limit, cpu_state.seg_gs.limit_low,
+		    cpu_state.seg_gs.limit_high, cpu_state.seg_gs.access, cpu_state.seg_gs.ar_high);
+    x386_common_log("SS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_ss.seg, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low,
+		    cpu_state.seg_ss.limit_high, cpu_state.seg_ss.access, cpu_state.seg_ss.ar_high);
+    x386_common_log("TR : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    tr.seg, tr.base, tr.limit, tr.limit_low, tr.limit_high, tr.access, tr.ar_high);
+    x386_common_log("LDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    ldt.seg, ldt.base, ldt.limit, ldt.limit_low, ldt.limit_high, ldt.access, ldt.ar_high);
+    x386_common_log("GDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    gdt.seg, gdt.base, gdt.limit, gdt.limit_low, gdt.limit_high, gdt.access, gdt.ar_high);
+    x386_common_log("IDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    idt.seg, idt.base, idt.limit, idt.limit_low, idt.limit_high, idt.access, idt.ar_high);
+    x386_common_log("CR0 = %08X, CR3 = %08X, CR4 = %08X, DR6 = %08X, DR7 = %08X\n", cr0, cr3, cr4, dr[6], dr[7]);
+    x386_common_log("EIP = %08X, EFLAGS = %04X%04X\n", cpu_state.pc, cpu_state.eflags, cpu_state.flags);
+    x386_common_log("EAX = %08X, EBX = %08X, ECX = %08X, EDX = %08X, ESI = %08X, EDI = %08X, ESP = %08X, EBP = %08X\n",
+		    EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP);
+
+    in_smm = 1;
+    mem_mapping_recalc(0x00030000, 0x00020000);
+    mem_mapping_recalc(0x000a0000, 0x00060000);
+
+    if (!cpu_16bitbus)
+	mem_mapping_recalc(0x100a0000, 0x00060000);
+
+    if (mem_size >= 1024)
+	mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20));
+
+    flushmmucache();
+
+    memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
+
+    if (is_pentium)			/* Intel P5 (Pentium) */
+	smram_save_state_p5(saved_state, in_hlt);
+    else if (is_k5 || is_k6)	/* AMD K5 and K6 */
+	smram_save_state_amd_k(saved_state, in_hlt);
+    else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
+	smram_save_state_p6(saved_state, in_hlt);
+
+    for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
+	smram_state -= 4;
+	mem_writel_phys(smram_state, saved_state[n]);
+    }
+
+    cr0 &= ~0x8000000d;
+    cpu_state.flags = 2;
+    cpu_state.eflags = 0;
+
+    cr4 = 0;
+    dr[7] = 0x400;
+    cpu_state.pc = 0x8000;
+
+    cpu_state.seg_ds.seg = 0x00000000;
+    cpu_state.seg_ds.base = 0x00000000;
+    cpu_state.seg_ds.limit = 0xffffffff;
+    cpu_state.seg_ds.access = 0x93;
+    cpu_state.seg_ds.ar_high = 0x80;
+
+    memcpy(&cpu_state.seg_es, &cpu_state.seg_ds, sizeof(x86seg));
+    memcpy(&cpu_state.seg_ss, &cpu_state.seg_ds, sizeof(x86seg));
+    memcpy(&cpu_state.seg_fs, &cpu_state.seg_ds, sizeof(x86seg));
+    memcpy(&cpu_state.seg_gs, &cpu_state.seg_ds, sizeof(x86seg));
+
+    if (is_p6)
+	cpu_state.seg_cs.seg = (smbase >> 4);
+    else
+	cpu_state.seg_cs.seg = 0x3000;
+
+    /* On Pentium, CS selector in SMM is always 3000, regardless of SMBASE. */
+    cpu_state.seg_cs.base = smbase;
+    cpu_state.seg_cs.limit = 0xffffffff;
+    cpu_state.seg_cs.access = 0x93;
+    cpu_state.seg_cs.ar_high = 0x80;
+    cpu_state.seg_cs.checked = 1;
+
+    smm_seg_load(&cpu_state.seg_es);
+    smm_seg_load(&cpu_state.seg_cs);
+    smm_seg_load(&cpu_state.seg_ds);
+    smm_seg_load(&cpu_state.seg_ss);
+    smm_seg_load(&cpu_state.seg_fs);
+    smm_seg_load(&cpu_state.seg_gs);
+
+    cpu_state.op32 = use32;
+
+    nmi_mask = 0;
+
+    if (smi_latched) {
+	in_smm = 2;
+	smi_latched = 0;
+    } else
+	in_smm = 1;
+
+    smm_in_hlt = in_hlt;
+
+    CPU_BLOCK_END();
+}
+
+
+void
+enter_smm_check(int in_hlt)
+{
+    if ((in_smm == 0) && smi_line) {
 #ifdef ENABLE_386_COMMON_LOG
-                                x386_log("Triple fault in real mode - reset\n");
+	x386_common_log("SMI while not in SMM\n");
 #endif
-                        }
-                        else
-                                x86_int(8);
-                }
-                else
-                {
-                        if (stack32)
-                        {
-                                writememw(ss,ESP-2,cpu_state.flags);
-                                writememw(ss,ESP-4,CS);
-                                writememw(ss,ESP-6,cpu_state.pc);
-                                ESP-=6;
-                        }
-                        else
-                        {
-                                writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
-                                writememw(ss,((SP-4)&0xFFFF),CS);
-                                writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
-                                SP-=6;
-                        }
+	enter_smm(in_hlt);
+    } else if ((in_smm == 1) && smi_line) {
+	/* Mark this so that we don't latch more than one SMI. */
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SMI while in unlatched SMM\n");
+#endif
+	smi_latched = 1;
+    } else if ((in_smm == 2) && smi_line) {
+	/* Mark this so that we don't latch more than one SMI. */
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SMI while in latched SMM\n");
+#endif
+    }
 
-                        cpu_state.flags &= ~I_FLAG;
-                        cpu_state.flags &= ~T_FLAG;
+    if (smi_line)
+	smi_line = 0;
+}
+
+
+void
+leave_smm(void)
+{
+    uint32_t saved_state[SMM_SAVE_STATE_MAP_SIZE], n;
+    uint32_t smram_state = smbase + 0x10000;
+
+    /* If it's a CPU on which SMM is not supported (or not implemented in 86Box), do nothing. */
+    if (!is_pentium && !is_k5 && !is_k6 && !is_p6)
+	return;
+
+    memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
+
+    for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
+	smram_state -= 4;
+	saved_state[n] = mem_readl_phys(smram_state);
+	x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
+    }
+
+    x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
+    if (is_pentium)			/* Intel P5 (Pentium) */
+	smram_restore_state_p5(saved_state);
+    else if (is_k5 || is_k6)	/* AMD K5 and K6 */
+	smram_restore_state_amd_k(saved_state);
+    else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
+	smram_restore_state_p6(saved_state);
+
+    in_smm = 0;
+    mem_mapping_recalc(0x00030000, 0x00020000);
+    mem_mapping_recalc(0x000a0000, 0x00060000);
+    if (!cpu_16bitbus)
+	mem_mapping_recalc(0x100a0000, 0x00060000);
+    if (mem_size >= 1024)
+	mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20));
+    flushmmucache();
+
+    cpu_state.op32 = use32;
+
+    nmi_mask = 1;
+
+    CPU_BLOCK_END();
+
+    x386_common_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,
+		    cpu_state.seg_cs.limit_high, cpu_state.seg_cs.access, cpu_state.seg_cs.ar_high);
+    x386_common_log("DS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_ds.seg, cpu_state.seg_ds.base, cpu_state.seg_ds.limit, cpu_state.seg_ds.limit_low,
+		    cpu_state.seg_ds.limit_high, cpu_state.seg_ds.access, cpu_state.seg_ds.ar_high);
+    x386_common_log("ES : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_es.seg, cpu_state.seg_es.base, cpu_state.seg_es.limit, cpu_state.seg_es.limit_low,
+		    cpu_state.seg_es.limit_high, cpu_state.seg_es.access, cpu_state.seg_es.ar_high);
+    x386_common_log("FS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_fs.seg, cpu_state.seg_fs.base, cpu_state.seg_fs.limit, cpu_state.seg_fs.limit_low,
+		    cpu_state.seg_fs.limit_high, cpu_state.seg_fs.access, cpu_state.seg_fs.ar_high);
+    x386_common_log("GS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_gs.seg, cpu_state.seg_gs.base, cpu_state.seg_gs.limit, cpu_state.seg_gs.limit_low,
+		    cpu_state.seg_gs.limit_high, cpu_state.seg_gs.access, cpu_state.seg_gs.ar_high);
+    x386_common_log("SS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    cpu_state.seg_ss.seg, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low,
+		    cpu_state.seg_ss.limit_high, cpu_state.seg_ss.access, cpu_state.seg_ss.ar_high);
+    x386_common_log("TR : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    tr.seg, tr.base, tr.limit, tr.limit_low, tr.limit_high, tr.access, tr.ar_high);
+    x386_common_log("LDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    ldt.seg, ldt.base, ldt.limit, ldt.limit_low, ldt.limit_high, ldt.access, ldt.ar_high);
+    x386_common_log("GDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    gdt.seg, gdt.base, gdt.limit, gdt.limit_low, gdt.limit_high, gdt.access, gdt.ar_high);
+    x386_common_log("IDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
+		    idt.seg, idt.base, idt.limit, idt.limit_low, idt.limit_high, idt.access, idt.ar_high);
+    x386_common_log("CR0 = %08X, CR3 = %08X, CR4 = %08X, DR6 = %08X, DR7 = %08X\n", cr0, cr3, cr4, dr[6], dr[7]);
+    x386_common_log("EIP = %08X, EFLAGS = %04X%04X\n", cpu_state.pc, cpu_state.eflags, cpu_state.flags);
+    x386_common_log("EAX = %08X, EBX = %08X, ECX = %08X, EDX = %08X, ESI = %08X, EDI = %08X, ESP = %08X, EBP = %08X\n",
+		    EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP);
+    x386_common_log("leave_smm()\n");
+}
+
+
+void
+x86_int(int num)
+{
+    uint32_t addr;
+
+    flags_rebuild();
+    cpu_state.pc=cpu_state.oldpc;
+
+    if (msw&1)
+	pmodeint(num,0);
+    else {
+	addr = (num << 2) + idt.base;
+
+	if ((num << 2) + 3 > idt.limit) {
+		if (idt.limit < 35) {
+			cpu_state.abrt = 0;
+			softresetx86();
+			cpu_set_edx();
+#ifdef ENABLE_386_COMMON_LOG
+			x386_common_log("Triple fault in real mode - reset\n");
+#endif
+		} else
+			x86_int(8);
+	} else {
+		if (stack32) {
+			writememw(ss, ESP - 2, cpu_state.flags);
+			writememw(ss, ESP - 4, CS);
+			writememw(ss, ESP - 6, cpu_state.pc);
+			ESP -= 6;
+		} else {
+			writememw(ss, ((SP - 2) & 0xFFFF), cpu_state.flags);
+			writememw(ss, ((SP - 4) & 0xFFFF), CS);
+			writememw(ss, ((SP - 6) & 0xFFFF), cpu_state.pc);
+			SP -= 6;
+		}
+
+		cpu_state.flags &= ~I_FLAG;
+		cpu_state.flags &= ~T_FLAG;
 #ifndef USE_NEW_DYNAREC
-			oxpc=cpu_state.pc;
+		oxpc = cpu_state.pc;
 #endif
-                        cpu_state.pc=readmemw(0,addr);
-                        loadcs(readmemw(0,addr+2));
-                }
-        }
-        cycles-=70;
-        CPU_BLOCK_END();
+		cpu_state.pc = readmemw(0, addr);
+		loadcs(readmemw(0, addr + 2));
+	}
+    }
+
+    cycles -= 70;
+    CPU_BLOCK_END();
 }
 
-void x86_int_sw(int num)
+
+void
+x86_int_sw(int num)
 {
-        uint32_t addr;
-        flags_rebuild();
-        cycles -= timing_int;
-        if (msw&1)
-        {
-                pmodeint(num,1);
-        }
-        else
-        {
-                addr = (num << 2) + idt.base;
+    uint32_t addr;
 
-                if ((num << 2) + 3 > idt.limit)
-                {
-                        x86_int(13);
-                }
-                else
-                {
-                        if (stack32)
-                        {
-                                writememw(ss,ESP-2,cpu_state.flags);
-                                writememw(ss,ESP-4,CS);
-                                writememw(ss,ESP-6,cpu_state.pc);
-                                ESP-=6;
-                        }
-                        else
-                        {
-                                writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
-                                writememw(ss,((SP-4)&0xFFFF),CS);
-                                writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
-                                SP-=6;
-                        }
+    flags_rebuild();
+    cycles -= timing_int;
 
-                        cpu_state.flags &= ~I_FLAG;
-                        cpu_state.flags &= ~T_FLAG;
+    if (msw&1)
+	pmodeint(num,1);
+    else {
+	addr = (num << 2) + idt.base;
+
+	if ((num << 2) + 3 > idt.limit)
+		x86_int(0x0d);
+	else {
+		if (stack32) {
+			writememw(ss, ESP - 2, cpu_state.flags);
+			writememw(ss, ESP - 4, CS);
+			writememw(ss, ESP - 6, cpu_state.pc);
+			ESP -= 6;
+		} else {
+			writememw(ss, ((SP - 2) & 0xFFFF), cpu_state.flags);
+			writememw(ss, ((SP - 4) & 0xFFFF), CS);
+			writememw(ss, ((SP - 6) & 0xFFFF), cpu_state.pc);
+			SP -= 6;
+		}
+
+		cpu_state.flags &= ~I_FLAG;
+		cpu_state.flags &= ~T_FLAG;
 #ifndef USE_NEW_DYNAREC
-			oxpc=cpu_state.pc;
+		oxpc = cpu_state.pc;
 #endif
-                        cpu_state.pc=readmemw(0,addr);
-                        loadcs(readmemw(0,addr+2));
-                        cycles -= timing_int_rm;
-                }
-        }
-        trap = 0;
-        CPU_BLOCK_END();
+		cpu_state.pc = readmemw(0, addr);
+		loadcs(readmemw(0, addr + 2));
+		cycles -= timing_int_rm;
+	}
+    }
+
+    trap = 0;
+    CPU_BLOCK_END();
 }
 
-int x86_int_sw_rm(int num)
+
+int
+x86_int_sw_rm(int num)
 {
-        uint32_t addr;
-        uint16_t new_pc, new_cs;
+    uint32_t addr;
+    uint16_t new_pc, new_cs;
 
-        flags_rebuild();
-        cycles -= timing_int;
+    flags_rebuild();
+    cycles -= timing_int;
 
-        addr = num << 2;
-        new_pc = readmemw(0, addr);
-        new_cs = readmemw(0, addr + 2);
+    addr = num << 2;
+    new_pc = readmemw(0, addr);
+    new_cs = readmemw(0, addr + 2);
 
-        if (cpu_state.abrt) return 1;
+    if (cpu_state.abrt)
+	return 1;
 
-        writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
-	if (cpu_state.abrt)
-		return 1;
-        writememw(ss,((SP-4)&0xFFFF),CS);
-        writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
-	if (cpu_state.abrt)
-		return 1;
-        SP-=6;
+    writememw(ss, ((SP - 2) & 0xFFFF), cpu_state.flags);
 
-        cpu_state.eflags &= ~VIF_FLAG;
-        cpu_state.flags &= ~T_FLAG;
-        cpu_state.pc = new_pc;
-        loadcs(new_cs);
+    if (cpu_state.abrt)
+	return 1;
+
+    writememw(ss, ((SP - 4) & 0xFFFF), CS);
+    writememw(ss, ((SP - 6) & 0xFFFF), cpu_state.pc);
+
+    if (cpu_state.abrt)
+	return 1;
+
+    SP -= 6;
+
+    cpu_state.eflags &= ~VIF_FLAG;
+    cpu_state.flags &= ~T_FLAG;
+    cpu_state.pc = new_pc;
+    loadcs(new_cs);
 #ifndef USE_NEW_DYNAREC
-	oxpc=cpu_state.pc;
+    oxpc = cpu_state.pc;
 #endif
 
-        cycles -= timing_int_rm;
-        trap = 0;
-        CPU_BLOCK_END();
+    cycles -= timing_int_rm;
+    trap = 0;
+    CPU_BLOCK_END();
 
-        return 0;
+    return 0;
 }
 
-void x86illegal()
+
+void
+x86illegal()
 {
-        x86_int(6);
+    x86_int(6);
 }
 
-int checkio(int port)
+
+int
+checkio(int port)
 {
-        uint16_t t;
-        uint8_t d;
-        cpl_override = 1;
-        t = readmemw(tr.base, 0x66);
-        cpl_override = 0;
-        if (cpu_state.abrt) return 0;
-        if ((t+(port>>3))>tr.limit) return 1;
-        cpl_override = 1;
+    uint16_t t;
+    uint8_t d;
+
+    cpl_override = 1;
+    t = readmemw(tr.base, 0x66);
+    cpl_override = 0;
+
+    if (cpu_state.abrt)
+	return 0;
+
+    if ((t + (port >> 3)) > tr.limit)
+	return 1;
+
+    cpl_override = 1;
 #ifdef USE_NEW_DYNAREC
-        d = readmembl(tr.base + t + (port >> 3));
+    d = readmembl(tr.base + t + (port >> 3));
 #else
-        d = readmemb386l(0, tr.base + t + (port >> 3));
+    d = readmemb386l(0, tr.base + t + (port >> 3));
 #endif
-        cpl_override = 0;
-        return d&(1<<(port&7));
+    cpl_override = 0;
+    return d & (1 << (port & 7));
 }
 
+
 #define divexcp() { \
-                x386_common_log("Divide exception at %04X(%06X):%04X\n",CS,cs,cpu_state.pc); \
-                x86_int(0); \
+	x386_common_log("Divide exception at %04X(%06X):%04X\n",CS,cs,cpu_state.pc); \
+	x86_int(0); \
 }
 
-int divl(uint32_t val)
+
+int
+divl(uint32_t val)
 {
-         uint64_t num, quo;
-         uint32_t rem, quo32;
- 
-        if (val==0) 
-        {
-                divexcp();
-                return 1;
-        }
+    uint64_t num, quo;
+    uint32_t rem, quo32;
 
-         num=(((uint64_t)EDX)<<32)|EAX;
-         quo=num/val;
-         rem=num%val;
-         quo32=(uint32_t)(quo&0xFFFFFFFF);
+    if (val == 0) {
+	divexcp();
+	return 1;
+    }
 
-        if (quo!=(uint64_t)quo32) 
-        {
-                divexcp();
-                return 1;
-        }
-        EDX=rem;
-        EAX=quo32;
-        return 0;
+    num = (((uint64_t) EDX) << 32) | EAX;
+    quo = num / val;
+    rem = num % val;
+    quo32=(uint32_t)(quo&0xFFFFFFFF);
+
+    if (quo != (uint64_t) quo32) {
+	divexcp();
+	return 1;
+    }
+
+    EDX = rem;
+    EAX = quo32;
+
+    return 0;
 }
-int idivl(int32_t val)
+
+
+int
+idivl(int32_t val)
 {
-         int64_t num, quo;
-         int32_t rem, quo32;
- 
-        if (val==0) 
-        {       
-                divexcp();
-                return 1;
-        }
+    int64_t num, quo;
+    int32_t rem, quo32;
 
-         num=(((uint64_t)EDX)<<32)|EAX;
-         quo=num/val;
-         rem=num%val;
-         quo32=(int32_t)(quo&0xFFFFFFFF);
+    if (val == 0)  {       
+	divexcp();
+	return 1;
+    }
 
-        if (quo!=(int64_t)quo32) 
-        {
-                divexcp();
-                return 1;
-        }
-        EDX=rem;
-        EAX=quo32;
-        return 0;
+    num = (((uint64_t) EDX) << 32) | EAX;
+    quo = num / val;
+    rem = num % val;
+    quo32 = (int32_t) (quo & 0xFFFFFFFF);
+
+    if (quo != (int64_t) quo32) {
+	divexcp();
+	return 1;
+    }
+
+    EDX = rem;
+    EAX = quo32;
+
+    return 0;
 }
 
 
-void cpu_386_flags_extract()
+void
+cpu_386_flags_extract()
 {
-        flags_extract();
+    flags_extract();
 }
-void cpu_386_flags_rebuild()
+
+
+void
+cpu_386_flags_rebuild()
 {
-        flags_rebuild();
+    flags_rebuild();
+}
+
+
+/*	0 = Limit 0-15
+	1 = Base 0-15
+	2 = Base 16-23 (bits 0-7), Access rights
+		8-11	Type
+		12	S
+		13, 14	DPL
+		15	P
+	3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
+		4	A
+		6	DB
+		7	G	*/
+static __inline void
+read_seg_data(uint16_t *seg_data, uint16_t seg, x86seg *s)
+{
+    uint32_t addr;
+
+    if (seg & 0x0004)
+	addr = (seg & 0xfff8) + ldt.base;
+    else
+	addr = (seg & 0xfff8) + gdt.base;
+
+    cpl_override = 1;
+    x386_common_log("read_seg_data(abrt = %02X): Begin (descriptor at %08X)\n", cpu_state.abrt, addr);
+    seg_data[0]=readmemw(0, addr);
+    x386_common_log("read_seg_data(abrt = %02X): seg_data[0] = %04X\n", cpu_state.abrt, seg_data[0]);
+    seg_data[1]=readmemw(0, addr + 2);
+    x386_common_log("read_seg_data(abrt = %02X): seg_data[1] = %04X\n", cpu_state.abrt, seg_data[1]);
+    seg_data[2]=readmemw(0, addr + 4);
+    x386_common_log("read_seg_data(abrt = %02X): seg_data[2] = %04X\n", cpu_state.abrt, seg_data[2]);
+    seg_data[3]=readmemw(0, addr + 6);
+    x386_common_log("read_seg_data(abrt = %02X): seg_data[3] = %04X\n", cpu_state.abrt, seg_data[3]);
+    if (s != &cpu_state.seg_cs) {
+	writememw(0, addr + 4, seg_data[2] | 0x100); /*Set accessed bit*/
+	x386_common_log("read_seg_data(abrt = %02X): accessed bit set\n", cpu_state.abrt);
+    }
+    cpl_override = 0;
+}
+
+
+int
+sysenter(uint32_t fetchdat)
+{
+    uint16_t seg_data[4];
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSENTER called\n");
+#endif
+
+    if (!(msw & 1)) {
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SYSENTER: CPU not in protected mode");
+#endif
+	x86gpf("SYSENTER: CPU not in protected mode", 0);
+	return cpu_state.abrt;
+    }
+
+    if (!(cs_msr & 0xFFF8)) {
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SYSENTER: CS MSR is zero");
+#endif
+	x86gpf("SYSENTER: CS MSR is zero", 0);
+	return cpu_state.abrt;
+    }
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSENTER started:\n");
+    x386_common_log("    CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
+    x386_common_log("    SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
+    x386_common_log("    Misc.  : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
+    x386_common_log("             EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
+#endif
+
+    /* Set VM, RF, and IF to 0. */
+    flags_rebuild();
+    cpu_state.eflags &= ~(RF_FLAG | VM_FLAG);
+    cpu_state.flags &= ~I_FLAG;
+    cpu_cur_status &= ~CPU_STATUS_V86;
+
+#ifndef USE_NEW_DYNAREC
+    oldcs = CS;
+#endif
+    cpu_state.oldpc = cpu_state.pc;
+#if 0
+    old_pc = cpu_state.pc;
+#endif
+    ESP = esp_msr;
+    cpu_state.pc = eip_msr;
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSENTER: Loading CS...\n");
+#endif
+    CS = (cs_msr & 0xFFFC);
+    cpu_state.seg_cs.access &= 0x9f;
+    read_seg_data(seg_data, CS, &cpu_state.seg_cs);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_cs, seg_data);
+    cpu_state.seg_cs.checked = 0;
+    set_use32(0x40);
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSENTER: Loading SS...\n");
+#endif
+    SS = ((cs_msr + 8) & 0xFFFC);
+    read_seg_data(seg_data, SS, &cpu_state.seg_ss);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_ss, seg_data);
+    cpu_state.seg_ss.checked = 0;
+    codegen_flat_ss = 0;
+    if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
+    cpu_state.seg_ss.limit_high == 0xffffffff)
+	cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
+    else
+	cpu_cur_status |= CPU_STATUS_NOTFLATSS;
+    set_stack32(1);
+
+    oldcpl = CPL;
+    flags_extract();
+    trap = 0;
+    in_sys = 1;
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSENTER completed:\n");
+    x386_common_log("    CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
+    x386_common_log("    SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
+    x386_common_log("    Misc.  : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
+    x386_common_log("             EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
+#endif
+
+    return 1;
+}
+
+
+int
+sysexit(uint32_t fetchdat)
+{
+    uint16_t seg_data[4];
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSEXIT called\n");
+#endif
+
+    if (!(cs_msr & 0xFFF8)) {
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SYSEXIT: CS MSR is zero");
+#endif
+	x86gpf("SYSEXIT: CS MSR is zero", 0);
+	return cpu_state.abrt;
+    }
+
+    if (!(msw & 1)) {
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SYSEXIT: CPU not in protected mode");
+#endif
+	x86gpf("SYSEXIT: CPU not in protected mode", 0);
+	return cpu_state.abrt;
+    }
+
+    if (CPL) {
+#ifdef ENABLE_386_COMMON_LOG
+	x386_common_log("SYSEXIT: CPL not 0");
+#endif
+	x86gpf("SYSEXIT: CPL not 0", 0);
+	return cpu_state.abrt;
+    }
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSEXIT start:\n");
+    x386_common_log("    CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
+    x386_common_log("    SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
+    x386_common_log("    Misc.  : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
+    x386_common_log("             EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
+#endif
+
+#ifndef USE_NEW_DYNAREC
+    oldcs = CS;
+#endif
+    cpu_state.oldpc = cpu_state.pc;
+    ESP = ECX;
+    cpu_state.pc = EDX;
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSEXIT: Loading CS...\n");
+#endif
+    CS = (((cs_msr + 16) & 0xFFFC) | 3);
+    read_seg_data(seg_data, CS, &cpu_state.seg_cs);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_cs, seg_data);
+    cpu_state.seg_cs.checked = 0;
+    set_use32(0x40);
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSEXIT: Loading SS...\n");
+#endif
+    SS = (((cs_msr + 24) & 0xFFFC) | 3);
+    read_seg_data(seg_data, SS, &cpu_state.seg_ss);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_ss, seg_data);
+    cpu_state.seg_ss.checked = 0;
+    codegen_flat_ss = 0;
+    if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
+	cpu_state.seg_ss.limit_high == 0xffffffff)
+	cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
+    else
+	cpu_cur_status |= CPU_STATUS_NOTFLATSS;
+    set_stack32(1);
+
+    flushmmucache_cr3();
+    oldcpl = CPL;
+    trap = 0;
+    in_sys = 0;
+
+#ifdef ENABLE_386_COMMON_LOG
+    x386_common_log("SYSEXIT completed:\n");
+    x386_common_log("    CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
+    x386_common_log("    SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
+    x386_common_log("    Misc.  : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
+    x386_common_log("             EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
+#endif
+
+    return 1;
+}
+
+
+int
+syscall(uint32_t fetchdat)
+{
+    uint16_t seg_data[4];
+
+// #ifdef ENABLE_386_COMMON_LOG
+    pclog("SYSCALL called\n");
+// #endif
+
+    if (!(cr0 & 1)) {
+	x86gpf("SYSCALL: CPU not in protected mode", 0);
+	return cpu_state.abrt;
+    }
+
+    if (!AMD_SYSCALL_SB) {
+	x86gpf("SYSCALL: AMD SYSCALL SB MSR is zero", 0);
+	return cpu_state.abrt;
+    }
+
+    /* Let's do this by the AMD spec. */
+    ECX = cpu_state.pc;
+
+    flags_rebuild();
+    cpu_state.eflags &= ~0x0002;
+    cpu_state.flags &= ~0x0200;
+    cpu_cur_status &= ~CPU_STATUS_V86;
+
+    /* CS */
+    CS = AMD_SYSCALL_SB & 0xFFFC;
+    read_seg_data(seg_data, CS, &cpu_state.seg_cs);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_cs, seg_data);
+    cpu_state.seg_cs.checked = 0;
+    set_use32(0x40);
+
+    /* SS */
+    SS = (AMD_SYSCALL_SB + 8) & 0xFFFC;
+    read_seg_data(seg_data, SS, &cpu_state.seg_ss);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_ss, seg_data);
+    cpu_state.seg_ss.checked = 0;
+    codegen_flat_ss = 0;
+    if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
+	cpu_state.seg_ss.limit_high == 0xffffffff)
+	cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
+    else
+	cpu_cur_status |= CPU_STATUS_NOTFLATSS;
+    set_stack32(1);
+
+    oldcpl = CPL;
+    flags_extract();
+    trap = 0;
+    in_sys = 1;
+
+    return 1;
+}
+
+
+int
+sysret(uint32_t fetchdat)
+{
+    uint16_t seg_data[4];
+
+// #ifdef ENABLE_386_COMMON_LOG
+    pclog("SYSRET called\n");
+// #endif
+
+    if (!AMD_SYSRET_SB) {
+	x86gpf("SYSRET: CS MSR is zero", 0);
+	return cpu_state.abrt;
+    }
+
+    if (!(cr0 & 1)) {
+	x86gpf("SYSRET: CPU not in protected mode", 0);
+	return cpu_state.abrt;
+    }
+
+    cpu_state.pc = ECX;
+
+    cpu_state.eflags |= (1 << 1);
+
+    /* CS */
+    CS = (AMD_SYSRET_SB & 0xFFFC) | 3;
+    cpu_state.seg_cs.seg = AMD_SYSRET_SB & ~7;
+    read_seg_data(seg_data, CS, &cpu_state.seg_cs);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_cs, seg_data);
+    cpu_state.seg_cs.checked = 0;
+    set_use32(0x40);
+
+    /* SS */
+    SS = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
+    read_seg_data(seg_data, SS, &cpu_state.seg_ss);
+    if (cpu_state.abrt)
+	return 1;
+    do_seg_load(&cpu_state.seg_ss, seg_data);
+    cpu_state.seg_ss.checked = 0;
+    codegen_flat_ss = 0;
+    if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
+	cpu_state.seg_ss.limit_high == 0xffffffff)
+	cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
+    else
+	cpu_cur_status |= CPU_STATUS_NOTFLATSS;
+    set_stack32(1);
+
+    flushmmucache_cr3();
+    oldcpl = CPL;
+    trap = 0;
+    in_sys = 0;
+
+    return 1;
 }
diff --git a/src/cpu_common/386_dynarec.c b/src/cpu_common/386_dynarec.c
index 53874af5b..7a08e4cee 100644
--- a/src/cpu_common/386_dynarec.c
+++ b/src/cpu_common/386_dynarec.c
@@ -22,7 +22,6 @@
 #include <86box/timer.h>
 #include <86box/fdd.h>
 #include <86box/fdc.h>
-#include <86box/keyboard.h>
 #ifdef USE_DYNAREC
 #include "codegen.h"
 #ifdef USE_NEW_DYNAREC
@@ -35,233 +34,13 @@
 #define CPU_BLOCK_END() cpu_block_end = 1
 
 
-/* These #define's and enum have been borrowed from Bochs. */
-/* SMM feature masks */
-#define SMM_IO_INSTRUCTION_RESTART  (0x00010000)
-#define SMM_SMBASE_RELOCATION       (0x00020000)
-
-/* TODO: Which CPU added SMBASE relocation? */
-#define SMM_REVISION_ID SMM_SMBASE_RELOCATION
-
-#define SMM_SAVE_STATE_MAP_SIZE 128
-
-
-enum SMMRAM_Fields_386_To_P5 {
-    SMRAM_FIELD_P5_CR0 = 0,		/* 1FC */
-    SMRAM_FIELD_P5_CR3,			/* 1F8 */
-    SMRAM_FIELD_P5_EFLAGS,		/* 1F4 */
-    SMRAM_FIELD_P5_EIP,			/* 1F0 */
-    SMRAM_FIELD_P5_EDI,			/* 1EC */
-    SMRAM_FIELD_P5_ESI,			/* 1E8 */
-    SMRAM_FIELD_P5_EBP,			/* 1E4 */
-    SMRAM_FIELD_P5_ESP,			/* 1E0 */
-    SMRAM_FIELD_P5_EBX,			/* 1DC */
-    SMRAM_FIELD_P5_EDX,			/* 1D8 */
-    SMRAM_FIELD_P5_ECX,			/* 1D4 */
-    SMRAM_FIELD_P5_EAX,			/* 1D0 */
-    SMRAM_FIELD_P5_DR6,			/* 1CC */
-    SMRAM_FIELD_P5_DR7,			/* 1C8 */
-    SMRAM_FIELD_P5_TR_SELECTOR,		/* 1C4 */
-    SMRAM_FIELD_P5_LDTR_SELECTOR,	/* 1C0 */
-    SMRAM_FIELD_P5_GS_SELECTOR,		/* 1BC */
-    SMRAM_FIELD_P5_FS_SELECTOR,		/* 1B8 */
-    SMRAM_FIELD_P5_DS_SELECTOR,		/* 1B4 */
-    SMRAM_FIELD_P5_SS_SELECTOR,		/* 1B0 */
-    SMRAM_FIELD_P5_CS_SELECTOR,		/* 1AC */
-    SMRAM_FIELD_P5_ES_SELECTOR,		/* 1A8 */
-    SMRAM_FIELD_P5_TR_ACCESS,		/* 1A4 */
-    SMRAM_FIELD_P5_TR_BASE,		/* 1A0 */
-    SMRAM_FIELD_P5_TR_LIMIT,		/* 19C */
-    SMRAM_FIELD_P5_IDTR_ACCESS,		/* 198 */
-    SMRAM_FIELD_P5_IDTR_BASE,		/* 194 */
-    SMRAM_FIELD_P5_IDTR_LIMIT,		/* 190 */
-    SMRAM_FIELD_P5_GDTR_ACCESS,		/* 18C */
-    SMRAM_FIELD_P5_GDTR_BASE,		/* 188 */
-    SMRAM_FIELD_P5_GDTR_LIMIT,		/* 184 */
-    SMRAM_FIELD_P5_LDTR_ACCESS,		/* 180 */
-    SMRAM_FIELD_P5_LDTR_BASE,		/* 17C */
-    SMRAM_FIELD_P5_LDTR_LIMIT,		/* 178 */
-    SMRAM_FIELD_P5_GS_ACCESS,		/* 174 */
-    SMRAM_FIELD_P5_GS_BASE,		/* 170 */
-    SMRAM_FIELD_P5_GS_LIMIT,		/* 16C */
-    SMRAM_FIELD_P5_FS_ACCESS,		/* 168 */
-    SMRAM_FIELD_P5_FS_BASE,		/* 164 */
-    SMRAM_FIELD_P5_FS_LIMIT,		/* 160 */
-    SMRAM_FIELD_P5_DS_ACCESS,		/* 15C */
-    SMRAM_FIELD_P5_DS_BASE,		/* 158 */
-    SMRAM_FIELD_P5_DS_LIMIT,		/* 154 */
-    SMRAM_FIELD_P5_SS_ACCESS,		/* 150 */
-    SMRAM_FIELD_P5_SS_BASE,		/* 14C */
-    SMRAM_FIELD_P5_SS_LIMIT,		/* 148 */
-    SMRAM_FIELD_P5_CS_ACCESS,		/* 144 */
-    SMRAM_FIELD_P5_CS_BASE,		/* 140 */
-    SMRAM_FIELD_P5_CS_LIMIT,		/* 13C */
-    SMRAM_FIELD_P5_ES_ACCESS,		/* 138 */
-    SMRAM_FIELD_P5_ES_BASE,		/* 134 */
-    SMRAM_FIELD_P5_ES_LIMIT,		/* 130 */
-    SMRAM_FIELD_P5_UNWRITTEN_1,		/* 12C */
-    SMRAM_FIELD_P5_CR4,			/* 128 */
-    SMRAM_FIELD_P5_ALTERNATE_DR6,	/* 124 */
-    SMRAM_FIELD_P5_RESERVED_1,		/* 120 */
-    SMRAM_FIELD_P5_RESERVED_2,		/* 11C */
-    SMRAM_FIELD_P5_RESERVED_3,		/* 118 */
-    SMRAM_FIELD_P5_RESERVED_4,		/* 114 */
-    SMRAM_FIELD_P5_IO_RESTART_EIP,	/* 110 */
-    SMRAM_FIELD_P5_IO_RESTART_ESI,	/* 10C */
-    SMRAM_FIELD_P5_IO_RESTART_ECX,	/* 108 */
-    SMRAM_FIELD_P5_IO_RESTART_EDI,	/* 104 */
-    SMRAM_FIELD_P5_AUTOHALT_RESTART,	/* 100 */
-    SMRAM_FIELD_P5_SMM_REVISION_ID,	/* 0FC */
-    SMRAM_FIELD_P5_SMBASE_OFFSET,	/* 0F8 */
-    SMRAM_FIELD_P5_LAST
-};
-
-enum SMMRAM_Fields_P6 {
-    SMRAM_FIELD_P6_CR0 = 0,		/* 1FC */
-    SMRAM_FIELD_P6_CR3,			/* 1F8 */
-    SMRAM_FIELD_P6_EFLAGS,		/* 1F4 */
-    SMRAM_FIELD_P6_EIP,			/* 1F0 */
-    SMRAM_FIELD_P6_EDI,			/* 1EC */
-    SMRAM_FIELD_P6_ESI,			/* 1E8 */
-    SMRAM_FIELD_P6_EBP,			/* 1E4 */
-    SMRAM_FIELD_P6_ESP,			/* 1E0 */
-    SMRAM_FIELD_P6_EBX,			/* 1DC */
-    SMRAM_FIELD_P6_EDX,			/* 1D8 */
-    SMRAM_FIELD_P6_ECX,			/* 1D4 */
-    SMRAM_FIELD_P6_EAX,			/* 1D0 */
-    SMRAM_FIELD_P6_DR6,			/* 1CC */
-    SMRAM_FIELD_P6_DR7,			/* 1C8 */
-    SMRAM_FIELD_P6_TR_SELECTOR,		/* 1C4 */
-    SMRAM_FIELD_P6_LDTR_SELECTOR,	/* 1C0 */
-    SMRAM_FIELD_P6_GS_SELECTOR,		/* 1BC */
-    SMRAM_FIELD_P6_FS_SELECTOR,		/* 1B8 */
-    SMRAM_FIELD_P6_DS_SELECTOR,		/* 1B4 */
-    SMRAM_FIELD_P6_SS_SELECTOR,		/* 1B0 */
-    SMRAM_FIELD_P6_CS_SELECTOR,		/* 1AC */
-    SMRAM_FIELD_P6_ES_SELECTOR,		/* 1A8 */
-    SMRAM_FIELD_P6_SS_BASE,		/* 1A4 */
-    SMRAM_FIELD_P6_SS_LIMIT,		/* 1A0 */
-    SMRAM_FIELD_P6_SS_SELECTOR_AR,	/* 19C */
-    SMRAM_FIELD_P6_CS_BASE,		/* 198 */
-    SMRAM_FIELD_P6_CS_LIMIT,		/* 194 */
-    SMRAM_FIELD_P6_CS_SELECTOR_AR,	/* 190 */
-    SMRAM_FIELD_P6_ES_BASE,		/* 18C */
-    SMRAM_FIELD_P6_ES_LIMIT,		/* 188 */
-    SMRAM_FIELD_P6_ES_SELECTOR_AR,	/* 184 */
-    SMRAM_FIELD_P6_LDTR_BASE,		/* 180 */
-    SMRAM_FIELD_P6_LDTR_LIMIT,		/* 17C */
-    SMRAM_FIELD_P6_LDTR_SELECTOR_AR,	/* 178 */
-    SMRAM_FIELD_P6_GDTR_BASE,		/* 174 */
-    SMRAM_FIELD_P6_GDTR_LIMIT,		/* 170 */
-    SMRAM_FIELD_P6_GDTR_SELECTOR_AR,	/* 16C */
-    SMRAM_FIELD_P6_SREG_STATUS1,	/* 168 */
-    SMRAM_FIELD_P6_TR_BASE,		/* 164 */
-    SMRAM_FIELD_P6_TR_LIMIT,		/* 160 */
-    SMRAM_FIELD_P6_TR_SELECTOR_AR,	/* 15C */
-    SMRAM_FIELD_P6_IDTR_BASE,		/* 158 */
-    SMRAM_FIELD_P6_IDTR_LIMIT,		/* 154 */
-    SMRAM_FIELD_P6_IDTR_SELECTOR_AR,	/* 150 */
-    SMRAM_FIELD_P6_GS_BASE,		/* 14C */
-    SMRAM_FIELD_P6_GS_LIMIT,		/* 148 */
-    SMRAM_FIELD_P6_GS_SELECTOR_AR,	/* 144 */
-    SMRAM_FIELD_P6_FS_BASE,		/* 140 */
-    SMRAM_FIELD_P6_FS_LIMIT,		/* 13C */
-    SMRAM_FIELD_P6_FS_SELECTOR_AR,	/* 138 */
-    SMRAM_FIELD_P6_DS_BASE,		/* 134 */
-    SMRAM_FIELD_P6_DS_LIMIT,		/* 130 */
-    SMRAM_FIELD_P6_DS_SELECTOR_AR,	/* 12C */
-    SMRAM_FIELD_P6_SREG_STATUS0,	/* 128 */
-    SMRAM_FIELD_P6_ALTERNATIVE_DR6,	/* 124 */
-    SMRAM_FIELD_P6_CPL,			/* 120 */
-    SMRAM_FIELD_P6_SMM_STATUS,		/* 11C */
-    SMRAM_FIELD_P6_A20M,		/* 118 */
-    SMRAM_FIELD_P6_CR4,			/* 114 */
-    SMRAM_FIELD_P6_IO_RESTART_EIP,	/* 110 */
-    SMRAM_FIELD_P6_IO_RESTART_ESI,	/* 10C */
-    SMRAM_FIELD_P6_IO_RESTART_ECX,	/* 108 */
-    SMRAM_FIELD_P6_IO_RESTART_EDI,	/* 104 */
-    SMRAM_FIELD_P6_AUTOHALT_RESTART,	/* 100 */
-    SMRAM_FIELD_P6_SMM_REVISION_ID,	/* 0FC */
-    SMRAM_FIELD_P6_SMBASE_OFFSET,	/* 0F8 */
-    SMRAM_FIELD_P6_LAST
-};
-
-enum SMMRAM_Fields_AMD_K {
-    SMRAM_FIELD_AMD_K_CR0 = 0,		/* 1FC */
-    SMRAM_FIELD_AMD_K_CR3,		/* 1F8 */
-    SMRAM_FIELD_AMD_K_EFLAGS,		/* 1F4 */
-    SMRAM_FIELD_AMD_K_EIP,		/* 1F0 */
-    SMRAM_FIELD_AMD_K_EDI,		/* 1EC */
-    SMRAM_FIELD_AMD_K_ESI,		/* 1E8 */
-    SMRAM_FIELD_AMD_K_EBP,		/* 1E4 */
-    SMRAM_FIELD_AMD_K_ESP,		/* 1E0 */
-    SMRAM_FIELD_AMD_K_EBX,		/* 1DC */
-    SMRAM_FIELD_AMD_K_EDX,		/* 1D8 */
-    SMRAM_FIELD_AMD_K_ECX,		/* 1D4 */
-    SMRAM_FIELD_AMD_K_EAX,		/* 1D0 */
-    SMRAM_FIELD_AMD_K_DR6,		/* 1CC */
-    SMRAM_FIELD_AMD_K_DR7,		/* 1C8 */
-    SMRAM_FIELD_AMD_K_TR_SELECTOR,	/* 1C4 */
-    SMRAM_FIELD_AMD_K_LDTR_SELECTOR,	/* 1C0 */
-    SMRAM_FIELD_AMD_K_GS_SELECTOR,	/* 1BC */
-    SMRAM_FIELD_AMD_K_FS_SELECTOR,	/* 1B8 */
-    SMRAM_FIELD_AMD_K_DS_SELECTOR,	/* 1B4 */
-    SMRAM_FIELD_AMD_K_SS_SELECTOR,	/* 1B0 */
-    SMRAM_FIELD_AMD_K_CS_SELECTOR,	/* 1AC */
-    SMRAM_FIELD_AMD_K_ES_SELECTOR,	/* 1A8 */
-    SMRAM_FIELD_AMD_K_IO_RESTART_DWORD,	/* 1A4 */
-    SMRAM_FIELD_AMD_K_RESERVED_1,	/* 1A0 */
-    SMRAM_FIELD_AMD_K_IO_RESTART_EIP,	/* 19C */
-    SMRAM_FIELD_AMD_K_RESERVED_2,	/* 198 */
-    SMRAM_FIELD_AMD_K_RESERVED_3,	/* 194 */
-    SMRAM_FIELD_AMD_K_IDTR_BASE,	/* 190 */
-    SMRAM_FIELD_AMD_K_IDTR_LIMIT,	/* 18C */
-    SMRAM_FIELD_AMD_K_GDTR_BASE,	/* 188 */
-    SMRAM_FIELD_AMD_K_GDTR_LIMIT,	/* 184 */
-    SMRAM_FIELD_AMD_K_TR_ACCESS,	/* 180 */
-    SMRAM_FIELD_AMD_K_TR_BASE,		/* 17C */
-    SMRAM_FIELD_AMD_K_TR_LIMIT,		/* 178 */
-    SMRAM_FIELD_AMD_K_LDTR_ACCESS,	/* 174 - reserved on K6 */
-    SMRAM_FIELD_AMD_K_LDTR_BASE,	/* 170 */
-    SMRAM_FIELD_AMD_K_LDTR_LIMIT,	/* 16C */
-    SMRAM_FIELD_AMD_K_GS_ACCESS,	/* 168 */
-    SMRAM_FIELD_AMD_K_GS_BASE,		/* 164 */
-    SMRAM_FIELD_AMD_K_GS_LIMIT,		/* 160 */
-    SMRAM_FIELD_AMD_K_FS_ACCESS,	/* 15C */
-    SMRAM_FIELD_AMD_K_FS_BASE,		/* 158 */
-    SMRAM_FIELD_AMD_K_FS_LIMIT,		/* 154 */
-    SMRAM_FIELD_AMD_K_DS_ACCESS,	/* 150 */
-    SMRAM_FIELD_AMD_K_DS_BASE,		/* 14C */
-    SMRAM_FIELD_AMD_K_DS_LIMIT,		/* 148 */
-    SMRAM_FIELD_AMD_K_SS_ACCESS,	/* 144 */
-    SMRAM_FIELD_AMD_K_SS_BASE,		/* 140 */
-    SMRAM_FIELD_AMD_K_SS_LIMIT,		/* 13C */
-    SMRAM_FIELD_AMD_K_CS_ACCESS,	/* 138 */
-    SMRAM_FIELD_AMD_K_CS_BASE,		/* 134 */
-    SMRAM_FIELD_AMD_K_CS_LIMIT,		/* 130 */
-    SMRAM_FIELD_AMD_K_ES_ACCESS,	/* 12C */
-    SMRAM_FIELD_AMD_K_ES_BASE,		/* 128 */
-    SMRAM_FIELD_AMD_K_ES_LIMIT,		/* 124 */
-    SMRAM_FIELD_AMD_K_RESERVED_4,	/* 120 */
-    SMRAM_FIELD_AMD_K_RESERVED_5,	/* 11C */
-    SMRAM_FIELD_AMD_K_RESERVED_6,	/* 118 */
-    SMRAM_FIELD_AMD_K_CR2,		/* 114 */
-    SMRAM_FIELD_AMD_K_CR4,		/* 110 */
-    SMRAM_FIELD_AMD_K_IO_RESTART_ESI,	/* 10C */
-    SMRAM_FIELD_AMD_K_IO_RESTART_ECX,	/* 108 */
-    SMRAM_FIELD_AMD_K_IO_RESTART_EDI,	/* 104 */
-    SMRAM_FIELD_AMD_K_AUTOHALT_RESTART,	/* 100 */
-    SMRAM_FIELD_AMD_K_SMM_REVISION_ID,	/* 0FC */
-    SMRAM_FIELD_AMD_K_SMBASE_OFFSET,	/* 0F8 */
-    SMRAM_FIELD_AMD_K_LAST
-};
-
-
 int inrecomp = 0, cpu_block_end = 0;
 int cpu_recomp_blocks, cpu_recomp_full_ins, cpu_new_blocks;
 int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latched, cpu_new_blocks_latched;
 
 
+#define SYSENTER_LOG 1
+#define ENABLE_386_DYNAREC_LOG 1
 #ifdef ENABLE_386_DYNAREC_LOG
 int x386_dynarec_do_log = ENABLE_386_DYNAREC_LOG;
 
@@ -485,846 +264,9 @@ static void prefetch_flush()
 #define PREFETCH_FLUSH() prefetch_flush()
 
 
-static void set_stack32(int s)
-{
-        stack32 = s;
-	if (stack32)
-	       cpu_cur_status |= CPU_STATUS_STACK32;
-	else
-	       cpu_cur_status &= ~CPU_STATUS_STACK32;
-}
-
-
-static void set_use32(int u)
-{
-        if (u) 
-        {
-                use32 = 0x300;
-                cpu_cur_status |= CPU_STATUS_USE32;
-        }
-        else
-        {
-                use32 = 0;
-                cpu_cur_status &= ~CPU_STATUS_USE32;
-        }
-}
-
-
-void smm_seg_load(x86seg *s)
-{
-        if (!is386)
-                s->base &= 0x00ffffff;
-
-        if ((s->access & 0x18) != 0x10 || !(s->access & (1 << 2))) /*expand-down*/
-        {
-                s->limit_high = s->limit;
-                s->limit_low = 0;
-        }
-        else
-        {
-                s->limit_high = (s->ar_high & 0x40) ? 0xffffffff : 0xffff;
-                s->limit_low = s->limit + 1;
-        }
-
-	if ((cr0 & 1) && !(cpu_state.eflags & VM_FLAG))
-		s->checked = s->seg ? 1 : 0;
-	else
-		s->checked = 1;
-
-        if (s == &cpu_state.seg_cs)
-		set_use32(s->ar_high & 0x40);
-        if (s == &cpu_state.seg_ds)
-        {
-                if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
-                        cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
-                else
-                        cpu_cur_status |= CPU_STATUS_NOTFLATDS;
-        }
-        if (s == &cpu_state.seg_ss)
-        {
-                if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
-                        cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
-                else
-                        cpu_cur_status |= CPU_STATUS_NOTFLATSS;
-		set_stack32((s->ar_high & 0x40) ? 1 : 0);
-        }
-}
-
-
-void smram_save_state_p5(uint32_t *saved_state)
-{
-	int n = 0;
-
-	saved_state[SMRAM_FIELD_P5_SMM_REVISION_ID] = SMM_REVISION_ID;
-	saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET] = smbase;
-
-	for (n = 0; n < 8; n++)
-		saved_state[SMRAM_FIELD_P5_EAX - n] = cpu_state.regs[n].l;
-
-	if (in_hlt) {
-		saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] = 1;
-		saved_state[SMRAM_FIELD_P5_EIP] = cpu_state.pc + 1;
-	} else {
-		saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] = 0;
-		saved_state[SMRAM_FIELD_P5_EIP] = cpu_state.pc;
-	}
-
-	saved_state[SMRAM_FIELD_P5_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
-
-	saved_state[SMRAM_FIELD_P5_CR0] = cr0;
-	saved_state[SMRAM_FIELD_P5_CR3] = cr3;
-	saved_state[SMRAM_FIELD_P5_CR4] = cr4;
-	saved_state[SMRAM_FIELD_P5_DR6] = dr[6];
-	saved_state[SMRAM_FIELD_P5_DR7] = dr[7];
-
-	/* TR */
-	saved_state[SMRAM_FIELD_P5_TR_SELECTOR] = tr.seg;
-	saved_state[SMRAM_FIELD_P5_TR_BASE] = tr.base;
-	saved_state[SMRAM_FIELD_P5_TR_LIMIT] = tr.limit;
-	saved_state[SMRAM_FIELD_P5_TR_ACCESS] = (tr.ar_high << 16) | (tr.access << 8);
-
-	/* LDTR */
-	saved_state[SMRAM_FIELD_P5_LDTR_SELECTOR] = ldt.seg;
-	saved_state[SMRAM_FIELD_P5_LDTR_BASE] = ldt.base;
-	saved_state[SMRAM_FIELD_P5_LDTR_LIMIT] = ldt.limit;
-	saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] = (ldt.ar_high << 16) | (ldt.access << 8);
-
-	/* IDTR */
-	saved_state[SMRAM_FIELD_P5_IDTR_BASE] = idt.base;
-	saved_state[SMRAM_FIELD_P5_IDTR_LIMIT] = idt.limit;
-	saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] = (idt.ar_high << 16) | (idt.access << 8);
-
-	/* GDTR */
-	saved_state[SMRAM_FIELD_P5_GDTR_BASE] = gdt.base;
-	saved_state[SMRAM_FIELD_P5_GDTR_LIMIT] = gdt.limit;
-	saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] = (gdt.ar_high << 16) | (gdt.access << 8);
-
-	/* ES */
-	saved_state[SMRAM_FIELD_P5_ES_SELECTOR] = cpu_state.seg_es.seg;
-	saved_state[SMRAM_FIELD_P5_ES_BASE] = cpu_state.seg_es.base;
-	saved_state[SMRAM_FIELD_P5_ES_LIMIT] = cpu_state.seg_es.limit;
-	saved_state[SMRAM_FIELD_P5_ES_ACCESS] = (cpu_state.seg_es.ar_high << 16) | (cpu_state.seg_es.access << 8);
-
-	/* CS */
-	saved_state[SMRAM_FIELD_P5_CS_SELECTOR] = cpu_state.seg_cs.seg;
-	saved_state[SMRAM_FIELD_P5_CS_BASE] = cpu_state.seg_cs.base;
-	saved_state[SMRAM_FIELD_P5_CS_LIMIT] = cpu_state.seg_cs.limit;
-	saved_state[SMRAM_FIELD_P5_CS_ACCESS] = (cpu_state.seg_cs.ar_high << 16) | (cpu_state.seg_cs.access << 8);
-
-	/* DS */
-	saved_state[SMRAM_FIELD_P5_DS_SELECTOR] = cpu_state.seg_ds.seg;
-	saved_state[SMRAM_FIELD_P5_DS_BASE] = cpu_state.seg_ds.base;
-	saved_state[SMRAM_FIELD_P5_DS_LIMIT] = cpu_state.seg_ds.limit;
-	saved_state[SMRAM_FIELD_P5_DS_ACCESS] = (cpu_state.seg_ds.ar_high << 16) | (cpu_state.seg_ds.access << 8);
-
-	/* SS */
-	saved_state[SMRAM_FIELD_P5_SS_SELECTOR] = cpu_state.seg_ss.seg;
-	saved_state[SMRAM_FIELD_P5_SS_BASE] = cpu_state.seg_ss.base;
-	saved_state[SMRAM_FIELD_P5_SS_LIMIT] = cpu_state.seg_ss.limit;
-	saved_state[SMRAM_FIELD_P5_SS_ACCESS] = (cpu_state.seg_ss.ar_high << 16) | (cpu_state.seg_ss.access << 8);
-
-	/* FS */
-	saved_state[SMRAM_FIELD_P5_FS_SELECTOR] = cpu_state.seg_fs.seg;
-	saved_state[SMRAM_FIELD_P5_FS_BASE] = cpu_state.seg_fs.base;
-	saved_state[SMRAM_FIELD_P5_FS_LIMIT] = cpu_state.seg_fs.limit;
-	saved_state[SMRAM_FIELD_P5_FS_ACCESS] = (cpu_state.seg_fs.ar_high << 16) | (cpu_state.seg_fs.access << 8);
-
-	/* GS */
-	saved_state[SMRAM_FIELD_P5_GS_SELECTOR] = cpu_state.seg_gs.seg;
-	saved_state[SMRAM_FIELD_P5_GS_BASE] = cpu_state.seg_gs.base;
-	saved_state[SMRAM_FIELD_P5_GS_LIMIT] = cpu_state.seg_gs.limit;
-	saved_state[SMRAM_FIELD_P5_GS_ACCESS] = (cpu_state.seg_gs.ar_high << 16) | (cpu_state.seg_gs.access << 8);
-}
-
-
-void smram_restore_state_p5(uint32_t *saved_state)
-{
-	int n = 0;
-
-	for (n = 0; n < 8; n++)
-		cpu_state.regs[n].l = saved_state[SMRAM_FIELD_P5_EAX - n];
-
-	if (saved_state[SMRAM_FIELD_P5_AUTOHALT_RESTART] & 0xffff)
-		cpu_state.pc = saved_state[SMRAM_FIELD_P5_EIP] - 1;
-	else
-		cpu_state.pc = saved_state[SMRAM_FIELD_P5_EIP];
-
-	cpu_state.eflags = saved_state[SMRAM_FIELD_P5_EFLAGS] >> 16;
-	cpu_state.flags = saved_state[SMRAM_FIELD_P5_EFLAGS] & 0xffff;
-
-	cr0 = saved_state[SMRAM_FIELD_P5_CR0];
-	cr3 = saved_state[SMRAM_FIELD_P5_CR3];
-	cr4 = saved_state[SMRAM_FIELD_P5_CR4];
-	dr[6] = saved_state[SMRAM_FIELD_P5_DR6];
-	dr[7] = saved_state[SMRAM_FIELD_P5_DR7];
-
-	/* TR */
-	tr.seg = saved_state[SMRAM_FIELD_P5_TR_SELECTOR];
-	tr.base = saved_state[SMRAM_FIELD_P5_TR_BASE];
-	tr.limit = saved_state[SMRAM_FIELD_P5_TR_LIMIT];
-	tr.access = (saved_state[SMRAM_FIELD_P5_TR_ACCESS] >> 8) & 0xff;
-	tr.ar_high = (saved_state[SMRAM_FIELD_P5_TR_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&tr);
-
-	/* LDTR */
-	ldt.seg = saved_state[SMRAM_FIELD_P5_LDTR_SELECTOR];
-	ldt.base = saved_state[SMRAM_FIELD_P5_LDTR_BASE];
-	ldt.limit = saved_state[SMRAM_FIELD_P5_LDTR_LIMIT];
-	ldt.access = (saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] >> 8) & 0xff;
-	ldt.ar_high = (saved_state[SMRAM_FIELD_P5_LDTR_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&ldt);
-
-	/* IDTR */
-	idt.base = saved_state[SMRAM_FIELD_P5_IDTR_BASE];
-	idt.limit = saved_state[SMRAM_FIELD_P5_IDTR_LIMIT];
-	idt.access = (saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] >> 8) & 0xff;
-	idt.ar_high = (saved_state[SMRAM_FIELD_P5_IDTR_ACCESS] >> 16) & 0xff;
-
-	/* GDTR */
-	gdt.base = saved_state[SMRAM_FIELD_P5_GDTR_BASE];
-	gdt.limit = saved_state[SMRAM_FIELD_P5_GDTR_LIMIT];
-	gdt.access = (saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] >> 8) & 0xff;
-	gdt.ar_high = (saved_state[SMRAM_FIELD_P5_GDTR_ACCESS] >> 16) & 0xff;
-
-	/* ES */
-	cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_P5_ES_SELECTOR];
-	cpu_state.seg_es.base = saved_state[SMRAM_FIELD_P5_ES_BASE];
-	cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_P5_ES_LIMIT];
-	cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_P5_ES_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_P5_ES_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_es);
-
-	/* CS */
-	cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_P5_CS_SELECTOR];
-	cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_P5_CS_BASE];
-	cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_P5_CS_LIMIT];
-	cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_P5_CS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_P5_CS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_cs);
-
-	/* DS */
-	cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_P5_DS_SELECTOR];
-	cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_P5_DS_BASE];
-	cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_P5_DS_LIMIT];
-	cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_P5_DS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_P5_DS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_ds);
-
-	/* SS */
-	cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_P5_SS_SELECTOR];
-	cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_P5_SS_BASE];
-	cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_P5_SS_LIMIT];
-	cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_P5_SS_ACCESS] >> 8) & 0xff;
-	/* The actual CPL (DPL of CS) is overwritten with DPL of SS. */
-	cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | (cpu_state.seg_ss.access & 0x60);
-	cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_P5_SS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_ss);
-
-	/* FS */
-	cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_P5_FS_SELECTOR];
-	cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_P5_FS_BASE];
-	cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_P5_FS_LIMIT];
-	cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_P5_FS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_P5_FS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_fs);
-
-	/* GS */
-	cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_P5_GS_SELECTOR];
-	cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_P5_GS_BASE];
-	cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_P5_GS_LIMIT];
-	cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_P5_GS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_P5_GS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_gs);
-
-	if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
-		smbase = saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET];
-}
-
-
-void smram_save_state_p6(uint32_t *saved_state)
-{
-	int n = 0;
-
-	saved_state[SMRAM_FIELD_P6_SMM_REVISION_ID] = SMM_REVISION_ID;
-	saved_state[SMRAM_FIELD_P6_SMBASE_OFFSET] = smbase;
-
-	for (n = 0; n < 8; n++)
-		saved_state[SMRAM_FIELD_P6_EAX - n] = cpu_state.regs[n].l;
-
-	if (in_hlt) {
-		saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] = 1;
-		saved_state[SMRAM_FIELD_P6_EIP] = cpu_state.pc + 1;
-	} else {
-		saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] = 0;
-		saved_state[SMRAM_FIELD_P6_EIP] = cpu_state.pc;
-	}
-
-	saved_state[SMRAM_FIELD_P6_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
-
-	saved_state[SMRAM_FIELD_P6_CR0] = cr0;
-	saved_state[SMRAM_FIELD_P6_CR3] = cr3;
-	saved_state[SMRAM_FIELD_P6_CR4] = cr4;
-	saved_state[SMRAM_FIELD_P6_DR6] = dr[6];
-	saved_state[SMRAM_FIELD_P6_DR7] = dr[7];
-	saved_state[SMRAM_FIELD_P6_CPL] = CPL;
-	saved_state[SMRAM_FIELD_P6_A20M] = !mem_a20_state;
-
-	/* TR */
-	saved_state[SMRAM_FIELD_P6_TR_SELECTOR] = tr.seg;
-	saved_state[SMRAM_FIELD_P6_TR_BASE] = tr.base;
-	saved_state[SMRAM_FIELD_P6_TR_LIMIT] = tr.limit;
-	saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] = (tr.ar_high << 24) | (tr.access << 16) | tr.seg;
-
-	/* LDTR */
-	saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR] = ldt.seg;
-	saved_state[SMRAM_FIELD_P6_LDTR_BASE] = ldt.base;
-	saved_state[SMRAM_FIELD_P6_LDTR_LIMIT] = ldt.limit;
-	saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] = (ldt.ar_high << 24) | (ldt.access << 16) | ldt.seg;
-
-	/* IDTR */
-	saved_state[SMRAM_FIELD_P6_IDTR_BASE] = idt.base;
-	saved_state[SMRAM_FIELD_P6_IDTR_LIMIT] = idt.limit;
-	saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] = (idt.ar_high << 24) | (idt.access << 16) | idt.seg;
-
-	/* GDTR */
-	saved_state[SMRAM_FIELD_P6_GDTR_BASE] = gdt.base;
-	saved_state[SMRAM_FIELD_P6_GDTR_LIMIT] = gdt.limit;
-	saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] = (gdt.ar_high << 24) | (gdt.access << 16) | gdt.seg;
-
-	/* ES */
-	saved_state[SMRAM_FIELD_P6_ES_SELECTOR] = cpu_state.seg_es.seg;
-	saved_state[SMRAM_FIELD_P6_ES_BASE] = cpu_state.seg_es.base;
-	saved_state[SMRAM_FIELD_P6_ES_LIMIT] = cpu_state.seg_es.limit;
-	saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] =
-		(cpu_state.seg_es.ar_high << 24) | (cpu_state.seg_es.access << 16) | cpu_state.seg_es.seg;
-
-	/* CS */
-	saved_state[SMRAM_FIELD_P6_CS_SELECTOR] = cpu_state.seg_cs.seg;
-	saved_state[SMRAM_FIELD_P6_CS_BASE] = cpu_state.seg_cs.base;
-	saved_state[SMRAM_FIELD_P6_CS_LIMIT] = cpu_state.seg_cs.limit;
-	saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] =
-		(cpu_state.seg_cs.ar_high << 24) | (cpu_state.seg_cs.access << 16) | cpu_state.seg_cs.seg;
-
-	/* DS */
-	saved_state[SMRAM_FIELD_P6_DS_SELECTOR] = cpu_state.seg_ds.seg;
-	saved_state[SMRAM_FIELD_P6_DS_BASE] = cpu_state.seg_ds.base;
-	saved_state[SMRAM_FIELD_P6_DS_LIMIT] = cpu_state.seg_ds.limit;
-	saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] =
-		(cpu_state.seg_ds.ar_high << 24) | (cpu_state.seg_ds.access << 16) | cpu_state.seg_ds.seg;
-
-	/* SS */
-	saved_state[SMRAM_FIELD_P6_SS_SELECTOR] = cpu_state.seg_ss.seg;
-	saved_state[SMRAM_FIELD_P6_SS_BASE] = cpu_state.seg_ss.base;
-	saved_state[SMRAM_FIELD_P6_SS_LIMIT] = cpu_state.seg_ss.limit;
-	saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] =
-		(cpu_state.seg_ss.ar_high << 24) | (cpu_state.seg_ss.access << 16) | cpu_state.seg_ss.seg;
-
-	/* FS */
-	saved_state[SMRAM_FIELD_P6_FS_SELECTOR] = cpu_state.seg_fs.seg;
-	saved_state[SMRAM_FIELD_P6_FS_BASE] = cpu_state.seg_fs.base;
-	saved_state[SMRAM_FIELD_P6_FS_LIMIT] = cpu_state.seg_fs.limit;
-	saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] =
-		(cpu_state.seg_fs.ar_high << 24) | (cpu_state.seg_fs.access << 16) | cpu_state.seg_fs.seg;
-
-	/* GS */
-	saved_state[SMRAM_FIELD_P6_GS_SELECTOR] = cpu_state.seg_gs.seg;
-	saved_state[SMRAM_FIELD_P6_GS_BASE] = cpu_state.seg_gs.base;
-	saved_state[SMRAM_FIELD_P6_GS_LIMIT] = cpu_state.seg_gs.limit;
-	saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] =
-		(cpu_state.seg_gs.ar_high << 24) | (cpu_state.seg_gs.access << 16) | cpu_state.seg_gs.seg;
-}
-
-
-void smram_restore_state_p6(uint32_t *saved_state)
-{
-	int n = 0;
-
-	for (n = 0; n < 8; n++)
-		cpu_state.regs[n].l = saved_state[SMRAM_FIELD_P6_EAX - n];
-
-	if (saved_state[SMRAM_FIELD_P6_AUTOHALT_RESTART] & 0xffff)
-		cpu_state.pc = saved_state[SMRAM_FIELD_P6_EIP] - 1;
-	else
-		cpu_state.pc = saved_state[SMRAM_FIELD_P6_EIP];
-
-	cpu_state.eflags = saved_state[SMRAM_FIELD_P6_EFLAGS] >> 16;
-	cpu_state.flags = saved_state[SMRAM_FIELD_P6_EFLAGS] & 0xffff;
-
-	cr0 = saved_state[SMRAM_FIELD_P6_CR0];
-	cr3 = saved_state[SMRAM_FIELD_P6_CR3];
-	cr4 = saved_state[SMRAM_FIELD_P6_CR4];
-	dr[6] = saved_state[SMRAM_FIELD_P6_DR6];
-	dr[7] = saved_state[SMRAM_FIELD_P6_DR7];
-
-	/* TR */
-	tr.seg = saved_state[SMRAM_FIELD_P6_TR_SELECTOR];
-	tr.base = saved_state[SMRAM_FIELD_P6_TR_BASE];
-	tr.limit = saved_state[SMRAM_FIELD_P6_TR_LIMIT];
-	tr.access = (saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] >> 16) & 0xff;
-	tr.ar_high = (saved_state[SMRAM_FIELD_P6_TR_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&tr);
-
-	/* LDTR */
-	ldt.seg = saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR];
-	ldt.base = saved_state[SMRAM_FIELD_P6_LDTR_BASE];
-	ldt.limit = saved_state[SMRAM_FIELD_P6_LDTR_LIMIT];
-	ldt.access = (saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] >> 16) & 0xff;
-	ldt.ar_high = (saved_state[SMRAM_FIELD_P6_LDTR_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&ldt);
-
-	/* IDTR */
-	idt.base = saved_state[SMRAM_FIELD_P6_IDTR_BASE];
-	idt.limit = saved_state[SMRAM_FIELD_P6_IDTR_LIMIT];
-	idt.access = (saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] >> 16) & 0xff;
-	idt.ar_high = (saved_state[SMRAM_FIELD_P6_IDTR_SELECTOR_AR] >> 24) & 0xff;
-
-	/* GDTR */
-	gdt.base = saved_state[SMRAM_FIELD_P6_GDTR_BASE];
-	gdt.limit = saved_state[SMRAM_FIELD_P6_GDTR_LIMIT];
-	gdt.access = (saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] >> 16) & 0xff;
-	gdt.ar_high = (saved_state[SMRAM_FIELD_P6_GDTR_SELECTOR_AR] >> 24) & 0xff;
-
-	/* ES */
-	cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_P6_ES_SELECTOR];
-	cpu_state.seg_es.base = saved_state[SMRAM_FIELD_P6_ES_BASE];
-	cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_P6_ES_LIMIT];
-	cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_P6_ES_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_es);
-
-	/* CS */
-	cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_P6_CS_SELECTOR];
-	cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_P6_CS_BASE];
-	cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_P6_CS_LIMIT];
-	cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_P6_CS_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_cs);
-	cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | ((saved_state[SMRAM_FIELD_P6_CPL] & 0x03) << 5);
-
-	/* DS */
-	cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_P6_DS_SELECTOR];
-	cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_P6_DS_BASE];
-	cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_P6_DS_LIMIT];
-	cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_P6_DS_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_ds);
-
-	/* SS */
-	cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_P6_SS_SELECTOR];
-	cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_P6_SS_BASE];
-	cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_P6_SS_LIMIT];
-	cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_P6_SS_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_ss);
-
-	/* FS */
-	cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_P6_FS_SELECTOR];
-	cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_P6_FS_BASE];
-	cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_P6_FS_LIMIT];
-	cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_P6_FS_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_fs);
-
-	/* GS */
-	cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_P6_GS_SELECTOR];
-	cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_P6_GS_BASE];
-	cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_P6_GS_LIMIT];
-	cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] >> 16) & 0xff;
-	cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_P6_GS_SELECTOR_AR] >> 24) & 0xff;
-	smm_seg_load(&cpu_state.seg_gs);
-
-	mem_a20_alt = 0;
-	keyboard_at_set_a20_key(!saved_state[SMRAM_FIELD_P6_A20M]);
-	mem_a20_recalc();
-
-	if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
-		smbase = saved_state[SMRAM_FIELD_P6_SMBASE_OFFSET];
-}
-
-
-void smram_save_state_amd_k(uint32_t *saved_state)
-{
-	int n = 0;
-
-	saved_state[SMRAM_FIELD_AMD_K_SMM_REVISION_ID] = SMM_REVISION_ID;
-	saved_state[SMRAM_FIELD_AMD_K_SMBASE_OFFSET] = smbase;
-
-	for (n = 0; n < 8; n++)
-		saved_state[SMRAM_FIELD_AMD_K_EAX - n] = cpu_state.regs[n].l;
-
-	if (in_hlt) {
-		saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] = 1;
-		saved_state[SMRAM_FIELD_AMD_K_EIP] = cpu_state.pc + 1;
-	} else {
-		saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] = 0;
-		saved_state[SMRAM_FIELD_AMD_K_EIP] = cpu_state.pc;
-	}
-
-	saved_state[SMRAM_FIELD_AMD_K_EFLAGS] = (cpu_state.eflags << 16) | (cpu_state.flags);
-
-	saved_state[SMRAM_FIELD_AMD_K_CR0] = cr0;
-	saved_state[SMRAM_FIELD_AMD_K_CR2] = cr2;
-	saved_state[SMRAM_FIELD_AMD_K_CR3] = cr3;
-	saved_state[SMRAM_FIELD_AMD_K_CR4] = cr4;
-	saved_state[SMRAM_FIELD_AMD_K_DR6] = dr[6];
-	saved_state[SMRAM_FIELD_AMD_K_DR7] = dr[7];
-
-	/* TR */
-	saved_state[SMRAM_FIELD_AMD_K_TR_SELECTOR] = tr.seg;
-	saved_state[SMRAM_FIELD_AMD_K_TR_BASE] = tr.base;
-	saved_state[SMRAM_FIELD_AMD_K_TR_LIMIT] = tr.limit;
-	saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] = (tr.ar_high << 16) | (tr.access << 8);
-
-	/* LDTR */
-	saved_state[SMRAM_FIELD_AMD_K_LDTR_SELECTOR] = ldt.seg;
-	saved_state[SMRAM_FIELD_AMD_K_LDTR_BASE] = ldt.base;
-	saved_state[SMRAM_FIELD_AMD_K_LDTR_LIMIT] = ldt.limit;
-	if (!is_k6)
-		saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] = (ldt.ar_high << 16) | (ldt.access << 8);
-
-	/* IDTR */
-	saved_state[SMRAM_FIELD_AMD_K_IDTR_BASE] = idt.base;
-	saved_state[SMRAM_FIELD_AMD_K_IDTR_LIMIT] = idt.limit;
-
-	/* GDTR */
-	saved_state[SMRAM_FIELD_AMD_K_GDTR_BASE] = gdt.base;
-	saved_state[SMRAM_FIELD_AMD_K_GDTR_LIMIT] = gdt.limit;
-
-	/* ES */
-	saved_state[SMRAM_FIELD_AMD_K_ES_SELECTOR] = cpu_state.seg_es.seg;
-	saved_state[SMRAM_FIELD_AMD_K_ES_BASE] = cpu_state.seg_es.base;
-	saved_state[SMRAM_FIELD_AMD_K_ES_LIMIT] = cpu_state.seg_es.limit;
-	saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] = (cpu_state.seg_es.ar_high << 16) | (cpu_state.seg_es.access << 8);
-
-	/* CS */
-	saved_state[SMRAM_FIELD_AMD_K_CS_SELECTOR] = cpu_state.seg_cs.seg;
-	saved_state[SMRAM_FIELD_AMD_K_CS_BASE] = cpu_state.seg_cs.base;
-	saved_state[SMRAM_FIELD_AMD_K_CS_LIMIT] = cpu_state.seg_cs.limit;
-	saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] = (cpu_state.seg_cs.ar_high << 16) | (cpu_state.seg_cs.access << 8);
-
-	/* DS */
-	saved_state[SMRAM_FIELD_AMD_K_DS_SELECTOR] = cpu_state.seg_ds.seg;
-	saved_state[SMRAM_FIELD_AMD_K_DS_BASE] = cpu_state.seg_ds.base;
-	saved_state[SMRAM_FIELD_AMD_K_DS_LIMIT] = cpu_state.seg_ds.limit;
-	saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] = (cpu_state.seg_ds.ar_high << 16) | (cpu_state.seg_ds.access << 8);
-
-	/* SS */
-	saved_state[SMRAM_FIELD_AMD_K_SS_SELECTOR] = cpu_state.seg_ss.seg;
-	saved_state[SMRAM_FIELD_AMD_K_SS_BASE] = cpu_state.seg_ss.base;
-	saved_state[SMRAM_FIELD_AMD_K_SS_LIMIT] = cpu_state.seg_ss.limit;
-	saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] = (cpu_state.seg_ss.ar_high << 16) | (cpu_state.seg_ss.access << 8);
-
-	/* FS */
-	saved_state[SMRAM_FIELD_AMD_K_FS_SELECTOR] = cpu_state.seg_fs.seg;
-	saved_state[SMRAM_FIELD_AMD_K_FS_BASE] = cpu_state.seg_fs.base;
-	saved_state[SMRAM_FIELD_AMD_K_FS_LIMIT] = cpu_state.seg_fs.limit;
-	saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] = (cpu_state.seg_fs.ar_high << 16) | (cpu_state.seg_fs.access << 8);
-
-	/* GS */
-	saved_state[SMRAM_FIELD_AMD_K_GS_SELECTOR] = cpu_state.seg_gs.seg;
-	saved_state[SMRAM_FIELD_AMD_K_GS_BASE] = cpu_state.seg_gs.base;
-	saved_state[SMRAM_FIELD_AMD_K_GS_LIMIT] = cpu_state.seg_gs.limit;
-	saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] = (cpu_state.seg_gs.ar_high << 16) | (cpu_state.seg_gs.access << 8);
-}
-
-
-void smram_restore_state_amd_k(uint32_t *saved_state)
-{
-	int n = 0;
-
-	for (n = 0; n < 8; n++)
-		cpu_state.regs[n].l = saved_state[SMRAM_FIELD_AMD_K_EAX - n];
-
-	if (saved_state[SMRAM_FIELD_AMD_K_AUTOHALT_RESTART] & 0xffff)
-		cpu_state.pc = saved_state[SMRAM_FIELD_AMD_K_EIP] - 1;
-	else
-		cpu_state.pc = saved_state[SMRAM_FIELD_AMD_K_EIP];
-
-	cpu_state.eflags = saved_state[SMRAM_FIELD_AMD_K_EFLAGS] >> 16;
-	cpu_state.flags = saved_state[SMRAM_FIELD_AMD_K_EFLAGS] & 0xffff;
-
-	cr0 = saved_state[SMRAM_FIELD_AMD_K_CR0];
-	cr2 = saved_state[SMRAM_FIELD_AMD_K_CR2];
-	cr3 = saved_state[SMRAM_FIELD_AMD_K_CR3];
-	cr4 = saved_state[SMRAM_FIELD_AMD_K_CR4];
-	dr[6] = saved_state[SMRAM_FIELD_AMD_K_DR6];
-	dr[7] = saved_state[SMRAM_FIELD_AMD_K_DR7];
-
-	/* TR */
-	tr.seg = saved_state[SMRAM_FIELD_AMD_K_TR_SELECTOR];
-	tr.base = saved_state[SMRAM_FIELD_AMD_K_TR_BASE];
-	tr.limit = saved_state[SMRAM_FIELD_AMD_K_TR_LIMIT];
-	tr.access = (saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] >> 8) & 0xff;
-	tr.ar_high = (saved_state[SMRAM_FIELD_AMD_K_TR_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&tr);
-
-	/* LDTR */
-	ldt.seg = saved_state[SMRAM_FIELD_AMD_K_LDTR_SELECTOR];
-	ldt.base = saved_state[SMRAM_FIELD_AMD_K_LDTR_BASE];
-	ldt.limit = saved_state[SMRAM_FIELD_AMD_K_LDTR_LIMIT];
-	if (!is_k6) {
-		ldt.access = (saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] >> 8) & 0xff;
-		ldt.ar_high = (saved_state[SMRAM_FIELD_AMD_K_LDTR_ACCESS] >> 16) & 0xff;
-	}
-	smm_seg_load(&ldt);
-
-	/* IDTR */
-	idt.base = saved_state[SMRAM_FIELD_AMD_K_IDTR_BASE];
-	idt.limit = saved_state[SMRAM_FIELD_AMD_K_IDTR_LIMIT];
-
-	/* GDTR */
-	gdt.base = saved_state[SMRAM_FIELD_AMD_K_GDTR_BASE];
-	gdt.limit = saved_state[SMRAM_FIELD_AMD_K_GDTR_LIMIT];
-
-	/* ES */
-	cpu_state.seg_es.seg = saved_state[SMRAM_FIELD_AMD_K_ES_SELECTOR];
-	cpu_state.seg_es.base = saved_state[SMRAM_FIELD_AMD_K_ES_BASE];
-	cpu_state.seg_es.limit = saved_state[SMRAM_FIELD_AMD_K_ES_LIMIT];
-	cpu_state.seg_es.access = (saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_es.ar_high = (saved_state[SMRAM_FIELD_AMD_K_ES_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_es);
-
-	/* CS */
-	cpu_state.seg_cs.seg = saved_state[SMRAM_FIELD_AMD_K_CS_SELECTOR];
-	cpu_state.seg_cs.base = saved_state[SMRAM_FIELD_AMD_K_CS_BASE];
-	cpu_state.seg_cs.limit = saved_state[SMRAM_FIELD_AMD_K_CS_LIMIT];
-	cpu_state.seg_cs.access = (saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_cs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_CS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_cs);
-
-	/* DS */
-	cpu_state.seg_ds.seg = saved_state[SMRAM_FIELD_AMD_K_DS_SELECTOR];
-	cpu_state.seg_ds.base = saved_state[SMRAM_FIELD_AMD_K_DS_BASE];
-	cpu_state.seg_ds.limit = saved_state[SMRAM_FIELD_AMD_K_DS_LIMIT];
-	cpu_state.seg_ds.access = (saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_ds.ar_high = (saved_state[SMRAM_FIELD_AMD_K_DS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_ds);
-
-	/* SS */
-	cpu_state.seg_ss.seg = saved_state[SMRAM_FIELD_AMD_K_SS_SELECTOR];
-	cpu_state.seg_ss.base = saved_state[SMRAM_FIELD_AMD_K_SS_BASE];
-	cpu_state.seg_ss.limit = saved_state[SMRAM_FIELD_AMD_K_SS_LIMIT];
-	cpu_state.seg_ss.access = (saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] >> 8) & 0xff;
-	/* The actual CPL (DPL of CS) is overwritten with DPL of SS. */
-	cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~0x60) | (cpu_state.seg_ss.access & 0x60);
-	cpu_state.seg_ss.ar_high = (saved_state[SMRAM_FIELD_AMD_K_SS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_ss);
-
-	/* FS */
-	cpu_state.seg_fs.seg = saved_state[SMRAM_FIELD_AMD_K_FS_SELECTOR];
-	cpu_state.seg_fs.base = saved_state[SMRAM_FIELD_AMD_K_FS_BASE];
-	cpu_state.seg_fs.limit = saved_state[SMRAM_FIELD_AMD_K_FS_LIMIT];
-	cpu_state.seg_fs.access = (saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_fs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_FS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_fs);
-
-	/* GS */
-	cpu_state.seg_gs.seg = saved_state[SMRAM_FIELD_AMD_K_GS_SELECTOR];
-	cpu_state.seg_gs.base = saved_state[SMRAM_FIELD_AMD_K_GS_BASE];
-	cpu_state.seg_gs.limit = saved_state[SMRAM_FIELD_AMD_K_GS_LIMIT];
-	cpu_state.seg_gs.access = (saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] >> 8) & 0xff;
-	cpu_state.seg_gs.ar_high = (saved_state[SMRAM_FIELD_AMD_K_GS_ACCESS] >> 16) & 0xff;
-	smm_seg_load(&cpu_state.seg_gs);
-
-	if (SMM_REVISION_ID & SMM_SMBASE_RELOCATION)
-		smbase = saved_state[SMRAM_FIELD_AMD_K_SMBASE_OFFSET];
-}
-
-
-void enter_smm()
-{
-	uint32_t saved_state[SMM_SAVE_STATE_MAP_SIZE], n;
-	uint32_t smram_state = smbase + 0x10000;
-
-	/* If it's a CPU on which SMM is not supporter, do nothing. */
-	if (!is_pentium && !is_k5 && !is_k6 && !is_p6)
-		return;
-
-	x386_dynarec_log("enter_smm(): smbase = %08X\n", smbase);
-	x386_dynarec_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,
-		cpu_state.seg_cs.limit_high, cpu_state.seg_cs.access, cpu_state.seg_cs.ar_high);
-	x386_dynarec_log("DS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_ds.seg, cpu_state.seg_ds.base, cpu_state.seg_ds.limit, cpu_state.seg_ds.limit_low,
-		cpu_state.seg_ds.limit_high, cpu_state.seg_ds.access, cpu_state.seg_ds.ar_high);
-	x386_dynarec_log("ES : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_es.seg, cpu_state.seg_es.base, cpu_state.seg_es.limit, cpu_state.seg_es.limit_low,
-		cpu_state.seg_es.limit_high, cpu_state.seg_es.access, cpu_state.seg_es.ar_high);
-	x386_dynarec_log("FS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_fs.seg, cpu_state.seg_fs.base, cpu_state.seg_fs.limit, cpu_state.seg_fs.limit_low,
-		cpu_state.seg_fs.limit_high, cpu_state.seg_fs.access, cpu_state.seg_fs.ar_high);
-	x386_dynarec_log("GS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_gs.seg, cpu_state.seg_gs.base, cpu_state.seg_gs.limit, cpu_state.seg_gs.limit_low,
-		cpu_state.seg_gs.limit_high, cpu_state.seg_gs.access, cpu_state.seg_gs.ar_high);
-	x386_dynarec_log("SS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_ss.seg, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low,
-		cpu_state.seg_ss.limit_high, cpu_state.seg_ss.access, cpu_state.seg_ss.ar_high);
-	x386_dynarec_log("TR : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		tr.seg, tr.base, tr.limit, tr.limit_low, tr.limit_high, tr.access, tr.ar_high);
-	x386_dynarec_log("LDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		ldt.seg, ldt.base, ldt.limit, ldt.limit_low, ldt.limit_high, ldt.access, ldt.ar_high);
-	x386_dynarec_log("GDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		gdt.seg, gdt.base, gdt.limit, gdt.limit_low, gdt.limit_high, gdt.access, gdt.ar_high);
-	x386_dynarec_log("IDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		idt.seg, idt.base, idt.limit, idt.limit_low, idt.limit_high, idt.access, idt.ar_high);
-	x386_dynarec_log("CR0 = %08X, CR3 = %08X, CR4 = %08X, DR6 = %08X, DR7 = %08X\n", cr0, cr3, cr4, dr[6], dr[7]);
-	x386_dynarec_log("EIP = %08X, EFLAGS = %04X%04X\n", cpu_state.pc, cpu_state.eflags, cpu_state.flags);
-	x386_dynarec_log("EAX = %08X, EBX = %08X, ECX = %08X, EDX = %08X, ESI = %08X, EDI = %08X, ESP = %08X, EBP = %08X\n",
-		EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP);
-
-	in_smm = 1;
-	mem_mapping_recalc(0x00030000, 0x00020000);
-	mem_mapping_recalc(0x000a0000, 0x00060000);
-	if (!cpu_16bitbus)
-		mem_mapping_recalc(0x100a0000, 0x00060000);
-	if (mem_size >= 1024)
-		mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20));
-	flushmmucache();
-
-	memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
-	if (is_pentium)			/* Intel P5 (Pentium) */
-		smram_save_state_p5(saved_state);
-	else if (is_k5 || is_k6)	/* AMD K5 and K6 */
-		smram_save_state_amd_k(saved_state);
-	else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
-		smram_save_state_p6(saved_state);
-	for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
-		smram_state -= 4;
-		mem_writel_phys(smram_state, saved_state[n]);
-	}
-
-	cr0 &= ~0x8000000d;
-	cpu_state.flags = 2;
-	cpu_state.eflags = 0;
-
-	cr4 = 0;
-	dr[7] = 0x400;
-	cpu_state.pc = 0x8000;
-
-	cpu_state.seg_ds.seg = 0x00000000;
-	cpu_state.seg_ds.base = 0x00000000;
-	cpu_state.seg_ds.limit = 0xffffffff;
-	cpu_state.seg_ds.access = 0x93;
-	cpu_state.seg_ds.ar_high = 0x80;
-
-	memcpy(&cpu_state.seg_es, &cpu_state.seg_ds, sizeof(x86seg));
-	memcpy(&cpu_state.seg_ss, &cpu_state.seg_ds, sizeof(x86seg));
-	memcpy(&cpu_state.seg_fs, &cpu_state.seg_ds, sizeof(x86seg));
-	memcpy(&cpu_state.seg_gs, &cpu_state.seg_ds, sizeof(x86seg));
-
-	if (is_p6)
-		cpu_state.seg_cs.seg = (smbase >> 4);
-	else
-		cpu_state.seg_cs.seg = 0x3000;
-		/* On Pentium, CS selector in SMM is always 3000, regardless of SMBASE. */
-	cpu_state.seg_cs.base = smbase;
-	cpu_state.seg_cs.limit = 0xffffffff;
-	cpu_state.seg_cs.access = 0x93;
-	cpu_state.seg_cs.ar_high = 0x80;
-	cpu_state.seg_cs.checked = 1;
-
-	smm_seg_load(&cpu_state.seg_es);
-	smm_seg_load(&cpu_state.seg_cs);
-	smm_seg_load(&cpu_state.seg_ds);
-	smm_seg_load(&cpu_state.seg_ss);
-	smm_seg_load(&cpu_state.seg_fs);
-	smm_seg_load(&cpu_state.seg_gs);
-
-	cpu_state.op32 = use32;
-
-	nmi_mask = 0;
-
-	if (smi_latched) {
-		in_smm = 2;
-		smi_latched = 0;
-	} else
-		in_smm = 1;
-
-	CPU_BLOCK_END();
-}
-
-
-void leave_smm()
-{
-	uint32_t saved_state[SMM_SAVE_STATE_MAP_SIZE], n;
-	uint32_t smram_state = smbase + 0x10000;
-
-	/* If it's a CPU on which SMM is not supporter, do nothing. */
-	if (!is_pentium && !is_k5 && !is_k6 && !is_p6)
-		return;
-
-	memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
-	for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
-		smram_state -= 4;
-		saved_state[n] = mem_readl_phys(smram_state);
-		x386_dynarec_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
-	}
-#ifdef ENABLE_386_DYNAREC_LOG
-	for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
-		if (saved_state[n] == 0x000a0000)
-			x86_dynarec_log("SMBASE found in array element %i (we have %i)\n", n, SMRAM_FIELD_P5_SMBASE_OFFSET);
-	}
-#endif
-	x386_dynarec_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
-	if (is_pentium)			/* Intel P5 (Pentium) */
-		smram_restore_state_p5(saved_state);
-	else if (is_k5 || is_k6)	/* AMD K5 and K6 */
-		smram_restore_state_amd_k(saved_state);
-	else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
-		smram_restore_state_p6(saved_state);
-
-	in_smm = 0;
-	mem_mapping_recalc(0x00030000, 0x00020000);
-	mem_mapping_recalc(0x000a0000, 0x00060000);
-	if (!cpu_16bitbus)
-		mem_mapping_recalc(0x100a0000, 0x00060000);
-	if (mem_size >= 1024)
-		mem_mapping_recalc((mem_size << 10) - (1 << 20), (1 << 20));
-	flushmmucache();
-
-	cpu_state.op32 = use32;
-
-	nmi_mask = 1;
-
-	CPU_BLOCK_END();
-
-	x386_dynarec_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,
-		cpu_state.seg_cs.limit_high, cpu_state.seg_cs.access, cpu_state.seg_cs.ar_high);
-	x386_dynarec_log("DS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_ds.seg, cpu_state.seg_ds.base, cpu_state.seg_ds.limit, cpu_state.seg_ds.limit_low,
-		cpu_state.seg_ds.limit_high, cpu_state.seg_ds.access, cpu_state.seg_ds.ar_high);
-	x386_dynarec_log("ES : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_es.seg, cpu_state.seg_es.base, cpu_state.seg_es.limit, cpu_state.seg_es.limit_low,
-		cpu_state.seg_es.limit_high, cpu_state.seg_es.access, cpu_state.seg_es.ar_high);
-	x386_dynarec_log("FS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_fs.seg, cpu_state.seg_fs.base, cpu_state.seg_fs.limit, cpu_state.seg_fs.limit_low,
-		cpu_state.seg_fs.limit_high, cpu_state.seg_fs.access, cpu_state.seg_fs.ar_high);
-	x386_dynarec_log("GS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_gs.seg, cpu_state.seg_gs.base, cpu_state.seg_gs.limit, cpu_state.seg_gs.limit_low,
-		cpu_state.seg_gs.limit_high, cpu_state.seg_gs.access, cpu_state.seg_gs.ar_high);
-	x386_dynarec_log("SS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		cpu_state.seg_ss.seg, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low,
-		cpu_state.seg_ss.limit_high, cpu_state.seg_ss.access, cpu_state.seg_ss.ar_high);
-	x386_dynarec_log("TR : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		tr.seg, tr.base, tr.limit, tr.limit_low, tr.limit_high, tr.access, tr.ar_high);
-	x386_dynarec_log("LDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		ldt.seg, ldt.base, ldt.limit, ldt.limit_low, ldt.limit_high, ldt.access, ldt.ar_high);
-	x386_dynarec_log("GDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		gdt.seg, gdt.base, gdt.limit, gdt.limit_low, gdt.limit_high, gdt.access, gdt.ar_high);
-	x386_dynarec_log("IDT: seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
-		idt.seg, idt.base, idt.limit, idt.limit_low, idt.limit_high, idt.access, idt.ar_high);
-	x386_dynarec_log("CR0 = %08X, CR3 = %08X, CR4 = %08X, DR6 = %08X, DR7 = %08X\n", cr0, cr3, cr4, dr[6], dr[7]);
-	x386_dynarec_log("EIP = %08X, EFLAGS = %04X%04X\n", cpu_state.pc, cpu_state.eflags, cpu_state.flags);
-	x386_dynarec_log("EAX = %08X, EBX = %08X, ECX = %08X, EDX = %08X, ESI = %08X, EDI = %08X, ESP = %08X, EBP = %08X\n",
-		EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP);
-	x386_dynarec_log("leave_smm()\n");
-}
-
-
 #define OP_TABLE(name) ops_ ## name
-#define CLOCK_CYCLES(c) do { cycles -= (c); in_hlt = 0; } while(0)
-#define CLOCK_CYCLES_ALWAYS(c) do { cycles -= (c); in_hlt = 0; } while(0)
+#define CLOCK_CYCLES(c) cycles -= (c)
+#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
 
 #include "386_ops.h"
 
@@ -1380,13 +322,14 @@ void exec386_dynarec(int cycs)
 
 					cpu_state.ea_seg = &cpu_state.seg_ds;
 					cpu_state.ssegs = 0;
-		
+
 					fetchdat = fastreadl(cs + cpu_state.pc);
 
 					if (!cpu_state.abrt)
 					{
 						opcode = fetchdat & 0xFF;
 						fetchdat >>= 8;
+
 						trap = cpu_state.flags & T_FLAG;
 
 						cpu_state.pc++;
@@ -1400,17 +343,17 @@ void exec386_dynarec(int cycs)
 					if (((cs + cpu_state.pc) >> 12) != pccache)
 						CPU_BLOCK_END();
 
-					if ((in_smm == 0) && smi_line)
-						CPU_BLOCK_END();
-
 					if (cpu_state.abrt)
 						CPU_BLOCK_END();
 					if (trap)
 						CPU_BLOCK_END();
-
-					if (nmi && nmi_enable && nmi_mask)
+					else if (smi_line)
 						CPU_BLOCK_END();
-					
+					else if (nmi && nmi_enable && nmi_mask)
+						CPU_BLOCK_END();
+					else if ((cpu_state.flags & I_FLAG) && pic_intpending)
+						CPU_BLOCK_END();
+
 					ins++;
 				}
 			}
@@ -1629,21 +572,20 @@ void exec386_dynarec(int cycs)
 #endif
 							CPU_BLOCK_END();
 						
-						if ((in_smm == 0) && smi_line)
-							CPU_BLOCK_END();
-
-						if (trap)
-							CPU_BLOCK_END();
-
-						if (nmi && nmi_enable && nmi_mask)
-							CPU_BLOCK_END();
-
 						if (cpu_state.abrt)
 						{
 							codegen_block_remove();
 							CPU_BLOCK_END();
 						}
 
+						if (trap)
+							CPU_BLOCK_END();
+						else if (smi_line)
+							CPU_BLOCK_END();
+						else if (nmi && nmi_enable && nmi_mask)
+							CPU_BLOCK_END();
+						else if ((cpu_state.flags & I_FLAG) && pic_intpending)
+							CPU_BLOCK_END();
 						ins++;
 					}
 			
@@ -1683,6 +625,7 @@ void exec386_dynarec(int cycs)
 						cpu_state.ssegs = 0;
 		
 						codegen_endpc = (cs + cpu_state.pc) + 8;
+
 						fetchdat = fastreadl(cs + cpu_state.pc);
 
 						if (!cpu_state.abrt)
@@ -1715,21 +658,21 @@ void exec386_dynarec(int cycs)
 #endif
 							CPU_BLOCK_END();
 
-						if ((in_smm == 0) && smi_line)
-							CPU_BLOCK_END();
-
-						if (trap)
-							CPU_BLOCK_END();
-
-						if (nmi && nmi_enable && nmi_mask)
-							CPU_BLOCK_END();
-
 						if (cpu_state.abrt)
 						{
 							codegen_block_remove();
 							CPU_BLOCK_END();
 						}
 
+						if (trap)
+							CPU_BLOCK_END();
+						else if (smi_line)
+							CPU_BLOCK_END();
+						else if (nmi && nmi_enable && nmi_mask)
+							CPU_BLOCK_END();
+						else if ((cpu_state.flags & I_FLAG) && pic_intpending)
+							CPU_BLOCK_END();
+
 						ins++;
 					}
 			
@@ -1774,27 +717,8 @@ void exec386_dynarec(int cycs)
 				}
 			}
 
-			if ((in_smm == 0) && smi_line) {
-#ifdef ENABLE_386_DYNAREC_LOG
-				x386_dynarec_log("SMI while not in SMM\n");
-#endif
-				enter_smm();
-				smi_line = 0;
-			} else if ((in_smm == 1) && smi_line) {
-				/* Mark this so that we don't latch more than one SMI. */
-#ifdef ENABLE_386_DYNAREC_LOG
-				x386_dynarec_log("SMI while in unlatched SMM\n");
-#endif
-				smi_latched = 1;
-				smi_line = 0;
-			} else if ((in_smm == 2) && smi_line) {
-				/* Mark this so that we don't latch more than one SMI. */
-#ifdef ENABLE_386_DYNAREC_LOG
-				x386_dynarec_log("SMI while in latched SMM\n");
-#endif
-				smi_line = 0;
-			}
-
+			if (smi_line)
+				enter_smm_check(0);
 			else if (trap)
 			{
 #ifdef USE_NEW_DYNAREC
@@ -1820,10 +744,11 @@ void exec386_dynarec(int cycs)
 			}
 			else if (nmi && nmi_enable && nmi_mask)
 			{
-				cpu_state.oldpc = cpu_state.pc;
+				CPU_BLOCK_END();
 #ifndef USE_NEW_DYNAREC
 				oldcs = CS;
 #endif
+				cpu_state.oldpc = cpu_state.pc;
 				x86_int(2);
 				nmi_enable = 0;
 				if (nmi_auto_clear)
@@ -1837,7 +762,6 @@ void exec386_dynarec(int cycs)
 				vector = picinterrupt();
 				if (vector != -1)
 				{
-					CPU_BLOCK_END();
 					flags_rebuild();
 					if (msw&1)
 					{
diff --git a/src/cpu_common/386_dynarec_ops.c b/src/cpu_common/386_dynarec_ops.c
index 4fc9a13af..626a8381e 100644
--- a/src/cpu_common/386_dynarec_ops.c
+++ b/src/cpu_common/386_dynarec_ops.c
@@ -26,6 +26,8 @@
 #include "386_common.h"
 
 
+#define SYSENTER_LOG 1
+
 static __inline void fetch_ea_32_long(uint32_t rmdat)
 {
         eal_r = eal_w = NULL;
@@ -66,7 +68,7 @@ static __inline void fetch_ea_16_long(uint32_t rmdat)
 
 #define OP_TABLE(name) dynarec_ops_ ## name
 
-#define CLOCK_CYCLES(c) in_hlt = 0
-#define CLOCK_CYCLES_ALWAYS(c) do { cycles -= (c); in_hlt = 0; } while(0)
+#define CLOCK_CYCLES(c)
+#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
 
 #include "386_ops.h"
diff --git a/src/cpu_common/386_ops.h b/src/cpu_common/386_ops.h
index a351689ca..f7c6e64d2 100644
--- a/src/cpu_common/386_ops.h
+++ b/src/cpu_common/386_ops.h
@@ -167,14 +167,6 @@ static int ILLEGAL(uint32_t fetchdat)
         return 0;
 }
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_AMD_K) || defined(USE_I686)))
-static int internal_illegal(char *s)
-{
-	cpu_state.pc = cpu_state.oldpc;
-	x86gpf(s, 0);
-	return cpu_state.abrt;
-}
-#endif
 
 #ifdef ENABLE_386_DYNAREC_LOG
 extern void	x386_dynarec_log(const char *fmt, ...);
@@ -224,9 +216,7 @@ extern void	x386_dynarec_log(const char *fmt, ...);
 #include "x86_ops_xchg.h"
 #include "x86_ops_call.h"
 #include "x86_ops_shift.h"
-#ifdef USE_NEW_DYNAREC
 #include "x86_ops_amd.h"
-#endif
 #include "x86_ops_3dnow.h"
 
 
@@ -909,7 +899,6 @@ const OpFn OP_TABLE(pentiummmx_0f)[1024] =
 /*f0*/  ILLEGAL,        opPSLLW_a32,    opPSLLD_a32,    opPSLLQ_a32,    ILLEGAL,        opPMADDWD_a32,  ILLEGAL,        ILLEGAL,        opPSUBB_a32,    opPSUBW_a32,    opPSUBD_a32,    ILLEGAL,        opPADDB_a32,    opPADDW_a32,    opPADDD_a32,    ILLEGAL,
 };
 
-#ifdef USE_NEW_DYNAREC
 const OpFn OP_TABLE(k6_0f)[1024] = 
 {
         /*16-bit data, 16-bit addr*/
@@ -1091,9 +1080,8 @@ const OpFn OP_TABLE(k62_0f)[1024] =
 /*e0*/  ILLEGAL,        opPSRAW_a32,    opPSRAD_a32,    ILLEGAL,        ILLEGAL,        opPMULHW_a32,   ILLEGAL,        ILLEGAL,        opPSUBSB_a32,   opPSUBSW_a32,   NULL,           opPOR_a32,      opPADDSB_a32,   opPADDSW_a32,   NULL,           opPXOR_a32,
 /*f0*/  ILLEGAL,        opPSLLW_a32,    opPSLLD_a32,    opPSLLQ_a32,    ILLEGAL,        opPMADDWD_a32,  ILLEGAL,        ILLEGAL,        opPSUBB_a32,    opPSUBW_a32,    opPSUBD_a32,    ILLEGAL,        opPADDB_a32,    opPADDW_a32,    opPADDD_a32,    ILLEGAL,
 };
-#endif
 
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
 const OpFn OP_TABLE(c6x86mx_0f)[1024] = 
 {
         /*16-bit data, 16-bit addr*/
diff --git a/src/cpu_common/808x.c b/src/cpu_common/808x.c
index ee805d30b..d3a576172 100644
--- a/src/cpu_common/808x.c
+++ b/src/cpu_common/808x.c
@@ -972,10 +972,11 @@ reset_common(int hard)
     cpu_alu_op = 0;
 
     in_smm = smi_latched = 0;
-    smi_line = in_hlt = 0;
+    smi_line = smm_in_hlt = 0;
 
     if (hard)
 	smbase = 0x00030000;
+    in_sys = 0;
 }
 
 
diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c
index f74e953af..e16e5f3f3 100644
--- a/src/cpu_common/cpu.c
+++ b/src/cpu_common/cpu.c
@@ -71,6 +71,7 @@ enum {
         CPUID_PSE = (1 << 3),
         CPUID_TSC = (1 << 4),
         CPUID_MSR = (1 << 5),
+        CPUID_PAE = (1 << 6),
         CPUID_CMPXCHG8B = (1 << 8),
 	CPUID_AMDSEP = (1 << 10),
 	CPUID_SEP = (1 << 11),
@@ -108,10 +109,8 @@ const OpFn	*x86_dynarec_opcodes_df_a16;
 const OpFn	*x86_dynarec_opcodes_df_a32;
 const OpFn	*x86_dynarec_opcodes_REPE;
 const OpFn	*x86_dynarec_opcodes_REPNE;
-#ifdef USE_NEW_DYNAREC
 const OpFn	*x86_dynarec_opcodes_3DNOW;
 #endif
-#endif
 
 const OpFn	*x86_opcodes;
 const OpFn	*x86_opcodes_0f;
@@ -135,7 +134,7 @@ const OpFn	*x86_opcodes_REPE;
 const OpFn	*x86_opcodes_REPNE;
 const OpFn	*x86_opcodes_3DNOW;
 
-int in_smm = 0, smi_line = 0, smi_latched = 0, in_hlt = 0;
+int in_smm = 0, smi_line = 0, smi_latched = 0, smm_in_hlt = 0;
 uint32_t smbase = 0x30000;
 
 CPU		*cpu_s;
@@ -178,7 +177,7 @@ uint64_t	pmc[2] = {0, 0};
 
 uint16_t	temp_seg_data[4] = {0, 0, 0, 0};
 
-uint64_t	mtrr_cap_msr = 0;
+uint64_t	mtrr_cap_msr = 0x00000508;
 uint64_t	mtrr_physbase_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
 uint64_t	mtrr_physmask_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
 uint64_t	mtrr_fix64k_8000_msr = 0;
@@ -206,21 +205,13 @@ uint64_t	ecx1e0_msr = 0;
 uint64_t	ecx570_msr = 0;
 #endif
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
 uint64_t	ecx83_msr = 0;			/* AMD K5 and K6 MSR's. */
-#ifdef USE_NEW_DYNAREC
 uint64_t	star = 0;			/* AMD K6-2+. */
-#endif
 
-#ifdef USE_NEW_DYNAREC
 uint64_t	amd_efer = 0, amd_whcr = 0,
 		amd_uwccr = 0, amd_epmr = 0,	/* AMD K6-2+ registers. */
 		amd_psor = 0, amd_pfir = 0,
 		amd_l2aar = 0;
-#else
-uint64_t	amd_efer = 0, amd_whcr = 0;
-#endif
-#endif
 
 int		timing_rr;
 int		timing_mr, timing_mrl;
@@ -317,21 +308,15 @@ cpu_set(void)
         is486dx2     = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4);	
         isdx4        = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
         is_pentium   = (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
         is_k5        = (cpu_s->cpu_type == CPU_K5) || (cpu_s->cpu_type == CPU_5K86);
 #else
-        is_k5        = 0;
+	is_k5        = 0;
 #endif
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
         is_k6        = (cpu_s->cpu_type == CPU_K6);
-#else
-        is_k6        = 0;
-#endif
-#ifdef USE_NEW_DYNAREC
-	is_k6        = is_k6 || (cpu_s->cpu_type == CPU_K6_2) || (cpu_s->cpu_type == CPU_K6_2C) ||
-				(cpu_s->cpu_type == CPU_K6_3) || (cpu_s->cpu_type == CPU_K6_2P) ||
-				(cpu_s->cpu_type == CPU_K6_3P);
-#endif
+	is_k6        = (cpu_s->cpu_type == CPU_K6) || (cpu_s->cpu_type == CPU_K6_2) ||
+				(cpu_s->cpu_type == CPU_K6_2C) || (cpu_s->cpu_type == CPU_K6_3) ||
+				(cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P);
 #if defined(DEV_BRANCH) && defined(USE_I686)
         is_p6        = (cpu_s->cpu_type == CPU_PENTIUMPRO) || (cpu_s->cpu_type == CPU_PENTIUM2) ||
 		       (cpu_s->cpu_type == CPU_PENTIUM2D);
@@ -340,7 +325,7 @@ cpu_set(void)
 #endif
         hasfpu       = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD);
 	hascache     = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
         cpu_iscyrix  = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
 #else
         cpu_iscyrix  = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
@@ -402,10 +387,8 @@ cpu_set(void)
 #ifdef USE_DYNAREC
         x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
         x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
-#ifdef USE_NEW_DYNAREC
         x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOW;
 #endif
-#endif
 
 #ifdef USE_DYNAREC
         if (hasfpu)
@@ -965,7 +948,6 @@ cpu_set(void)
                 cpu_cyrix_alignment = 1;
                 break;
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_WINCHIP2:
 #ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
@@ -1009,7 +991,6 @@ cpu_set(void)
                 codegen_timing_set(&codegen_timing_winchip2);
 #endif		
                 break;
-#endif
 
                 case CPU_PENTIUM:
 #ifdef USE_DYNAREC
@@ -1097,7 +1078,7 @@ cpu_set(void)
 #endif
                 break;
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
   		case CPU_Cx6x86:
 #ifdef USE_DYNAREC
                 x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
@@ -1268,7 +1249,7 @@ cpu_set(void)
                 break;
 #endif
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
                 case CPU_K5:
                 case CPU_5K86:
 #ifdef USE_DYNAREC
@@ -1308,16 +1289,17 @@ cpu_set(void)
                 cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
-#if defined(USE_NEW_DYNAREC) && defined(USE_DYNAREC)
+#ifdef USE_DYNAREC
                 codegen_timing_set(&codegen_timing_k6);
 #endif
                 break;
+#endif
 
                 case CPU_K6:
 #ifdef USE_DYNAREC
-                x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
+                x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
 #else
-                x86_setopcodes(ops_386, ops_pentiummmx_0f);
+                x86_setopcodes(ops_386, ops_k6_0f);
 #endif
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 2; /*register dest - memory src*/
@@ -1352,16 +1334,10 @@ cpu_set(void)
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
 #ifdef USE_DYNAREC
-#ifdef USE_NEW_DYNAREC
                 codegen_timing_set(&codegen_timing_k6);
-#else
-                codegen_timing_set(&codegen_timing_pentium);
-#endif
 #endif
                 break;
-#endif
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_K6_2:
                 case CPU_K6_2C:
                 case CPU_K6_3:
@@ -1406,7 +1382,6 @@ cpu_set(void)
                 cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE;
                 codegen_timing_set(&codegen_timing_k6);
                 break;
-#endif
 
 #if defined(DEV_BRANCH) && defined(USE_I686)
                 case CPU_PENTIUMPRO:
@@ -1458,13 +1433,9 @@ cpu_set(void)
                 timing_misaligned = 3;
                 cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
-                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_PAE | CR4_MCE | CR4_PCE;
 #ifdef USE_DYNAREC
-#ifdef USE_NEW_DYNAREC
          	codegen_timing_set(&codegen_timing_p6);
-#else
-         	codegen_timing_set(&codegen_timing_686);
-#endif
 #endif
                 break;
 
@@ -1517,13 +1488,9 @@ cpu_set(void)
                 timing_misaligned = 3;
                 cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
-                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_PAE | CR4_MCE | CR4_PCE;
 #ifdef USE_DYNAREC
-#ifdef USE_NEW_DYNAREC
          	codegen_timing_set(&codegen_timing_p6);
-#else
-         	codegen_timing_set(&codegen_timing_686);
-#endif
 #endif
                 break;
 
@@ -1576,13 +1543,9 @@ cpu_set(void)
                 timing_misaligned = 3;
                 cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
-                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
+                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE | CR4_OSFXSR;
 #ifdef USE_DYNAREC
-#ifdef USE_NEW_DYNAREC
          	codegen_timing_set(&codegen_timing_p6);
-#else
-         	codegen_timing_set(&codegen_timing_686);
-#endif
 #endif
                 break;
 #endif
@@ -1763,7 +1726,6 @@ cpu_CPUID(void)
                    EAX = EBX = ECX = EDX = 0;
                 break;
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_WINCHIP2:
                 switch (EAX)
                 {
@@ -1823,7 +1785,6 @@ cpu_CPUID(void)
                         break;
                 }
                 break;
-#endif
 
                 case CPU_PENTIUM:
                 if (!EAX)
@@ -1843,7 +1804,7 @@ cpu_CPUID(void)
                         EAX = EBX = ECX = EDX = 0;
                 break;
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
                 case CPU_K5:
                 if (!EAX)
                 {
@@ -1913,6 +1874,7 @@ cpu_CPUID(void)
                 else
                         EAX = EBX = ECX = EDX = 0;
                 break;
+#endif
 
                 case CPU_K6:
                 if (!EAX)
@@ -1975,9 +1937,7 @@ cpu_CPUID(void)
                 else
                         EAX = EBX = ECX = EDX = 0;
                 break;
-#endif
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_K6_2:
                 case CPU_K6_2C:
                 switch (EAX)
@@ -1998,7 +1958,7 @@ cpu_CPUID(void)
                         break;
                         case 0x80000001:
                         EAX = CPUID+0x100;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
                         break;
 
                         case 0x80000002: /*Processor name string*/
@@ -2046,7 +2006,7 @@ cpu_CPUID(void)
                         break;
                         case 0x80000001:
                         EAX = CPUID+0x100;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
                         break;
 
                         case 0x80000002: /*Processor name string*/
@@ -2099,7 +2059,7 @@ cpu_CPUID(void)
                         break;
                         case 0x80000001:
                         EAX = CPUID+0x100;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
                         break;
 
                         case 0x80000002: /*Processor name string*/
@@ -2138,7 +2098,6 @@ cpu_CPUID(void)
                         break;
                 }
                 break;
-#endif
 
                 case CPU_PENTIUMMMX:
                 if (!EAX)
@@ -2159,7 +2118,7 @@ cpu_CPUID(void)
                 break;
 
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
                 case CPU_Cx6x86:
                 if (!EAX)
                 {
@@ -2251,7 +2210,7 @@ cpu_CPUID(void)
                 {
                         EAX = CPUID;
                         EBX = ECX = 0;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_SEP | CPUID_CMOV;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_CMOV;
                 }
 		else if (EAX == 2)
 		{
@@ -2272,7 +2231,7 @@ cpu_CPUID(void)
                 {
                         EAX = CPUID;
                         EBX = ECX = 0;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_CMOV;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_CMOV;
                 }
 		else if (EAX == 2)
 		{
@@ -2296,7 +2255,7 @@ cpu_CPUID(void)
                 {
                         EAX = CPUID;
                         EBX = ECX = 0;
-                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_FXSR | CPUID_CMOV;
                 }
 		else if (EAX == 2)
 		{
@@ -2366,15 +2325,15 @@ cpu_CPUID(void)
 
 void cpu_ven_reset(void)
 {
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
         switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
         {
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
                 case CPU_K5:
                 case CPU_5K86:
+#endif
                 case CPU_K6:
 			amd_efer = amd_whcr = 0ULL;
 			break;
-#ifdef USE_NEW_DYNAREC
 		case CPU_K6_2:
 			amd_efer = amd_whcr = 0ULL;
 			star = 0ULL;
@@ -2401,9 +2360,7 @@ void cpu_ven_reset(void)
 			amd_pfir = amd_l2aar = 0ULL;
 			amd_epmr = 0ULL;
 			break;
-#endif
 	}
-#endif
 }
 
 void cpu_RDMSR()
@@ -2412,9 +2369,7 @@ void cpu_RDMSR()
         switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
         {
                 case CPU_WINCHIP:
-#ifdef USE_NEW_DYNAREC
                 case CPU_WINCHIP2:
-#endif
                 EAX = EDX = 0;
                 switch (ECX)
                 {
@@ -2517,9 +2472,10 @@ void cpu_RDMSR()
                 }
                 break;
 		
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
                 case CPU_K5:
                 case CPU_5K86:
+#endif
                 case CPU_K6:
                 EAX = EDX = 0;
                 switch (ECX)
@@ -2548,9 +2504,7 @@ void cpu_RDMSR()
 			break;
                 }
                 break;
-#endif
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_K6_2:
                 EAX = EDX = 0;
                 switch (ECX)
@@ -2731,7 +2685,6 @@ void cpu_RDMSR()
 			break;
                 }
                 break;
-#endif
 
                 case CPU_PENTIUM:
                 case CPU_PENTIUMMMX:
@@ -2744,7 +2697,7 @@ void cpu_RDMSR()
 				break;
                 }
                 break;
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
                 case CPU_Cx6x86:
                 case CPU_Cx6x86L:
                 case CPU_CxGX1:
@@ -2779,6 +2732,7 @@ void cpu_RDMSR()
 			case 0x1B:
                         EAX = apic_base_msr & 0xffffffff;
                         EDX = apic_base_msr >> 32;
+			/* pclog("APIC_BASE read : %08X%08X\n", EDX, EAX); */
 			break;
 			case 0x2A:
 			EAX = 0xC5800000;
@@ -2892,17 +2846,13 @@ i686_invalid_rdmsr:
 
 void cpu_WRMSR()
 {
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
 	uint64_t temp;
-#endif
 
 	cpu_log("WRMSR %08X %08X%08X\n", ECX, EDX, EAX);
         switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
         {
                 case CPU_WINCHIP:
-#ifdef USE_NEW_DYNAREC
                 case CPU_WINCHIP2:
-#endif
                 switch (ECX)
                 {
                         case 0x02:
@@ -2927,12 +2877,10 @@ void cpu_WRMSR()
 				cpu_features |= CPU_FEATURE_CX8;
 			else
 				cpu_features &= ~CPU_FEATURE_CX8;
-#ifdef USE_NEW_DYNAREC
 			if ((EAX & (1 << 20)) && machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type >= CPU_WINCHIP2)
                                 cpu_features |= CPU_FEATURE_3DNOW;
 			else
                                 cpu_features &= ~CPU_FEATURE_3DNOW;
-#endif
                          if (EAX & (1 << 29))
                                  CPUID = 0;
                          else
@@ -2990,9 +2938,10 @@ void cpu_WRMSR()
                 }
                 break;
 		
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
                 case CPU_K5:
                 case CPU_5K86:
+#endif
                 case CPU_K6:
                 switch (ECX)
                 {
@@ -3020,9 +2969,7 @@ void cpu_WRMSR()
 			break;
                 }
                 break;
-#endif
 
-#ifdef USE_NEW_DYNAREC
                 case CPU_K6_2:
                 switch (ECX)
                 {
@@ -3183,7 +3130,6 @@ void cpu_WRMSR()
 			break;
                 }
                 break;
-#endif
 
                 case CPU_PENTIUM:
                 case CPU_PENTIUMMMX:
@@ -3194,7 +3140,7 @@ void cpu_WRMSR()
 				break;
                 }
                 break;
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
                 case CPU_Cx6x86:
                 case CPU_Cx6x86L:
                 case CPU_CxGX1:
@@ -3223,7 +3169,8 @@ void cpu_WRMSR()
 			ecx17_msr = EAX | ((uint64_t)EDX << 32);
 			break;
 			case 0x1B:
-			apic_base_msr = EAX | ((uint64_t)EDX << 32);
+			/* pclog("APIC_BASE write: %08X%08X\n", EDX, EAX); */
+			// apic_base_msr = EAX | ((uint64_t)EDX << 32);
 			break;
 			case 0x79:
 			ecx79_msr = EAX | ((uint64_t)EDX << 32);
@@ -3341,7 +3288,7 @@ static void cpu_write(uint16_t addr, uint8_t val, void *priv)
                 if ((ccr3 & 0xf0) == 0x10)
                 {
                         ccr4 = val;
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
                         if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_Cx6x86)
                         {
                                 if (val & 0x80)
diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h
index d626e2816..c471b1e75 100644
--- a/src/cpu_common/cpu.h
+++ b/src/cpu_common/cpu.h
@@ -53,9 +53,7 @@ enum {
     CPU_Am5x86,
     CPU_Cx5x86,
     CPU_WINCHIP,	/* 586 class CPUs */
-#ifdef USE_NEW_DYNAREC
     CPU_WINCHIP2,
-#endif
     CPU_PENTIUM,
     CPU_PENTIUMMMX,
 #if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
@@ -64,18 +62,16 @@ enum {
     CPU_Cx6x86L,
     CPU_CxGX1,
 #endif
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
     CPU_K5,
     CPU_5K86,
-    CPU_K6,
 #endif
-#ifdef USE_NEW_DYNAREC
+    CPU_K6,
     CPU_K6_2,
     CPU_K6_2C,
     CPU_K6_3,
     CPU_K6_2P,
     CPU_K6_3P,
-#endif
     CPU_CYRIX3S,
 #if defined(DEV_BRANCH) && defined(USE_I686)
     CPU_PENTIUMPRO,	/* 686 class CPUs */
@@ -131,28 +127,24 @@ extern CPU	cpus_i486[];
 extern CPU	cpus_Am486[];
 extern CPU	cpus_Cx486[];
 extern CPU	cpus_WinChip[];
-#ifdef USE_NEW_DYNAREC
 extern CPU	cpus_WinChip_SS7[];
-#endif
 extern CPU	cpus_Pentium5V[];
 extern CPU	cpus_Pentium5V50[];
 extern CPU	cpus_PentiumS5[];
 extern CPU	cpus_Pentium3V[];
 extern CPU	cpus_Pentium[];
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
 extern CPU	cpus_K5[];
+#endif
 extern CPU	cpus_K56[];
-#endif
-#ifdef USE_NEW_DYNAREC
 extern CPU	cpus_K56_SS7[];
-#endif
-#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
 extern CPU	cpus_6x863V[];
 extern CPU	cpus_6x86[];
-#endif
 #ifdef USE_NEW_DYNAREC
 extern CPU	cpus_6x86SS7[];
 #endif
+#endif
 extern CPU  cpus_Cyrix3[];
 #if defined(DEV_BRANCH) && defined(USE_I686)
 extern CPU	cpus_PentiumPro[];
@@ -172,14 +164,17 @@ extern CPU	cpus_Celeron[];
 #define V_FLAG		0x0800
 #define NT_FLAG		0x4000
 
+#define RF_FLAG		0x0001			/* in EFLAGS */
 #define VM_FLAG		0x0002			/* in EFLAGS */
 #define VIF_FLAG	0x0008			/* in EFLAGS */
 #define VIP_FLAG	0x0010			/* in EFLAGS */
+#define VID_FLAG	0x0020			/* in EFLAGS */
 
 #define WP_FLAG		0x10000			/* in CR0 */
 #define CR4_VME		(1 << 0)
 #define CR4_PVI		(1 << 1)
 #define CR4_PSE		(1 << 4)
+#define CR4_PAE		(1 << 5)
 
 #define CPL ((cpu_state.seg_cs.access>>5)&3)
 
@@ -400,7 +395,7 @@ extern int	hasfpu;
 
 extern uint32_t	cpu_features;
 
-extern int	in_smm, smi_line, smi_latched, in_hlt;
+extern int	in_smm, smi_line, smi_latched, smm_in_hlt;
 extern uint32_t	smbase;
 
 #ifdef USE_NEW_DYNAREC
@@ -486,6 +481,7 @@ extern int	timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
 extern int	timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
 extern int	timing_misaligned;
 
+extern int	in_sys;
 
 extern CPU	cpus_pcjr[];		// FIXME: should be in machine file!
 extern CPU	cpus_europc[];		// FIXME: should be in machine file!
@@ -526,8 +522,9 @@ extern void	codegen_reset(void);
 extern void	cpu_set_edx(void);
 extern int	divl(uint32_t val);
 extern void	execx86(int cycs);
-extern void	enter_smm();
-extern void	leave_smm();
+extern void	enter_smm(int in_hlt);
+extern void	enter_smm_check(int in_hlt);
+extern void	leave_smm(void);
 extern void	exec386(int cycs);
 extern void	exec386_dynarec(int cycs);
 extern int	idivl(int32_t val);
@@ -568,5 +565,10 @@ extern void	cpu_dynamic_switch(int new_cpu);
 
 extern void	cpu_ven_reset(void);
 
+extern int	sysenter(uint32_t fetchdat);
+extern int	sysexit(uint32_t fetchdat);
+extern int	syscall(uint32_t fetchdat);
+extern int	sysret(uint32_t fetchdat);
+
 
 #endif	/*EMU_CPU_H*/
diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c
index 2a63b44b5..326556317 100644
--- a/src/cpu_common/cpu_table.c
+++ b/src/cpu_common/cpu_table.c
@@ -259,199 +259,193 @@ CPU cpus_Am486S1[] = {
 };
 CPU cpus_Cx486S1[] = {
     /*Cyrix 486*/
-    {"Cx486S/25",    CPU_Cx486S,   25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
-    {"Cx486S/33",    CPU_Cx486S,   33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
-    {"Cx486S/40",    CPU_Cx486S,   40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
-    {"Cx486DX/33",   CPU_Cx486DX,  33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
-    {"Cx486DX/40",   CPU_Cx486DX,  40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
-    {"Cx486DX2/50",  CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
-    {"Cx486DX2/66",  CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
-    {"Cx486DX2/80",  CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
-    {"",             -1,                  0, 0,     0, 0,      0,                    0,  0, 0, 0, 0,  0}
+    {"Cx486S/25",            CPU_Cx486S,   25000000, 1.0,  0x420,      0, 0x0010, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
+    {"Cx486S/33",            CPU_Cx486S,   33333333, 1.0,  0x420,      0, 0x0010, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"Cx486S/40",            CPU_Cx486S,   40000000, 1.0,  0x420,      0, 0x0010, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
+    {"Cx486DX/33",          CPU_Cx486DX,   33333333, 1.0,  0x430,      0, 0x051a, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"Cx486DX/40",          CPU_Cx486DX,   40000000, 1.0,  0x430,      0, 0x051a, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
+    {"Cx486DX2/50",        CPU_Cx486DX2,   50000000, 2.0,  0x430,      0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
+    {"Cx486DX2/66",        CPU_Cx486DX2,   66666666, 2.0,  0x430,      0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
+    {"Cx486DX2/80",        CPU_Cx486DX2,   80000000, 2.0,  0x430,      0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+    {"",                             -1,          0, 0.0,      0,      0, 0x0000,                    0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_i486[] = {
     /*i486/P24T*/
-    {"i486SX/16",            CPU_i486SX,   16000000, 1,    0x420,       0, 0, CPU_SUPPORTS_DYNAREC,  3, 3,3,3,  2},
-    {"i486SX/20",            CPU_i486SX,   20000000, 1,    0x420,       0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
-    {"i486SX/25",            CPU_i486SX,   25000000, 1,    0x422,       0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
-    {"i486SX/33",            CPU_i486SX,   33333333, 1,    0x42a,       0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
-    {"i486SX2/50",           CPU_i486SX,   50000000, 2,    0x45b,       0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
-    {"i486SX2/66 (Q0569)",   CPU_i486SX,   66666666, 2,    0x45b,       0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  8},
-    {"i486DX/25",            CPU_i486DX,   25000000, 1,    0x404,       0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
-    {"i486DX/33",            CPU_i486DX,   33333333, 1,    0x414,       0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
-    {"i486DX/50",            CPU_i486DX,   50000000, 1,    0x411,       0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,4,4,  6},
-    {"i486DX2/40",           CPU_i486DX,   40000000, 2,    0x430,   0x430, 0, CPU_SUPPORTS_DYNAREC,  7, 7,6,6,  5},
-    {"i486DX2/50",           CPU_i486DX,   50000000, 2,    0x433,   0x433, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
-    {"i486DX2/66",           CPU_i486DX,   66666666, 2,    0x435,   0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
-    {"iDX4/75",              CPU_iDX4,     75000000, 3,    0x480,   0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9,  9}, /*CPUID available on DX4, >= 75 MHz*/
-    {"iDX4/100",             CPU_iDX4,    100000000, 3,    0x483,   0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
-    {"iDX4 OverDrive 75",    CPU_iDX4,     75000000, 3,   0x1480,  0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9,  9},
-    {"iDX4 OverDrive 100",   CPU_iDX4,    100000000, 3,   0x1480,  0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, 
-    {"Pentium OverDrive 63", CPU_PENTIUM,  62500000, 5/2, 0x1531,  0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
-    {"Pentium OverDrive 83", CPU_PENTIUM,  83333333, 5/2, 0x1532,  0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
-    {"",                     -1,                  0, 0,        0,       0, 0,                    0,  0, 0,0,0,  0}
+    {"i486SX/16",            CPU_i486SX,   16000000, 1.0,  0x420,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  3, 3, 3, 3,  2},
+    {"i486SX/20",            CPU_i486SX,   20000000, 1.0,  0x420,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
+    {"i486SX/25",            CPU_i486SX,   25000000, 1.0,  0x422,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
+    {"i486SX/33",            CPU_i486SX,   33333333, 1.0,  0x42a,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"i486SX2/50",           CPU_i486SX,   50000000, 2.0,  0x45b,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
+    {"i486SX2/66 (Q0569)",   CPU_i486SX,   66666666, 2.0,  0x45b,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  8},
+    {"i486DX/25",            CPU_i486DX,   25000000, 1.0,  0x404,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
+    {"i486DX/33",            CPU_i486DX,   33333333, 1.0,  0x414,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"i486DX/50",            CPU_i486DX,   50000000, 1.0,  0x411,      0, 0x0000, CPU_SUPPORTS_DYNAREC,  8, 8, 4, 4,  6},
+    {"i486DX2/40",           CPU_i486DX,   40000000, 2.0,  0x430,  0x430, 0x0000, CPU_SUPPORTS_DYNAREC,  7, 7, 6, 6,  5},
+    {"i486DX2/50",           CPU_i486DX,   50000000, 2.0,  0x433,  0x433, 0x0000, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
+    {"i486DX2/66",           CPU_i486DX,   66666666, 2.0,  0x435,  0x435, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
+    {"iDX4/75",              CPU_iDX4,     75000000, 3.0,  0x480,  0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9}, /*CPUID available on DX4, >= 75 MHz*/
+    {"iDX4/100",             CPU_iDX4,    100000000, 3.0,  0x483,  0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
+    {"iDX4 OverDrive 75",    CPU_iDX4,     75000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9},
+    {"iDX4 OverDrive 100",   CPU_iDX4,    100000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, 
+    {"Pentium OverDrive 63", CPU_PENTIUM,  62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
+    {"Pentium OverDrive 83", CPU_PENTIUM,  83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
+    {"",                     -1,                  0, 0,        0,      0, 0x0000,                    0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_Am486[] = {
     /*Am486/5x86*/
-    {"Am486SX/33",   CPU_Am486SX,   33333333, 1, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
-    {"Am486SX/40",   CPU_Am486SX,   40000000, 1, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5}, 
-    {"Am486SX2/50",  CPU_Am486SX2,  50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
-    {"Am486SX2/66",  CPU_Am486SX2,  66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
-    {"Am486DX/33",   CPU_Am486DX,   33333333, 1, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
-    {"Am486DX/40",   CPU_Am486DX,   40000000, 1, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
-    {"Am486DX2/50",  CPU_Am486DX2,  50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
-    {"Am486DX2/66",  CPU_Am486DX2,  66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
-    {"Am486DX2/80",  CPU_Am486DX2,  80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
-    {"Am486DX4/75",  CPU_Am486DX4,  75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
-    {"Am486DX4/90",  CPU_Am486DX4,  90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
-    {"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
-    {"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
-    {"Am5x86/P75",   CPU_Am5x86,   133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
-    {"Am5x86/P75+",  CPU_Am5x86,   150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
-    {"Am5x86/P90",   CPU_Am5x86,   160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ 
+    {"Am486SX/33",   CPU_Am486SX,   33333333, 1.0, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+    {"Am486SX/40",   CPU_Am486SX,   40000000, 1.0, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5}, 
+    {"Am486SX2/50",  CPU_Am486SX2,  50000000, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
+    {"Am486SX2/66",  CPU_Am486SX2,  66666666, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+    {"Am486DX/33",   CPU_Am486DX,   33333333, 1.0, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+    {"Am486DX/40",   CPU_Am486DX,   40000000, 1.0, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
+    {"Am486DX2/50",  CPU_Am486DX2,  50000000, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
+    {"Am486DX2/66",  CPU_Am486DX2,  66666666, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+    {"Am486DX2/80",  CPU_Am486DX2,  80000000, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+    {"Am486DX4/75",  CPU_Am486DX4,  75000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
+    {"Am486DX4/90",  CPU_Am486DX4,  90000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+    {"Am486DX4/100", CPU_Am486DX4, 100000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+    {"Am486DX4/120", CPU_Am486DX4, 120000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
+    {"Am5x86/P75",   CPU_Am5x86,   133333333, 4.0, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
+    {"Am5x86/P75+",  CPU_Am5x86,   150000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
+    {"Am5x86/P90",   CPU_Am5x86,   160000000, 4.0, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ 
     {"",             -1,                   0, 0,     0,     0, 0,                    0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_Cx486[] = {
     /*Cyrix 486*/
-    {"Cx486S/25",    CPU_Cx486S,    25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
-    {"Cx486S/33",    CPU_Cx486S,    33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
-    {"Cx486S/40",    CPU_Cx486S,    40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
-    {"Cx486DX/33",   CPU_Cx486DX,   33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
-    {"Cx486DX/40",   CPU_Cx486DX,   40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
-    {"Cx486DX2/50",  CPU_Cx486DX2,  50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
-    {"Cx486DX2/66",  CPU_Cx486DX2,  66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
-    {"Cx486DX2/80",  CPU_Cx486DX2,  80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
-    {"Cx486DX4/75",  CPU_Cx486DX4,  75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9},
-    {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+    {"Cx486S/25",    CPU_Cx486S,    25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  4, 4, 3, 3,  3},
+    {"Cx486S/33",    CPU_Cx486S,    33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"Cx486S/40",    CPU_Cx486S,    40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
+    {"Cx486DX/33",   CPU_Cx486DX,   33333333, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3,  4},
+    {"Cx486DX/40",   CPU_Cx486DX,   40000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3,  5},
+    {"Cx486DX2/50",  CPU_Cx486DX2,  50000000, 2.0, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
+    {"Cx486DX2/66",  CPU_Cx486DX2,  66666666, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
+    {"Cx486DX2/80",  CPU_Cx486DX2,  80000000, 2.0, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+    {"Cx486DX4/75",  CPU_Cx486DX4,  75000000, 3.0, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9},
+    {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3.0, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
 
     /*Cyrix 5x86*/
-    {"Cx5x86/80",    CPU_Cx5x86,    80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
-    {"Cx5x86/100",   CPU_Cx5x86,   100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
-    {"Cx5x86/120",   CPU_Cx5x86,   120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
-    {"Cx5x86/133",   CPU_Cx5x86,   133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
+    {"Cx5x86/80",    CPU_Cx5x86,    80000000, 2.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
+    {"Cx5x86/100",   CPU_Cx5x86,   100000000, 3.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+    {"Cx5x86/120",   CPU_Cx5x86,   120000000, 3.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
+    {"Cx5x86/133",   CPU_Cx5x86,   133333333, 4.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
     {"",             -1,                   0, 0,     0, 0,      0,                    0,  0, 0, 0, 0,  0}
 };
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
 CPU cpus_6x863V[] = {
     /*Cyrix 6x86*/
-    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
-    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
-    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
+    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
+    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
+    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
     {"",               -1,                   0, 0, 0,     0,     0,      0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_6x86[] = {
     /*Cyrix 6x86*/
-    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
-    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
-    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
+    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
+    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
+    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
 
     /*Cyrix 6x86L*/
-    {"Cx6x86L/PR133+", CPU_Cx6x86L,  110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
-    {"Cx6x86L/PR150+", CPU_Cx6x86L,  120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Cx6x86L/PR166+", CPU_Cx6x86L,  133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Cx6x86L/PR200+", CPU_Cx6x86L,  150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
+    {"Cx6x86L/PR133+", CPU_Cx6x86L,  110000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
+    {"Cx6x86L/PR150+", CPU_Cx6x86L,  120000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Cx6x86L/PR166+", CPU_Cx6x86L,  133333333, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Cx6x86L/PR200+", CPU_Cx6x86L,  150000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
 
     /*Cyrix 6x86MX/MII*/
-    {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2,   0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
-    {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
-    {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
-    {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7,   25},
-    {"MII/PR300",      CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11,   28},
-    {"MII/PR333",      CPU_Cx6x86MX, 250000000, 3,   0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9,   30},
+    {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2.0, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
+    {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
+    {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
+    {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7,   25},
+    {"MII/PR300",      CPU_Cx6x86MX, 233333333, 3.5, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11,   28},
+    {"MII/PR333",      CPU_Cx6x86MX, 250000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9,   30},
     {"",               -1,                   0, 0,   0,     0,     0,      0,  0, 0, 0, 0,  0}
  };
-#endif
 
-#ifdef USE_NEW_DYNAREC
  CPU cpus_6x86SS7[] = {
     /*Cyrix 6x86*/
-    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
-    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
-    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
+    {"Cx6x86/P90",     CPU_Cx6x86,    80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  8, 8, 6, 6, 10},
+    {"Cx6x86/PR120+",  CPU_Cx6x86,   100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Cx6x86/PR133+",  CPU_Cx6x86,   110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
+    {"Cx6x86/PR150+",  CPU_Cx6x86,   120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Cx6x86/PR166+",  CPU_Cx6x86,   133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Cx6x86/PR200+",  CPU_Cx6x86,   150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
 
     /*Cyrix 6x86L*/
-    {"Cx6x86L/PR133+", CPU_Cx6x86L,  110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
-    {"Cx6x86L/PR150+", CPU_Cx6x86L,  120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Cx6x86L/PR166+", CPU_Cx6x86L,  133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Cx6x86L/PR200+", CPU_Cx6x86L,  150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
+    {"Cx6x86L/PR133+", CPU_Cx6x86L,  110000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
+    {"Cx6x86L/PR150+", CPU_Cx6x86L,  120000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Cx6x86L/PR166+", CPU_Cx6x86L,  133333333, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Cx6x86L/PR200+", CPU_Cx6x86L,  150000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
 
     /*Cyrix 6x86MX/MII*/
-    {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2,   0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
-    {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
-    {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
-    {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7,   25},
-    {"MII/PR300",      CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11,   28},
-    {"MII/PR333",      CPU_Cx6x86MX, 250000000, 3,   0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9,   30},
-    {"MII/PR366",      CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7,   30},
-    {"MII/PR400",      CPU_Cx6x86MX, 285000000, 3,   0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9,   34},
-    {"MII/PR433",      CPU_Cx6x86MX, 300000000, 3,   0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9,   36},
+    {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2.0, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
+    {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
+    {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
+    {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7,   25},
+    {"MII/PR300",      CPU_Cx6x86MX, 233333333, 3.5, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11,   28},
+    {"MII/PR333",      CPU_Cx6x86MX, 250000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9,   30},
+    {"MII/PR366",      CPU_Cx6x86MX, 250000000, 2.5, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7,   30},
+    {"MII/PR400",      CPU_Cx6x86MX, 285000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9,   34},
+    {"MII/PR433",      CPU_Cx6x86MX, 300000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9,   36},
     {"",               -1,                   0, 0,   0,     0,     0,      0,  0, 0, 0, 0,  0}
  };
 #endif
 
 CPU cpus_WinChip[] = {
     /*IDT WinChip*/
-    {"WinChip 75",     CPU_WINCHIP,   75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  8,  8,  4,  4,  9},
-    {"WinChip 90",     CPU_WINCHIP,   90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 21/2},
-    {"WinChip 100",    CPU_WINCHIP,  100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 12},
-    {"WinChip 120",    CPU_WINCHIP,  120000000, 2,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 14},
-    {"WinChip 133",    CPU_WINCHIP,  133333333, 2,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 16},
-    {"WinChip 150",    CPU_WINCHIP,  150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 35/2},
-    {"WinChip 166",    CPU_WINCHIP,  166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 40},
-    {"WinChip 180",    CPU_WINCHIP,  180000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 21},
-    {"WinChip 200",    CPU_WINCHIP,  200000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
-    {"WinChip 225",    CPU_WINCHIP,  225000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
-    {"WinChip 240",    CPU_WINCHIP,  240000000, 4,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
-#ifdef USE_NEW_DYNAREC
-    {"WinChip 2/200",  CPU_WINCHIP2, 200000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
-    {"WinChip 2/225",  CPU_WINCHIP2, 225000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
-    {"WinChip 2/240",  CPU_WINCHIP2, 240000000, 4,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
-    {"WinChip 2/250",  CPU_WINCHIP2, 250000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
-    {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3,   0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
-    {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, (7*8)/2},
-#endif
+    {"WinChip 75",     CPU_WINCHIP,   75000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  8,  8,  4,  4,  9},
+    {"WinChip 90",     CPU_WINCHIP,   90000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 21/2},
+    {"WinChip 100",    CPU_WINCHIP,  100000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 12},
+    {"WinChip 120",    CPU_WINCHIP,  120000000, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 14},
+    {"WinChip 133",    CPU_WINCHIP,  133333333, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 16},
+    {"WinChip 150",    CPU_WINCHIP,  150000000, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 35/2},
+    {"WinChip 166",    CPU_WINCHIP,  166666666, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 40},
+    {"WinChip 180",    CPU_WINCHIP,  180000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 21},
+    {"WinChip 200",    CPU_WINCHIP,  200000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
+    {"WinChip 225",    CPU_WINCHIP,  225000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
+    {"WinChip 240",    CPU_WINCHIP,  240000000, 4.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
+    {"WinChip 2/200",  CPU_WINCHIP2, 200000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
+    {"WinChip 2/225",  CPU_WINCHIP2, 225000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
+    {"WinChip 2/240",  CPU_WINCHIP2, 240000000, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
+    {"WinChip 2/250",  CPU_WINCHIP2, 250000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
+    {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3.0, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
+    {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 3.5, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, (7*8)/2},
     {"",               -1,                   0, 0,   0,     0,     0, 0,                     0,  0,  0,  0,  0}
 };
 
-#ifdef USE_NEW_DYNAREC
 CPU cpus_WinChip_SS7[] = {
     /*IDT WinChip*/
-    {"WinChip 75",     CPU_WINCHIP,   75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  8,  8,  4,  4,  9},
-    {"WinChip 90",     CPU_WINCHIP,   90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 21/2},
-    {"WinChip 100",    CPU_WINCHIP,  100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 12},
-    {"WinChip 120",    CPU_WINCHIP,  120000000, 2,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 14},
-    {"WinChip 133",    CPU_WINCHIP,  133333333, 2,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 16},
-    {"WinChip 150",    CPU_WINCHIP,  150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 35/2},
-    {"WinChip 166",    CPU_WINCHIP,  166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 40},
-    {"WinChip 180",    CPU_WINCHIP,  180000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 21},
-    {"WinChip 200",    CPU_WINCHIP,  200000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
-    {"WinChip 225",    CPU_WINCHIP,  225000000, 3,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
-    {"WinChip 240",    CPU_WINCHIP,  240000000, 4,   0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
-    {"WinChip 2/200",  CPU_WINCHIP2, 200000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*8},
-    {"WinChip 2/225",  CPU_WINCHIP2, 225000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*9},
-    {"WinChip 2/240",  CPU_WINCHIP2, 240000000, 4,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
-    {"WinChip 2/250",  CPU_WINCHIP2, 250000000, 3,   0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
-    {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3,   0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*8},
-    {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  9,  9, (7*8)/2},
-    {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  7,  7, 28},
-    {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24,  8,  8, 30},
-    {"",               -1,                   0, 0,   0,     0,     0, 0,                     0,  0,  0,  0,  0}
+    {"WinChip 75",     CPU_WINCHIP,   75000000, 1.5,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  8,  8,  4,  4,  9},
+    {"WinChip 90",     CPU_WINCHIP,   90000000, 1.5,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 21/2},
+    {"WinChip 100",    CPU_WINCHIP,  100000000, 1.5,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC,  9,  9,  4,  4, 12},
+    {"WinChip 120",    CPU_WINCHIP,  120000000, 2.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 14},
+    {"WinChip 133",    CPU_WINCHIP,  133333333, 2.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12,  6,  6, 16},
+    {"WinChip 150",    CPU_WINCHIP,  150000000, 2.5,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 35/2},
+    {"WinChip 166",    CPU_WINCHIP,  166666666, 2.5,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15,  7,  7, 40},
+    {"WinChip 180",    CPU_WINCHIP,  180000000, 3.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 21},
+    {"WinChip 200",    CPU_WINCHIP,  200000000, 3.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 24},
+    {"WinChip 225",    CPU_WINCHIP,  225000000, 3.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 27},
+    {"WinChip 240",    CPU_WINCHIP,  240000000, 4.0,     0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
+    {"WinChip 2/200",  CPU_WINCHIP2, 200000000, 3.0,     0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*8},
+    {"WinChip 2/225",  CPU_WINCHIP2, 225000000, 3.0,     0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*9},
+    {"WinChip 2/240",  CPU_WINCHIP2, 240000000, 4.0,     0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
+    {"WinChip 2/250",  CPU_WINCHIP2, 250000000, 3.0,     0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
+    {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3.0,     0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18,  9,  9, 3*8},
+    {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 3.5,     0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  9,  9, (7*8)/2},
+    {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7.0/3.0, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  7,  7, 28},
+    {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 2.5,     0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24,  8,  8, 30},
+    {"",               -1,                   0, 0,           0,     0, 0, 0,                     0,  0,  0,  0,  0}
 };
-#endif
 
 CPU cpus_Pentium5V[] = {
     /*Intel Pentium (5V, socket 4)*/
@@ -475,282 +469,288 @@ CPU cpus_Pentium5V50[] = {
 
 CPU cpus_PentiumS5[] = {
     /*Intel Pentium (Socket 5)*/
-    {"Pentium 75",                   CPU_PENTIUM,     75000000, 3/2,  0x522,  0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
-    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
-    {"Pentium 90",                   CPU_PENTIUM,     90000000, 3/2,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
-    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2,    0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
-    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 3/2,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
-    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2,    0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
+    {"Pentium 75",                   CPU_PENTIUM,     75000000, 1.5,  0x522,  0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
+    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
+    {"Pentium 90",                   CPU_PENTIUM,     90000000, 1.5,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
+    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2.0,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
+    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 1.5,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
+    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2.0,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
 
-	/*Intel Pentium OverDrive*/
-    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 3,    0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16},
-    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
-    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40},
-    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15},
-    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
-    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
-    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21},
-    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
-    {"",                             -1,                     0, 0,        0,      0, 0, 0,  0, 0, 0, 0,  0}
+    /*Intel Pentium OverDrive*/
+    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 3.0,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16},
+    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
+    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40},
+    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15},
+    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
+    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
+    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21},
+    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
+    {"",                             -1,                     0, 0.0,      0,      0, 0, 0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_Pentium3V[] = {
     /*Intel Pentium*/
-    {"Pentium 75",                   CPU_PENTIUM,     75000000, 3/2,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"Pentium 90",                   CPU_PENTIUM,     90000000, 3/2,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2,    0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 3/2,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
-    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2,    0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Pentium 133",                  CPU_PENTIUM,    133333333, 2,    0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Pentium 150",                  CPU_PENTIUM,    150000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium 166",                  CPU_PENTIUM,    166666666, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium 200",                  CPU_PENTIUM,    200000000, 3,    0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Pentium 75",                   CPU_PENTIUM,     75000000, 1.5,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"Pentium 90",                   CPU_PENTIUM,     90000000, 1.5,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2.0,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 1.5,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
+    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2.0,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Pentium 133",                  CPU_PENTIUM,    133333333, 2.0,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Pentium 150",                  CPU_PENTIUM,    150000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium 166",                  CPU_PENTIUM,    166666666, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium 200",                  CPU_PENTIUM,    200000000, 3.0,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
 
 	/*Intel Pentium OverDrive*/
-    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
-    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
-    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
-    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
+    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
+    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
+    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
     {"",                                         -1,         0, 0,         0,     0, 0, 0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_Pentium[] = {
     /*Intel Pentium*/
-    {"Pentium 75",                   CPU_PENTIUM,     75000000, 3/2,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"Pentium 90",                   CPU_PENTIUM,     90000000, 3/2,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2,    0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 3/2,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
-    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2,    0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Pentium 133",                  CPU_PENTIUM,    133333333, 2,    0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Pentium 150",                  CPU_PENTIUM,    150000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium 166",                  CPU_PENTIUM,    166666666, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium 200",                  CPU_PENTIUM,    200000000, 3,    0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Pentium 75",                   CPU_PENTIUM,     75000000, 1.5,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"Pentium OverDrive MMX 75",     CPU_PENTIUMMMX,  75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"Pentium 90",                   CPU_PENTIUM,     90000000, 1.5,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"Pentium 100/50",               CPU_PENTIUM,    100000000, 2.0,  0x524,  0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Pentium 100/66",               CPU_PENTIUM,    100000000, 1.5,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
+    {"Pentium 120",                  CPU_PENTIUM,    120000000, 2.0,  0x526,  0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Pentium 133",                  CPU_PENTIUM,    133333333, 2.0,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Pentium 150",                  CPU_PENTIUM,    150000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium 166",                  CPU_PENTIUM,    166666666, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium 200",                  CPU_PENTIUM,    200000000, 3.0,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
 
 	/*Intel Pentium MMX*/
-    {"Pentium MMX 166",              CPU_PENTIUMMMX, 166666666, 5/2,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium MMX 200",              CPU_PENTIUMMMX, 200000000, 3,    0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
-    {"Pentium MMX 233",              CPU_PENTIUMMMX, 233333333, 7/2,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"Pentium MMX 166",              CPU_PENTIUMMMX, 166666666, 2.5,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium MMX 200",              CPU_PENTIUMMMX, 200000000, 3.0,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Pentium MMX 233",              CPU_PENTIUMMMX, 233333333, 3.5,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
 
 	/*Mobile Pentium*/
-    {"Mobile Pentium MMX 120",       CPU_PENTIUMMMX, 120000000, 2,    0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"Mobile Pentium MMX 133",       CPU_PENTIUMMMX, 133333333, 2,    0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"Mobile Pentium MMX 150",       CPU_PENTIUMMMX, 150000000, 5/2,  0x544,  0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Mobile Pentium MMX 166",       CPU_PENTIUMMMX, 166666666, 5/2,  0x544,  0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Mobile Pentium MMX 200",       CPU_PENTIUMMMX, 200000000, 3,    0x581,  0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
-    {"Mobile Pentium MMX 233",       CPU_PENTIUMMMX, 233333333, 7/2,  0x581,  0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-    {"Mobile Pentium MMX 266",       CPU_PENTIUMMMX, 266666666, 4,    0x582,  0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-    {"Mobile Pentium MMX 300",       CPU_PENTIUMMMX, 300000000, 9/2,  0x582,  0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+    {"Mobile Pentium MMX 120",       CPU_PENTIUMMMX, 120000000, 2.0,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"Mobile Pentium MMX 133",       CPU_PENTIUMMMX, 133333333, 2.0,  0x543,  0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"Mobile Pentium MMX 150",       CPU_PENTIUMMMX, 150000000, 2.5,  0x544,  0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Mobile Pentium MMX 166",       CPU_PENTIUMMMX, 166666666, 2.5,  0x544,  0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Mobile Pentium MMX 200",       CPU_PENTIUMMMX, 200000000, 3.0,  0x581,  0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Mobile Pentium MMX 233",       CPU_PENTIUMMMX, 233333333, 3.5,  0x581,  0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"Mobile Pentium MMX 266",       CPU_PENTIUMMMX, 266666666, 4.0,  0x582,  0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+    {"Mobile Pentium MMX 300",       CPU_PENTIUMMMX, 300000000, 4.5,  0x582,  0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
 
 	/*Intel Pentium OverDrive*/
-    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
-    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 5/2,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
-    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
-    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3,   0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
-    {"",                                         -1,         0, 0,         0,     0, 0, 0,  0, 0, 0, 0,  0}
+    {"Pentium OverDrive 125",        CPU_PENTIUM,    125000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
+    {"Pentium OverDrive 150",        CPU_PENTIUM,    150000000, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium OverDrive 166",        CPU_PENTIUM,    166666666, 2.5,  0x52c,  0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
+    {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
+    {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"",                                         -1,         0, 0.0,      0,     0, 0, 0,  0, 0, 0, 0,  0}
 };
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
 CPU cpus_K5[] = {
     /*AMD K5 (Socket 5)*/
-    {"K5 (5k86) 75 (P75)",      CPU_K5,    75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
-    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,    75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
-    {"K5 (5k86) 90 (P90)",      CPU_K5,    90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
-    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,    90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
-    {"K5 (5k86) 100 (P100)",    CPU_K5,   100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
-    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,   100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
-    {"K5 (5k86) 90 (PR120)",    CPU_5K86, 120000000, 2,   0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
-    {"K5 (5k86) 100 (PR133)",   CPU_5K86, 133333333, 2,   0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
-    {"K5 (5k86) 105 (PR150)",   CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
-    {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
-    {"K5 (5k86) 133 (PR200)",   CPU_5K86, 200000000, 3,   0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
-    {"",                        -1,               0, 0,   0,     0,     0, 0,  0, 0, 0, 0,  0}
+    {"K5 (5k86) 75 (P75)",      CPU_K5,    75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
+    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,    75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7,4,4,  9},
+    {"K5 (5k86) 90 (P90)",      CPU_K5,    90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
+    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,    90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 21/2},
+    {"K5 (5k86) 100 (P100)",    CPU_K5,   100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
+    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,   100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9,4,4, 12},
+    {"K5 (5k86) 90 (PR120)",    CPU_5K86, 120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
+    {"K5 (5k86) 100 (PR133)",   CPU_5K86, 133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
+    {"K5 (5k86) 105 (PR150)",   CPU_5K86, 150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
+    {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
+    {"K5 (5k86) 133 (PR200)",   CPU_5K86, 200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
+    {"",                        -1,               0, 0.0, 0,     0,     0, 0,  0, 0, 0, 0,  0}
 };
+#endif
 
 CPU cpus_K56[] = {
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
     /*AMD K5 (Socket 7)*/
-    {"K5 (5k86) 75 (P75)",      CPU_K5,    75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,    75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
-    {"K5 (5k86) 90 (P90)",      CPU_K5,    90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,    90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"K5 (5k86) 100 (P100)",    CPU_K5,   100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
-    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,   100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
-    {"K5 (5k86) 90 (PR120)",    CPU_5K86, 120000000, 2,   0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
-    {"K5 (5k86) 100 (PR133)",   CPU_5K86, 133333333, 2,   0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
-    {"K5 (5k86) 105 (PR150)",   CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"K5 (5k86) 133 (PR200)",   CPU_5K86, 200000000, 3,   0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"K5 (5k86) 75 (P75)",      CPU_K5,    75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,    75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,  9},
+    {"K5 (5k86) 90 (P90)",      CPU_K5,    90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,    90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"K5 (5k86) 100 (P100)",    CPU_K5,   100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
+    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,   100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 12},
+    {"K5 (5k86) 90 (PR120)",    CPU_5K86, 120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
+    {"K5 (5k86) 100 (PR133)",   CPU_5K86, 133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
+    {"K5 (5k86) 105 (PR150)",   CPU_5K86, 150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"K5 (5k86) 133 (PR200)",   CPU_5K86, 200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+#endif
 
     /*AMD K6 (Socket 7*/
-    {"K6 (Model 6) 166",        CPU_K6,   166666666, 5/2,  0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,   7,   7, 20},
-    {"K6 (Model 6) 200",        CPU_K6,   200000000, 3,    0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,   9,   9, 24},
-    {"K6 (Model 6) 233",        CPU_K6,   233333333, 7/2,  0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
-    {"K6 (Model 7) 200",        CPU_K6,   200000000, 3,    0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,   9,   9, 24},
-    {"K6 (Model 7) 233",        CPU_K6,   233333333, 7/2,  0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
-    {"K6 (Model 7) 266",        CPU_K6,   266666666, 4,    0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,  12,  12, 32},
-    {"K6 (Model 7) 300",        CPU_K6,   300000000, 9/2,  0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,  13,  13, 36},
-#ifdef USE_NEW_DYNAREC
-    {"K6-2/233",                CPU_K6_2, 233333333, 7/2,  0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
-    {"K6-2/266",                CPU_K6_2, 266666666, 4,    0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,  12,  12, 32},
-    {"K6-2/300 AFR-66",         CPU_K6_2, 300000000, 9/2,  0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,  13,  13, 36},
-    {"K6-2/366",                CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,  17,  17, 44},
-#endif
+    {"K6 (Model 6) 166",        CPU_K6,   166666666, 2.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,   7,   7, 20},
+    {"K6 (Model 6) 200",        CPU_K6,   200000000, 3.0, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,   9,   9, 24},
+    {"K6 (Model 6) 233",        CPU_K6,   233333333, 3.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
+    {"K6 (Model 7) 200",        CPU_K6,   200000000, 3.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,   9,   9, 24},
+    {"K6 (Model 7) 233",        CPU_K6,   233333333, 3.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
+    {"K6 (Model 7) 266",        CPU_K6,   266666666, 4.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,  12,  12, 32},
+    {"K6 (Model 7) 300",        CPU_K6,   300000000, 4.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,  13,  13, 36},
+
+    /*AMD K6-2 (Socket 7)*/
+    {"K6-2/233",                CPU_K6_2, 233333333, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,  10,  10, 28},
+    {"K6-2/266",                CPU_K6_2, 266666666, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,  12,  12, 32},
+    {"K6-2/300 AFR-66",         CPU_K6_2, 300000000, 4.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,  13,  13, 36},
+    {"K6-2/366",                CPU_K6_2, 366666666, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,  17,  17, 44},
     {"",                              -1,         0, 0,    0,     0,     0, 0,  0, 0, 0, 0,  0}
 };
+
+CPU cpus_K56_SS7[] = {
+#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
+    /*AMD K5 (Socket 7)*/
+    {"K5 (5k86) 75 (P75)",      CPU_K5,     75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,    9},
+    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,     75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,    9},
+    {"K5 (5k86) 90 (P90)",      CPU_K5,     90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,     90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
+    {"K5 (5k86) 100 (P100)",    CPU_K5,    100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4,   12},
+    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,    100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4,   12},
+    {"K5 (5k86) 90 (PR120)",    CPU_5K86,  120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   14},
+    {"K5 (5k86) 100 (PR133)",   CPU_5K86,  133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
+    {"K5 (5k86) 105 (PR150)",   CPU_5K86,  150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"K5 (5k86) 116.5 (PR166)", CPU_5K86,  166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
+    {"K5 (5k86) 133 (PR200)",   CPU_5K86,  200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9,   24},
 #endif
 
-#ifdef USE_NEW_DYNAREC
-CPU cpus_K56_SS7[] = {
-    /*AMD K5 (Socket 7)*/
-    {"K5 (5k86) 75 (P75)",      CPU_K5,     75000000, 3/2,  0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,    9},
-    {"K5 (SSA/5) 75 (PR75)",    CPU_K5,     75000000, 3/2,  0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4,    9},
-    {"K5 (5k86) 90 (P90)",      CPU_K5,     90000000, 3/2,  0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"K5 (SSA/5) 90 (PR90)",    CPU_K5,     90000000, 3/2,  0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4, 21/2},
-    {"K5 (5k86) 100 (P100)",    CPU_K5,    100000000, 3/2,  0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4,   12},
-    {"K5 (SSA/5) 100 (PR100)",  CPU_K5,    100000000, 3/2,  0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  9, 9, 4, 4,   12},
-    {"K5 (5k86) 90 (PR120)",    CPU_5K86,  120000000, 2,    0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   14},
-    {"K5 (5k86) 100 (PR133)",   CPU_5K86,  133333333, 2,    0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6,   16},
-    {"K5 (5k86) 105 (PR150)",   CPU_5K86,  150000000, 5/2,  0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"K5 (5k86) 116.5 (PR166)", CPU_5K86,  166666666, 5/2,  0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7,   20},
-    {"K5 (5k86) 133 (PR200)",   CPU_5K86,  200000000, 3,    0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9,   24},
+    /*AMD K6 (Socket 7)*/
+    {"K6 (Model 6) 166",        CPU_K6,    166666666, 2.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"K6 (Model 6) 200",        CPU_K6,    200000000, 3.0, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"K6 (Model 6) 233",        CPU_K6,    233333333, 3.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"K6 (Model 7) 200",        CPU_K6,    200000000, 3.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"K6 (Model 7) 233",        CPU_K6,    233333333, 3.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"K6 (Model 7) 266",        CPU_K6,    266666666, 4.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+    {"K6 (Model 7) 300",        CPU_K6,    300000000, 4.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
 
-	/*AMD K6 (Socket 7)*/
-    {"K6 (Model 6) 166",        CPU_K6,    166666666, 5/2,  0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"K6 (Model 6) 200",        CPU_K6,    200000000, 3,    0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
-    {"K6 (Model 6) 233",        CPU_K6,    233333333, 7/2,  0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-    {"K6 (Model 7) 200",        CPU_K6,    200000000, 3,    0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
-    {"K6 (Model 7) 233",        CPU_K6,    233333333, 7/2,  0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-    {"K6 (Model 7) 266",        CPU_K6,    266666666, 4,    0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-    {"K6 (Model 7) 300",        CPU_K6,    300000000, 9/2,  0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+    /*AMD K6-2 (Socket 7/Super Socket 7)*/
+    {"K6-2/233",                CPU_K6_2,  233333333, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    21,   21,  10,  10, 28},
+    {"K6-2/266",                CPU_K6_2,  266666666, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    24,   24,  12,  12, 32},
+    {"K6-2/300",                CPU_K6_2,  300000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    27,   27,   9,   9, 36},
+    {"K6-2/333",                CPU_K6_2,  332500000, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    30,   30,  11,  11, 40},
+    {"K6-2/350",                CPU_K6_2C, 350000000, 3.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    32,   32,  11,  11, 42},
+    {"K6-2/366",                CPU_K6_2C, 366666666, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    33,   33,  17,  17, 44},
+    {"K6-2/380",                CPU_K6_2C, 380000000, 4.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    34,   34,  12,  12, 46},
+    {"K6-2/400",                CPU_K6_2C, 400000000, 4.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
+    {"K6-2/450",                CPU_K6_2C, 450000000, 4.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
+    {"K6-2/475",                CPU_K6_2C, 475000000, 5.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
+    {"K6-2/500",                CPU_K6_2C, 500000000, 5.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
+    {"K6-2/533",                CPU_K6_2C, 533333333, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    48,   48,  17,  17, 64},
+    {"K6-2/550",                CPU_K6_2C, 550000000, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    50,   50,  17,  17, 66},
 
-	/*AMD K6-2 (Socket 7/Super Socket 7)*/
-    {"K6-2/233",                CPU_K6_2,  233333333, 7/2,  0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    21,   21,  10,  10, 28},
-    {"K6-2/266",                CPU_K6_2,  266666666, 4,    0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    24,   24,  12,  12, 32},
-    {"K6-2/300",                CPU_K6_2,  300000000, 3,    0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    27,   27,   9,   9, 36},
-    {"K6-2/333",                CPU_K6_2,  332500000, 7/2,  0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    30,   30,  11,  11, 40},
-    {"K6-2/350",                CPU_K6_2C, 350000000, 7/2,  0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    32,   32,  11,  11, 42},
-    {"K6-2/366",                CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    33,   33,  17,  17, 44},
-    {"K6-2/380",                CPU_K6_2C, 380000000, 4,    0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    34,   34,  12,  12, 46},
-    {"K6-2/400",                CPU_K6_2C, 400000000, 4,    0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
-    {"K6-2/450",                CPU_K6_2C, 450000000, 9/2,  0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
-    {"K6-2/475",                CPU_K6_2C, 475000000, 5,    0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
-    {"K6-2/500",                CPU_K6_2C, 500000000, 5,    0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
-    {"K6-2/533",                CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    48,   48,  17,  17, 64},
-    {"K6-2/550",                CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    50,   50,  17,  17, 66},
-
-	/*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/
-    {"K6-2+/450",               CPU_K6_2P, 450000000, 9/2,  0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
-    {"K6-2+/475",               CPU_K6_2P, 475000000, 5,    0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
-    {"K6-2+/500",               CPU_K6_2P, 500000000, 5,    0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
-    {"K6-2+/533",               CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    48,   48,  17,  17, 64},
-    {"K6-2+/550",               CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    50,   50,  17,  17, 66},
-    {"K6-III/400",              CPU_K6_3,  400000000, 4,    0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
-    {"K6-III/450",              CPU_K6_3,  450000000, 9/2,  0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
-    {"K6-III+/400",             CPU_K6_3P, 400000000, 4,    0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
-    {"K6-III+/450",             CPU_K6_3P, 450000000, 9/2,  0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
-    {"K6-III+/475",             CPU_K6_3P, 475000000, 5,    0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
-    {"K6-III+/500",             CPU_K6_3P, 500000000, 5,    0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
+    /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/
+    {"K6-2+/450",               CPU_K6_2P, 450000000, 4.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
+    {"K6-2+/475",               CPU_K6_2P, 475000000, 5.0, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
+    {"K6-2+/500",               CPU_K6_2P, 500000000, 5.0, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
+    {"K6-2+/533",               CPU_K6_2P, 533333333, 5.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    48,   48,  17,  17, 64},
+    {"K6-2+/550",               CPU_K6_2P, 550000000, 5.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    50,   50,  17,  17, 66},
+    {"K6-III/400",              CPU_K6_3,  400000000, 4.0, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
+    {"K6-III/450",              CPU_K6_3,  450000000, 4.5, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
+    {"K6-III+/75",              CPU_K6_3P,  75000000, 1.5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,     7,    7,   4,   4,  9},
+    {"K6-III+/400",             CPU_K6_3P, 400000000, 4.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    36,   36,  12,  12, 48},
+    {"K6-III+/450",             CPU_K6_3P, 450000000, 4.5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    41,   41,  14,  14, 54},
+    {"K6-III+/475",             CPU_K6_3P, 475000000, 5.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    43,   43,  15,  15, 57},
+    {"K6-III+/500",             CPU_K6_3P, 500000000, 5.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,    45,   45,  15,  15, 60},
     {"",                               -1,         0, 0,        0,     0, 0, 0,  0, 0, 0, 0,  0}
 };
-#endif
 
 #ifdef DEV_BRANCH
 #ifdef USE_I686
 CPU cpus_PentiumPro[] = {
     /*Intel Pentium Pro*/
-    {"Pentium Pro 50",              CPU_PENTIUMPRO,  50000000, 1,   0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
-    {"Pentium Pro 60" ,             CPU_PENTIUMPRO,  60000000, 1,   0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
-    {"Pentium Pro 66" ,             CPU_PENTIUMPRO,  66666666, 1,   0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
-    {"Pentium Pro 75",              CPU_PENTIUMPRO,  75000000, 3/2, 0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
-    {"Pentium Pro 150",             CPU_PENTIUMPRO, 150000000, 5/2, 0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
-    {"Pentium Pro 166",             CPU_PENTIUMPRO, 166666666, 5/2, 0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
-    {"Pentium Pro 180",             CPU_PENTIUMPRO, 180000000, 3,   0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
-    {"Pentium Pro 200",             CPU_PENTIUMPRO, 200000000, 3,   0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
+    {"Pentium Pro 50",              CPU_PENTIUMPRO,  50000000, 1.0,  0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
+    {"Pentium Pro 60" ,             CPU_PENTIUMPRO,  60000000, 1.0,  0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
+    {"Pentium Pro 66" ,             CPU_PENTIUMPRO,  66666666, 1.0,  0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
+    {"Pentium Pro 75",              CPU_PENTIUMPRO,  75000000, 1.5,  0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
+    {"Pentium Pro 150",             CPU_PENTIUMPRO, 150000000, 2.5,  0x612,  0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
+    {"Pentium Pro 166",             CPU_PENTIUMPRO, 166666666, 2.5,  0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
+    {"Pentium Pro 180",             CPU_PENTIUMPRO, 180000000, 3.0,  0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
+    {"Pentium Pro 200",             CPU_PENTIUMPRO, 200000000, 3.0,  0x617,  0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
 
-	/*Intel Pentium II OverDrive*/
-    {"Pentium II Overdrive 50",     CPU_PENTIUM2D,   50000000, 1,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
-    {"Pentium II Overdrive 60",     CPU_PENTIUM2D,   60000000, 1,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
-    {"Pentium II Overdrive 66",     CPU_PENTIUM2D,   66666666, 1,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
-    {"Pentium II Overdrive 75",     CPU_PENTIUM2D,   75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
-    {"Pentium II Overdrive 210",    CPU_PENTIUM2D,  210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
-    {"Pentium II Overdrive 233",    CPU_PENTIUM2D,  233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-    {"Pentium II Overdrive 240",    CPU_PENTIUM2D,  240000000, 4,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
-    {"Pentium II Overdrive 266",    CPU_PENTIUM2D,  266666666, 4,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-    {"Pentium II Overdrive 270",    CPU_PENTIUM2D,  270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33},
-    {"Pentium II Overdrive 300/66", CPU_PENTIUM2D,  300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
-    {"Pentium II Overdrive 300/60", CPU_PENTIUM2D,  300000000, 5,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
-    {"Pentium II Overdrive 333",    CPU_PENTIUM2D,  333333333, 5,   0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
+    /*Intel Pentium II OverDrive*/
+    {"Pentium II Overdrive 50",     CPU_PENTIUM2D,   50000000, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
+    {"Pentium II Overdrive 60",     CPU_PENTIUM2D,   60000000, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
+    {"Pentium II Overdrive 66",     CPU_PENTIUM2D,   66666666, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
+    {"Pentium II Overdrive 75",     CPU_PENTIUM2D,   75000000, 1.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
+    {"Pentium II Overdrive 210",    CPU_PENTIUM2D,  210000000, 3.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
+    {"Pentium II Overdrive 233",    CPU_PENTIUM2D,  233333333, 3.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"Pentium II Overdrive 240",    CPU_PENTIUM2D,  240000000, 4.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
+    {"Pentium II Overdrive 266",    CPU_PENTIUM2D,  266666666, 4.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+    {"Pentium II Overdrive 270",    CPU_PENTIUM2D,  270000000, 4.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33},
+    {"Pentium II Overdrive 300/66", CPU_PENTIUM2D,  300000000, 4.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
+    {"Pentium II Overdrive 300/60", CPU_PENTIUM2D,  300000000, 5.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+    {"Pentium II Overdrive 333",    CPU_PENTIUM2D,  333333333, 5.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
     {"",                                       -1,          0, 0,   0,      0,      0, 0,  0, 0, 0, 0,  0}
 };
 
 CPU cpus_PentiumII[] = {
     /*Intel Pentium II Klamath*/
-    {"Pentium II Klamath 50",        CPU_PENTIUM2,   50000000, 1,    0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
-    {"Pentium II Klamath 60",        CPU_PENTIUM2,   60000000, 1,    0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
-    {"Pentium II Klamath 66",        CPU_PENTIUM2,   66666666, 1,    0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
-    {"Pentium II Klamath 75",        CPU_PENTIUM2,   75000000, 3/2,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
-    {"Pentium II Klamath 233",       CPU_PENTIUM2,  233333333, 7/2,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-    {"Pentium II Klamath 266",       CPU_PENTIUM2,  266666666, 4,    0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
-    {"Pentium II Klamath 300/66",    CPU_PENTIUM2,  300000000, 9/2,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
+    {"Pentium II Klamath 50",        CPU_PENTIUM2,   50000000, 1.0,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
+    {"Pentium II Klamath 60",        CPU_PENTIUM2,   60000000, 1.0,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
+    {"Pentium II Klamath 66",        CPU_PENTIUM2,   66666666, 1.0,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
+    {"Pentium II Klamath 75",        CPU_PENTIUM2,   75000000, 1.5,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
+    {"Pentium II Klamath 233",       CPU_PENTIUM2,  233333333, 3.5,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+    {"Pentium II Klamath 266",       CPU_PENTIUM2,  266666666, 4.0,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
+    {"Pentium II Klamath 300/66",    CPU_PENTIUM2,  300000000, 4.5,  0x634,  0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
 
-	/*Intel Pentium II Deschutes*/
-    {"Pentium II Deschutes 50",     CPU_PENTIUM2D,   50000000, 1,    0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
-    {"Pentium II Deschutes 60",     CPU_PENTIUM2D,   60000000, 1,    0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
-    {"Pentium II Deschutes 66",     CPU_PENTIUM2D,   66666666, 1,    0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
-    {"Pentium II Deschutes 75",     CPU_PENTIUM2D,   75000000, 3/2,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
-    {"Pentium II Deschutes 266",    CPU_PENTIUM2D,  266666666, 4,    0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
-    {"Pentium II Deschutes 300/66", CPU_PENTIUM2D,  300000000, 9/2,  0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
-    {"Pentium II Deschutes 333",    CPU_PENTIUM2D,  333333333, 5,    0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
-    {"Pentium II Deschutes 350",    CPU_PENTIUM2D,  350000000, 7/2,  0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42},
-    {"Pentium II Deschutes 400",    CPU_PENTIUM2D,  400000000, 4,    0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
-    {"Pentium II Deschutes 450",    CPU_PENTIUM2D,  450000000, 9/2,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54},
+    /*Intel Pentium II Deschutes*/
+    {"Pentium II Deschutes 50",     CPU_PENTIUM2D,   50000000, 1.0,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
+    {"Pentium II Deschutes 60",     CPU_PENTIUM2D,   60000000, 1.0,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 7},
+    {"Pentium II Deschutes 66",     CPU_PENTIUM2D,   66666666, 1.0,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
+    {"Pentium II Deschutes 75",     CPU_PENTIUM2D,   75000000, 1.5,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  7, 7, 4, 4, 9},
+    {"Pentium II Deschutes 266",    CPU_PENTIUM2D,  266666666, 4.0,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
+    {"Pentium II Deschutes 300/66", CPU_PENTIUM2D,  300000000, 4.5,  0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
+    {"Pentium II Deschutes 333",    CPU_PENTIUM2D,  333333333, 5.0,  0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
+    {"Pentium II Deschutes 350",    CPU_PENTIUM2D,  350000000, 3.5,  0x651,  0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42},
+    {"Pentium II Deschutes 400",    CPU_PENTIUM2D,  400000000, 4.0,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
+    {"Pentium II Deschutes 450",    CPU_PENTIUM2D,  450000000, 4.5,  0x652,  0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54},
     {"",                                       -1,          0, 0,        0,      0, 0, 0,  0, 0, 0, 0,  0}
 
 };
 
-CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D series. Intended for
-                       // the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1
-					   // adaptor card so they work on Slot 1 motherboards too!.
-					   
-					   // The 100Mhz Mendocino is only meant to not cause any struggle
-					   // to the recompiler.
-    {"Celeron Mendocino 66",        CPU_PENTIUM2D,   66666666, 1,    0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
-    {"Celeron Mendocino 100",       CPU_PENTIUM2D,  100000000, 3/2,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
-    {"Celeron Mendocino 300/66",    CPU_PENTIUM2D,  300000000, 9/2,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
-    {"Celeron Mendocino 333",       CPU_PENTIUM2D,  333333333, 5,    0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
-    {"Celeron Mendocino 366",       CPU_PENTIUM2D,  366666666, 11/2, 0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44},
-    {"Celeron Mendocino 400",       CPU_PENTIUM2D,  400000000, 4,    0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
-    {"Celeron Mendocino 433",       CPU_PENTIUM2D,  433333333, 9/2,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51},
-    {"Celeron Mendocino 466",       CPU_PENTIUM2D,  466666666, 5,    0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57},
-    {"Celeron Mendocino 500",       CPU_PENTIUM2D,  500000000, 5,    0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60},
-    {"Celeron Mendocino 533",       CPU_PENTIUM2D,  533333333, 11/2, 0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64},
-    {"",                                       -1,          0, 0,        0,      0, 0, 0,  0, 0, 0, 0,  0}	
+CPU cpus_Celeron[] = {
+    /* Mendocino Celerons. Exact architecture as the P2D series. Intended for
+       the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1
+       adaptor card so they work on Slot 1 motherboards too!.
+
+       The 100Mhz Mendocino is only meant to not cause any struggle
+       to the recompiler. */
+    {"Celeron Mendocino 25",        CPU_PENTIUM2D,   25000000, 1.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 3},
+    {"Celeron Mendocino 50",        CPU_PENTIUM2D,   50000000, 1.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  4, 4, 3, 3, 6},
+    {"Celeron Mendocino 66",        CPU_PENTIUM2D,   66666666, 1.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,  6, 6, 3, 3, 8},
+    {"Celeron Mendocino 100",       CPU_PENTIUM2D,  100000000, 1.5,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
+    {"Celeron Mendocino 300/66",    CPU_PENTIUM2D,  300000000, 4.5,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
+    {"Celeron Mendocino 333",       CPU_PENTIUM2D,  333333333, 5.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
+    {"Celeron Mendocino 366",       CPU_PENTIUM2D,  366666666, 5.5,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44},
+    {"Celeron Mendocino 400",       CPU_PENTIUM2D,  400000000, 4.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
+    {"Celeron Mendocino 433",       CPU_PENTIUM2D,  433333333, 4.5,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51},
+    {"Celeron Mendocino 466",       CPU_PENTIUM2D,  466666666, 5.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57},
+    {"Celeron Mendocino 500",       CPU_PENTIUM2D,  500000000, 5.0,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60},
+    {"Celeron Mendocino 533",       CPU_PENTIUM2D,  533333333, 5.5,  0x665,  0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64},
+    {"",                                       -1,          0,   0,      0,      0, 0, 0,  0, 0, 0, 0,  0}	
 };
 #endif
 #endif
 CPU cpus_Cyrix3[] = {
     /*VIA Cyrix III (Samuel)*/
-    {"Cyrix III 66",  CPU_CYRIX3S,  66666666, 1,    0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC,  6,  6,  3,  3,  8}, /*66 MHz version*/
-    {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5,  0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  9,  9, 28},
-    {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4,    0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
-    {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5,  0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
-    {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5,    0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
-    {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5,  0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
-    {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4,    0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
-    {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5,  0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
-    {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5,    0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
-    {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5,  0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
-    {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6,    0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
-    {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5,  0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
-    {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7,    0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
-    {"",               -1,                   0, 0,        0,     0,     0, 0,                    0,   0, 0,  0,  0}
+    {"Cyrix III 66",  CPU_CYRIX3S,  66666666, 1.0,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC,  6,  6,  3,  3,  8}, /*66 MHz version*/
+    {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21,  9,  9, 28},
+    {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4.0,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
+    {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
+    {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5.0,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
+    {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
+    {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4.0,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
+    {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
+    {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5.0,   0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
+    {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5,   0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
+    {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6.0,   0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
+    {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5,   0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
+    {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7.0,   0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
+    {"",                       -1,         0, 0.0,       0,     0, 0, 0,                    0,   0, 0,  0,  0}
 };
diff --git a/src/cpu_common/x86_ops.h b/src/cpu_common/x86_ops.h
index cf192f79e..d41cca96f 100644
--- a/src/cpu_common/x86_ops.h
+++ b/src/cpu_common/x86_ops.h
@@ -86,14 +86,12 @@ extern const OpFn dynarec_ops_winchip2_0f[1024];
 extern const OpFn dynarec_ops_pentium_0f[1024];
 extern const OpFn dynarec_ops_pentiummmx_0f[1024];
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
 extern const OpFn dynarec_ops_c6x86mx_0f[1024];
 #endif
 
-#ifdef USE_NEW_DYNAREC
 extern const OpFn dynarec_ops_k6_0f[1024];
 extern const OpFn dynarec_ops_k62_0f[1024];
-#endif
 
 #if defined(DEV_BRANCH) && defined(USE_I686)
 extern const OpFn dynarec_ops_pentiumpro_0f[1024];
@@ -185,14 +183,12 @@ extern const OpFn ops_winchip2_0f[1024];
 extern const OpFn ops_pentium_0f[1024];
 extern const OpFn ops_pentiummmx_0f[1024];
 
-#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
+#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
 extern const OpFn ops_c6x86mx_0f[1024];
 #endif
 
-#ifdef USE_NEW_DYNAREC
 extern const OpFn ops_k6_0f[1024];
 extern const OpFn ops_k62_0f[1024];
-#endif
 
 #if defined(DEV_BRANCH) && defined(USE_I686)
 extern const OpFn ops_pentiumpro_0f[1024];
diff --git a/src/cpu_common/x86_ops_amd.h b/src/cpu_common/x86_ops_amd.h
index aa42c3d8e..b152f548f 100644
--- a/src/cpu_common/x86_ops_amd.h
+++ b/src/cpu_common/x86_ops_amd.h
@@ -13,180 +13,33 @@
  * Author:	Miran Grca, <mgrca8@gmail.com>
  *		Copyright 2016-2018 Miran Grca.
  */
-
-/*	0 = Limit 0-15
-	1 = Base 0-15
-	2 = Base 16-23 (bits 0-7), Access rights
-		8-11	Type
-		12	S
-		13, 14	DPL
-		15	P
-	3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
-		4	A
-		6	DB
-		7	G	*/
-
-#define AMD_SYSCALL_EIP	(star & 0xFFFFFFFF)
-#define AMD_SYSCALL_SB	((star >> 32) & 0xFFFF)
-#define AMD_SYSRET_SB	((star >> 48) & 0xFFFF)
-
-/* 0F 05 */
-static int opSYSCALL(uint32_t fetchdat)
+static int
+opSYSCALL(uint32_t fetchdat)
 {
-	uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
-	uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
-
-	if (!(cr0 & 1))  return internal_illegal("SYSCALL: CPU not in protected mode");
-	if (!AMD_SYSCALL_SB)  return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
-
-	/* Set VM, IF, RF to 0. */
-	/* cpu_state.eflags &= ~0x00030200;
-	cpu_state.flags &= ~0x0200; */
-
-	/* Let's do this by the AMD spec. */
-	ECX = cpu_state.pc;
-
-	cpu_state.eflags &= ~0x0002;
-	cpu_state.flags &= ~0x0200;
-
-	/* CS */
-	cpu_state.seg_cs.seg = AMD_SYSCALL_SB & ~7;
-	if (AMD_SYSCALL_SB & 4)
-	{
-		if (cpu_state.seg_cs.seg >= ldt.limit)
-		{
-			x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSCALL_SB,ldt.limit);
-			x86gpf(NULL, AMD_SYSCALL_SB & ~3);
-			return 1;
-		}
-		cpu_state.seg_cs.seg +=ldt.base;
-	}
-	else
-	{
-		if (cpu_state.seg_cs.seg >= gdt.limit)
-		{
-			x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSCALL_SB,gdt.limit);
-			x86gpf(NULL, AMD_SYSCALL_SB & ~3);
-			return 1;
-		}
-		cpu_state.seg_cs.seg += gdt.base;
-	}
-	cpl_override = 1;
-
-	syscall_cs_seg_data[0] = 0xFFFF;
-	syscall_cs_seg_data[1] = 0;
-	syscall_cs_seg_data[2] = 0x9B00;
-	syscall_cs_seg_data[3] = 0xC0;
-
-	cpl_override = 0;
-
-	use32 = 0x300;
-	CS = (AMD_SYSCALL_SB & ~3) | 0;
-
-	do_seg_load(&cpu_state.seg_cs, syscall_cs_seg_data);
-	use32 = 0x300;
-
-	CS = (CS & 0xFFFC) | 0;
-
-	cpu_state.seg_cs.limit = 0xFFFFFFFF;
-	cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
-
-	/* SS */
-	syscall_ss_seg_data[0] = 0xFFFF;
-	syscall_ss_seg_data[1] = 0;
-	syscall_ss_seg_data[2] = 0x9300;
-	syscall_ss_seg_data[3] = 0xC0;
-	do_seg_load(&cpu_state.seg_ss, syscall_ss_seg_data);
-	cpu_state.seg_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
-	stack32 = 1;
-
-	cpu_state.seg_ss.limit = 0xFFFFFFFF;
-	cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
-
-	cpu_state.seg_ss.checked = 0;
-
-	cpu_state.pc = AMD_SYSCALL_EIP;
+    int ret = syscall(fetchdat);
 
+    if (ret <= 1) {
 	CLOCK_CYCLES(20);
-
+	PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
+	PREFETCH_FLUSH();
 	CPU_BLOCK_END();
+    }
 
-	return 0;
+    return ret;
 }
 
-/* 0F 07 */
-static int opSYSRET(uint32_t fetchdat)
+
+static int
+opSYSRET(uint32_t fetchdat)
 {
-	uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
-	uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
-
-	if (!AMD_SYSRET_SB)  return internal_illegal("SYSRET: CS MSR is zero");
-	if (!(cr0 & 1))  return internal_illegal("SYSRET: CPU not in protected mode");
-
-	cpu_state.pc = ECX;
-
-	cpu_state.eflags |= (1 << 1);
-
-	/* CS */
-	cpu_state.seg_cs.seg = AMD_SYSRET_SB & ~7;
-	if (AMD_SYSRET_SB & 4)
-	{
-		if (cpu_state.seg_cs.seg >= ldt.limit)
-		{
-			x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSRET_SB,ldt.limit);
-			x86gpf(NULL, AMD_SYSRET_SB & ~3);
-			return 1;
-		}
-		cpu_state.seg_cs.seg +=ldt.base;
-	}
-	else
-	{
-		if (cpu_state.seg_cs.seg >= gdt.limit)
-		{
-			x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSRET_SB,gdt.limit);
-			x86gpf(NULL, AMD_SYSRET_SB & ~3);
-			return 1;
-		}
-		cpu_state.seg_cs.seg += gdt.base;
-	}
-	cpl_override = 1;
-
-	sysret_cs_seg_data[0] = 0xFFFF;
-	sysret_cs_seg_data[1] = 0;
-	sysret_cs_seg_data[2] = 0xFB00;
-	sysret_cs_seg_data[3] = 0xC0;
-
-	cpl_override = 0;
-
-	use32 = 0x300;
-	CS = (AMD_SYSRET_SB & ~3) | 3;
-
-	do_seg_load(&cpu_state.seg_cs, sysret_cs_seg_data);
-	flushmmucache_cr3();
-	use32 = 0x300;
-
-	CS = (CS & 0xFFFC) | 3;
-
-	cpu_state.seg_cs.limit = 0xFFFFFFFF;
-	cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
-
-	/* SS */
-	sysret_ss_seg_data[0] = 0xFFFF;
-	sysret_ss_seg_data[1] = 0;
-	sysret_ss_seg_data[2] = 0xF300;
-	sysret_ss_seg_data[3] = 0xC0;
-	do_seg_load(&cpu_state.seg_ss, sysret_ss_seg_data);
-	cpu_state.seg_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
-	stack32 = 1;
-
-	cpu_state.seg_ss.limit = 0xFFFFFFFF;
-	cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
-
-	cpu_state.seg_ss.checked = 0;
+    int ret = sysret(fetchdat);
 
+    if (ret <= 1) {
 	CLOCK_CYCLES(20);
-
+	PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
+	PREFETCH_FLUSH();
 	CPU_BLOCK_END();
+    }
 
-	return 0;
+    return ret;
 }
diff --git a/src/cpu_common/x86_ops_i686.h b/src/cpu_common/x86_ops_i686.h
index 21c6b5a7b..469076c8b 100644
--- a/src/cpu_common/x86_ops_i686.h
+++ b/src/cpu_common/x86_ops_i686.h
@@ -13,145 +13,40 @@
  * Author:	Miran Grca, <mgrca8@gmail.com>
  *		Copyright 2016-2020 Miran Grca.
  */
-
-/*	0 = Limit 0-15
-	1 = Base 0-15
-	2 = Base 16-23 (bits 0-7), Access rights
-		8-11	Type
-		12	S
-		13, 14	DPL
-		15	P
-	3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
-		4	A
-		6	DB
-		7	G	*/
-
-static void make_seg_data(uint16_t *seg_data, uint32_t base, uint32_t limit, uint8_t type, uint8_t s, uint8_t dpl, uint8_t p, uint8_t g, uint8_t db, uint8_t a)
+static int
+opSYSENTER(uint32_t fetchdat)
 {
-	seg_data[0] = limit & 0xFFFF;
-	seg_data[1] = base & 0xFFFF;
-	seg_data[2] = ((base >> 16) & 0xFF) | (type << 8) | (p << 15) | (dpl << 13) | (s << 12);
-	seg_data[3] = ((limit >> 16) & 0xF) | (a << 4) | (db << 6) | (g << 7) | ((base >> 16) & 0xFF00);
-}
-
-static int opSYSENTER(uint32_t fetchdat)
-{
-	uint16_t sysenter_cs_seg_data[4];
-	uint16_t sysenter_ss_seg_data[4];
-
-#ifdef SYSENTER_LOG
-	x386_dynarec_log("SYSENTER called\n");
-#endif
-
-	if (!(msw & 1))  return internal_illegal("SYSENTER: CPU not in protected mode");
-	if (!(cs_msr & 0xFFFC))  return internal_illegal("SYSENTER: CS MSR is zero");
-
-#ifdef SYSENTER_LOG
-	x386_dynarec_log("SYSENTER started:\n");
-	x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
-	x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
-	x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
-	x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32);
-#endif
-
-	if (cpu_state.abrt)  return 1;
-
-	ESP = esp_msr;
-	cpu_state.pc = eip_msr;
-
-        optype = CALL;                                                          \
-        cgate16 = cgate32 = 0;                                                  \
-
-	/* Set VM, RF, and IF to 0. */
-	cpu_state.eflags &= ~0x0003;
-	cpu_state.flags &= ~0x0200;
-
-	CS = (cs_msr & 0xFFFC);
-	make_seg_data(sysenter_cs_seg_data, 0, 0xFFFFF, 11, 1, 0, 1, 1, 1, 0);
-	do_seg_load(&cpu_state.seg_cs, sysenter_cs_seg_data);
-	use32 = 0x300;
-
-	SS = ((cs_msr + 8) & 0xFFFC);
-	make_seg_data(sysenter_ss_seg_data, 0, 0xFFFFF, 3, 1, 0, 1, 1, 1, 0);
-	do_seg_load(&cpu_state.seg_ss, sysenter_ss_seg_data);
-	stack32 = 1;
-
-	cycles -= timing_call_pm;
-
-	optype = 0;
+    int ret = sysenter(fetchdat);
 
+    if (ret <= 1) {
+	CLOCK_CYCLES(20);
+	PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
+	PREFETCH_FLUSH();
 	CPU_BLOCK_END();
+    }
 
-#ifdef SYSENTER_LOG
-	x386_dynarec_log("SYSENTER completed:\n");
-	x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
-	x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
-	x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
-	x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32);
-#endif
-
-	return 0;
+    return ret;
 }
 
-static int opSYSEXIT(uint32_t fetchdat)
+
+static int
+opSYSEXIT(uint32_t fetchdat)
 {
-	uint16_t sysexit_cs_seg_data[4];
-	uint16_t sysexit_ss_seg_data[4];
-
-#ifdef SYSEXIT_LOG
-	x386_dynarec_log("SYSEXIT called\n");
-#endif
-
-	if (!(cs_msr & 0xFFFC))  return internal_illegal("SYSEXIT: CS MSR is zero");
-	if (!(msw & 1))  return internal_illegal("SYSEXIT: CPU not in protected mode");
-	if (CPL)  return internal_illegal("SYSEXIT: CPL not 0");
-
-#ifdef SYSEXIT_LOG
-	x386_dynarec_log("SYSEXIT start:\n");
-	x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
-	x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
-	x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
-	x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32, ECX, EDX);
-#endif
-
-	if (cpu_state.abrt)  return 1;
-
-	ESP = ECX;
-	cpu_state.pc = EDX;
-
-        optype = CALL;                                                          \
-        cgate16 = cgate32 = 0;                                                  \
-
-	CS = ((cs_msr + 16) & 0xFFFC) | 3;
-	make_seg_data(sysexit_cs_seg_data, 0, 0xFFFFF, 11, 1, 3, 1, 1, 1, 0);
-	do_seg_load(&cpu_state.seg_cs, sysexit_cs_seg_data);
-	use32 = 0x300;
-
-	SS = CS + 8;
-	make_seg_data(sysexit_ss_seg_data, 0, 0xFFFFF, 3, 1, 3, 1, 1, 1, 0);
-	do_seg_load(&cpu_state.seg_ss, sysexit_ss_seg_data);
-	stack32 = 1;
-
-	flushmmucache();
-
-	cycles -= timing_call_pm;
-
-	optype = 0;
+    int ret = sysexit(fetchdat);
 
+    if (ret <= 1) {
+	CLOCK_CYCLES(20);
+	PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
+	PREFETCH_FLUSH();
 	CPU_BLOCK_END();
+    }
 
-#ifdef SYSEXIT_LOG
-	x386_dynarec_log("SYSEXIT completed:\n");
-	x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
-	x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
-	x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
-	x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32, ECX, EDX);
-#endif
-
-	return 0;
+    return ret;
 }
 
-static int opFXSAVESTOR_a16(uint32_t fetchdat)
+
+static int
+opFXSAVESTOR_a16(uint32_t fetchdat)
 {
 	uint8_t fxinst = 0;
 	uint16_t twd = x87_gettag();
diff --git a/src/cpu_common/x86_ops_misc.h b/src/cpu_common/x86_ops_misc.h
index b1a836085..16a628fd1 100644
--- a/src/cpu_common/x86_ops_misc.h
+++ b/src/cpu_common/x86_ops_misc.h
@@ -607,20 +607,18 @@ static int opF7_l_a32(uint32_t fetchdat)
 
 static int opHLT(uint32_t fetchdat)
 {
-	in_hlt = 0;
-
         if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
         {
                 x86gpf(NULL,0);
                 return 1;
         }
-        if (!((cpu_state.flags & I_FLAG) && pic_intpending))
+	if (smi_line)
+		enter_smm_check(1);
+        else if (!((cpu_state.flags & I_FLAG) && pic_intpending))
         {
                 CLOCK_CYCLES_ALWAYS(100);
-		if (!((cpu_state.flags & I_FLAG) && pic_intpending)) {
-			in_hlt = 1;
+		if (!((cpu_state.flags & I_FLAG) && pic_intpending))
                 	cpu_state.pc--;
-		}
         }
         else
                 CLOCK_CYCLES(5);
@@ -959,7 +957,7 @@ static int opRSM(uint32_t fetchdat)
         {
                	leave_smm();
 		if (smi_latched)
-			enter_smm();
+			enter_smm(smm_in_hlt);
                 CPU_BLOCK_END();
                 return 0;
         }
diff --git a/src/cpu_common/x86_ops_mmx_arith.h b/src/cpu_common/x86_ops_mmx_arith.h
index 22c34c738..3b9e2066c 100644
--- a/src/cpu_common/x86_ops_mmx_arith.h
+++ b/src/cpu_common/x86_ops_mmx_arith.h
@@ -491,6 +491,7 @@ static int opPSUBD_a32(uint32_t fetchdat)
 static int opPSUBSB_a16(uint32_t fetchdat)
 {
         MMX_REG src;
+	pclog("opPSUBSB_a16(%08X)\n", fetchdat);
         MMX_ENTER();
         
         fetch_ea_16(fetchdat);
@@ -510,6 +511,7 @@ static int opPSUBSB_a16(uint32_t fetchdat)
 static int opPSUBSB_a32(uint32_t fetchdat)
 {
         MMX_REG src;
+	pclog("opPSUBSB_a32(%08X)\n", fetchdat);
         MMX_ENTER();
         
         fetch_ea_32(fetchdat);
diff --git a/src/cpu_common/x86_ops_mov_ctrl.h b/src/cpu_common/x86_ops_mov_ctrl.h
index 569fb4dce..c1c9b623f 100644
--- a/src/cpu_common/x86_ops_mov_ctrl.h
+++ b/src/cpu_common/x86_ops_mov_ctrl.h
@@ -139,6 +139,8 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
                 case 4:
                 if (cpu_has_feature(CPU_FEATURE_CR4))
                 {
+			if (cpu_state.regs[cpu_rm].l & 0x00000020)
+				fatal("PAE enable\n");
                         cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
                         break;
                 }
diff --git a/src/cpu_common/x87.h b/src/cpu_common/x87.h
index be30c280c..cb7751fe6 100644
--- a/src/cpu_common/x87.h
+++ b/src/cpu_common/x87.h
@@ -51,7 +51,7 @@ void x87_settag(uint16_t new_tag);
 
 void codegen_set_rounding_mode(int mode);
 #else
-#define TAG_EMPTY  0
+#define TAG_EMPTY  3
 #define TAG_VALID  (1 << 0)
 /*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
 #define TAG_UINT64 (1 << 2)
diff --git a/src/cpu_common/x87_ops.h b/src/cpu_common/x87_ops.h
index 061a23019..b1975e2d6 100644
--- a/src/cpu_common/x87_ops.h
+++ b/src/cpu_common/x87_ops.h
@@ -483,8 +483,8 @@ typedef union
         } while (0)
 #endif
 
-// #ifdef USE_NEW_DYNAREC
-#if 1
+#ifdef USE_NEW_DYNAREC
+#define FP_CHECKTOP64 cpu_state.tag[cpu_state.TOP&7] & TAG_UINT64
 #define FP_TAG() cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
 #define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
 #define FP_LSTAG()  cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64;
@@ -512,6 +512,7 @@ typedef union
 #define FP_686
 #endif
 #else
+#define FP_CHECKTOP64 cpu_state.tag[cpu_state.TOP] & TAG_UINT64
 #define FP_TAG() cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
 #define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
 #define FP_LSTAG()  cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
diff --git a/src/cpu_common/x87_ops_loadstore.h b/src/cpu_common/x87_ops_loadstore.h
index 925fe87bd..a4fa12ec4 100644
--- a/src/cpu_common/x87_ops_loadstore.h
+++ b/src/cpu_common/x87_ops_loadstore.h
@@ -185,7 +185,7 @@ static int FISTPiq_a16(uint32_t fetchdat)
         FP_ENTER();
         fetch_ea_16(fetchdat);
 	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
+        if (FP_CHECKTOP64)
                 FP_LSRETQ()
         else
                 temp64 = x87_fround(ST(0));
@@ -201,7 +201,7 @@ static int FISTPiq_a32(uint32_t fetchdat)
         FP_ENTER();
         fetch_ea_32(fetchdat);
 	SEG_CHECK_WRITE(cpu_state.ea_seg);
-        if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
+        if (FP_CHECKTOP64)
                 FP_LSRETQ()
         else
                 temp64 = x87_fround(ST(0));
diff --git a/src/cpu_new/x86seg.c b/src/cpu_new/x86seg.c
index 48e3233e9..f8738e824 100644
--- a/src/cpu_new/x86seg.c
+++ b/src/cpu_new/x86seg.c
@@ -382,12 +382,17 @@ int loadseg(uint16_t seg, x86seg *s)
                 {
                         if (!(seg&~3))
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Zero stack segment",seg&~3);
                                 return 1;
                         }
-                        if ((seg&3)!=CPL || dpl!=CPL)
+                        if ((seg&3)!=CPL)
                         {
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
+                                return 1;
+                        }
+                        if (dpl!=CPL)
+                        {
+                                x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
                                 return 1;
                         }
                         switch ((segdat[2]>>8)&0x1F)
@@ -395,7 +400,7 @@ int loadseg(uint16_t seg, x86seg *s)
                                 case 0x12: case 0x13: case 0x16: case 0x17: /*r/w*/
                                 break;
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Unknown stack segment type",seg&~3);
                                 return 1;
                         }
                         if (!(segdat[2]&0x8000))
@@ -414,16 +419,21 @@ int loadseg(uint16_t seg, x86seg *s)
                                 case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
                                 case 0x14: case 0x15: case 0x16: case 0x17:
                                 case 0x1A: case 0x1B: /*Readable non-conforming code*/
-                                if ((seg&3)>dpl || (CPL)>dpl)
+                                if ((seg&3)>dpl)
                                 {
-                                        x86gpf(NULL,seg&~3);
+                                        x86gpf("loadseg(): Normal segment RPL > DPL",seg&~3);
+                                        return 1;
+                                }
+                                if ((CPL)>dpl)
+                                {
+                                        x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
                                         return 1;
                                 }
                                 break;
                                 case 0x1E: case 0x1F: /*Readable conforming code*/
                                 break;
                                 default:
-                                x86gpf(NULL,seg&~3);
+                                x86gpf("loadseg(): Unknown normal segment type",seg&~3);
                                 return 1;
                         }
                 }
diff --git a/src/include/86box/mem.h b/src/include/86box/mem.h
index 167755a2d..429d98652 100644
--- a/src/include/86box/mem.h
+++ b/src/include/86box/mem.h
@@ -63,6 +63,7 @@
 #define MEM_GRANULARITY_MASK	(MEM_GRANULARITY_SIZE - 1)
 #define MEM_GRANULARITY_HMASK	((1 << (MEM_GRANULARITY_BITS - 1)) - 1)
 #define MEM_GRANULARITY_QMASK	((1 << (MEM_GRANULARITY_BITS - 2)) - 1)
+#define MEM_GRANULARITY_PMASK	((1 << (MEM_GRANULARITY_BITS - 3)) - 1)
 #define MEM_MAPPINGS_NO		((0x100000 >> MEM_GRANULARITY_BITS) << 12)
 #define MEM_GRANULARITY_PAGE	(MEM_GRANULARITY_MASK & ~0xfff)
 #else
@@ -73,6 +74,7 @@
 #define MEM_GRANULARITY_MASK	(MEM_GRANULARITY_SIZE - 1)
 #define MEM_GRANULARITY_HMASK	((1 << (MEM_GRANULARITY_BITS - 1)) - 1)
 #define MEM_GRANULARITY_QMASK	((1 << (MEM_GRANULARITY_BITS - 2)) - 1)
+#define MEM_GRANULARITY_PMASK	((1 << (MEM_GRANULARITY_BITS - 3)) - 1)
 #define MEM_MAPPINGS_NO		((0x100000 >> MEM_GRANULARITY_BITS) << 12)
 #define MEM_GRANULARITY_PAGE	(MEM_GRANULARITY_MASK & ~0xfff)
 #endif
@@ -233,7 +235,8 @@ void writememql(uint32_t addr, uint64_t val);
 #endif
 
 extern uint8_t	*getpccache(uint32_t a);
-extern uint32_t	mmutranslatereal(uint32_t addr, int rw);
+extern uint64_t	mmutranslatereal(uint32_t addr, int rw);
+extern uint32_t	mmutranslatereal32(uint32_t addr, int rw);
 extern void	addreadlookup(uint32_t virt, uint32_t phys);
 extern void	addwritelookup(uint32_t virt, uint32_t phys);
 
@@ -300,7 +303,7 @@ extern void	mem_write_nulll(uint32_t addr, uint32_t val, void *p);
 
 extern int	mem_addr_is_ram(uint32_t addr);
 
-extern uint32_t	mmutranslate_noabrt(uint32_t addr, int rw);
+extern uint64_t	mmutranslate_noabrt(uint32_t addr, int rw);
 
 extern void	mem_invalidate_range(uint32_t start_addr, uint32_t end_addr);
 
@@ -331,6 +334,8 @@ extern void	mem_remap_top(int kb);
 #ifdef EMU_CPU_H
 static __inline uint32_t get_phys(uint32_t addr)
 {
+    uint64_t pa64;
+
     if (!((addr ^ get_phys_virt) & ~0xfff))
 	return get_phys_phys | (addr & 0xfff);
 
@@ -344,7 +349,12 @@ static __inline uint32_t get_phys(uint32_t addr)
     if (((int) (readlookup2[addr >> 12])) != -1)
 	get_phys_phys = ((uintptr_t)readlookup2[addr >> 12] + (addr & ~0xfff)) - (uintptr_t)ram;
     else {
-	get_phys_phys = (mmutranslatereal(addr, 0) & rammask) & ~0xfff;
+	pa64 = mmutranslatereal(addr, 0);
+	if (pa64 > 0xffffffffULL)
+		get_phys_phys = 0xffffffff;
+	else
+		get_phys_phys = (uint32_t) pa64;
+	get_phys_phys = (get_phys_phys & rammask) & ~0xfff;
 	if (!cpu_state.abrt && mem_addr_is_ram(get_phys_phys))
 		addreadlookup(get_phys_virt, get_phys_phys);
     }
@@ -355,7 +365,8 @@ static __inline uint32_t get_phys(uint32_t addr)
 
 static __inline uint32_t get_phys_noabrt(uint32_t addr)
 {
-    uint32_t phys_addr;
+    uint64_t phys_addr;
+    uint32_t phys_addr32;
 
     if (!(cr0 >> 31))
 	return addr & rammask;
@@ -363,11 +374,16 @@ static __inline uint32_t get_phys_noabrt(uint32_t addr)
     if (((int) (readlookup2[addr >> 12])) != -1)
 	return ((uintptr_t)readlookup2[addr >> 12] + addr) - (uintptr_t)ram;
 
-    phys_addr = mmutranslate_noabrt(addr, 0) & rammask;
-    if (phys_addr != 0xffffffff && mem_addr_is_ram(phys_addr))
-	addreadlookup(addr, phys_addr);
+    phys_addr = mmutranslate_noabrt(addr, 0);
+    phys_addr32 = (uint32_t) phys_addr;
+    if ((phys_addr != 0xffffffffffffffffULL) && (phys_addr <= 0xffffffffULL) &&
+	mem_addr_is_ram(phys_addr32 & rammask))
+	addreadlookup(addr, phys_addr32 & rammask);
 
-    return phys_addr;
+    if (phys_addr > 0xffffffffULL)
+	phys_addr32 = 0xffffffff;
+
+    return phys_addr32;
 }
 #endif
 
diff --git a/src/mem.c b/src/mem.c
index 600cd106a..3075e3721 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -288,14 +288,16 @@ mem_flush_write_page(uint32_t addr, uint32_t virt)
 #define mmutranslate_read(addr) mmutranslatereal(addr,0)
 #define mmutranslate_write(addr) mmutranslatereal(addr,1)
 #define rammap(x)	((uint32_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK]
+#define rammap64(x)	((uint64_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK]
 
-uint32_t
-mmutranslatereal(uint32_t addr, int rw)
+static uint64_t
+mmutranslatereal_normal(uint32_t addr, int rw)
 {
     uint32_t temp,temp2,temp3;
     uint32_t addr2;
 
-    if (cpu_state.abrt) return -1;
+    if (cpu_state.abrt)
+	return 0xffffffffffffffffULL;
 
     addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
     temp = temp2 = rammap(addr2);
@@ -306,7 +308,7 @@ mmutranslatereal(uint32_t addr, int rw)
 	if (rw) temp |= 2;
 	cpu_state.abrt = ABRT_PF;
 	abrt_error = temp;
-	return -1;
+	return 0xffffffffffffffffULL;
     }
 
     if ((temp & 0x80) && (cr4 & CR4_PSE)) {
@@ -321,7 +323,7 @@ mmutranslatereal(uint32_t addr, int rw)
 		cpu_state.abrt = ABRT_PF;
 		abrt_error = temp;
 
-		return -1;
+		return 0xffffffffffffffffULL;
 	}
 
 	mmu_perm = temp & 4;
@@ -339,36 +341,129 @@ mmutranslatereal(uint32_t addr, int rw)
 	if (rw) temp |= 2;
 	cpu_state.abrt = ABRT_PF;
 	abrt_error = temp;
-	return -1;
+	return 0xffffffffffffffffULL;
     }
 
     mmu_perm = temp & 4;
     rammap(addr2) |= 0x20;
     rammap((temp2 & ~0xfff) + ((addr >> 10) & 0xffc)) |= (rw?0x60:0x20);
 
-    return (temp&~0xfff)+(addr&0xfff);
+    return (uint64_t) ((temp&~0xfff)+(addr&0xfff));
 }
 
 
+static uint64_t
+mmutranslatereal_pae(uint32_t addr, int rw)
+{
+    uint64_t temp,temp2,temp3;
+    uint64_t addr2,addr3,addr4;
+
+    if (cpu_state.abrt)
+	return 0xffffffffffffffffULL;
+
+    addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
+    temp = temp2 = rammap64(addr2);
+    if (! (temp&1)) {
+	cr2 = addr;
+	temp &= 1;
+	if (CPL == 3) temp |= 4;
+	if (rw) temp |= 2;
+	cpu_state.abrt = ABRT_PF;
+	abrt_error = temp;
+	return 0xffffffffffffffffULL;
+    }
+
+    addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
+    temp = rammap64(addr3);
+    temp3 = temp & temp2;
+    if (! (temp&1)) {
+	cr2 = addr;
+	temp &= 1;
+	if (CPL == 3) temp |= 4;
+	if (rw) temp |= 2;
+	cpu_state.abrt = ABRT_PF;
+	abrt_error = temp;
+	return 0xffffffffffffffffULL;
+    }
+
+    if (temp & 0x80) {
+	/*4MB page*/
+	if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3 && !cpl_override) || cr0 & WP_FLAG))) {
+		cr2 = addr;
+		temp &= 1;
+		if (CPL == 3)
+			temp |= 4;
+		if (rw)
+			temp |= 2;
+		cpu_state.abrt = ABRT_PF;
+		abrt_error = temp;
+
+		return 0xffffffffffffffffULL;
+	}
+	mmu_perm = temp & 4;
+	rammap64(addr3) |= 0x20;
+
+	return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
+    }
+
+    addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
+    temp = rammap64(addr4);
+    temp3 = temp3 & temp2;
+    if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && ((CPL == 3 && !cpl_override) || cr0&WP_FLAG))) {
+	cr2 = addr;
+	temp &= 1;
+	if (CPL == 3) temp |= 4;
+	if (rw) temp |= 2;
+	cpu_state.abrt = ABRT_PF;
+	abrt_error = temp;
+	return 0xffffffffffffffffULL;
+    }
+
+    mmu_perm = temp & 4;
+    rammap64(addr3) |= 0x20;
+    rammap64(addr4) |= (rw? 0x60 : 0x20);
+
+    return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff)))& 0x0000000fffffffffULL;
+}
+
+
+uint64_t
+mmutranslatereal(uint32_t addr, int rw)
+{
+    if (cr4 & CR4_PAE)
+	return mmutranslatereal_pae(addr, rw);
+    else
+	return mmutranslatereal_normal(addr, rw);
+}
+
+
+/* This is needed because the old recompiler calls this to check for page fault. */
 uint32_t
-mmutranslate_noabrt(uint32_t addr, int rw)
+mmutranslatereal32(uint32_t addr, int rw)
+{
+    return (uint32_t) mmutranslatereal(addr, rw);
+}
+
+
+static uint64_t
+mmutranslate_noabrt_normal(uint32_t addr, int rw)
 {
     uint32_t temp,temp2,temp3;
     uint32_t addr2;
 
     if (cpu_state.abrt) 
-	return -1;
+	return 0xffffffffffffffffULL;
 
     addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
     temp = temp2 = rammap(addr2);
 
     if (! (temp & 1))
-	return -1;
+	return 0xffffffffffffffffULL;
 
     if ((temp & 0x80) && (cr4 & CR4_PSE)) {
 	/*4MB page*/
 	if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (CPL == 3 || cr0 & WP_FLAG)))
-		return -1;
+		return 0xffffffffffffffffULL;
 
 	return (temp & ~0x3fffff) + (addr & 0x3fffff);
     }
@@ -377,9 +472,60 @@ mmutranslate_noabrt(uint32_t addr, int rw)
     temp3 = temp & temp2;
 
     if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && (CPL==3 || cr0&WP_FLAG)))
-	return -1;
+	return 0xffffffffffffffffULL;
 
-    return (temp & ~0xfff) + (addr & 0xfff);
+    return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
+}
+
+
+static uint64_t
+mmutranslate_noabrt_pae(uint32_t addr, int rw)
+{
+    uint32_t temp,temp2,temp3;
+    uint32_t addr2,addr3,addr4;
+
+    if (cpu_state.abrt) 
+	return 0xffffffffffffffffULL;
+
+    addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
+    temp = temp2 = rammap64(addr2);
+
+    if (! (temp & 1))
+	return 0xffffffffffffffffULL;
+
+    addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
+    temp = rammap64(addr3);
+    temp3 = temp & temp2;
+
+    if (! (temp & 1))
+	return 0xffffffffffffffffULL;
+
+    if (temp & 0x80) {
+	/*2MB page*/
+	if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (CPL == 3 || cr0 & WP_FLAG)))
+		return 0xffffffffffffffffULL;
+
+	return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
+    }
+
+    addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
+    temp = rammap64(addr4);
+    temp3 = temp3 & temp2;
+
+    if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && (CPL==3 || cr0&WP_FLAG)))
+	return 0xffffffffffffffffULL;
+
+    return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff))) & 0x0000000fffffffffULL;
+}
+
+
+uint64_t
+mmutranslate_noabrt(uint32_t addr, int rw)
+{
+    if (cr4 & CR4_PAE)
+	return mmutranslate_noabrt_pae(addr, rw);
+    else
+	return mmutranslate_noabrt_normal(addr, rw);
 }
 
 
@@ -467,29 +613,30 @@ addwritelookup(uint32_t virt, uint32_t phys)
 uint8_t *
 getpccache(uint32_t a)
 {
+    uint64_t a64 = (uint64_t) a;
     uint32_t a2;
 
     a2 = a;
 
     if (cr0 >> 31) {
-	a = mmutranslate_read(a);
+	a64 = mmutranslate_read(a64);
 
-	if (a == 0xffffffff) return ram;
+	if (a64 == 0xffffffffffffffffULL) return ram;
     }
-    a &= rammask;
+    a64 &= rammask;
 
-    if (_mem_exec[a >> MEM_GRANULARITY_BITS]) {
+    if (_mem_exec[a64 >> MEM_GRANULARITY_BITS]) {
 	if (is286) {
-		if (read_mapping[a >> MEM_GRANULARITY_BITS] && (read_mapping[a >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM))
+		if (read_mapping[a64 >> MEM_GRANULARITY_BITS] && (read_mapping[a64 >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM))
 			cpu_prefetch_cycles = cpu_rom_prefetch_cycles;
 		else
 			cpu_prefetch_cycles = cpu_mem_prefetch_cycles;
 	}
 	
-	return &_mem_exec[a >> MEM_GRANULARITY_BITS][(uintptr_t)(a & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)];
+	return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t)(a64 & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)];
     }
 
-    mem_log("Bad getpccache %08X\n", a);
+    mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a >> 32), (uint32_t) (a & 0xffffffff));
 
 #if FIXME
     return &ff_array[0-(uintptr_t)(a2 & ~0xfff)];
@@ -502,15 +649,19 @@ getpccache(uint32_t a)
 uint8_t
 readmembl(uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
 
     if (cr0 >> 31) {
-	addr = mmutranslate_read(addr);
-	if (addr == 0xffffffff) return 0xff;
+	addr64 = mmutranslate_read(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return 0xff;
+	if (addr64 > 0xffffffffULL)
+		return 0xff;
     }
-    addr &= rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map && map->read_b)
@@ -523,6 +674,7 @@ readmembl(uint32_t addr)
 void
 writemembl(uint32_t addr, uint8_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     mem_logical_addr = addr;
 
@@ -532,11 +684,13 @@ writemembl(uint32_t addr, uint8_t val)
     }
 
     if (cr0 >> 31) {
-	addr = mmutranslate_write(addr);
-	if (addr == 0xffffffff)
+	addr64 = mmutranslate_write(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
 		return;
     }
-    addr &= rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map && map->write_b)
@@ -548,18 +702,19 @@ writemembl(uint32_t addr, uint8_t val)
 uint16_t
 readmemwl(uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
 
-    if (addr & 1) {
-	if (!cpu_cyrix_alignment || (addr & 7) == 7)
+    if (addr64 & 1) {
+	if (!cpu_cyrix_alignment || (addr64 & 7) == 7)
 		sub_cycles(timing_misaligned);
-	if ((addr & 0xfff) > 0xffe) {
+	if ((addr64 & 0xfff) > 0xffe) {
 		if (cr0 >> 31) {
-			if (mmutranslate_read(addr)   == 0xffffffff)
+			if (mmutranslate_read(addr)   == 0xffffffffffffffffULL)
 				return 0xffff;
-			if (mmutranslate_read(addr+1) == 0xffffffff)
+			if (mmutranslate_read(addr+1) == 0xffffffffffffffffULL)
 				return 0xffff;
 		}
 		return readmembl(addr)|(readmembl(addr+1)<<8);
@@ -567,12 +722,14 @@ readmemwl(uint32_t addr)
 		return *(uint16_t *)(readlookup2[addr >> 12] + addr);
     }
     if (cr0>>31) {
-	addr = mmutranslate_read(addr);
-	if (addr == 0xffffffff)
+	addr64 = mmutranslate_read(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return 0xffff;
+	if (addr64 > 0xffffffffULL)
 		return 0xffff;
     }
 
-    addr &= rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr >> MEM_GRANULARITY_BITS];
 
@@ -589,6 +746,7 @@ readmemwl(uint32_t addr)
 void
 writememwl(uint32_t addr, uint16_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -617,12 +775,14 @@ writememwl(uint32_t addr, uint16_t val)
 	return;
     }
     if (cr0>>31) {
-	addr = mmutranslate_write(addr);
-	if (addr==0xFFFFFFFF)
+	addr64 = mmutranslate_write(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
 		return;
     }
 
-    addr &= rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map) {
@@ -639,6 +799,7 @@ writememwl(uint32_t addr, uint16_t val)
 uint32_t
 readmemll(uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -646,11 +807,11 @@ readmemll(uint32_t addr)
     if (addr & 3) {
 	if (!cpu_cyrix_alignment || (addr & 7) > 4)
 		sub_cycles(timing_misaligned);
-	if ((addr&0xFFF)>0xFFC) {
+	if ((addr & 0xfff) > 0xffc) {
 		if (cr0>>31) {
-			if (mmutranslate_read(addr)   == 0xffffffff)
+			if (mmutranslate_read(addr)   == 0xffffffffffffffffULL)
 				return 0xffffffff;
-			if (mmutranslate_read(addr+3) == 0xffffffff)
+			if (mmutranslate_read(addr+3) == 0xffffffffffffffffULL)
 				return 0xffffffff;
 		}
 		return readmemwl(addr)|(readmemwl(addr+2)<<16);
@@ -658,13 +819,15 @@ readmemll(uint32_t addr)
 		return *(uint32_t *)(readlookup2[addr >> 12] + addr);
     }
 
-    if (cr0>>31) {
-	addr = mmutranslate_read(addr);
-	if (addr==0xFFFFFFFF)
-		return 0xFFFFFFFF;
+    if (cr0 >> 31) {
+	addr64 = mmutranslate_read(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return 0xffffffff;
+	if (addr64 > 0xffffffffULL)
+		return 0xffffffff;
     }
 
-    addr&=rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map) {
@@ -686,6 +849,7 @@ readmemll(uint32_t addr)
 void
 writememll(uint32_t addr, uint32_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -695,9 +859,9 @@ writememll(uint32_t addr, uint32_t val)
 		sub_cycles(timing_misaligned);
 	if ((addr & 0xFFF) > 0xFFC) {
 		if (cr0>>31) {
-			if (mmutranslate_write(addr)   == 0xffffffff)
+			if (mmutranslate_write(addr)   == 0xffffffffffffffffULL)
 				return;
-			if (mmutranslate_write(addr+3) == 0xffffffff)
+			if (mmutranslate_write(addr+3) == 0xffffffffffffffffULL)
 				return;
 		}
 		writememwl(addr,val);
@@ -713,12 +877,14 @@ writememll(uint32_t addr, uint32_t val)
 	return;
     }
     if (cr0>>31) {
-	addr = mmutranslate_write(addr);
-	if (addr==0xFFFFFFFF)
+	addr64 = mmutranslate_write(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
 		return;
     }
 
-    addr&=rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map) {
@@ -740,6 +906,7 @@ writememll(uint32_t addr, uint32_t val)
 uint64_t
 readmemql(uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -748,10 +915,10 @@ readmemql(uint32_t addr)
 	sub_cycles(timing_misaligned);
 	if ((addr & 0xFFF) > 0xFF8) {
 		if (cr0>>31) {
-			if (mmutranslate_read(addr)   == 0xffffffff)
-				return 0xffffffff;
-			if (mmutranslate_read(addr+7) == 0xffffffff)
-				return 0xffffffff;
+			if (mmutranslate_read(addr)   == 0xffffffffffffffffULL)
+				return 0xffffffffffffffffULL;
+			if (mmutranslate_read(addr+7) == 0xffffffffffffffffULL)
+				return 0xffffffffffffffffULL;
 		}
 		return readmemll(addr)|((uint64_t)readmemll(addr+4)<<32);
 	} else if (readlookup2[addr >> 12] != -1)
@@ -759,12 +926,14 @@ readmemql(uint32_t addr)
     }
 
     if (cr0>>31) {
-	addr = mmutranslate_read(addr);
-	if (addr==0xFFFFFFFF)
-		return 0xFFFFFFFF;
+	addr64 = mmutranslate_read(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return 0xffffffffffffffffULL;
+	if (addr64 > 0xffffffffULL)
+		return 0xffffffffffffffffULL;
     }
 
-    addr&=rammask;
+    addr  = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map && map->read_l)
@@ -777,6 +946,7 @@ readmemql(uint32_t addr)
 void
 writememql(uint32_t addr, uint64_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -785,9 +955,9 @@ writememql(uint32_t addr, uint64_t val)
 	sub_cycles(timing_misaligned);
 	if ((addr & 0xFFF) > 0xFF8) {
 		if (cr0>>31) {
-			if (mmutranslate_write(addr)   == 0xffffffff)
+			if (mmutranslate_write(addr)   == 0xffffffffffffffffULL)
 				return;
-			if (mmutranslate_write(addr+7) == 0xffffffff)
+			if (mmutranslate_write(addr+7) == 0xffffffffffffffffULL)
 				return;
 		}
 		writememll(addr, val);
@@ -804,12 +974,14 @@ writememql(uint32_t addr, uint64_t val)
 	return;
     }
     if (cr0>>31) {
-	addr = mmutranslate_write(addr);
-	if (addr==0xFFFFFFFF)
+	addr64 = mmutranslate_write(addr);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
 		return;
     }
 
-    addr&=rammask;
+    addr = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr >> MEM_GRANULARITY_BITS];
     if (map) {
@@ -851,6 +1023,7 @@ writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
 uint16_t
 readmemwl(uint32_t seg, uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -859,9 +1032,9 @@ readmemwl(uint32_t seg, uint32_t addr)
 		sub_cycles(timing_misaligned);
 	if ((addr2 & 0xfff) > 0xffe) {
 		if (cr0 >> 31) {
-			if (mmutranslate_read(addr2)   == 0xffffffff)
+			if (mmutranslate_read(addr2)   == 0xffffffffffffffffULL)
 				return 0xffff;
-			if (mmutranslate_read(addr2+1) == 0xffffffff)
+			if (mmutranslate_read(addr2+1) == 0xffffffffffffffffULL)
 				return 0xffff;
 		}
 		if (is386) return readmemb386l(seg,addr)|(((uint16_t) readmemb386l(seg,addr+1))<<8);
@@ -872,12 +1045,15 @@ readmemwl(uint32_t seg, uint32_t addr)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_read(addr2);
-	if (addr2 == 0xffffffff)
+	addr64 = mmutranslate_read(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
 		return 0xffff;
-    }
+	if (addr64 > 0xffffffffULL)
+		return 0xffff;
+    } else
+	addr64 = (uint64_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
 
@@ -900,6 +1076,7 @@ readmemwl(uint32_t seg, uint32_t addr)
 void
 writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -908,8 +1085,8 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 		sub_cycles(timing_misaligned);
 	if ((addr2 & 0xFFF) > 0xffe) {
 		if (cr0 >> 31) {
-			if (mmutranslate_write(addr2)   == 0xffffffff) return;
-			if (mmutranslate_write(addr2+1) == 0xffffffff) return;
+			if (mmutranslate_write(addr2)   == 0xffffffffffffffffULL) return;
+			if (mmutranslate_write(addr2+1) == 0xffffffffffffffffULL) return;
 		}
 		if (is386) {
 			writememb386l(seg,addr,val);
@@ -931,11 +1108,15 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_write(addr2);
-	if (addr2 == 0xffffffff) return;
-    }
+	addr64 = mmutranslate_write(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
+		return;
+    } else
+	addr64 = (uint64_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
 
@@ -955,6 +1136,7 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 uint32_t
 readmemll(uint32_t seg, uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -963,8 +1145,8 @@ readmemll(uint32_t seg, uint32_t addr)
 		sub_cycles(timing_misaligned);
 	if ((addr2 & 0xfff) > 0xffc) {
 		if (cr0 >> 31) {
-			if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
-			if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
+			if (mmutranslate_read(addr2)   == 0xffffffffffffffffULL) return 0xffffffff;
+			if (mmutranslate_read(addr2+3) == 0xffffffffffffffffULL) return 0xffffffff;
 		}
 		return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
 	} else if (readlookup2[addr2 >> 12] != (uintptr_t) -1)
@@ -972,12 +1154,15 @@ readmemll(uint32_t seg, uint32_t addr)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_read(addr2);
-	if (addr2 == 0xffffffff)
+	addr64 = mmutranslate_read(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
 		return 0xffffffff;
-    }
+	if (addr64 > 0xffffffffULL)
+		return 0xffffffff;
+    } else
+	addr64 = (uint64_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
 
@@ -1001,6 +1186,7 @@ readmemll(uint32_t seg, uint32_t addr)
 void
 writememll(uint32_t seg, uint32_t addr, uint32_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1009,8 +1195,8 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
 		sub_cycles(timing_misaligned);
 	if ((addr2 & 0xfff) > 0xffc) {
 		if (cr0 >> 31) {
-			if (mmutranslate_write(addr2)   == 0xffffffff) return;
-			if (mmutranslate_write(addr2+3) == 0xffffffff) return;
+			if (mmutranslate_write(addr2)   == 0xffffffffffffffffULL) return;
+			if (mmutranslate_write(addr2+3) == 0xffffffffffffffffULL) return;
 		}
 		writememwl(seg,addr,val);
 		writememwl(seg,addr+2,val>>16);
@@ -1027,11 +1213,15 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_write(addr2);
-	if (addr2 == 0xffffffff) return;
-    }
+	addr64 = mmutranslate_write(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
+		return;
+    } else
+	addr64 = (uint32_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
 
@@ -1057,6 +1247,7 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
 uint64_t
 readmemql(uint32_t seg, uint32_t addr)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1064,8 +1255,8 @@ readmemql(uint32_t seg, uint32_t addr)
 	sub_cycles(timing_misaligned);
 	if ((addr2 & 0xfff) > 0xff8) {
 		if (cr0 >> 31) {
-			if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
-			if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
+			if (mmutranslate_read(addr2)   == 0xffffffffffffffffULL) return 0xffffffffffffffffULL;
+			if (mmutranslate_read(addr2+7) == 0xffffffffffffffffULL) return 0xffffffffffffffffULL;
 		}
 		return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
 	} else if (readlookup2[addr2 >> 12] != (uintptr_t) -1)
@@ -1073,12 +1264,15 @@ readmemql(uint32_t seg, uint32_t addr)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_read(addr2);
-	if (addr2 == 0xffffffff)
-		return -1;
-    }
+	addr64 = mmutranslate_read(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
+		return 0xffffffffffffffffULL;
+	if (addr64 > 0xffffffffULL)
+		return 0xffffffffffffffffULL;
+    } else
+	addr64 = (uint64_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
     if (map && map->read_l)
@@ -1091,6 +1285,7 @@ readmemql(uint32_t seg, uint32_t addr)
 void
 writememql(uint32_t seg, uint32_t addr, uint64_t val)
 {
+    uint64_t addr64 = (uint64_t) addr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1098,8 +1293,8 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
 	sub_cycles(timing_misaligned);
 	if ((addr2 & 0xfff) > 0xff8) {
 		if (cr0 >> 31) {
-			if (mmutranslate_write(addr2)   == 0xffffffff) return;
-			if (mmutranslate_write(addr2+7) == 0xffffffff) return;
+			if (mmutranslate_write(addr2)   == 0xffffffffffffffffULL) return;
+			if (mmutranslate_write(addr2+7) == 0xffffffffffffffffULL) return;
 		}
 		writememll(seg, addr, val);
 		writememll(seg, addr+4, val >> 32);
@@ -1117,11 +1312,15 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
     }
 
     if (cr0 >> 31) {
-	addr2 = mmutranslate_write(addr2);
-	if (addr2 == 0xffffffff) return;
-    }
+	addr64 = mmutranslate_write(addr2);
+	if (addr64 == 0xffffffffffffffffULL)
+		return;
+	if (addr64 > 0xffffffffULL)
+		return;
+    } else
+	addr64 = (uint64_t) addr2;
 
-    addr2 &= rammask;
+    addr2 = (uint32_t) (addr64 & rammask);
 
     map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
 
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index 85e2850fb..311d50036 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -38,8 +38,8 @@ ifeq ($(DEV_BUILD), y)
  ifndef DEV_BRANCH
   DEV_BRANCH	:= y
  endif
- ifndef AMD_K
-  AMD_K		:= y
+ ifndef AMD_K5
+  AMD_K5	:= y
  endif
  ifndef CL5422
   CL5422	:= y
@@ -108,8 +108,8 @@ else
  ifndef DEV_BRANCH
   DEV_BRANCH	:= n
  endif
- ifndef AMD_K
-  AMD_K		:= n
+ ifndef AMD_K5
+  AMD_K5	:= n
  endif
  ifndef CL5422
   CL5422	:= n
@@ -377,10 +377,9 @@ OPTS		+= -DUSE_DYNAREC
 RFLAGS		+= -DUSE_DYNAREC
 DYNARECOBJ	:= 386_dynarec_ops.o \
 		    codegen.o \
-		    codegen_ops.o \
-		    codegen_timing_common.o codegen_timing_486.o \
-		    codegen_timing_686.o codegen_timing_pentium.o \
-		    codegen_timing_winchip.o $(PLATCG)
+		    codegen_ops.o codegen_timing_486.o \
+		    codegen_timing_686.o codegen_timing_common.o codegen_timing_k6.o codegen_timing_pentium.o \
+		    codegen_timing_p6.o codegen_timing_winchip.o codegen_timing_winchip2.o $(PLATCG)
 endif
 
 ifneq ($(WX), n)
@@ -453,8 +452,8 @@ ifeq ($(DEV_BRANCH), y)
 OPTS		+= -DDEV_BRANCH
 DEVBROBJ	:=
 
-ifeq ($(AMD_K), y)
-OPTS		+= -DUSE_AMD_K
+ifeq ($(AMD_K5), y)
+OPTS		+= -DUSE_AMD_K5
 endif
 
 ifeq ($(CL5422), y)
@@ -548,7 +547,11 @@ CFLAGS		:= $(WX_FLAGS) $(OPTS) $(DFLAGS) $(COPTIM) $(AOPTIM) \
 # -funroll-loops
 
 # Add freetyp2 references through pkgconfig
+ifeq ($(DEBUG), y)
+CFLAGS          := $(CFLAGS) -fstack-protector-all  `pkg-config --cflags freetype2`
+else
 CFLAGS          := $(CFLAGS)  `pkg-config --cflags freetype2`
+endif
 
 CXXFLAGS	:= $(CFLAGS)
 
@@ -738,6 +741,9 @@ endif
 
 LIBS		:= -mwindows -lcomctl32 \
 		   -lopenal -lole32
+ifeq ($(DEBUG), y)
+ LIBS    += -lssp
+endif
 
 ifeq ($(D2D), y)
 LIBS		+= $(D2DLIB)
@@ -821,8 +827,10 @@ pcap_if.res:	pcap_if.rc
 
 pcap_if.exe:	pcap_if.o win_dynld.o pcap_if.res
 		@echo Linking pcap_if.exe ..
+ifeq ($(DEBUG), y)
+		@$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res -lssp
+else
 		@$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res
-ifneq ($(DEBUG), y)
 		@$(STRIP) pcap_if.exe
 endif
 
diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw
index 077ccfdd9..8a61d111e 100644
--- a/src/win/Makefile_ndr.mingw
+++ b/src/win/Makefile_ndr.mingw
@@ -38,8 +38,8 @@ ifeq ($(DEV_BUILD), y)
  ifndef DEV_BRANCH
   DEV_BRANCH	:= y
  endif
- ifndef AMD_K
-  AMD_K		:= y
+ ifndef AMD_K5
+  AMD_K5	:= y
  endif
  ifndef CL5422
   CL5422	:= y
@@ -108,8 +108,8 @@ else
  ifndef DEV_BRANCH
   DEV_BRANCH	:= n
  endif
- ifndef AMD_K
-  AMD_K		:= n
+ ifndef AMD_K5
+  AMD_K5	:= n
  endif
  ifndef CL5422
   CL5422	:= n
@@ -461,8 +461,8 @@ ifeq ($(DEV_BRANCH), y)
 OPTS		+= -DDEV_BRANCH
 DEVBROBJ	:=
 
-ifeq ($(AMD_K), y)
-OPTS		+= -DUSE_AMD_K
+ifeq ($(AMD_K5), y)
+OPTS		+= -DUSE_AMD_K5
 endif
 
 ifeq ($(CL5422), y)
diff --git a/src/win/win_new_floppy.c b/src/win/win_new_floppy.c
index 05fd207cc..1dd3aa2c1 100644
--- a/src/win/win_new_floppy.c
+++ b/src/win/win_new_floppy.c
@@ -51,8 +51,8 @@ typedef struct {
 } disk_size_t;
 
 
-static const disk_size_t disk_sizes[14] = {	{	0,  1, 2, 1, 0,  40,  8, 2, 0xfe, 2, 2,  1, 112 },		/* 160k */
-						{	0,  1, 2, 1, 0,  40,  9, 2, 0xfc, 2, 2,  1, 112 },		/* 180k */
+static const disk_size_t disk_sizes[14] = {	{	0,  1, 2, 1, 0,  40,  8, 2, 0xfe, 2, 2,  1,  64 },		/* 160k */
+						{	0,  1, 2, 1, 0,  40,  9, 2, 0xfc, 2, 2,  1,  64 },		/* 180k */
 						{	0,  2, 2, 1, 0,  40,  8, 2, 0xff, 2, 2,  1, 112 },		/* 320k */
 						{	0,  2, 2, 1, 0,  40,  9, 2, 0xfd, 2, 2,  2, 112 },		/* 360k */
 						{	0,  2, 2, 1, 0,  80,  8, 2, 0xfb, 2, 2,  2, 112 },		/* 640k */