Added the LG IBM Multinet i x7G (MSI MS-6119), fixed the ASUS P2B-LS, and some SiS 551x fixes.

src/chipset/sis_5511.c

@@ -820,13 +820,13 @@ sis_5511_reset(void *priv)
     dev->pci_conf_sb[0][0x40] = 0x00;
     dev->pci_conf_sb[0][0x41] = dev->pci_conf_sb[0][0x42] = 0x80;
     dev->pci_conf_sb[0][0x43] = dev->pci_conf_sb[0][0x44] = 0x80;
-    dev->pci_conf_sb[0][0x48] = dev->pci_conf_sb[0][0x49] = 0x80;
+    dev->pci_conf_sb[0][0x48] = dev->pci_conf_sb[0][0x49] = 0x00;
-    dev->pci_conf_sb[0][0x4a] = dev->pci_conf_sb[0][0x4b] = 0x80;
+    dev->pci_conf_sb[0][0x4a] = dev->pci_conf_sb[0][0x4b] = 0x00;
-    dev->pci_conf_sb[0][0x60] = dev->pci_conf_sb[0][0x51] = 0x80;
+    dev->pci_conf_sb[0][0x60] = dev->pci_conf_sb[0][0x61] = 0x80;
     dev->pci_conf_sb[0][0x62] = 0x00;
     dev->pci_conf_sb[0][0x63] = 0x80;
     dev->pci_conf_sb[0][0x64] = 0x00;
-    dev->pci_conf_sb[0][0x65] = 0x80;
+    dev->pci_conf_sb[0][0x65] = 0x00;
     dev->pci_conf_sb[0][0x66] = dev->pci_conf_sb[0][0x67] = 0x00;
     dev->pci_conf_sb[0][0x68] = dev->pci_conf_sb[0][0x69] = 0x00;
     dev->pci_conf_sb[0][0x6a] = 0x04;

src/include/86box/machine.h

@@ -733,6 +733,7 @@ extern int machine_at_mate_nx_ma30d_23d_init(const machine_t *);
 extern int machine_at_p6i440e2_init(const machine_t *);
 
 extern int machine_at_p2bls_init(const machine_t *);
+extern int machine_at_lgibm440bx_init(const machine_t *);
 extern int machine_at_p3bf_init(const machine_t *);
 extern int machine_at_bf6_init(const machine_t *);
 extern int machine_at_ax6bc_init(const machine_t *);

src/machine/m_at_slot1.c

@@ -236,21 +236,13 @@ machine_at_p2bls_init(const machine_t *model)
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
-    // pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
+    pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
-    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
+    pci_register_slot(0x06, PCI_CARD_SCSI,        4, 1, 2, 3);
-    // pci_register_slot(0x06, PCI_CARD_SCSI,        4, 1, 2, 3);
+    pci_register_slot(0x07, PCI_CARD_NETWORK,     3, 4, 1, 2);
-    // pci_register_slot(0x07, PCI_CARD_NETWORK,     3, 4, 1, 2);
-#if 0
     pci_register_slot(0x0B, PCI_CARD_NORMAL,      2, 3, 4, 1);
     pci_register_slot(0x0C, PCI_CARD_NORMAL,      1, 2, 3, 4);
     pci_register_slot(0x09, PCI_CARD_NORMAL,      4, 1, 2, 3);
     pci_register_slot(0x0A, PCI_CARD_NORMAL,      3, 4, 1, 2);
-#else
-    pci_register_slot(0x0E, PCI_CARD_NORMAL,      1, 2, 3, 4);
-    pci_register_slot(0x10, PCI_CARD_NORMAL,      2, 3, 4, 1);
-    pci_register_slot(0x12, PCI_CARD_NORMAL,      3, 4, 1, 2);
-    pci_register_slot(0x14, PCI_CARD_NORMAL,      4, 1, 2, 3);
-#endif
     pci_register_slot(0x01, PCI_CARD_AGPBRIDGE,   1, 2, 3, 4);
     device_add(&i440bx_device);
     device_add(&piix4e_device);
@@ -261,9 +253,40 @@ machine_at_p2bls_init(const machine_t *model)
 #endif
     device_add(&sst_flash_39sf020_device);
     spd_register(SPD_TYPE_SDRAM, 0xF, 256);
-    // device_add(&w83781d_device);     /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
+    device_add(&w83781d_device);     /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
-    // hwm_values.temperatures[1] = 0;  /* unused */
+    hwm_values.temperatures[1] = 0;  /* unused */
-    // hwm_values.temperatures[2] -= 3; /* CPU offset */
+    hwm_values.temperatures[2] -= 3; /* CPU offset */
+
+    return ret;
+}
+
+int
+machine_at_lgibm440bx_init(const machine_t *model)
+{
+    int ret;
+
+    ret = bios_load_linear("roms/machines/lgibm440bx/ms6119.331",
+                           0x000c0000, 262144, 0);
+
+    if (bios_only || !ret)
+        return ret;
+
+    machine_at_common_init_ex(model, 2);
+
+    pci_init(PCI_CONFIG_TYPE_1);
+    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
+    pci_register_slot(0x0E, PCI_CARD_NORMAL,      1, 2, 3, 4);
+    pci_register_slot(0x10, PCI_CARD_NORMAL,      2, 3, 4, 1);
+    pci_register_slot(0x12, PCI_CARD_NORMAL,      3, 4, 1, 2);
+    pci_register_slot(0x14, PCI_CARD_NORMAL,      4, 1, 2, 3);
+    pci_register_slot(0x01, PCI_CARD_AGPBRIDGE,   1, 2, 3, 4);
+    device_add(&i440bx_device);
+    device_add(&piix4e_device);
+    device_add(&keyboard_ps2_ami_pci_device);
+    device_add(&w83977tf_device);
+    device_add(&winbond_flash_w29c020_device);
+    spd_register(SPD_TYPE_SDRAM, 0x7, 256);
 
     return ret;
 }

src/machine/machine_table.c

@@ -12484,6 +12484,46 @@ const machine_t machines[] = {
         .snd_device = NULL,
         .net_device = NULL
     },
+    /* Has the AMIKey-2 (updated 'H') KBC firmware. */
+    {
+        .name = "[i440BX] LG IBM Multinet i x7G (MSI MS-6119)",
+        .internal_name = "lgibm440bx",
+        .type = MACHINE_TYPE_SLOT1,
+        .chipset = MACHINE_CHIPSET_INTEL_440BX,
+        .init = machine_at_lgibm440bx_init,
+        .p1_handler = NULL,
+        .gpio_handler = NULL,
+        .available_flag = MACHINE_AVAILABLE,
+        .gpio_acpi_handler = NULL,
+        .cpu = {
+            .package = CPU_PKG_SLOT1,
+            .block = CPU_BLOCK_NONE,
+            .min_bus = 50000000,
+            .max_bus = 112121212,
+            .min_voltage = 1300,
+            .max_voltage = 3500,
+            .min_multi = 1.5,
+            .max_multi = 8.0
+        },
+        .bus_flags = MACHINE_PS2_AGP,
+        .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI,
+        .ram = {
+            .min = 8192,
+            .max = 1048576,
+            .step = 8192
+        },
+        .nvrmask = 255,
+        .kbc_device = NULL,
+        .kbc_p1 = 0xff,
+        .gpio = 0xffffffff,
+        .gpio_acpi = 0xffffffff,
+        .device = NULL,
+        .fdc_device = NULL,
+        .sio_device = NULL,
+        .vid_device = NULL,
+        .snd_device = NULL,
+        .net_device = NULL
+    },
     /* Has a National Semiconductors PC87309 Super I/O chip with on-chip KBC
        with most likely AMIKey-2 KBC firmware. */
     {

src/pit.c

@@ -659,12 +659,13 @@ pit_read_reg(void *priv, uint8_t reg)
             break;
         case 0x07:
             /* The SiS 551x datasheet is unclear about how exactly
-               this register is structured. */
+               this register is structured.
+               Update: But the SiS 5571 datasheet is clear. */
             ret = (dev->counters[0].rm & 0x80) ? 0x01 : 0x00;
-            ret = (dev->counters[0].wm & 0x80) ? 0x02 : 0x00;
+            ret = (dev->counters[1].rm & 0x80) ? 0x02 : 0x00;
-            ret = (dev->counters[1].rm & 0x80) ? 0x04 : 0x00;
+            ret = (dev->counters[2].rm & 0x80) ? 0x04 : 0x00;
-            ret = (dev->counters[1].wm & 0x80) ? 0x08 : 0x00;
+            ret = (dev->counters[0].wm & 0x80) ? 0x08 : 0x00;
-            ret = (dev->counters[2].rm & 0x80) ? 0x10 : 0x00;
+            ret = (dev->counters[1].wm & 0x80) ? 0x10 : 0x00;
             ret = (dev->counters[2].wm & 0x80) ? 0x20 : 0x00;
             break;
     }