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Make sure timers don't go completely out of sync upon altering TSC via WRMSR

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This commit is contained in:
Cacodemon345
2024-06-18 20:05:44 +06:00
parent 382b941ff9
commit 2b3d3ad5bd
3 changed files with 38 additions and 6 deletions
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13
src/cpu/cpu.c
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@@ -40,6 +40,7 @@
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/gdbstub.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
@@ -3492,7 +3493,7 @@ cpu_WRMSR(void)
break;
/* Time Stamp Counter */
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* Performance Monitor - Control and Event Select */
case 0x11:
@@ -3568,7 +3569,7 @@ cpu_WRMSR(void)
break;
/* Time Stamp Counter */
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* PERFCTR0 - Performance Counter Register 0 - aliased to TSC */
case 0xc1:
@@ -3664,7 +3665,7 @@ cpu_WRMSR(void)
break;
/* Time Stamp Counter */
case 0x00000010:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* Array Access Register */
case 0x00000082:
@@ -3834,7 +3835,7 @@ amd_k_invalid_wrmsr:
/* Time Stamp Counter */
case 0x00000010:
case 0x80000010:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* Performance Monitor - Control and Event Select */
case 0x00000011:
@@ -3919,7 +3920,7 @@ pentium_invalid_wrmsr:
msr.tr5 = EAX & 0x008f0f3b;
/* Time Stamp Counter */
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* Performance Monitor - Control and Event Select */
case 0x11:
@@ -3952,7 +3953,7 @@ pentium_invalid_wrmsr:
break;
/* Time Stamp Counter */
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
timer_set_new_tsc(EAX | ((uint64_t) EDX << 32));
break;
/* Unknown */
case 0x18: