diff --git a/src/chipset/via_vpx.c b/src/chipset/via_vpx.c index 5985f8493..c9798e319 100644 --- a/src/chipset/via_vpx.c +++ b/src/chipset/via_vpx.c @@ -1,22 +1,25 @@ /* - - 86Box A hypervisor and IBM PC system emulator that specializes in - running old operating systems and software designed for IBM - PC systems and compatibles from 1981 through fairly recent - system designs based on the PCI bus. - - - -VIA Apollo VPX North Bridge emulation - -VT82C585VPX used in the Zida Tomato TX100 board -based on the model of VIA MVP3 by mooch & Sarah - -Authors: Sarah Walker, -Copyright(C) 2020 Tiseno100 -Copyright(C) 2020 Melissa Goad -Copyright(C) 2020 Miran Grca - +* +* 86Box A hypervisor and IBM PC system emulator that specializes in +* running old operating systems and software designed for IBM +* PC systems and compatibles from 1981 through fairly recent +* system designs based on the PCI bus. +* +* +* +* VIA Apollo VPX North Bridge emulation +* +* VT82C585VPX used in the FIC VA-502 board +* based on the model of VIA MVP3 by mooch & Sarah +* +* There's also a SOYO board using the ETEQ chipset which is a rebranded +* VPX + 586B but fails to save on CMOS properly. +* +* Authors: Sarah Walker, +* Copyright(C) 2020 Tiseno100 +* Copyright(C) 2020 Melissa Goad +* Copyright(C) 2020 Miran Grca +* */ #include @@ -35,7 +38,7 @@ Copyright(C) 2020 Miran Grca typedef struct via_vpx_t { - uint8_t pci_conf[2][256]; + uint8_t pci_conf[256]; } via_vpx_t; static void @@ -60,109 +63,73 @@ vpx_map(uint32_t addr, uint32_t size, int state) } static void -via_vpx_pci_regs(via_vpx_t *dev) -{ - memset(dev, 0, sizeof(via_vpx_t)); - -// Host Bridge registers - - dev->pci_conf[0][0x00] = 0x06; // VIA - dev->pci_conf[0][0x01] = 0x11; - - dev->pci_conf[0][0x02] = 0x85; // VT82C585VPX - dev->pci_conf[0][0x03] = 0x05; - - dev->pci_conf[0][0x04] = 7; // Command - dev->pci_conf[0][0x05] = 0; - - dev->pci_conf[0][0x06] = 0xa0; // Status - dev->pci_conf[0][0x07] = 2; - - dev->pci_conf[0][0x09] = 0; // Program Interface - - dev->pci_conf[0][0x0a] = 0; // Sub Class Code - - dev->pci_conf[0][0x0b] = 6; // Base Class Code - - dev->pci_conf[0][0x0c] = 0; // reserved - - dev->pci_conf[0][0x0d] = 0; // Latency Timer - - dev->pci_conf[0][0x0e] = 0; // Header Type - - dev->pci_conf[0][0x0f] = 0; // Built-in Self test - - dev->pci_conf[0][0x58] = 0x40; // DRAM Configuration 1 - dev->pci_conf[0][0x59] = 5; // DRAM Configuration 2 - - dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending - dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending - dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending - dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending - dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending - dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending - - dev->pci_conf[0][0x64] = 0xab; // DRAM reference timing - -} - -static void -host_bridge_write(int func, int addr, uint8_t val, void *priv) +via_vpx_write(int func, int addr, uint8_t val, void *priv) { via_vpx_t *dev = (via_vpx_t *) priv; - // Read-Only registers. Exact same as MVP3 - if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) || - ((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) || - ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd))) - return; + // Read-Only registers + switch(addr){ + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x08: case 0x09: case 0x0a: case 0x0b: + case 0x0e: case 0x0f: + return; + } switch(addr){ - case 0x04: // Command - dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40); + case 0x04: + // Bitfield 6: Parity Error Response + // Bitfield 8: SERR# Enable + // Bitfield 9: Fast Back-to-Back Cycle Enable + if(dev->pci_conf[0x04] && 0x40){ //Bitfield 6 + dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40); + } else if(dev->pci_conf[0x04] && 0x100){ //Bitfield 8 + dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x100) | (val & 0x100); + } else if(dev->pci_conf[0x04] && 0x200){ //Bitfield 9 + dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x200) | (val & 0x200); + } + break; case 0x07: // Status - dev->pci_conf[0][0x07] &= ~(val & 0xb0); + dev->pci_conf[0x07] &= ~(val & 0xb0); break; case 0x61: // Shadow RAM control 1 - if ((dev->pci_conf[0][0x61] ^ val) & 0x03) + if ((dev->pci_conf[0x61] ^ val) & 0x03) vpx_map(0xc0000, 0x04000, val & 0x03); - if ((dev->pci_conf[0][0x61] ^ val) & 0x0c) + if ((dev->pci_conf[0x61] ^ val) & 0x0c) vpx_map(0xc4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->pci_conf[0][0x61] ^ val) & 0x30) + if ((dev->pci_conf[0x61] ^ val) & 0x30) vpx_map(0xc8000, 0x04000, (val & 0x30) >> 4); - if ((dev->pci_conf[0][0x61] ^ val) & 0xc0) + if ((dev->pci_conf[0x61] ^ val) & 0xc0) vpx_map(0xcc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0][0x61] = val; + dev->pci_conf[0x61] = val; return; case 0x62: // Shadow RAM Control 2 - if ((dev->pci_conf[0][0x62] ^ val) & 0x03) + if ((dev->pci_conf[0x62] ^ val) & 0x03) vpx_map(0xd0000, 0x04000, val & 0x03); - if ((dev->pci_conf[0][0x62] ^ val) & 0x0c) + if ((dev->pci_conf[0x62] ^ val) & 0x0c) vpx_map(0xd4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->pci_conf[0][0x62] ^ val) & 0x30) + if ((dev->pci_conf[0x62] ^ val) & 0x30) vpx_map(0xd8000, 0x04000, (val & 0x30) >> 4); - if ((dev->pci_conf[0][0x62] ^ val) & 0xc0) + if ((dev->pci_conf[0x62] ^ val) & 0xc0) vpx_map(0xdc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0][0x62] = val; + dev->pci_conf[0x62] = val; return; case 0x63: // Shadow RAM Control 3 - if ((dev->pci_conf[0][0x63] ^ val) & 0x30) { + if ((dev->pci_conf[0x63] ^ val) & 0x30) { vpx_map(0xf0000, 0x10000, (val & 0x30) >> 4); shadowbios = (((val & 0x30) >> 4) & 0x02); } - if ((dev->pci_conf[0][0x63] ^ val) & 0xc0) + if ((dev->pci_conf[0x63] ^ val) & 0xc0) vpx_map(0xe0000, 0x10000, (val & 0xc0) >> 6); - dev->pci_conf[0][0x63] = val; + dev->pci_conf[0x63] = val; return; - //In case we throw somewhere default: - dev->pci_conf[0][addr] = val; + dev->pci_conf[addr] = val; break; } } @@ -175,19 +142,13 @@ via_vpx_read(int func, int addr, void *priv) switch(func) { case 0: - ret = dev->pci_conf[0][addr]; + ret = dev->pci_conf[addr]; break; } return ret; } -static void -via_vpx_write(int func, int addr, uint8_t val, void *priv) -{ - host_bridge_write(func, addr, val, priv); -} - static void via_vpx_reset(void *priv) { @@ -198,10 +159,49 @@ static void * via_vpx_init(const device_t *info) { via_vpx_t *dev = (via_vpx_t *) malloc(sizeof(via_vpx_t)); + memset(dev, 0, sizeof(via_vpx_t)); pci_add_card(PCI_ADD_NORTHBRIDGE, via_vpx_read, via_vpx_write, dev); - via_vpx_pci_regs(dev); + dev->pci_conf[0x00] = 0x06; // VIA + dev->pci_conf[0x01] = 0x11; + + dev->pci_conf[0x02] = 0x85; // VT82C585VPX + dev->pci_conf[0x03] = 0x05; + + dev->pci_conf[0x04] = 7; // Command + dev->pci_conf[0x05] = 0; + + dev->pci_conf[0x06] = 0xa0; // Status + dev->pci_conf[0x07] = 2; + + dev->pci_conf[0x08] = 0; // Silicon Rev. + + dev->pci_conf[0x09] = 0; // Program Interface + + dev->pci_conf[0x0a] = 0; // Sub Class Code + + dev->pci_conf[0x0b] = 6; // Base Class Code + + dev->pci_conf[0x0c] = 0; // reserved + + dev->pci_conf[0x0d] = 0; // Latency Timer + + dev->pci_conf[0x0e] = 0; // Header Type + + dev->pci_conf[0x0f] = 0; // Built-in Self test + + dev->pci_conf[0x58] = 0x40; // DRAM Configuration 1 + dev->pci_conf[0x59] = 0x05; // DRAM Configuration 2 + + dev->pci_conf[0x5a] = 1; // Bank 0 Ending + dev->pci_conf[0x5b] = 1; // Bank 1 Ending + dev->pci_conf[0x5c] = 1; // Bank 2 Ending + dev->pci_conf[0x5d] = 1; // Bank 3 Ending + dev->pci_conf[0x5e] = 1; // Bank 4 Ending + dev->pci_conf[0x5f] = 1; // Bank 5 Ending + + dev->pci_conf[0x64] = 0xab; // DRAM reference timing return dev; } diff --git a/src/cpu/codegen_timing_p6.c b/src/cpu/codegen_timing_p6.c index ec5c54640..a69f68f04 100644 --- a/src/cpu/codegen_timing_p6.c +++ b/src/cpu/codegen_timing_p6.c @@ -19,8 +19,8 @@ typedef enum uop_type_t { - UOP_ALU = 0, /*Executes in Integer X or Y units*/ - UOP_ALUX, /*Executes in Integer X unit*/ + UOP_ALU = 0, /*Executes in Port 0 or 1 ALU units*/ + UOP_ALUP0, /*Executes in Port 0 ALU unit*/ UOP_LOAD, /*Executes in Load unit*/ UOP_STORED, /*Executes in Data Store unit*/ UOP_STOREA, /*Executes in Address Store unit*/ @@ -31,11 +31,11 @@ typedef enum uop_type_t UOP_MSTORED, /*Executes in Data Store unit*/ UOP_MSTOREA, /*Executes in Address Store unit*/ UOP_FLOAT, /*Executes in Floating Point unit*/ - UOP_MMX, /*Executes in Integer X or Y units as MMX*/ - UOP_MMX_SHIFT, /*Executes in Integer Y unit. Uses MMX shifter*/ - UOP_MMX_MUL, /*Executes in Integer X unit. Uses MMX multiplier*/ + UOP_MMX, /*Executes in Port 0 or 1 ALU units as MMX*/ + UOP_MMX_SHIFT, /*Executes in Port 1 ALU unit. Uses MMX shifter*/ + UOP_MMX_MUL, /*Executes in Port 0 ALU unit. Uses MMX multiplier*/ UOP_BRANCH, /*Executes in Branch unit*/ - UOP_LIMM /*Does not require an execution unit*/ + UOP_FXCH /*Does not require an execution unit*/ } uop_type_t; typedef enum decode_type_t @@ -46,46 +46,46 @@ typedef enum decode_type_t #define MAX_UOPS 10 -typedef struct risc86_uop_t +typedef struct p6_uop_t { uop_type_t type; - double latency; -} risc86_uop_t; + int latency; +} p6_uop_t; -typedef struct risc86_instruction_t +typedef struct macro_op_t { int nr_uops; decode_type_t decode_type; - risc86_uop_t uop[MAX_UOPS]; -} risc86_instruction_t; + p6_uop_t uop[MAX_UOPS]; +} macro_op_t; -static const risc86_instruction_t alu_op = +static const macro_op_t alu_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t alux_op = +static const macro_op_t alup0_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t load_alu_op = +static const macro_op_t load_alu_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t load_alux_op = +static const macro_op_t load_alup0_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t alu_store_op = +static const macro_op_t alu_store_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -94,38 +94,38 @@ static const risc86_instruction_t alu_store_op = .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t alux_store_op = +static const macro_op_t alup0_store_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t branch_op = +static const macro_op_t branch_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_BRANCH, .latency = 1} + .uop[0] = {.type = UOP_BRANCH, .latency = 2} }; -static const risc86_instruction_t limm_op = +static const macro_op_t fxch_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_LIMM, .latency = 1} + .uop[0] = {.type = UOP_FXCH, .latency = 1} }; -static const risc86_instruction_t load_op = +static const macro_op_t load_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t store_op = +static const macro_op_t store_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, @@ -134,14 +134,14 @@ static const risc86_instruction_t store_op = }; -static const risc86_instruction_t bswap_op = +static const macro_op_t bswap_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1}, }; -static const risc86_instruction_t leave_op = +static const macro_op_t leave_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -149,27 +149,27 @@ static const risc86_instruction_t leave_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t lods_op = +static const macro_op_t lods_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t loop_op = +static const macro_op_t loop_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, - .uop[1] = {.type = UOP_BRANCH, .latency = 1} + .uop[1] = {.type = UOP_BRANCH, .latency = 2} }; -static const risc86_instruction_t mov_reg_seg_op = +static const macro_op_t mov_reg_seg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, }; -static const risc86_instruction_t movs_op = +static const macro_op_t movs_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -178,14 +178,14 @@ static const risc86_instruction_t movs_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t pop_reg_op = +static const macro_op_t pop_reg_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t pop_mem_op = +static const macro_op_t pop_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -194,14 +194,14 @@ static const risc86_instruction_t pop_mem_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t push_imm_op = +static const macro_op_t push_imm_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_STORED, .latency = 1}, .uop[1] = {.type = UOP_STOREA, .latency = 1}, }; -static const risc86_instruction_t push_mem_op = +static const macro_op_t push_mem_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -209,7 +209,7 @@ static const risc86_instruction_t push_mem_op = .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t push_seg_op = +static const macro_op_t push_seg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -218,7 +218,7 @@ static const risc86_instruction_t push_seg_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t stos_op = +static const macro_op_t stos_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -226,33 +226,33 @@ static const risc86_instruction_t stos_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_reg_op = -{ - .nr_uops = 1, - .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_ALU, .latency = 1} -}; -static const risc86_instruction_t test_reg_b_op = +static const macro_op_t test_reg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_mem_imm_op = +static const macro_op_t test_reg_b_op = +{ + .nr_uops = 1, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} +}; +static const macro_op_t test_mem_imm_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_mem_imm_b_op = +static const macro_op_t test_mem_imm_b_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t xchg_op = +static const macro_op_t xchg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -262,98 +262,98 @@ static const risc86_instruction_t xchg_op = }; -static const risc86_instruction_t mmx_op = +static const macro_op_t mmx_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX, .latency = 1.5} + .uop[0] = {.type = UOP_MMX, .latency = 1} }; -static const risc86_instruction_t mmx_mul_op = +static const macro_op_t mmx_mul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_MUL, .latency = 1} }; -static const risc86_instruction_t mmx_shift_op = +static const macro_op_t mmx_shift_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1} }; -static const risc86_instruction_t load_mmx_op = +static const macro_op_t load_mmx_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_MMX, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX, .latency = 2} }; -static const risc86_instruction_t load_mmx_mul_op = +static const macro_op_t load_mmx_mul_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_MUL, .latency = 2} }; -static const risc86_instruction_t load_mmx_shift_op = +static const macro_op_t load_mmx_shift_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 2} }; -static const risc86_instruction_t mload_op = +static const macro_op_t mload_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_MLOAD, .latency = 3}, + .uop[0] = {.type = UOP_MLOAD, .latency = 1}, }; -static const risc86_instruction_t mstore_op = +static const macro_op_t mstore_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_MSTORED, .latency = 1}, .uop[1] = {.type = UOP_MSTOREA, .latency = 1} }; -static const risc86_instruction_t pmul_op = +static const macro_op_t pmul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_MUL, .latency = 1} }; -static const risc86_instruction_t pmul_mem_op = +static const macro_op_t pmul_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_MUL, .latency = 2} }; -static const risc86_instruction_t float_op = +static const macro_op_t float_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fadd_op = +static const macro_op_t fadd_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_FLOAT, .latency = 3} + .uop[0] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t fmul_op = +static const macro_op_t fmul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_ALU, .latency = 5} + .uop[0] = {.type = UOP_ALUP0, .latency = 3} }; -static const risc86_instruction_t float2_op = +static const macro_op_t float2_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 1}, .uop[1] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fchs_op = +static const macro_op_t fchs_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -361,35 +361,35 @@ static const risc86_instruction_t fchs_op = .uop[1] = {.type = UOP_FLOAT, .latency = 2}, .uop[2] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t load_float_op = +static const macro_op_t load_float_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, .uop[1] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t load_fadd_op = +static const macro_op_t load_fadd_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, - .uop[1] = {.type = UOP_FLOAT, .latency = 3} + .uop[1] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t load_fmul_op = +static const macro_op_t load_fmul_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 5} + .uop[1] = {.type = UOP_ALU, .latency = 4} }; -static const risc86_instruction_t fstore_op = +static const macro_op_t fstore_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FSTORED, .latency = 1}, .uop[1] = {.type = UOP_FSTOREA, .latency = 1}, }; -static const risc86_instruction_t load_fiadd_op = +static const macro_op_t load_fiadd_op = { .nr_uops = 7, .decode_type = DECODE_COMPLEX, @@ -401,51 +401,51 @@ static const risc86_instruction_t load_fiadd_op = .uop[5] = {.type = UOP_FLOAT, .latency = 1}, .uop[6] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fdiv_op = +static const macro_op_t fdiv_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_FLOAT, .latency = 32} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_FLOAT, .latency = 37} }; -static const risc86_instruction_t fdiv_mem_op = +static const macro_op_t fdiv_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, - .uop[1] = {.type = UOP_FLOAT, .latency = 38} + .uop[1] = {.type = UOP_FLOAT, .latency = 37} }; -static const risc86_instruction_t fsin_op = +static const macro_op_t fsin_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_FLOAT, .latency = 60} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_FLOAT, .latency = 62} }; -static const risc86_instruction_t fsqrt_op = +static const macro_op_t fsqrt_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 69} }; -static const risc86_instruction_t complex_fldcw_op = +static const macro_op_t fldcw_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 10} }; -static const risc86_instruction_t complex_float_op = +static const macro_op_t complex_float_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t complex_float_l_op = +static const macro_op_t complex_float_l_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 50} }; -static const risc86_instruction_t complex_flde_op = +static const macro_op_t flde_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -453,7 +453,7 @@ static const risc86_instruction_t complex_flde_op = .uop[1] = {.type = UOP_FLOAD, .latency = 1}, .uop[2] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t complex_fste_op = +static const macro_op_t fste_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -462,20 +462,20 @@ static const risc86_instruction_t complex_fste_op = .uop[2] = {.type = UOP_FSTOREA, .latency = 1} }; -static const risc86_instruction_t complex_alu1_op = +static const macro_op_t complex_alu1_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu2_op = +static const macro_op_t alu2_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu3_op = +static const macro_op_t alu3_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -483,7 +483,7 @@ static const risc86_instruction_t complex_alu3_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu6_op = +static const macro_op_t alu6_op = { .nr_uops = 6, .decode_type = DECODE_COMPLEX, @@ -494,57 +494,39 @@ static const risc86_instruction_t complex_alu6_op = .uop[4] = {.type = UOP_ALU, .latency = 1}, .uop[5] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alux1_op = +static const macro_op_t complex_alup0_1_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alux3_op = +static const macro_op_t alup0_3_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alux6_op = +static const macro_op_t alup0_6_op = { .nr_uops = 6, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1}, - .uop[3] = {.type = UOP_ALUX, .latency = 1}, - .uop[4] = {.type = UOP_ALUX, .latency = 1}, - .uop[5] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1}, + .uop[3] = {.type = UOP_ALUP0, .latency = 1}, + .uop[4] = {.type = UOP_ALUP0, .latency = 1}, + .uop[5] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alu_store_op = -{ - .nr_uops = 4, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1}, -}; -static const risc86_instruction_t complex_alux_store_op = -{ - .nr_uops = 4, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1} -}; -static const risc86_instruction_t complex_arpl_op = +static const macro_op_t arpl_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3}, .uop[1] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_bound_op = +static const macro_op_t bound_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -553,13 +535,13 @@ static const risc86_instruction_t complex_bound_op = .uop[2] = {.type = UOP_ALU, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_bsx_op = +static const macro_op_t bsx_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 10} }; -static const risc86_instruction_t complex_call_far_op = +static const macro_op_t call_far_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -568,13 +550,13 @@ static const risc86_instruction_t complex_call_far_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_cli_sti_op = +static const macro_op_t cli_sti_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 7} }; -static const risc86_instruction_t complex_cmps_op = +static const macro_op_t cmps_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -582,15 +564,15 @@ static const risc86_instruction_t complex_cmps_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_cmpsb_op = +static const macro_op_t cmpsb_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_cmpxchg_op = +static const macro_op_t cmpxchg_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -599,54 +581,62 @@ static const risc86_instruction_t complex_cmpxchg_op = .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t complex_cmpxchg_b_op = +static const macro_op_t cmpxchg_b_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_STORED, .latency = 1}, + .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t complex_cpuid_op = +static const macro_op_t complex_push_mem_op = +{ + .nr_uops = 2, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_STORED, .latency = 1}, + .uop[1] = {.type = UOP_STOREA, .latency = 1} +}; + +static const macro_op_t cpuid_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 23} }; -static const risc86_instruction_t complex_div16_op = +static const macro_op_t div16_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 10} + .uop[0] = {.type = UOP_ALUP0, .latency = 21} }; -static const risc86_instruction_t complex_div16_mem_op = +static const macro_op_t div16_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 10} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 21} }; -static const risc86_instruction_t complex_div32_op = +static const macro_op_t div32_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 18} + .uop[0] = {.type = UOP_ALUP0, .latency = 37} }; -static const risc86_instruction_t complex_div32_mem_op = +static const macro_op_t div32_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 18} + .uop[1] = {.type = UOP_ALUP0, .latency = 37} }; -static const risc86_instruction_t complex_emms_op = +static const macro_op_t emms_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALU, .latency = 25} + .uop[0] = {.type = UOP_ALU, .latency = 50} }; -static const risc86_instruction_t complex_enter_op = +static const macro_op_t enter_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -654,28 +644,28 @@ static const risc86_instruction_t complex_enter_op = .uop[1] = {.type = UOP_STOREA, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 10} }; -static const risc86_instruction_t complex_femms_op = +static const macro_op_t femms_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 6} }; -static const risc86_instruction_t complex_in_op = +static const macro_op_t in_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 10} + .uop[0] = {.type = UOP_LOAD, .latency = 18} }; -static const risc86_instruction_t complex_ins_op = +static const macro_op_t ins_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 10}, + .uop[0] = {.type = UOP_LOAD, .latency = 18}, .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_int_op = +static const macro_op_t int_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -688,7 +678,7 @@ static const risc86_instruction_t complex_int_op = .uop[6] = {.type = UOP_STOREA, .latency = 1}, .uop[7] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_iret_op = +static const macro_op_t iret_op = { .nr_uops = 5, .decode_type = DECODE_COMPLEX, @@ -698,41 +688,20 @@ static const risc86_instruction_t complex_iret_op = .uop[3] = {.type = UOP_ALU, .latency = 20}, .uop[4] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_invd_op = +static const macro_op_t invd_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 500} }; -static const risc86_instruction_t complex_jmp_far_op = +static const macro_op_t jmp_far_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3}, .uop[1] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_load_alu_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 1} -}; -static const risc86_instruction_t complex_load_alux_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} -}; -static const risc86_instruction_t complex_loop_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALU, .latency = 1}, - .uop[1] = {.type = UOP_BRANCH, .latency = 1} -}; -static const risc86_instruction_t complex_lss_op = +static const macro_op_t lss_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -740,7 +709,7 @@ static const risc86_instruction_t complex_lss_op = .uop[1] = {.type = UOP_LOAD, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mov_mem_seg_op = +static const macro_op_t mov_mem_seg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -748,68 +717,63 @@ static const risc86_instruction_t complex_mov_mem_seg_op = .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1}, }; -static const risc86_instruction_t complex_mov_seg_mem_op = +static const macro_op_t mov_seg_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mov_seg_reg_op = +static const macro_op_t mov_seg_reg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mul_op = +static const macro_op_t mul_op = +{ + .nr_uops = 1, + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} +}; +static const macro_op_t mul_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_mul_mem_op = +static const macro_op_t mul64_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_mul64_op = -{ - .nr_uops = 3, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} -}; -static const risc86_instruction_t complex_mul64_mem_op = +static const macro_op_t mul64_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1}, - .uop[3] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1}, + .uop[3] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_out_op = +static const macro_op_t out_op = { - .nr_uops = 2, + .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_STORED, .latency = 10}, - .uop[1] = {.type = UOP_STOREA, .latency = 10}, + .uop[0] = {.type = UOP_ALU, .latency = 18} }; -static const risc86_instruction_t complex_outs_op = +static const macro_op_t outs_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_STORED, .latency = 10}, - .uop[1] = {.type = UOP_STOREA, .latency = 10}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[1] = {.type = UOP_ALU, .latency = 18} }; -static const risc86_instruction_t complex_pusha_op = +static const macro_op_t pusha_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -822,7 +786,7 @@ static const risc86_instruction_t complex_pusha_op = .uop[6] = {.type = UOP_STORED, .latency = 2}, .uop[7] = {.type = UOP_STOREA, .latency = 2} }; -static const risc86_instruction_t complex_popa_op = +static const macro_op_t popa_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -835,36 +799,30 @@ static const risc86_instruction_t complex_popa_op = .uop[6] = {.type = UOP_LOAD, .latency = 1}, .uop[7] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t complex_popf_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_ALUX, .latency = 17} -}; -static const risc86_instruction_t complex_push_mem_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_STORED, .latency = 1}, - .uop[1] = {.type = UOP_STOREA, .latency = 1} -}; -static const risc86_instruction_t complex_pushf_op = +static const macro_op_t popf_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_STORED, .latency = 1}, - .uop[2] = {.type = UOP_STOREA, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALU, .latency = 6}, + .uop[2] = {.type = UOP_ALUP0, .latency = 10} }; -static const risc86_instruction_t complex_ret_op = +static const macro_op_t pushf_op = +{ + .nr_uops = 3, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_STORED, .latency = 1}, + .uop[2] = {.type = UOP_STOREA, .latency = 1} +}; +static const macro_op_t ret_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_retf_op = +static const macro_op_t retf_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -872,52 +830,52 @@ static const risc86_instruction_t complex_retf_op = .uop[1] = {.type = UOP_ALU, .latency = 3}, .uop[2] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_scas_op = +static const macro_op_t scas_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_scasb_op = +static const macro_op_t scasb_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_setcc_mem_op = +static const macro_op_t setcc_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_FSTORED, .latency = 1}, - .uop[3] = {.type = UOP_FSTOREA, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_FSTORED, .latency = 1}, + .uop[3] = {.type = UOP_FSTOREA, .latency = 1} }; -static const risc86_instruction_t complex_setcc_reg_op = +static const macro_op_t setcc_reg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_test_mem_op = +static const macro_op_t test_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_test_mem_b_op = +static const macro_op_t test_mem_b_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_xchg_mem_op = +static const macro_op_t xchg_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -926,60 +884,58 @@ static const risc86_instruction_t complex_xchg_mem_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_xlat_op = +static const macro_op_t xlat_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t complex_wbinvd_op = +static const macro_op_t wbinvd_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 10000} }; - - #define INVALID NULL -static const risc86_instruction_t *opcode_timings[256] = +static const macro_op_t *opcode_timings[256] = { /* ADD ADD ADD ADD*/ -/*00*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*00*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* ADD ADD PUSH ES POP ES*/ - &alux_op, &alu_op, &push_seg_op, &complex_mov_seg_mem_op, + &alup0_op, &alu_op, &push_seg_op, &mov_seg_mem_op, /* OR OR OR OR*/ - &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, + &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* OR OR PUSH CS */ - &alux_op, &alu_op, &push_seg_op, INVALID, + &alup0_op, &alu_op, &push_seg_op, INVALID, /* ADC ADC ADC ADC*/ -/*10*/ &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op, +/*10*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* ADC ADC PUSH SS POP SS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* SBB SBB SBB SBB*/ -/*10*/ &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op, +/*10*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* SBB SBB PUSH DS POP DS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* AND AND AND AND*/ -/*20*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*20*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* AND AND DAA*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* SUB SUB SUB SUB*/ - &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, + &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* SUB SUB DAS*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* XOR XOR XOR XOR*/ -/*30*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*30*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* XOR XOR AAA*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* CMP CMP CMP CMP*/ - &load_alux_op, &load_alu_op, &load_alux_op, &load_alu_op, + &load_alup0_op, &load_alu_op, &load_alup0_op, &load_alu_op, /* CMP CMP AAS*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* INC EAX INC ECX INC EDX INC EBX*/ /*40*/ &alu_op, &alu_op, &alu_op, &alu_op, @@ -1000,12 +956,12 @@ static const risc86_instruction_t *opcode_timings[256] = &pop_reg_op, &pop_reg_op, &pop_reg_op, &pop_reg_op, /* PUSHA POPA BOUND ARPL*/ -/*60*/ &complex_pusha_op, &complex_popa_op, &complex_bound_op, &complex_arpl_op, +/*60*/ &pusha_op, &popa_op, &bound_op, &arpl_op, INVALID, INVALID, INVALID, INVALID, /* PUSH imm IMUL PUSH imm IMUL*/ - &push_imm_op, &complex_mul_op, &push_imm_op, &complex_mul_op, + &push_imm_op, &mul_op, &push_imm_op, &mul_op, /* INSB INSW OUTSB OUTSW*/ - &complex_ins_op, &complex_ins_op, &complex_outs_op, &complex_outs_op, + &ins_op, &ins_op, &outs_op, &outs_op, /* Jxx*/ /*70*/ &branch_op, &branch_op, &branch_op, &branch_op, @@ -1015,107 +971,107 @@ static const risc86_instruction_t *opcode_timings[256] = /*80*/ INVALID, INVALID, INVALID, INVALID, /* TEST TEST XCHG XCHG*/ - &complex_test_mem_b_op, &complex_test_mem_op, &complex_xchg_mem_op, &complex_xchg_mem_op, + &test_mem_b_op, &test_mem_op, &xchg_mem_op, &xchg_mem_op, /* MOV MOV MOV MOV*/ &store_op, &store_op, &load_op, &load_op, /* MOV from seg LEA MOV to seg POP*/ - &complex_mov_mem_seg_op, &store_op, &complex_mov_seg_mem_op, &pop_mem_op, + &mov_mem_seg_op, &store_op, &mov_seg_mem_op, &pop_mem_op, /* NOP XCHG XCHG XCHG*/ -/*90*/ &limm_op, &xchg_op, &xchg_op, &xchg_op, +/*90*/ &fxch_op, &xchg_op, &xchg_op, &xchg_op, /* XCHG XCHG XCHG XCHG*/ &xchg_op, &xchg_op, &xchg_op, &xchg_op, /* CBW CWD CALL far WAIT*/ - &complex_alu1_op, &complex_alu1_op, &complex_call_far_op, &limm_op, + &complex_alu1_op, &complex_alu1_op, &call_far_op, &fxch_op, /* PUSHF POPF SAHF LAHF*/ - &complex_pushf_op, &complex_popf_op, &complex_alux1_op, &complex_alux1_op, + &pushf_op, &popf_op, &complex_alup0_1_op, &complex_alup0_1_op, /* MOV MOV MOV MOV*/ /*a0*/ &load_op, &load_op, &store_op, &store_op, /* MOVSB MOVSW CMPSB CMPSW*/ - &movs_op, &movs_op, &complex_cmpsb_op, &complex_cmps_op, + &movs_op, &movs_op, &cmpsb_op, &cmps_op, /* TEST TEST STOSB STOSW*/ &test_reg_b_op, &test_reg_op, &stos_op, &stos_op, /* LODSB LODSW SCASB SCASW*/ - &lods_op, &lods_op, &complex_scasb_op, &complex_scas_op, + &lods_op, &lods_op, &scasb_op, &scas_op, /* MOV*/ -/*b0*/ &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, +/*b0*/ &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, /* RET imm RET*/ -/*c0*/ INVALID, INVALID, &complex_ret_op, &complex_ret_op, +/*c0*/ INVALID, INVALID, &ret_op, &ret_op, /* LES LDS MOV MOV*/ - &complex_lss_op, &complex_lss_op, &store_op, &store_op, + &lss_op, &lss_op, &store_op, &store_op, /* ENTER LEAVE RETF RETF*/ - &complex_enter_op, &leave_op, &complex_retf_op, &complex_retf_op, + &enter_op, &leave_op, &retf_op, &retf_op, /* INT3 INT INTO IRET*/ - &complex_int_op, &complex_int_op, &complex_int_op, &complex_iret_op, + &int_op, &int_op, &int_op, &iret_op, /*d0*/ INVALID, INVALID, INVALID, INVALID, /* AAM AAD SETALC XLAT*/ - &complex_alux6_op, &complex_alux3_op, &complex_alux1_op, &complex_xlat_op, + &alup0_6_op, &alup0_3_op, &complex_alup0_1_op, &xlat_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, /* LOOPNE LOOPE LOOP JCXZ*/ -/*e0*/ &complex_loop_op, &complex_loop_op, &loop_op, &complex_loop_op, +/*e0*/ &loop_op, &loop_op, &loop_op, &loop_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* CALL JMP JMP JMP*/ - &store_op, &branch_op, &complex_jmp_far_op, &branch_op, + &store_op, &branch_op, &jmp_far_op, &branch_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* REPNE REPE*/ /*f0*/ INVALID, INVALID, INVALID, INVALID, /* HLT CMC*/ - &complex_alux1_op, &complex_alu2_op, INVALID, INVALID, + &complex_alup0_1_op, &alu2_op, INVALID, INVALID, /* CLC STC CLI STI*/ - &complex_alu1_op, &complex_alu1_op, &complex_cli_sti_op, &complex_cli_sti_op, + &complex_alu1_op, &complex_alu1_op, &cli_sti_op, &cli_sti_op, /* CLD STD INCDEC*/ - &complex_alu1_op, &complex_alu1_op, &alux_store_op, INVALID + &complex_alu1_op, &complex_alu1_op, &alup0_store_op, INVALID }; -static const risc86_instruction_t *opcode_timings_mod3[256] = +static const macro_op_t *opcode_timings_mod3[256] = { /* ADD ADD ADD ADD*/ -/*00*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*00*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* ADD ADD PUSH ES POP ES*/ - &alux_op, &alu_op, &push_seg_op, &complex_mov_seg_mem_op, + &alup0_op, &alu_op, &push_seg_op, &mov_seg_mem_op, /* OR OR OR OR*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* OR OR PUSH CS */ - &alux_op, &alu_op, &push_seg_op, INVALID, + &alup0_op, &alu_op, &push_seg_op, INVALID, /* ADC ADC ADC ADC*/ -/*10*/ &complex_alux1_op, &complex_alu1_op, &complex_alux1_op, &complex_alu1_op, +/*10*/ &complex_alup0_1_op, &complex_alu1_op, &complex_alup0_1_op, &complex_alu1_op, /* ADC ADC PUSH SS POP SS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* SBB SBB SBB SBB*/ - &complex_alux1_op, &complex_alu1_op, &complex_alux1_op, &complex_alu1_op, + &complex_alup0_1_op, &complex_alu1_op, &complex_alup0_1_op, &complex_alu1_op, /* SBB SBB PUSH DS POP DS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* AND AND AND AND*/ -/*20*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*20*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* AND AND DAA*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* SUB SUB SUB SUB*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* SUB SUB DAS*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* XOR XOR XOR XOR*/ -/*30*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*30*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* XOR XOR AAA*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* CMP CMP CMP CMP*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* CMP CMP AAS*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* INC EAX INC ECX INC EDX INC EBX*/ /*40*/ &alu_op, &alu_op, &alu_op, &alu_op, @@ -1136,12 +1092,12 @@ static const risc86_instruction_t *opcode_timings_mod3[256] = &pop_reg_op, &pop_reg_op, &pop_reg_op, &pop_reg_op, /* PUSHA POPA BOUND ARPL*/ -/*60*/ &complex_pusha_op, &complex_popa_op, &complex_bound_op, &complex_arpl_op, +/*60*/ &pusha_op, &popa_op, &bound_op, &arpl_op, INVALID, INVALID, INVALID, INVALID, /* PUSH imm IMUL PUSH imm IMUL*/ - &push_imm_op, &complex_mul_op, &push_imm_op, &complex_mul_op, + &push_imm_op, &mul_op, &push_imm_op, &mul_op, /* INSB INSW OUTSB OUTSW*/ - &complex_ins_op, &complex_ins_op, &complex_outs_op, &complex_outs_op, + &ins_op, &ins_op, &outs_op, &outs_op, /* Jxx*/ /*70*/ &branch_op, &branch_op, &branch_op, &branch_op, @@ -1151,88 +1107,89 @@ static const risc86_instruction_t *opcode_timings_mod3[256] = /*80*/ INVALID, INVALID, INVALID, INVALID, /* TEST TEST XCHG XCHG*/ - &complex_alu1_op, &complex_alu1_op, &complex_alu3_op, &complex_alu3_op, + &complex_alu1_op, &complex_alu1_op, &alu3_op, &alu3_op, /* MOV MOV MOV MOV*/ &store_op, &store_op, &load_op, &load_op, /* MOV from seg LEA MOV to seg POP*/ - &mov_reg_seg_op, &store_op, &complex_mov_seg_reg_op, &pop_reg_op, + &mov_reg_seg_op, &store_op, &mov_seg_reg_op, &pop_reg_op, /* NOP XCHG XCHG XCHG*/ -/*90*/ &limm_op, &xchg_op, &xchg_op, &xchg_op, +/*90*/ &fxch_op, &xchg_op, &xchg_op, &xchg_op, /* XCHG XCHG XCHG XCHG*/ &xchg_op, &xchg_op, &xchg_op, &xchg_op, /* CBW CWD CALL far WAIT*/ - &complex_alu1_op, &complex_alu1_op, &complex_call_far_op, &limm_op, + &complex_alu1_op, &complex_alu1_op, &call_far_op, &fxch_op, /* PUSHF POPF SAHF LAHF*/ - &complex_pushf_op, &complex_popf_op, &complex_alux1_op, &complex_alux1_op, + &pushf_op, &popf_op, &complex_alup0_1_op, &complex_alup0_1_op, /* MOV MOV MOV MOV*/ /*a0*/ &load_op, &load_op, &store_op, &store_op, /* MOVSB MOVSW CMPSB CMPSW*/ - &movs_op, &movs_op, &complex_cmpsb_op, &complex_cmps_op, + &movs_op, &movs_op, &cmpsb_op, &cmps_op, /* TEST TEST STOSB STOSW*/ &test_reg_b_op, &test_reg_op, &stos_op, &stos_op, /* LODSB LODSW SCASB SCASW*/ - &lods_op, &lods_op, &complex_scasb_op, &complex_scas_op, + &lods_op, &lods_op, &scasb_op, &scas_op, /* MOV*/ -/*b0*/ &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, +/*b0*/ &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, /* RET imm RET*/ -/*c0*/ INVALID, INVALID, &complex_ret_op, &complex_ret_op, +/*c0*/ INVALID, INVALID, &ret_op, &ret_op, /* LES LDS MOV MOV*/ - &complex_lss_op, &complex_lss_op, &store_op, &store_op, + &lss_op, &lss_op, &store_op, &store_op, /* ENTER LEAVE RETF RETF*/ - &complex_enter_op, &leave_op, &complex_retf_op, &complex_retf_op, + &enter_op, &leave_op, &retf_op, &retf_op, /* INT3 INT INTO IRET*/ - &complex_int_op, &complex_int_op, &complex_int_op, &complex_iret_op, + &int_op, &int_op, &int_op, &iret_op, /*d0*/ INVALID, INVALID, INVALID, INVALID, /* AAM AAD SETALC XLAT*/ - &complex_alux6_op, &complex_alux3_op, &complex_alux1_op, &complex_xlat_op, + &alup0_6_op, &alup0_3_op, &complex_alup0_1_op, &xlat_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, + /* LOOPNE LOOPE LOOP JCXZ*/ -/*e0*/ &complex_loop_op, &complex_loop_op, &loop_op, &complex_loop_op, +/*e0*/ &loop_op, &loop_op, &loop_op, &loop_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* CALL JMP JMP JMP*/ - &store_op, &branch_op, &complex_jmp_far_op, &branch_op, + &store_op, &branch_op, &jmp_far_op, &branch_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* REPNE REPE*/ /*f0*/ INVALID, INVALID, INVALID, INVALID, /* HLT CMC*/ - &complex_alux1_op, &complex_alu2_op, INVALID, INVALID, + &complex_alup0_1_op, &alu2_op, INVALID, INVALID, /* CLC STC CLI STI*/ - &complex_alu1_op, &complex_alu1_op, &complex_cli_sti_op, &complex_cli_sti_op, + &complex_alu1_op, &complex_alu1_op, &cli_sti_op, &cli_sti_op, /* CLD STD INCDEC*/ - &complex_alu1_op, &complex_alu1_op, &complex_alux1_op, INVALID + &complex_alu1_op, &complex_alu1_op, &complex_alup0_1_op, INVALID }; -static const risc86_instruction_t *opcode_timings_0f[256] = +static const macro_op_t *opcode_timings_0f[256] = { -/*00*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - INVALID, &complex_alu6_op, &complex_alu6_op, INVALID, - &complex_invd_op, &complex_wbinvd_op, INVALID, INVALID, - INVALID, &load_op, &complex_femms_op, INVALID, +/*00*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + INVALID, &alu6_op, &alu6_op, INVALID, + &invd_op, &wbinvd_op, INVALID, INVALID, + INVALID, &load_op, &femms_op, INVALID, /*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*20*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - &complex_alu6_op, &complex_alu6_op, INVALID, INVALID, +/*20*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*30*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, INVALID, +/*30*/ &alu6_op, &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, @@ -1253,7 +1210,7 @@ static const risc86_instruction_t *opcode_timings_0f[256] = INVALID, INVALID, &mload_op, &mload_op, /*70*/ INVALID, &load_mmx_shift_op, &load_mmx_shift_op, &load_mmx_shift_op, - &load_mmx_op, &load_mmx_op, &load_mmx_op, &complex_emms_op, + &load_mmx_op, &load_mmx_op, &load_mmx_op, &emms_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, &mstore_op, &mstore_op, @@ -1262,23 +1219,23 @@ static const risc86_instruction_t *opcode_timings_0f[256] = &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, -/*90*/ &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, +/*90*/ &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, -/*a0*/ &push_seg_op, &complex_mov_seg_mem_op,&complex_cpuid_op, &complex_load_alu_op, - &complex_alu_store_op, &complex_alu_store_op, INVALID, INVALID, - &push_seg_op, &complex_mov_seg_mem_op,INVALID, &complex_load_alu_op, - &complex_alu_store_op, &complex_alu_store_op, INVALID, &complex_mul_op, +/*a0*/ &push_seg_op, &mov_seg_mem_op, &cpuid_op, &load_alu_op, + &alu_store_op, &alu_store_op, INVALID, INVALID, + &push_seg_op, &mov_seg_mem_op, INVALID, &load_alu_op, + &alu_store_op, &alu_store_op, INVALID, &mul_op, -/*b0*/ &complex_cmpxchg_b_op, &complex_cmpxchg_op, &complex_lss_op, &complex_load_alu_op, - &complex_lss_op, &complex_lss_op, &load_alux_op, &load_alu_op, - INVALID, INVALID, &complex_load_alu_op, &complex_load_alu_op, - &complex_bsx_op, &complex_bsx_op, &load_alux_op, &load_alu_op, +/*b0*/ &cmpxchg_b_op, &cmpxchg_op, &lss_op, &load_alu_op, + &lss_op, &lss_op, &load_alup0_op, &load_alu_op, + INVALID, INVALID, &load_alu_op, &load_alu_op, + &bsx_op, &bsx_op, &load_alup0_op, &load_alu_op, -/*c0*/ &complex_alux_store_op, &complex_alu_store_op, INVALID, INVALID, - INVALID, INVALID, INVALID, &complex_cmpxchg_op, +/*c0*/ &alup0_store_op, &alu_store_op, INVALID, INVALID, + INVALID, INVALID, INVALID, &cmpxchg_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, @@ -1297,182 +1254,182 @@ static const risc86_instruction_t *opcode_timings_0f[256] = &load_mmx_op, &load_mmx_op, &load_mmx_op, INVALID, &load_mmx_op, &load_mmx_op, &load_mmx_op, INVALID, }; -static const risc86_instruction_t *opcode_timings_0f_mod3[256] = +static const macro_op_t *opcode_timings_0f_mod3[256] = { -/*00*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - INVALID, &complex_alu6_op, &complex_alu6_op, INVALID, - &complex_invd_op, &complex_wbinvd_op, INVALID, INVALID, - INVALID, INVALID, &complex_femms_op, INVALID, +/*00*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + INVALID, &alu6_op, &alu6_op, INVALID, + &invd_op, &wbinvd_op, INVALID, INVALID, + INVALID, INVALID, &femms_op, INVALID, /*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*20*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - &complex_alu6_op, &complex_alu6_op, INVALID, INVALID, +/*20*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*30*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*30*/ &alu6_op, &alu6_op, &alu6_op, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*40*/ INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*40*/ INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*50*/ INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*50*/ INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*60*/ &mmx_op, &mmx_op, &mmx_op, &mmx_op, - &mmx_op, &mmx_op, &mmx_op, &mmx_op, - &mmx_op, &mmx_op, &mmx_op, &mmx_op, - INVALID, INVALID, &mmx_op, &mmx_op, +/*60*/ &mmx_op, &mmx_op, &mmx_op, &mmx_op, + &mmx_op, &mmx_op, &mmx_op, &mmx_op, + &mmx_op, &mmx_op, &mmx_op, &mmx_op, + INVALID, INVALID, &mmx_op, &mmx_op, -/*70*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - &mmx_op, &mmx_op, &mmx_op, &complex_emms_op, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, &mmx_op, &mmx_op, +/*70*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + &mmx_op, &mmx_op, &mmx_op, &emms_op, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, &mmx_op, &mmx_op, /*80*/ &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, -/*90*/ &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, +/*90*/ &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, -/*a0*/ &push_seg_op, &complex_mov_seg_mem_op, &complex_cpuid_op, &complex_alu1_op, - &complex_alu1_op, &complex_alu1_op, INVALID, INVALID, - &push_seg_op, &complex_mov_seg_mem_op, INVALID, &complex_alu1_op, - &complex_alu1_op, &complex_alu1_op, INVALID, &complex_mul_op, +/*a0*/ &push_seg_op, &mov_seg_mem_op, &cpuid_op, &complex_alu1_op, + &complex_alu1_op, &complex_alu1_op, INVALID, INVALID, + &push_seg_op, &mov_seg_mem_op, INVALID, &complex_alu1_op, + &complex_alu1_op, &complex_alu1_op, INVALID, &mul_op, -/*b0*/ &complex_cmpxchg_b_op, &complex_cmpxchg_op, &complex_lss_op, &complex_alu1_op, - &complex_lss_op, &complex_lss_op, &alux_op, &alu_op, - INVALID, INVALID, &complex_alu1_op, &complex_alu1_op, - &complex_bsx_op, &complex_bsx_op, &alux_op, &alu_op, +/*b0*/ &cmpxchg_b_op, &cmpxchg_op, &lss_op, &complex_alu1_op, + &lss_op, &lss_op, &alup0_op, &alu_op, + INVALID, INVALID, &complex_alu1_op, &complex_alu1_op, + &bsx_op, &bsx_op, &alup0_op, &alu_op, -/*c0*/ &complex_alux1_op, &complex_alu1_op, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - &bswap_op, &bswap_op, &bswap_op, &bswap_op, - &bswap_op, &bswap_op, &bswap_op, &bswap_op, +/*c0*/ &complex_alup0_1_op, &complex_alu1_op, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + &bswap_op, &bswap_op, &bswap_op, &bswap_op, + &bswap_op, &bswap_op, &bswap_op, &bswap_op, -/*d0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - INVALID, &mmx_mul_op, INVALID, INVALID, - &mmx_op, &mmx_op, INVALID, &mmx_op, - &mmx_op, &mmx_op, INVALID, &mmx_op, +/*d0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + INVALID, &mmx_mul_op, INVALID, INVALID, + &mmx_op, &mmx_op, INVALID, &mmx_op, + &mmx_op, &mmx_op, INVALID, &mmx_op, -/*e0*/ &mmx_op, &mmx_shift_op, &mmx_shift_op, INVALID, - INVALID, &pmul_op, INVALID, INVALID, - &mmx_op, &mmx_op, INVALID, &mmx_op, - &mmx_op, &mmx_op, INVALID, &mmx_op, +/*e0*/ &mmx_op, &mmx_shift_op, &mmx_shift_op, INVALID, + INVALID, &pmul_op, INVALID, INVALID, + &mmx_op, &mmx_op, INVALID, &mmx_op, + &mmx_op, &mmx_op, INVALID, &mmx_op, -/*f0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - INVALID, &pmul_op, INVALID, INVALID, - &mmx_op, &mmx_op, &mmx_op, INVALID, - &mmx_op, &mmx_op, &mmx_op, INVALID, +/*f0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + INVALID, &pmul_op, INVALID, INVALID, + &mmx_op, &mmx_op, &mmx_op, INVALID, + &mmx_op, &mmx_op, &mmx_op, INVALID, }; -static const risc86_instruction_t *opcode_timings_shift[8] = +static const macro_op_t *opcode_timings_shift[8] = { - &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, - &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op }; -static const risc86_instruction_t *opcode_timings_shift_b[8] = +static const macro_op_t *opcode_timings_shift_b[8] = { - &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, - &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op }; -static const risc86_instruction_t *opcode_timings_shift_mod3[8] = +static const macro_op_t *opcode_timings_shift_mod3[8] = { &complex_alu1_op, &complex_alu1_op, &complex_alu1_op, &complex_alu1_op, &alu_op, &alu_op, &alu_op, &alu_op }; -static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] = +static const macro_op_t *opcode_timings_shift_b_mod3[8] = { - &complex_alux1_op, &complex_alux1_op, &complex_alux1_op, &complex_alux1_op, - &alux_op, &alux_op, &alux_op, &alux_op + &complex_alup0_1_op, &complex_alup0_1_op, &complex_alup0_1_op, &complex_alup0_1_op, + &alup0_op, &alup0_op, &alup0_op, &alup0_op }; -static const risc86_instruction_t *opcode_timings_80[8] = +static const macro_op_t *opcode_timings_80[8] = { - &alux_store_op, &alux_store_op, &complex_alux_store_op, &complex_alux_store_op, - &alux_store_op, &alux_store_op, &alux_store_op, &alux_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, }; -static const risc86_instruction_t *opcode_timings_80_mod3[8] = +static const macro_op_t *opcode_timings_80_mod3[8] = { - &alux_op, &alux_op, &alux_store_op, &alux_store_op, - &alux_op, &alux_op, &alux_op, &alux_op, + &alup0_op, &alup0_op, &alup0_store_op, &alup0_store_op, + &alup0_op, &alup0_op, &alup0_op, &alup0_op, }; -static const risc86_instruction_t *opcode_timings_8x[8] = +static const macro_op_t *opcode_timings_8x[8] = { - &alu_store_op, &alu_store_op, &complex_alu_store_op, &complex_alu_store_op, - &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, -}; -static const risc86_instruction_t *opcode_timings_8x_mod3[8] = + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, +}; +static const macro_op_t *opcode_timings_8x_mod3[8] = { - &alu_op, &alu_op, &alu_store_op, &alu_store_op, - &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_store_op, &alu_store_op, + &alu_op, &alu_op, &alu_op, &alu_op, }; -static const risc86_instruction_t *opcode_timings_f6[8] = +static const macro_op_t *opcode_timings_f6[8] = { /* TST NOT NEG*/ - &test_mem_imm_b_op, INVALID, &complex_alux_store_op, &complex_alux_store_op, + &test_mem_imm_b_op, INVALID, &alup0_store_op, &alup0_store_op, /* MUL IMUL DIV IDIV*/ - &complex_mul_mem_op, &complex_mul_mem_op, &complex_div16_mem_op, &complex_div16_mem_op, + &mul_mem_op, &mul_mem_op, &div16_mem_op, &div16_mem_op, }; -static const risc86_instruction_t *opcode_timings_f6_mod3[8] = +static const macro_op_t *opcode_timings_f6_mod3[8] = { /* TST NOT NEG*/ - &test_reg_b_op, INVALID, &alux_op, &alux_op, + &test_reg_b_op, INVALID, &alup0_op, &alup0_op, /* MUL IMUL DIV IDIV*/ - &complex_mul_op, &complex_mul_op, &complex_div16_op, &complex_div16_op, + &mul_op, &mul_op, &div16_op, &div16_op, }; -static const risc86_instruction_t *opcode_timings_f7[8] = +static const macro_op_t *opcode_timings_f7[8] = { /* TST NOT NEG*/ - &test_mem_imm_op, INVALID, &complex_alu_store_op, &complex_alu_store_op, + &test_mem_imm_op, INVALID, &alu_store_op, &alu_store_op, /* MUL IMUL DIV IDIV*/ - &complex_mul64_mem_op, &complex_mul64_mem_op, &complex_div32_mem_op, &complex_div32_mem_op, + &mul64_mem_op, &mul64_mem_op, &div32_mem_op, &div32_mem_op, }; -static const risc86_instruction_t *opcode_timings_f7_mod3[8] = +static const macro_op_t *opcode_timings_f7_mod3[8] = { /* TST NOT NEG*/ &test_reg_op, INVALID, &alu_op, &alu_op, /* MUL IMUL DIV IDIV*/ - &complex_mul64_op, &complex_mul64_op, &complex_div32_op, &complex_div32_op, + &mul64_op, &mul64_op, &div32_op, &div32_op, }; -static const risc86_instruction_t *opcode_timings_ff[8] = +static const macro_op_t *opcode_timings_ff[8] = { /* INC DEC CALL CALL far*/ - &alu_store_op, &alu_store_op, &store_op, &complex_call_far_op, + &alu_store_op, &alu_store_op, &store_op, &call_far_op, /* JMP JMP far PUSH*/ - &branch_op, &complex_jmp_far_op, &push_mem_op, INVALID + &branch_op, &jmp_far_op, &push_mem_op, INVALID }; -static const risc86_instruction_t *opcode_timings_ff_mod3[8] = +static const macro_op_t *opcode_timings_ff_mod3[8] = { /* INC DEC CALL CALL far*/ - &complex_alu1_op, &complex_alu1_op, &store_op, &complex_call_far_op, + &complex_alu1_op, &complex_alu1_op, &store_op, &call_far_op, /* JMP JMP far PUSH*/ - &branch_op, &complex_jmp_far_op, &complex_push_mem_op, INVALID + &branch_op, &jmp_far_op, &complex_push_mem_op, INVALID }; -static const risc86_instruction_t *opcode_timings_d8[8] = +static const macro_op_t *opcode_timings_d8[8] = { /* FADDs FMULs FCOMs FCOMPs*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FSUBs FSUBRs FDIVs FDIVRs*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_d8_mod3[8] = +static const macro_op_t *opcode_timings_d8_mod3[8] = { /* FADD FMUL FCOM FCOMP*/ &fadd_op, &fmul_op, &float_op, &float_op, @@ -1480,27 +1437,27 @@ static const risc86_instruction_t *opcode_timings_d8_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op, }; -static const risc86_instruction_t *opcode_timings_d9[8] = +static const macro_op_t *opcode_timings_d9[8] = { /* FLDs FSTs FSTPs*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FLDENV FLDCW FSTENV FSTCW*/ - &complex_float_l_op, &complex_fldcw_op, &complex_float_l_op, &complex_float_op + &complex_float_l_op, &fldcw_op, &complex_float_l_op, &complex_float_op }; -static const risc86_instruction_t *opcode_timings_d9_mod3[64] = +static const macro_op_t *opcode_timings_d9_mod3[64] = { /*FLD*/ &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, /*FXCH*/ - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, + &fxch_op, &fxch_op, &fxch_op, &fxch_op, + &fxch_op, &fxch_op, &fxch_op, &fxch_op, /*FNOP*/ &float_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, /*FSTP*/ - &float2_op, &float2_op, &float2_op, &float2_op, - &float2_op, &float2_op, &float2_op, &float2_op, + &float2_op, &float2_op, &float2_op, &float2_op, + &float2_op, &float2_op, &float2_op, &float2_op, /* opFCHS opFABS*/ &fchs_op, &float_op, INVALID, INVALID, /* opFTST opFXAM*/ @@ -1519,28 +1476,28 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] = &float_op, &fdiv_op, &fsin_op, &fsin_op }; -static const risc86_instruction_t *opcode_timings_da[8] = +static const macro_op_t *opcode_timings_da[8] = { /* FIADDl FIMULl FICOMl FICOMPl*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FISUBl FISUBRl FIDIVl FIDIVRl*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_da_mod3[8] = +static const macro_op_t *opcode_timings_da_mod3[8] = { INVALID, INVALID, INVALID, INVALID, /* FCOMPP*/ INVALID, &float_op, INVALID, INVALID }; -static const risc86_instruction_t *opcode_timings_db[8] = +static const macro_op_t *opcode_timings_db[8] = { /* FLDil FSTil FSTPil*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FLDe FSTPe*/ - INVALID, &complex_flde_op, INVALID, &complex_fste_op + INVALID, &flde_op, INVALID, &fste_op }; -static const risc86_instruction_t *opcode_timings_db_mod3[64] = +static const macro_op_t *opcode_timings_db_mod3[64] = { INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, @@ -1569,14 +1526,14 @@ static const risc86_instruction_t *opcode_timings_db_mod3[64] = INVALID, INVALID, INVALID, INVALID, }; -static const risc86_instruction_t *opcode_timings_dc[8] = +static const macro_op_t *opcode_timings_dc[8] = { /* FADDd FMULd FCOMd FCOMPd*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FSUBd FSUBRd FDIVd FDIVRd*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_dc_mod3[8] = +static const macro_op_t *opcode_timings_dc_mod3[8] = { /* opFADDr opFMULr*/ &fadd_op, &fmul_op, INVALID, INVALID, @@ -1584,14 +1541,14 @@ static const risc86_instruction_t *opcode_timings_dc_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op }; -static const risc86_instruction_t *opcode_timings_dd[8] = +static const macro_op_t *opcode_timings_dd[8] = { /* FLDd FSTd FSTPd*/ - &load_float_op, INVALID, &fstore_op, &fstore_op, + &load_float_op, INVALID, &fstore_op, &fstore_op, /* FRSTOR FSAVE FSTSW*/ &complex_float_l_op, INVALID, &complex_float_l_op, &complex_float_l_op }; -static const risc86_instruction_t *opcode_timings_dd_mod3[8] = +static const macro_op_t *opcode_timings_dd_mod3[8] = { /* FFFREE FST FSTP*/ &float_op, INVALID, &float_op, &float_op, @@ -1599,14 +1556,14 @@ static const risc86_instruction_t *opcode_timings_dd_mod3[8] = &float_op, &float_op, INVALID, INVALID }; -static const risc86_instruction_t *opcode_timings_de[8] = +static const macro_op_t *opcode_timings_de[8] = { /* FIADDw FIMULw FICOMw FICOMPw*/ &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, /* FISUBw FISUBRw FIDIVw FIDIVRw*/ &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, }; -static const risc86_instruction_t *opcode_timings_de_mod3[8] = +static const macro_op_t *opcode_timings_de_mod3[8] = { /* FADDP FMULP FCOMPP*/ &fadd_op, &fmul_op, INVALID, &float_op, @@ -1614,14 +1571,14 @@ static const risc86_instruction_t *opcode_timings_de_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op, }; -static const risc86_instruction_t *opcode_timings_df[8] = +static const macro_op_t *opcode_timings_df[8] = { /* FILDiw FISTiw FISTPiw*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FILDiq FBSTP FISTPiq*/ INVALID, &load_float_op, &complex_float_l_op, &fstore_op, }; -static const risc86_instruction_t *opcode_timings_df_mod3[8] = +static const macro_op_t *opcode_timings_df_mod3[8] = { INVALID, INVALID, INVALID, INVALID, /* FSTSW AX*/ @@ -1647,35 +1604,35 @@ static p6_unit_t *units; /*Pentium Pro has no MMX*/ static p6_unit_t ppro_units[] = { - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT)}, /*Integer X & Floating point*/ - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)}, /*Integer Y*/ - {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD)}, /*Load*/ - {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)}, /*Data Store*/ - {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)}, /*Address Store*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUP0) | (1 << UOP_FLOAT)}, /*Port 0*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)}, /*Port 1*/ + {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD)}, /*Port 2*/ + {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)}, /*Port 3*/ + {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)}, /*Port 4*/ }; #define NR_PPRO_UNITS (sizeof(ppro_units) / sizeof(p6_unit_t)) /*Pentium II/Celeron assigns the multiplier to port 0, the shifter to port 1, and shares the MMX ALU*/ static p6_unit_t p2_units[] = { - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT) | /*Integer X & Floating point*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUP0) | (1 << UOP_FLOAT) | /*Port 0*/ (1 << UOP_MMX) | (1 << UOP_MMX_MUL)}, - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) | /*Integer Y*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) | /*Port 1*/ (1 << UOP_MMX) | (1 << UOP_MMX_SHIFT)}, - {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD) | (1 << UOP_MLOAD)}, /*Load*/ - {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)}, /*Data Store*/ - {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, /*Address Store*/ + {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD) | (1 << UOP_MLOAD)}, /*Port 2*/ + {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)}, /*Port 3*/ + {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, /*Port 4*/ }; #define NR_P2_UNITS (sizeof(p2_units) / sizeof(p6_unit_t)) -static int uop_run(const risc86_uop_t *uop, int decode_time) +static int uop_run(const p6_uop_t *uop, int decode_time) { int c; p6_unit_t *best_unit = NULL; - double best_start_cycle = 99999; + int best_start_cycle = 99999; - /*UOP_LIMM does not require execution*/ - if (uop->type == UOP_LIMM) + /*UOP_FXCH does not require execution*/ + if (uop->type == UOP_FXCH) return decode_time; /*Find execution unit for this uOP*/ @@ -1709,7 +1666,7 @@ static int uop_run(const risc86_uop_t *uop, int decode_time) static struct { int nr_uops; - const risc86_uop_t *uops[6]; + const p6_uop_t *uops[6]; /*Earliest time a uop can start. If the timestamp is -1, then the uop is part of a dependency chain and the start time is the completion time of the previous uop*/ @@ -1748,7 +1705,10 @@ void decode_flush_p6() /*Submit uops to execution units, and determine the latest completion time*/ for (c = 0; c < (decode_buffer.nr_uops); c++) { - start_timestamp = decode_buffer.earliest_start[c]; + if (decode_buffer.earliest_start[c] == -1) + start_timestamp = last_uop_timestamp; + else + start_timestamp = decode_buffer.earliest_start[c]; last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp); if (last_uop_timestamp > uop_timestamp) @@ -1822,7 +1782,7 @@ static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_ return len; } -static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8) +static void decode_instruction(const macro_op_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8) { uint32_t regmask_required; uint32_t regmask_modified; @@ -1858,10 +1818,8 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u } /*Simple decoders are limited to 7 bytes & 1 uOP*/ - if (decode_type == DECODE_SIMPLE && instr_length > 7) + if ((decode_type == DECODE_SIMPLE && instr_length > 7) || (decode_type == DECODE_SIMPLE && ins->nr_uops > 1)) decode_type = DECODE_COMPLEX; - else if (decode_type == DECODE_SIMPLE && ins->nr_uops > 1) - decode_type = DECODE_COMPLEX; switch (decode_type) { @@ -1904,7 +1862,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u for (c = 0; c < ins->nr_uops; c++) { decode_buffer.uops[d] = &ins->uop[c]; - decode_buffer.earliest_start[d] = earliest_start; + if (c == 0) + decode_buffer.earliest_start[d] = earliest_start; + else + decode_buffer.earliest_start[d] = -1; d++; if ((d == 3) && (ins->nr_uops > 4)) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/ @@ -2009,7 +1970,7 @@ void codegen_timing_p6_prefix(uint8_t prefix, uint32_t fetchdat) void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc) { - const risc86_instruction_t **ins_table; + const macro_op_t **ins_table; uint64_t *deps; int mod3 = ((fetchdat & 0xc0) == 0xc0); int old_last_complete_timestamp = last_complete_timestamp; diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index 620d94eaa..8fb271b47 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -720,29 +720,29 @@ CPU cpus_PentiumII[] = { {"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 3.5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, {"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, {"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 4.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + + /*Intel Celeron Mendocino Mobile(Applied on a BGA615 Socket)*/ + {"Mobile Celeron Mendocino 466", CPU_PENTIUM2D, 466666666, 7.0, 0x66a, 0x66a, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 40,40,14,14, 52}, {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; CPU cpus_Celeron[] = { - /* Mendocino Celerons. Exact architecture as the P2D series. Intended for - the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1 + /* Mendocino Celerons. Exact architecture as the P2D series with their L2 cache on-dye. + Intended for the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1 adaptor card so they work on Slot 1 motherboards too!. - The 100Mhz Mendocino is only meant to not cause any struggle + The 100Mhz & 166Mhz Mendocino is only meant to not cause any struggle to the recompiler. */ - {"Celeron Mendocino 25", CPU_PENTIUM2D, 25000000, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 3}, - {"Celeron Mendocino 50", CPU_PENTIUM2D, 50000000, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Celeron Mendocino 66", CPU_PENTIUM2D, 66666666, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 1.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Celeron Mendocino 166", CPU_PENTIUM2D, 166666666, 2.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, {"Celeron Mendocino 300/66", CPU_PENTIUM2D, 300000000, 4.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, {"Celeron Mendocino 366", CPU_PENTIUM2D, 366666666, 5.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44}, - {"Celeron Mendocino 400", CPU_PENTIUM2D, 400000000, 4.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"Celeron Mendocino 433", CPU_PENTIUM2D, 433333333, 4.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51}, - {"Celeron Mendocino 466", CPU_PENTIUM2D, 466666666, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57}, - {"Celeron Mendocino 500", CPU_PENTIUM2D, 500000000, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60}, - {"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 5.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64}, + {"Celeron Mendocino 400", CPU_PENTIUM2D, 400000000, 6.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"Celeron Mendocino 433", CPU_PENTIUM2D, 433333333, 6.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51}, + {"Celeron Mendocino 500", CPU_PENTIUM2D, 500000000, 7.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60}, + {"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 8.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64}, {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; diff --git a/src/cpu_new/codegen_timing_p6.c b/src/cpu_new/codegen_timing_p6.c index a51b4df32..3cb15bf68 100644 --- a/src/cpu_new/codegen_timing_p6.c +++ b/src/cpu_new/codegen_timing_p6.c @@ -16,8 +16,8 @@ typedef enum uop_type_t { - UOP_ALU = 0, /*Executes in Integer X or Y units*/ - UOP_ALUX, /*Executes in Integer X unit*/ + UOP_ALU = 0, /*Executes in Port 0 or 1 ALU units*/ + UOP_ALUP0, /*Executes in Port 0 ALU unit*/ UOP_LOAD, /*Executes in Load unit*/ UOP_STORED, /*Executes in Data Store unit*/ UOP_STOREA, /*Executes in Address Store unit*/ @@ -28,11 +28,11 @@ typedef enum uop_type_t UOP_MSTORED, /*Executes in Data Store unit*/ UOP_MSTOREA, /*Executes in Address Store unit*/ UOP_FLOAT, /*Executes in Floating Point unit*/ - UOP_MMX, /*Executes in Integer X or Y units as MMX*/ - UOP_MMX_SHIFT, /*Executes in Integer Y unit. Uses MMX shifter*/ - UOP_MMX_MUL, /*Executes in Integer X unit. Uses MMX multiplier*/ + UOP_MMX, /*Executes in Port 0 or 1 ALU units as MMX*/ + UOP_MMX_SHIFT, /*Executes in Port 1 ALU unit. Uses MMX shifter*/ + UOP_MMX_MUL, /*Executes in Port 0 ALU unit. Uses MMX multiplier*/ UOP_BRANCH, /*Executes in Branch unit*/ - UOP_LIMM /*Does not require an execution unit*/ + UOP_FXCH /*Does not require an execution unit*/ } uop_type_t; typedef enum decode_type_t @@ -43,46 +43,46 @@ typedef enum decode_type_t #define MAX_UOPS 10 -typedef struct risc86_uop_t +typedef struct p6_uop_t { uop_type_t type; - double latency; -} risc86_uop_t; + int latency; +} p6_uop_t; -typedef struct risc86_instruction_t +typedef struct macro_op_t { int nr_uops; decode_type_t decode_type; - risc86_uop_t uop[MAX_UOPS]; -} risc86_instruction_t; + p6_uop_t uop[MAX_UOPS]; +} macro_op_t; -static const risc86_instruction_t alu_op = +static const macro_op_t alu_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t alux_op = +static const macro_op_t alup0_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t load_alu_op = +static const macro_op_t load_alu_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t load_alux_op = +static const macro_op_t load_alup0_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t alu_store_op = +static const macro_op_t alu_store_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -91,38 +91,38 @@ static const risc86_instruction_t alu_store_op = .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t alux_store_op = +static const macro_op_t alup0_store_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t branch_op = +static const macro_op_t branch_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_BRANCH, .latency = 1} + .uop[0] = {.type = UOP_BRANCH, .latency = 2} }; -static const risc86_instruction_t limm_op = +static const macro_op_t fxch_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_LIMM, .latency = 1} + .uop[0] = {.type = UOP_FXCH, .latency = 1} }; -static const risc86_instruction_t load_op = +static const macro_op_t load_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t store_op = +static const macro_op_t store_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, @@ -131,14 +131,14 @@ static const risc86_instruction_t store_op = }; -static const risc86_instruction_t bswap_op = +static const macro_op_t bswap_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1}, }; -static const risc86_instruction_t leave_op = +static const macro_op_t leave_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -146,27 +146,27 @@ static const risc86_instruction_t leave_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t lods_op = +static const macro_op_t lods_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t loop_op = +static const macro_op_t loop_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, - .uop[1] = {.type = UOP_BRANCH, .latency = 1} + .uop[1] = {.type = UOP_BRANCH, .latency = 2} }; -static const risc86_instruction_t mov_reg_seg_op = +static const macro_op_t mov_reg_seg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, }; -static const risc86_instruction_t movs_op = +static const macro_op_t movs_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -175,14 +175,14 @@ static const risc86_instruction_t movs_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t pop_reg_op = +static const macro_op_t pop_reg_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t pop_mem_op = +static const macro_op_t pop_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -191,14 +191,14 @@ static const risc86_instruction_t pop_mem_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t push_imm_op = +static const macro_op_t push_imm_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_STORED, .latency = 1}, .uop[1] = {.type = UOP_STOREA, .latency = 1}, }; -static const risc86_instruction_t push_mem_op = +static const macro_op_t push_mem_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -206,7 +206,7 @@ static const risc86_instruction_t push_mem_op = .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t push_seg_op = +static const macro_op_t push_seg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -215,7 +215,7 @@ static const risc86_instruction_t push_seg_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t stos_op = +static const macro_op_t stos_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -223,33 +223,33 @@ static const risc86_instruction_t stos_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_reg_op = -{ - .nr_uops = 1, - .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_ALU, .latency = 1} -}; -static const risc86_instruction_t test_reg_b_op = +static const macro_op_t test_reg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_mem_imm_op = +static const macro_op_t test_reg_b_op = +{ + .nr_uops = 1, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} +}; +static const macro_op_t test_mem_imm_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t test_mem_imm_b_op = +static const macro_op_t test_mem_imm_b_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t xchg_op = +static const macro_op_t xchg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -259,98 +259,98 @@ static const risc86_instruction_t xchg_op = }; -static const risc86_instruction_t mmx_op = +static const macro_op_t mmx_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX, .latency = 1.5} + .uop[0] = {.type = UOP_MMX, .latency = 1} }; -static const risc86_instruction_t mmx_mul_op = +static const macro_op_t mmx_mul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_MUL, .latency = 1} }; -static const risc86_instruction_t mmx_shift_op = +static const macro_op_t mmx_shift_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_SHIFT, .latency = 1} }; -static const risc86_instruction_t load_mmx_op = +static const macro_op_t load_mmx_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_MMX, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX, .latency = 2} }; -static const risc86_instruction_t load_mmx_mul_op = +static const macro_op_t load_mmx_mul_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_MUL, .latency = 2} }; -static const risc86_instruction_t load_mmx_shift_op = +static const macro_op_t load_mmx_shift_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_SHIFT, .latency = 2} }; -static const risc86_instruction_t mload_op = +static const macro_op_t mload_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_MLOAD, .latency = 3}, + .uop[0] = {.type = UOP_MLOAD, .latency = 1}, }; -static const risc86_instruction_t mstore_op = +static const macro_op_t mstore_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_MSTORED, .latency = 1}, .uop[1] = {.type = UOP_MSTOREA, .latency = 1} }; -static const risc86_instruction_t pmul_op = +static const macro_op_t pmul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_MMX_MUL, .latency = 1} }; -static const risc86_instruction_t pmul_mem_op = +static const macro_op_t pmul_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_MMX_MUL, .latency = 1.5} + .uop[0] = {.type = UOP_LOAD, .latency = 2}, + .uop[1] = {.type = UOP_MMX_MUL, .latency = 2} }; -static const risc86_instruction_t float_op = +static const macro_op_t float_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fadd_op = +static const macro_op_t fadd_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_FLOAT, .latency = 3} + .uop[0] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t fmul_op = +static const macro_op_t fmul_op = { .nr_uops = 1, .decode_type = DECODE_SIMPLE, - .uop[0] = {.type = UOP_ALU, .latency = 5} + .uop[0] = {.type = UOP_ALUP0, .latency = 3} }; -static const risc86_instruction_t float2_op = +static const macro_op_t float2_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 1}, .uop[1] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fchs_op = +static const macro_op_t fchs_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -358,35 +358,35 @@ static const risc86_instruction_t fchs_op = .uop[1] = {.type = UOP_FLOAT, .latency = 2}, .uop[2] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t load_float_op = +static const macro_op_t load_float_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, .uop[1] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t load_fadd_op = +static const macro_op_t load_fadd_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, - .uop[1] = {.type = UOP_FLOAT, .latency = 3} + .uop[1] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t load_fmul_op = +static const macro_op_t load_fmul_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 5} + .uop[1] = {.type = UOP_ALU, .latency = 4} }; -static const risc86_instruction_t fstore_op = +static const macro_op_t fstore_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FSTORED, .latency = 1}, .uop[1] = {.type = UOP_FSTOREA, .latency = 1}, }; -static const risc86_instruction_t load_fiadd_op = +static const macro_op_t load_fiadd_op = { .nr_uops = 7, .decode_type = DECODE_COMPLEX, @@ -398,51 +398,51 @@ static const risc86_instruction_t load_fiadd_op = .uop[5] = {.type = UOP_FLOAT, .latency = 1}, .uop[6] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t fdiv_op = +static const macro_op_t fdiv_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_FLOAT, .latency = 32} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_FLOAT, .latency = 37} }; -static const risc86_instruction_t fdiv_mem_op = +static const macro_op_t fdiv_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAD, .latency = 1}, - .uop[1] = {.type = UOP_FLOAT, .latency = 38} + .uop[1] = {.type = UOP_FLOAT, .latency = 37} }; -static const risc86_instruction_t fsin_op = +static const macro_op_t fsin_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_FLOAT, .latency = 60} + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_FLOAT, .latency = 62} }; -static const risc86_instruction_t fsqrt_op = +static const macro_op_t fsqrt_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 69} }; -static const risc86_instruction_t complex_fldcw_op = +static const macro_op_t fldcw_op = { .nr_uops = 1, - .decode_type = DECODE_COMPLEX, + .decode_type = DECODE_SIMPLE, .uop[0] = {.type = UOP_FLOAT, .latency = 10} }; -static const risc86_instruction_t complex_float_op = +static const macro_op_t complex_float_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 1} }; -static const risc86_instruction_t complex_float_l_op = +static const macro_op_t complex_float_l_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_FLOAT, .latency = 50} }; -static const risc86_instruction_t complex_flde_op = +static const macro_op_t flde_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -450,7 +450,7 @@ static const risc86_instruction_t complex_flde_op = .uop[1] = {.type = UOP_FLOAD, .latency = 1}, .uop[2] = {.type = UOP_FLOAT, .latency = 2} }; -static const risc86_instruction_t complex_fste_op = +static const macro_op_t fste_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -459,20 +459,20 @@ static const risc86_instruction_t complex_fste_op = .uop[2] = {.type = UOP_FSTOREA, .latency = 1} }; -static const risc86_instruction_t complex_alu1_op = +static const macro_op_t complex_alu1_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu2_op = +static const macro_op_t alu2_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu3_op = +static const macro_op_t alu3_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -480,7 +480,7 @@ static const risc86_instruction_t complex_alu3_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alu6_op = +static const macro_op_t alu6_op = { .nr_uops = 6, .decode_type = DECODE_COMPLEX, @@ -491,57 +491,39 @@ static const risc86_instruction_t complex_alu6_op = .uop[4] = {.type = UOP_ALU, .latency = 1}, .uop[5] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_alux1_op = +static const macro_op_t complex_alup0_1_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alux3_op = +static const macro_op_t alup0_3_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alux6_op = +static const macro_op_t alup0_6_op = { .nr_uops = 6, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1}, - .uop[3] = {.type = UOP_ALUX, .latency = 1}, - .uop[4] = {.type = UOP_ALUX, .latency = 1}, - .uop[5] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1}, + .uop[3] = {.type = UOP_ALUP0, .latency = 1}, + .uop[4] = {.type = UOP_ALUP0, .latency = 1}, + .uop[5] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_alu_store_op = -{ - .nr_uops = 4, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1}, -}; -static const risc86_instruction_t complex_alux_store_op = -{ - .nr_uops = 4, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1} -}; -static const risc86_instruction_t complex_arpl_op = +static const macro_op_t arpl_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3}, .uop[1] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_bound_op = +static const macro_op_t bound_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -550,13 +532,13 @@ static const risc86_instruction_t complex_bound_op = .uop[2] = {.type = UOP_ALU, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_bsx_op = +static const macro_op_t bsx_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 10} }; -static const risc86_instruction_t complex_call_far_op = +static const macro_op_t call_far_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -565,13 +547,13 @@ static const risc86_instruction_t complex_call_far_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_cli_sti_op = +static const macro_op_t cli_sti_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 7} }; -static const risc86_instruction_t complex_cmps_op = +static const macro_op_t cmps_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -579,15 +561,15 @@ static const risc86_instruction_t complex_cmps_op = .uop[1] = {.type = UOP_ALU, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_cmpsb_op = +static const macro_op_t cmpsb_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_cmpxchg_op = +static const macro_op_t cmpxchg_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -596,54 +578,62 @@ static const risc86_instruction_t complex_cmpxchg_op = .uop[2] = {.type = UOP_STORED, .latency = 1}, .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t complex_cmpxchg_b_op = +static const macro_op_t cmpxchg_b_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_STORED, .latency = 1}, - .uop[3] = {.type = UOP_STOREA, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_STORED, .latency = 1}, + .uop[3] = {.type = UOP_STOREA, .latency = 1} }; -static const risc86_instruction_t complex_cpuid_op = +static const macro_op_t complex_push_mem_op = +{ + .nr_uops = 2, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_STORED, .latency = 1}, + .uop[1] = {.type = UOP_STOREA, .latency = 1} +}; + +static const macro_op_t cpuid_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 23} }; -static const risc86_instruction_t complex_div16_op = +static const macro_op_t div16_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 10} + .uop[0] = {.type = UOP_ALUP0, .latency = 21} }; -static const risc86_instruction_t complex_div16_mem_op = +static const macro_op_t div16_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 10} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 21} }; -static const risc86_instruction_t complex_div32_op = +static const macro_op_t div32_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 18} + .uop[0] = {.type = UOP_ALUP0, .latency = 37} }; -static const risc86_instruction_t complex_div32_mem_op = +static const macro_op_t div32_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 18} + .uop[1] = {.type = UOP_ALUP0, .latency = 37} }; -static const risc86_instruction_t complex_emms_op = +static const macro_op_t emms_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALU, .latency = 25} + .uop[0] = {.type = UOP_ALU, .latency = 50} }; -static const risc86_instruction_t complex_enter_op = +static const macro_op_t enter_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -651,28 +641,28 @@ static const risc86_instruction_t complex_enter_op = .uop[1] = {.type = UOP_STOREA, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 10} }; -static const risc86_instruction_t complex_femms_op = +static const macro_op_t femms_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 6} }; -static const risc86_instruction_t complex_in_op = +static const macro_op_t in_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 10} + .uop[0] = {.type = UOP_LOAD, .latency = 18} }; -static const risc86_instruction_t complex_ins_op = +static const macro_op_t ins_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 10}, + .uop[0] = {.type = UOP_LOAD, .latency = 18}, .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_int_op = +static const macro_op_t int_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -685,7 +675,7 @@ static const risc86_instruction_t complex_int_op = .uop[6] = {.type = UOP_STOREA, .latency = 1}, .uop[7] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_iret_op = +static const macro_op_t iret_op = { .nr_uops = 5, .decode_type = DECODE_COMPLEX, @@ -695,41 +685,20 @@ static const risc86_instruction_t complex_iret_op = .uop[3] = {.type = UOP_ALU, .latency = 20}, .uop[4] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_invd_op = +static const macro_op_t invd_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 500} }; -static const risc86_instruction_t complex_jmp_far_op = +static const macro_op_t jmp_far_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3}, .uop[1] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_load_alu_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALU, .latency = 1} -}; -static const risc86_instruction_t complex_load_alux_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} -}; -static const risc86_instruction_t complex_loop_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALU, .latency = 1}, - .uop[1] = {.type = UOP_BRANCH, .latency = 1} -}; -static const risc86_instruction_t complex_lss_op = +static const macro_op_t lss_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -737,7 +706,7 @@ static const risc86_instruction_t complex_lss_op = .uop[1] = {.type = UOP_LOAD, .latency = 1}, .uop[2] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mov_mem_seg_op = +static const macro_op_t mov_mem_seg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -745,68 +714,63 @@ static const risc86_instruction_t complex_mov_mem_seg_op = .uop[1] = {.type = UOP_STORED, .latency = 1}, .uop[2] = {.type = UOP_STOREA, .latency = 1}, }; -static const risc86_instruction_t complex_mov_seg_mem_op = +static const macro_op_t mov_seg_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mov_seg_reg_op = +static const macro_op_t mov_seg_reg_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 3} }; -static const risc86_instruction_t complex_mul_op = +static const macro_op_t mul_op = +{ + .nr_uops = 1, + .decode_type = DECODE_SIMPLE, + .uop[0] = {.type = UOP_ALUP0, .latency = 1} +}; +static const macro_op_t mul_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_mul_mem_op = +static const macro_op_t mul64_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_mul64_op = -{ - .nr_uops = 3, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1} -}; -static const risc86_instruction_t complex_mul64_mem_op = +static const macro_op_t mul64_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALUX, .latency = 1}, - .uop[3] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALUP0, .latency = 1}, + .uop[3] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_out_op = +static const macro_op_t out_op = { - .nr_uops = 2, + .nr_uops = 1, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_STORED, .latency = 10}, - .uop[1] = {.type = UOP_STOREA, .latency = 10}, + .uop[0] = {.type = UOP_ALU, .latency = 18} }; -static const risc86_instruction_t complex_outs_op = +static const macro_op_t outs_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_STORED, .latency = 10}, - .uop[1] = {.type = UOP_STOREA, .latency = 10}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[1] = {.type = UOP_ALU, .latency = 18} }; -static const risc86_instruction_t complex_pusha_op = +static const macro_op_t pusha_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -819,7 +783,7 @@ static const risc86_instruction_t complex_pusha_op = .uop[6] = {.type = UOP_STORED, .latency = 2}, .uop[7] = {.type = UOP_STOREA, .latency = 2} }; -static const risc86_instruction_t complex_popa_op = +static const macro_op_t popa_op = { .nr_uops = 8, .decode_type = DECODE_COMPLEX, @@ -832,36 +796,30 @@ static const risc86_instruction_t complex_popa_op = .uop[6] = {.type = UOP_LOAD, .latency = 1}, .uop[7] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t complex_popf_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 3}, - .uop[1] = {.type = UOP_ALUX, .latency = 17} -}; -static const risc86_instruction_t complex_push_mem_op = -{ - .nr_uops = 2, - .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_STORED, .latency = 1}, - .uop[1] = {.type = UOP_STOREA, .latency = 1} -}; -static const risc86_instruction_t complex_pushf_op = +static const macro_op_t popf_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_STORED, .latency = 1}, - .uop[2] = {.type = UOP_STOREA, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALU, .latency = 6}, + .uop[2] = {.type = UOP_ALUP0, .latency = 10} }; -static const risc86_instruction_t complex_ret_op = +static const macro_op_t pushf_op = +{ + .nr_uops = 3, + .decode_type = DECODE_COMPLEX, + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_STORED, .latency = 1}, + .uop[2] = {.type = UOP_STOREA, .latency = 1} +}; +static const macro_op_t ret_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_retf_op = +static const macro_op_t retf_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, @@ -869,52 +827,52 @@ static const risc86_instruction_t complex_retf_op = .uop[1] = {.type = UOP_ALU, .latency = 3}, .uop[2] = {.type = UOP_BRANCH, .latency = 1} }; -static const risc86_instruction_t complex_scas_op = +static const macro_op_t scas_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_scasb_op = +static const macro_op_t scasb_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_setcc_mem_op = +static const macro_op_t setcc_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_FSTORED, .latency = 1}, - .uop[3] = {.type = UOP_FSTOREA, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_FSTORED, .latency = 1}, + .uop[3] = {.type = UOP_FSTOREA, .latency = 1} }; -static const risc86_instruction_t complex_setcc_reg_op = +static const macro_op_t setcc_reg_op = { .nr_uops = 3, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_ALUX, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1}, - .uop[2] = {.type = UOP_ALU, .latency = 1} + .uop[0] = {.type = UOP_ALUP0, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1}, + .uop[2] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_test_mem_op = +static const macro_op_t test_mem_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_LOAD, .latency = 1}, .uop[1] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_test_mem_b_op = +static const macro_op_t test_mem_b_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, - .uop[0] = {.type = UOP_LOAD, .latency = 1}, - .uop[1] = {.type = UOP_ALUX, .latency = 1} + .uop[0] = {.type = UOP_LOAD, .latency = 1}, + .uop[1] = {.type = UOP_ALUP0, .latency = 1} }; -static const risc86_instruction_t complex_xchg_mem_op = +static const macro_op_t xchg_mem_op = { .nr_uops = 4, .decode_type = DECODE_COMPLEX, @@ -923,60 +881,58 @@ static const risc86_instruction_t complex_xchg_mem_op = .uop[2] = {.type = UOP_STOREA, .latency = 1}, .uop[3] = {.type = UOP_ALU, .latency = 1} }; -static const risc86_instruction_t complex_xlat_op = +static const macro_op_t xlat_op = { .nr_uops = 2, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 1}, .uop[1] = {.type = UOP_LOAD, .latency = 1} }; -static const risc86_instruction_t complex_wbinvd_op = +static const macro_op_t wbinvd_op = { .nr_uops = 1, .decode_type = DECODE_COMPLEX, .uop[0] = {.type = UOP_ALU, .latency = 10000} }; - - #define INVALID NULL -static const risc86_instruction_t *opcode_timings[256] = +static const macro_op_t *opcode_timings[256] = { /* ADD ADD ADD ADD*/ -/*00*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*00*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* ADD ADD PUSH ES POP ES*/ - &alux_op, &alu_op, &push_seg_op, &complex_mov_seg_mem_op, + &alup0_op, &alu_op, &push_seg_op, &mov_seg_mem_op, /* OR OR OR OR*/ - &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, + &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* OR OR PUSH CS */ - &alux_op, &alu_op, &push_seg_op, INVALID, + &alup0_op, &alu_op, &push_seg_op, INVALID, /* ADC ADC ADC ADC*/ -/*10*/ &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op, +/*10*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* ADC ADC PUSH SS POP SS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* SBB SBB SBB SBB*/ -/*10*/ &complex_alux_store_op,&complex_alu_store_op, &complex_load_alux_op,&complex_load_alu_op, +/*10*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* SBB SBB PUSH DS POP DS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* AND AND AND AND*/ -/*20*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*20*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* AND AND DAA*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* SUB SUB SUB SUB*/ - &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, + &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* SUB SUB DAS*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* XOR XOR XOR XOR*/ -/*30*/ &alux_store_op, &alu_store_op, &load_alux_op, &load_alu_op, +/*30*/ &alup0_store_op, &alu_store_op, &load_alup0_op, &load_alu_op, /* XOR XOR AAA*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* CMP CMP CMP CMP*/ - &load_alux_op, &load_alu_op, &load_alux_op, &load_alu_op, + &load_alup0_op, &load_alu_op, &load_alup0_op, &load_alu_op, /* CMP CMP AAS*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* INC EAX INC ECX INC EDX INC EBX*/ /*40*/ &alu_op, &alu_op, &alu_op, &alu_op, @@ -997,12 +953,12 @@ static const risc86_instruction_t *opcode_timings[256] = &pop_reg_op, &pop_reg_op, &pop_reg_op, &pop_reg_op, /* PUSHA POPA BOUND ARPL*/ -/*60*/ &complex_pusha_op, &complex_popa_op, &complex_bound_op, &complex_arpl_op, +/*60*/ &pusha_op, &popa_op, &bound_op, &arpl_op, INVALID, INVALID, INVALID, INVALID, /* PUSH imm IMUL PUSH imm IMUL*/ - &push_imm_op, &complex_mul_op, &push_imm_op, &complex_mul_op, + &push_imm_op, &mul_op, &push_imm_op, &mul_op, /* INSB INSW OUTSB OUTSW*/ - &complex_ins_op, &complex_ins_op, &complex_outs_op, &complex_outs_op, + &ins_op, &ins_op, &outs_op, &outs_op, /* Jxx*/ /*70*/ &branch_op, &branch_op, &branch_op, &branch_op, @@ -1012,107 +968,107 @@ static const risc86_instruction_t *opcode_timings[256] = /*80*/ INVALID, INVALID, INVALID, INVALID, /* TEST TEST XCHG XCHG*/ - &complex_test_mem_b_op, &complex_test_mem_op, &complex_xchg_mem_op, &complex_xchg_mem_op, + &test_mem_b_op, &test_mem_op, &xchg_mem_op, &xchg_mem_op, /* MOV MOV MOV MOV*/ &store_op, &store_op, &load_op, &load_op, /* MOV from seg LEA MOV to seg POP*/ - &complex_mov_mem_seg_op, &store_op, &complex_mov_seg_mem_op, &pop_mem_op, + &mov_mem_seg_op, &store_op, &mov_seg_mem_op, &pop_mem_op, /* NOP XCHG XCHG XCHG*/ -/*90*/ &limm_op, &xchg_op, &xchg_op, &xchg_op, +/*90*/ &fxch_op, &xchg_op, &xchg_op, &xchg_op, /* XCHG XCHG XCHG XCHG*/ &xchg_op, &xchg_op, &xchg_op, &xchg_op, /* CBW CWD CALL far WAIT*/ - &complex_alu1_op, &complex_alu1_op, &complex_call_far_op, &limm_op, + &complex_alu1_op, &complex_alu1_op, &call_far_op, &fxch_op, /* PUSHF POPF SAHF LAHF*/ - &complex_pushf_op, &complex_popf_op, &complex_alux1_op, &complex_alux1_op, + &pushf_op, &popf_op, &complex_alup0_1_op, &complex_alup0_1_op, /* MOV MOV MOV MOV*/ /*a0*/ &load_op, &load_op, &store_op, &store_op, /* MOVSB MOVSW CMPSB CMPSW*/ - &movs_op, &movs_op, &complex_cmpsb_op, &complex_cmps_op, + &movs_op, &movs_op, &cmpsb_op, &cmps_op, /* TEST TEST STOSB STOSW*/ &test_reg_b_op, &test_reg_op, &stos_op, &stos_op, /* LODSB LODSW SCASB SCASW*/ - &lods_op, &lods_op, &complex_scasb_op, &complex_scas_op, + &lods_op, &lods_op, &scasb_op, &scas_op, /* MOV*/ -/*b0*/ &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, +/*b0*/ &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, /* RET imm RET*/ -/*c0*/ INVALID, INVALID, &complex_ret_op, &complex_ret_op, +/*c0*/ INVALID, INVALID, &ret_op, &ret_op, /* LES LDS MOV MOV*/ - &complex_lss_op, &complex_lss_op, &store_op, &store_op, + &lss_op, &lss_op, &store_op, &store_op, /* ENTER LEAVE RETF RETF*/ - &complex_enter_op, &leave_op, &complex_retf_op, &complex_retf_op, + &enter_op, &leave_op, &retf_op, &retf_op, /* INT3 INT INTO IRET*/ - &complex_int_op, &complex_int_op, &complex_int_op, &complex_iret_op, + &int_op, &int_op, &int_op, &iret_op, /*d0*/ INVALID, INVALID, INVALID, INVALID, /* AAM AAD SETALC XLAT*/ - &complex_alux6_op, &complex_alux3_op, &complex_alux1_op, &complex_xlat_op, + &alup0_6_op, &alup0_3_op, &complex_alup0_1_op, &xlat_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, /* LOOPNE LOOPE LOOP JCXZ*/ -/*e0*/ &complex_loop_op, &complex_loop_op, &loop_op, &complex_loop_op, +/*e0*/ &loop_op, &loop_op, &loop_op, &loop_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* CALL JMP JMP JMP*/ - &store_op, &branch_op, &complex_jmp_far_op, &branch_op, + &store_op, &branch_op, &jmp_far_op, &branch_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* REPNE REPE*/ /*f0*/ INVALID, INVALID, INVALID, INVALID, /* HLT CMC*/ - &complex_alux1_op, &complex_alu2_op, INVALID, INVALID, + &complex_alup0_1_op, &alu2_op, INVALID, INVALID, /* CLC STC CLI STI*/ - &complex_alu1_op, &complex_alu1_op, &complex_cli_sti_op, &complex_cli_sti_op, + &complex_alu1_op, &complex_alu1_op, &cli_sti_op, &cli_sti_op, /* CLD STD INCDEC*/ - &complex_alu1_op, &complex_alu1_op, &alux_store_op, INVALID + &complex_alu1_op, &complex_alu1_op, &alup0_store_op, INVALID }; -static const risc86_instruction_t *opcode_timings_mod3[256] = +static const macro_op_t *opcode_timings_mod3[256] = { /* ADD ADD ADD ADD*/ -/*00*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*00*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* ADD ADD PUSH ES POP ES*/ - &alux_op, &alu_op, &push_seg_op, &complex_mov_seg_mem_op, + &alup0_op, &alu_op, &push_seg_op, &mov_seg_mem_op, /* OR OR OR OR*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* OR OR PUSH CS */ - &alux_op, &alu_op, &push_seg_op, INVALID, + &alup0_op, &alu_op, &push_seg_op, INVALID, /* ADC ADC ADC ADC*/ -/*10*/ &complex_alux1_op, &complex_alu1_op, &complex_alux1_op, &complex_alu1_op, +/*10*/ &complex_alup0_1_op, &complex_alu1_op, &complex_alup0_1_op, &complex_alu1_op, /* ADC ADC PUSH SS POP SS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* SBB SBB SBB SBB*/ - &complex_alux1_op, &complex_alu1_op, &complex_alux1_op, &complex_alu1_op, + &complex_alup0_1_op, &complex_alu1_op, &complex_alup0_1_op, &complex_alu1_op, /* SBB SBB PUSH DS POP DS*/ - &complex_alux1_op, &complex_alu1_op, &push_seg_op, &complex_mov_seg_mem_op, + &complex_alup0_1_op, &complex_alu1_op, &push_seg_op, &mov_seg_mem_op, /* AND AND AND AND*/ -/*20*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*20*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* AND AND DAA*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* SUB SUB SUB SUB*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* SUB SUB DAS*/ - &alux_op, &alu_op, INVALID, &complex_alux1_op, + &alup0_op, &alu_op, INVALID, &complex_alup0_1_op, /* XOR XOR XOR XOR*/ -/*30*/ &alux_op, &alu_op, &alux_op, &alu_op, +/*30*/ &alup0_op, &alu_op, &alup0_op, &alu_op, /* XOR XOR AAA*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* CMP CMP CMP CMP*/ - &alux_op, &alu_op, &alux_op, &alu_op, + &alup0_op, &alu_op, &alup0_op, &alu_op, /* CMP CMP AAS*/ - &alux_op, &alu_op, INVALID, &complex_alux6_op, + &alup0_op, &alu_op, INVALID, &alup0_6_op, /* INC EAX INC ECX INC EDX INC EBX*/ /*40*/ &alu_op, &alu_op, &alu_op, &alu_op, @@ -1133,12 +1089,12 @@ static const risc86_instruction_t *opcode_timings_mod3[256] = &pop_reg_op, &pop_reg_op, &pop_reg_op, &pop_reg_op, /* PUSHA POPA BOUND ARPL*/ -/*60*/ &complex_pusha_op, &complex_popa_op, &complex_bound_op, &complex_arpl_op, +/*60*/ &pusha_op, &popa_op, &bound_op, &arpl_op, INVALID, INVALID, INVALID, INVALID, /* PUSH imm IMUL PUSH imm IMUL*/ - &push_imm_op, &complex_mul_op, &push_imm_op, &complex_mul_op, + &push_imm_op, &mul_op, &push_imm_op, &mul_op, /* INSB INSW OUTSB OUTSW*/ - &complex_ins_op, &complex_ins_op, &complex_outs_op, &complex_outs_op, + &ins_op, &ins_op, &outs_op, &outs_op, /* Jxx*/ /*70*/ &branch_op, &branch_op, &branch_op, &branch_op, @@ -1148,88 +1104,89 @@ static const risc86_instruction_t *opcode_timings_mod3[256] = /*80*/ INVALID, INVALID, INVALID, INVALID, /* TEST TEST XCHG XCHG*/ - &complex_alu1_op, &complex_alu1_op, &complex_alu3_op, &complex_alu3_op, + &complex_alu1_op, &complex_alu1_op, &alu3_op, &alu3_op, /* MOV MOV MOV MOV*/ &store_op, &store_op, &load_op, &load_op, /* MOV from seg LEA MOV to seg POP*/ - &mov_reg_seg_op, &store_op, &complex_mov_seg_reg_op, &pop_reg_op, + &mov_reg_seg_op, &store_op, &mov_seg_reg_op, &pop_reg_op, /* NOP XCHG XCHG XCHG*/ -/*90*/ &limm_op, &xchg_op, &xchg_op, &xchg_op, +/*90*/ &fxch_op, &xchg_op, &xchg_op, &xchg_op, /* XCHG XCHG XCHG XCHG*/ &xchg_op, &xchg_op, &xchg_op, &xchg_op, /* CBW CWD CALL far WAIT*/ - &complex_alu1_op, &complex_alu1_op, &complex_call_far_op, &limm_op, + &complex_alu1_op, &complex_alu1_op, &call_far_op, &fxch_op, /* PUSHF POPF SAHF LAHF*/ - &complex_pushf_op, &complex_popf_op, &complex_alux1_op, &complex_alux1_op, + &pushf_op, &popf_op, &complex_alup0_1_op, &complex_alup0_1_op, /* MOV MOV MOV MOV*/ /*a0*/ &load_op, &load_op, &store_op, &store_op, /* MOVSB MOVSW CMPSB CMPSW*/ - &movs_op, &movs_op, &complex_cmpsb_op, &complex_cmps_op, + &movs_op, &movs_op, &cmpsb_op, &cmps_op, /* TEST TEST STOSB STOSW*/ &test_reg_b_op, &test_reg_op, &stos_op, &stos_op, /* LODSB LODSW SCASB SCASW*/ - &lods_op, &lods_op, &complex_scasb_op, &complex_scas_op, + &lods_op, &lods_op, &scasb_op, &scas_op, /* MOV*/ -/*b0*/ &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, +/*b0*/ &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_op, &alu_op, /* RET imm RET*/ -/*c0*/ INVALID, INVALID, &complex_ret_op, &complex_ret_op, +/*c0*/ INVALID, INVALID, &ret_op, &ret_op, /* LES LDS MOV MOV*/ - &complex_lss_op, &complex_lss_op, &store_op, &store_op, + &lss_op, &lss_op, &store_op, &store_op, /* ENTER LEAVE RETF RETF*/ - &complex_enter_op, &leave_op, &complex_retf_op, &complex_retf_op, + &enter_op, &leave_op, &retf_op, &retf_op, /* INT3 INT INTO IRET*/ - &complex_int_op, &complex_int_op, &complex_int_op, &complex_iret_op, + &int_op, &int_op, &int_op, &iret_op, /*d0*/ INVALID, INVALID, INVALID, INVALID, /* AAM AAD SETALC XLAT*/ - &complex_alux6_op, &complex_alux3_op, &complex_alux1_op, &complex_xlat_op, + &alup0_6_op, &alup0_3_op, &complex_alup0_1_op, &xlat_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, + /* LOOPNE LOOPE LOOP JCXZ*/ -/*e0*/ &complex_loop_op, &complex_loop_op, &loop_op, &complex_loop_op, +/*e0*/ &loop_op, &loop_op, &loop_op, &loop_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* CALL JMP JMP JMP*/ - &store_op, &branch_op, &complex_jmp_far_op, &branch_op, + &store_op, &branch_op, &jmp_far_op, &branch_op, /* IN AL IN AX OUT_AL OUT_AX*/ - &complex_in_op, &complex_in_op, &complex_out_op, &complex_out_op, + &in_op, &in_op, &out_op, &out_op, /* REPNE REPE*/ /*f0*/ INVALID, INVALID, INVALID, INVALID, /* HLT CMC*/ - &complex_alux1_op, &complex_alu2_op, INVALID, INVALID, + &complex_alup0_1_op, &alu2_op, INVALID, INVALID, /* CLC STC CLI STI*/ - &complex_alu1_op, &complex_alu1_op, &complex_cli_sti_op, &complex_cli_sti_op, + &complex_alu1_op, &complex_alu1_op, &cli_sti_op, &cli_sti_op, /* CLD STD INCDEC*/ - &complex_alu1_op, &complex_alu1_op, &complex_alux1_op, INVALID + &complex_alu1_op, &complex_alu1_op, &complex_alup0_1_op, INVALID }; -static const risc86_instruction_t *opcode_timings_0f[256] = +static const macro_op_t *opcode_timings_0f[256] = { -/*00*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - INVALID, &complex_alu6_op, &complex_alu6_op, INVALID, - &complex_invd_op, &complex_wbinvd_op, INVALID, INVALID, - INVALID, &load_op, &complex_femms_op, INVALID, +/*00*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + INVALID, &alu6_op, &alu6_op, INVALID, + &invd_op, &wbinvd_op, INVALID, INVALID, + INVALID, &load_op, &femms_op, INVALID, /*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*20*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - &complex_alu6_op, &complex_alu6_op, INVALID, INVALID, +/*20*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*30*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, INVALID, +/*30*/ &alu6_op, &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, @@ -1250,7 +1207,7 @@ static const risc86_instruction_t *opcode_timings_0f[256] = INVALID, INVALID, &mload_op, &mload_op, /*70*/ INVALID, &load_mmx_shift_op, &load_mmx_shift_op, &load_mmx_shift_op, - &load_mmx_op, &load_mmx_op, &load_mmx_op, &complex_emms_op, + &load_mmx_op, &load_mmx_op, &load_mmx_op, &emms_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, &mstore_op, &mstore_op, @@ -1259,23 +1216,23 @@ static const risc86_instruction_t *opcode_timings_0f[256] = &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, -/*90*/ &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, - &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, &complex_setcc_reg_op, +/*90*/ &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, + &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, &setcc_reg_op, -/*a0*/ &push_seg_op, &complex_mov_seg_mem_op,&complex_cpuid_op, &complex_load_alu_op, - &complex_alu_store_op, &complex_alu_store_op, INVALID, INVALID, - &push_seg_op, &complex_mov_seg_mem_op,INVALID, &complex_load_alu_op, - &complex_alu_store_op, &complex_alu_store_op, INVALID, &complex_mul_op, +/*a0*/ &push_seg_op, &mov_seg_mem_op, &cpuid_op, &load_alu_op, + &alu_store_op, &alu_store_op, INVALID, INVALID, + &push_seg_op, &mov_seg_mem_op, INVALID, &load_alu_op, + &alu_store_op, &alu_store_op, INVALID, &mul_op, -/*b0*/ &complex_cmpxchg_b_op, &complex_cmpxchg_op, &complex_lss_op, &complex_load_alu_op, - &complex_lss_op, &complex_lss_op, &load_alux_op, &load_alu_op, - INVALID, INVALID, &complex_load_alu_op, &complex_load_alu_op, - &complex_bsx_op, &complex_bsx_op, &load_alux_op, &load_alu_op, +/*b0*/ &cmpxchg_b_op, &cmpxchg_op, &lss_op, &load_alu_op, + &lss_op, &lss_op, &load_alup0_op, &load_alu_op, + INVALID, INVALID, &load_alu_op, &load_alu_op, + &bsx_op, &bsx_op, &load_alup0_op, &load_alu_op, -/*c0*/ &complex_alux_store_op, &complex_alu_store_op, INVALID, INVALID, - INVALID, INVALID, INVALID, &complex_cmpxchg_op, +/*c0*/ &alup0_store_op, &alu_store_op, INVALID, INVALID, + INVALID, INVALID, INVALID, &cmpxchg_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, &bswap_op, @@ -1294,182 +1251,182 @@ static const risc86_instruction_t *opcode_timings_0f[256] = &load_mmx_op, &load_mmx_op, &load_mmx_op, INVALID, &load_mmx_op, &load_mmx_op, &load_mmx_op, INVALID, }; -static const risc86_instruction_t *opcode_timings_0f_mod3[256] = +static const macro_op_t *opcode_timings_0f_mod3[256] = { -/*00*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - INVALID, &complex_alu6_op, &complex_alu6_op, INVALID, - &complex_invd_op, &complex_wbinvd_op, INVALID, INVALID, - INVALID, INVALID, &complex_femms_op, INVALID, +/*00*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + INVALID, &alu6_op, &alu6_op, INVALID, + &invd_op, &wbinvd_op, INVALID, INVALID, + INVALID, INVALID, &femms_op, INVALID, /*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*20*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, - &complex_alu6_op, &complex_alu6_op, INVALID, INVALID, +/*20*/ &alu6_op, &alu6_op, &alu6_op, &alu6_op, + &alu6_op, &alu6_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, -/*30*/ &complex_alu6_op, &complex_alu6_op, &complex_alu6_op, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*30*/ &alu6_op, &alu6_op, &alu6_op, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*40*/ INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*40*/ INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*50*/ INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, +/*50*/ INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, -/*60*/ &mmx_op, &mmx_op, &mmx_op, &mmx_op, - &mmx_op, &mmx_op, &mmx_op, &mmx_op, - &mmx_op, &mmx_op, &mmx_op, &mmx_op, - INVALID, INVALID, &mmx_op, &mmx_op, +/*60*/ &mmx_op, &mmx_op, &mmx_op, &mmx_op, + &mmx_op, &mmx_op, &mmx_op, &mmx_op, + &mmx_op, &mmx_op, &mmx_op, &mmx_op, + INVALID, INVALID, &mmx_op, &mmx_op, -/*70*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - &mmx_op, &mmx_op, &mmx_op, &complex_emms_op, - INVALID, INVALID, INVALID, INVALID, - INVALID, INVALID, &mmx_op, &mmx_op, +/*70*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + &mmx_op, &mmx_op, &mmx_op, &emms_op, + INVALID, INVALID, INVALID, INVALID, + INVALID, INVALID, &mmx_op, &mmx_op, /*80*/ &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, &branch_op, -/*90*/ &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, - &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, &complex_setcc_mem_op, +/*90*/ &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, + &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, &setcc_mem_op, -/*a0*/ &push_seg_op, &complex_mov_seg_mem_op, &complex_cpuid_op, &complex_alu1_op, - &complex_alu1_op, &complex_alu1_op, INVALID, INVALID, - &push_seg_op, &complex_mov_seg_mem_op, INVALID, &complex_alu1_op, - &complex_alu1_op, &complex_alu1_op, INVALID, &complex_mul_op, +/*a0*/ &push_seg_op, &mov_seg_mem_op, &cpuid_op, &complex_alu1_op, + &complex_alu1_op, &complex_alu1_op, INVALID, INVALID, + &push_seg_op, &mov_seg_mem_op, INVALID, &complex_alu1_op, + &complex_alu1_op, &complex_alu1_op, INVALID, &mul_op, -/*b0*/ &complex_cmpxchg_b_op, &complex_cmpxchg_op, &complex_lss_op, &complex_alu1_op, - &complex_lss_op, &complex_lss_op, &alux_op, &alu_op, - INVALID, INVALID, &complex_alu1_op, &complex_alu1_op, - &complex_bsx_op, &complex_bsx_op, &alux_op, &alu_op, +/*b0*/ &cmpxchg_b_op, &cmpxchg_op, &lss_op, &complex_alu1_op, + &lss_op, &lss_op, &alup0_op, &alu_op, + INVALID, INVALID, &complex_alu1_op, &complex_alu1_op, + &bsx_op, &bsx_op, &alup0_op, &alu_op, -/*c0*/ &complex_alux1_op, &complex_alu1_op, INVALID, INVALID, - INVALID, INVALID, INVALID, INVALID, - &bswap_op, &bswap_op, &bswap_op, &bswap_op, - &bswap_op, &bswap_op, &bswap_op, &bswap_op, +/*c0*/ &complex_alup0_1_op, &complex_alu1_op, INVALID, INVALID, + INVALID, INVALID, INVALID, INVALID, + &bswap_op, &bswap_op, &bswap_op, &bswap_op, + &bswap_op, &bswap_op, &bswap_op, &bswap_op, -/*d0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - INVALID, &mmx_mul_op, INVALID, INVALID, - &mmx_op, &mmx_op, INVALID, &mmx_op, - &mmx_op, &mmx_op, INVALID, &mmx_op, +/*d0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + INVALID, &mmx_mul_op, INVALID, INVALID, + &mmx_op, &mmx_op, INVALID, &mmx_op, + &mmx_op, &mmx_op, INVALID, &mmx_op, -/*e0*/ &mmx_op, &mmx_shift_op, &mmx_shift_op, INVALID, - INVALID, &pmul_op, INVALID, INVALID, - &mmx_op, &mmx_op, INVALID, &mmx_op, - &mmx_op, &mmx_op, INVALID, &mmx_op, +/*e0*/ &mmx_op, &mmx_shift_op, &mmx_shift_op, INVALID, + INVALID, &pmul_op, INVALID, INVALID, + &mmx_op, &mmx_op, INVALID, &mmx_op, + &mmx_op, &mmx_op, INVALID, &mmx_op, -/*f0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, - INVALID, &pmul_op, INVALID, INVALID, - &mmx_op, &mmx_op, &mmx_op, INVALID, - &mmx_op, &mmx_op, &mmx_op, INVALID, +/*f0*/ INVALID, &mmx_shift_op, &mmx_shift_op, &mmx_shift_op, + INVALID, &pmul_op, INVALID, INVALID, + &mmx_op, &mmx_op, &mmx_op, INVALID, + &mmx_op, &mmx_op, &mmx_op, INVALID, }; -static const risc86_instruction_t *opcode_timings_shift[8] = +static const macro_op_t *opcode_timings_shift[8] = { - &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, - &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op, &complex_alu_store_op + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op }; -static const risc86_instruction_t *opcode_timings_shift_b[8] = +static const macro_op_t *opcode_timings_shift_b[8] = { - &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, - &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op, &complex_alux_store_op + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op }; -static const risc86_instruction_t *opcode_timings_shift_mod3[8] = +static const macro_op_t *opcode_timings_shift_mod3[8] = { &complex_alu1_op, &complex_alu1_op, &complex_alu1_op, &complex_alu1_op, &alu_op, &alu_op, &alu_op, &alu_op }; -static const risc86_instruction_t *opcode_timings_shift_b_mod3[8] = +static const macro_op_t *opcode_timings_shift_b_mod3[8] = { - &complex_alux1_op, &complex_alux1_op, &complex_alux1_op, &complex_alux1_op, - &alux_op, &alux_op, &alux_op, &alux_op + &complex_alup0_1_op, &complex_alup0_1_op, &complex_alup0_1_op, &complex_alup0_1_op, + &alup0_op, &alup0_op, &alup0_op, &alup0_op }; -static const risc86_instruction_t *opcode_timings_80[8] = +static const macro_op_t *opcode_timings_80[8] = { - &alux_store_op, &alux_store_op, &complex_alux_store_op, &complex_alux_store_op, - &alux_store_op, &alux_store_op, &alux_store_op, &alux_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, + &alup0_store_op, &alup0_store_op, &alup0_store_op, &alup0_store_op, }; -static const risc86_instruction_t *opcode_timings_80_mod3[8] = +static const macro_op_t *opcode_timings_80_mod3[8] = { - &alux_op, &alux_op, &alux_store_op, &alux_store_op, - &alux_op, &alux_op, &alux_op, &alux_op, + &alup0_op, &alup0_op, &alup0_store_op, &alup0_store_op, + &alup0_op, &alup0_op, &alup0_op, &alup0_op, }; -static const risc86_instruction_t *opcode_timings_8x[8] = +static const macro_op_t *opcode_timings_8x[8] = { - &alu_store_op, &alu_store_op, &complex_alu_store_op, &complex_alu_store_op, - &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, -}; -static const risc86_instruction_t *opcode_timings_8x_mod3[8] = + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, + &alu_store_op, &alu_store_op, &alu_store_op, &alu_store_op, +}; +static const macro_op_t *opcode_timings_8x_mod3[8] = { - &alu_op, &alu_op, &alu_store_op, &alu_store_op, - &alu_op, &alu_op, &alu_op, &alu_op, + &alu_op, &alu_op, &alu_store_op, &alu_store_op, + &alu_op, &alu_op, &alu_op, &alu_op, }; -static const risc86_instruction_t *opcode_timings_f6[8] = +static const macro_op_t *opcode_timings_f6[8] = { /* TST NOT NEG*/ - &test_mem_imm_b_op, INVALID, &complex_alux_store_op, &complex_alux_store_op, + &test_mem_imm_b_op, INVALID, &alup0_store_op, &alup0_store_op, /* MUL IMUL DIV IDIV*/ - &complex_mul_mem_op, &complex_mul_mem_op, &complex_div16_mem_op, &complex_div16_mem_op, + &mul_mem_op, &mul_mem_op, &div16_mem_op, &div16_mem_op, }; -static const risc86_instruction_t *opcode_timings_f6_mod3[8] = +static const macro_op_t *opcode_timings_f6_mod3[8] = { /* TST NOT NEG*/ - &test_reg_b_op, INVALID, &alux_op, &alux_op, + &test_reg_b_op, INVALID, &alup0_op, &alup0_op, /* MUL IMUL DIV IDIV*/ - &complex_mul_op, &complex_mul_op, &complex_div16_op, &complex_div16_op, + &mul_op, &mul_op, &div16_op, &div16_op, }; -static const risc86_instruction_t *opcode_timings_f7[8] = +static const macro_op_t *opcode_timings_f7[8] = { /* TST NOT NEG*/ - &test_mem_imm_op, INVALID, &complex_alu_store_op, &complex_alu_store_op, + &test_mem_imm_op, INVALID, &alu_store_op, &alu_store_op, /* MUL IMUL DIV IDIV*/ - &complex_mul64_mem_op, &complex_mul64_mem_op, &complex_div32_mem_op, &complex_div32_mem_op, + &mul64_mem_op, &mul64_mem_op, &div32_mem_op, &div32_mem_op, }; -static const risc86_instruction_t *opcode_timings_f7_mod3[8] = +static const macro_op_t *opcode_timings_f7_mod3[8] = { /* TST NOT NEG*/ &test_reg_op, INVALID, &alu_op, &alu_op, /* MUL IMUL DIV IDIV*/ - &complex_mul64_op, &complex_mul64_op, &complex_div32_op, &complex_div32_op, + &mul64_op, &mul64_op, &div32_op, &div32_op, }; -static const risc86_instruction_t *opcode_timings_ff[8] = +static const macro_op_t *opcode_timings_ff[8] = { /* INC DEC CALL CALL far*/ - &alu_store_op, &alu_store_op, &store_op, &complex_call_far_op, + &alu_store_op, &alu_store_op, &store_op, &call_far_op, /* JMP JMP far PUSH*/ - &branch_op, &complex_jmp_far_op, &push_mem_op, INVALID + &branch_op, &jmp_far_op, &push_mem_op, INVALID }; -static const risc86_instruction_t *opcode_timings_ff_mod3[8] = +static const macro_op_t *opcode_timings_ff_mod3[8] = { /* INC DEC CALL CALL far*/ - &complex_alu1_op, &complex_alu1_op, &store_op, &complex_call_far_op, + &complex_alu1_op, &complex_alu1_op, &store_op, &call_far_op, /* JMP JMP far PUSH*/ - &branch_op, &complex_jmp_far_op, &complex_push_mem_op, INVALID + &branch_op, &jmp_far_op, &complex_push_mem_op, INVALID }; -static const risc86_instruction_t *opcode_timings_d8[8] = +static const macro_op_t *opcode_timings_d8[8] = { /* FADDs FMULs FCOMs FCOMPs*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FSUBs FSUBRs FDIVs FDIVRs*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_d8_mod3[8] = +static const macro_op_t *opcode_timings_d8_mod3[8] = { /* FADD FMUL FCOM FCOMP*/ &fadd_op, &fmul_op, &float_op, &float_op, @@ -1477,27 +1434,27 @@ static const risc86_instruction_t *opcode_timings_d8_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op, }; -static const risc86_instruction_t *opcode_timings_d9[8] = +static const macro_op_t *opcode_timings_d9[8] = { /* FLDs FSTs FSTPs*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FLDENV FLDCW FSTENV FSTCW*/ - &complex_float_l_op, &complex_fldcw_op, &complex_float_l_op, &complex_float_op + &complex_float_l_op, &fldcw_op, &complex_float_l_op, &complex_float_op }; -static const risc86_instruction_t *opcode_timings_d9_mod3[64] = +static const macro_op_t *opcode_timings_d9_mod3[64] = { /*FLD*/ &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, &float_op, /*FXCH*/ - &limm_op, &limm_op, &limm_op, &limm_op, - &limm_op, &limm_op, &limm_op, &limm_op, + &fxch_op, &fxch_op, &fxch_op, &fxch_op, + &fxch_op, &fxch_op, &fxch_op, &fxch_op, /*FNOP*/ &float_op, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, /*FSTP*/ - &float2_op, &float2_op, &float2_op, &float2_op, - &float2_op, &float2_op, &float2_op, &float2_op, + &float2_op, &float2_op, &float2_op, &float2_op, + &float2_op, &float2_op, &float2_op, &float2_op, /* opFCHS opFABS*/ &fchs_op, &float_op, INVALID, INVALID, /* opFTST opFXAM*/ @@ -1516,28 +1473,28 @@ static const risc86_instruction_t *opcode_timings_d9_mod3[64] = &float_op, &fdiv_op, &fsin_op, &fsin_op }; -static const risc86_instruction_t *opcode_timings_da[8] = +static const macro_op_t *opcode_timings_da[8] = { /* FIADDl FIMULl FICOMl FICOMPl*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FISUBl FISUBRl FIDIVl FIDIVRl*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_da_mod3[8] = +static const macro_op_t *opcode_timings_da_mod3[8] = { INVALID, INVALID, INVALID, INVALID, /* FCOMPP*/ INVALID, &float_op, INVALID, INVALID }; -static const risc86_instruction_t *opcode_timings_db[8] = +static const macro_op_t *opcode_timings_db[8] = { /* FLDil FSTil FSTPil*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FLDe FSTPe*/ - INVALID, &complex_flde_op, INVALID, &complex_fste_op + INVALID, &flde_op, INVALID, &fste_op }; -static const risc86_instruction_t *opcode_timings_db_mod3[64] = +static const macro_op_t *opcode_timings_db_mod3[64] = { INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, @@ -1566,14 +1523,14 @@ static const risc86_instruction_t *opcode_timings_db_mod3[64] = INVALID, INVALID, INVALID, INVALID, }; -static const risc86_instruction_t *opcode_timings_dc[8] = +static const macro_op_t *opcode_timings_dc[8] = { /* FADDd FMULd FCOMd FCOMPd*/ &load_fadd_op, &load_fmul_op, &load_float_op, &load_float_op, /* FSUBd FSUBRd FDIVd FDIVRd*/ &load_float_op, &load_float_op, &fdiv_mem_op, &fdiv_mem_op, }; -static const risc86_instruction_t *opcode_timings_dc_mod3[8] = +static const macro_op_t *opcode_timings_dc_mod3[8] = { /* opFADDr opFMULr*/ &fadd_op, &fmul_op, INVALID, INVALID, @@ -1581,14 +1538,14 @@ static const risc86_instruction_t *opcode_timings_dc_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op }; -static const risc86_instruction_t *opcode_timings_dd[8] = +static const macro_op_t *opcode_timings_dd[8] = { /* FLDd FSTd FSTPd*/ - &load_float_op, INVALID, &fstore_op, &fstore_op, + &load_float_op, INVALID, &fstore_op, &fstore_op, /* FRSTOR FSAVE FSTSW*/ &complex_float_l_op, INVALID, &complex_float_l_op, &complex_float_l_op }; -static const risc86_instruction_t *opcode_timings_dd_mod3[8] = +static const macro_op_t *opcode_timings_dd_mod3[8] = { /* FFFREE FST FSTP*/ &float_op, INVALID, &float_op, &float_op, @@ -1596,14 +1553,14 @@ static const risc86_instruction_t *opcode_timings_dd_mod3[8] = &float_op, &float_op, INVALID, INVALID }; -static const risc86_instruction_t *opcode_timings_de[8] = +static const macro_op_t *opcode_timings_de[8] = { /* FIADDw FIMULw FICOMw FICOMPw*/ &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, /* FISUBw FISUBRw FIDIVw FIDIVRw*/ &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, &load_fiadd_op, }; -static const risc86_instruction_t *opcode_timings_de_mod3[8] = +static const macro_op_t *opcode_timings_de_mod3[8] = { /* FADDP FMULP FCOMPP*/ &fadd_op, &fmul_op, INVALID, &float_op, @@ -1611,14 +1568,14 @@ static const risc86_instruction_t *opcode_timings_de_mod3[8] = &float_op, &float_op, &fdiv_op, &fdiv_op, }; -static const risc86_instruction_t *opcode_timings_df[8] = +static const macro_op_t *opcode_timings_df[8] = { /* FILDiw FISTiw FISTPiw*/ &load_float_op, INVALID, &fstore_op, &fstore_op, /* FILDiq FBSTP FISTPiq*/ INVALID, &load_float_op, &complex_float_l_op, &fstore_op, }; -static const risc86_instruction_t *opcode_timings_df_mod3[8] = +static const macro_op_t *opcode_timings_df_mod3[8] = { INVALID, INVALID, INVALID, INVALID, /* FSTSW AX*/ @@ -1644,35 +1601,35 @@ static p6_unit_t *units; /*Pentium Pro has no MMX*/ static p6_unit_t ppro_units[] = { - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT)}, /*Integer X & Floating point*/ - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)}, /*Integer Y*/ - {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD)}, /*Load*/ - {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)}, /*Data Store*/ - {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)}, /*Address Store*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUP0) | (1 << UOP_FLOAT)}, /*Port 0*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH)}, /*Port 1*/ + {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD)}, /*Port 2*/ + {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED)}, /*Port 3*/ + {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA)}, /*Port 4*/ }; #define NR_PPRO_UNITS (sizeof(ppro_units) / sizeof(p6_unit_t)) /*Pentium II/Celeron assigns the multiplier to port 0, the shifter to port 1, and shares the MMX ALU*/ static p6_unit_t p2_units[] = { - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUX) | (1 << UOP_FLOAT) | /*Integer X & Floating point*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_ALUP0) | (1 << UOP_FLOAT) | /*Port 0*/ (1 << UOP_MMX) | (1 << UOP_MMX_MUL)}, - {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) | /*Integer Y*/ + {.uop_mask = (1 << UOP_ALU) | (1 << UOP_BRANCH) | /*Port 1*/ (1 << UOP_MMX) | (1 << UOP_MMX_SHIFT)}, - {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD) | (1 << UOP_MLOAD)}, /*Load*/ - {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)}, /*Data Store*/ - {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, /*Address Store*/ + {.uop_mask = (1 << UOP_LOAD) | (1 << UOP_FLOAD) | (1 << UOP_MLOAD)}, /*Port 2*/ + {.uop_mask = (1 << UOP_STORED) | (1 << UOP_FSTORED) | (1 << UOP_MSTORED)}, /*Port 3*/ + {.uop_mask = (1 << UOP_STOREA) | (1 << UOP_FSTOREA) | (1 << UOP_MSTOREA)}, /*Port 4*/ }; #define NR_P2_UNITS (sizeof(p2_units) / sizeof(p6_unit_t)) -static int uop_run(const risc86_uop_t *uop, int decode_time) +static int uop_run(const p6_uop_t *uop, int decode_time) { int c; p6_unit_t *best_unit = NULL; - double best_start_cycle = 99999; + int best_start_cycle = 99999; - /*UOP_LIMM does not require execution*/ - if (uop->type == UOP_LIMM) + /*UOP_FXCH does not require execution*/ + if (uop->type == UOP_FXCH) return decode_time; /*Find execution unit for this uOP*/ @@ -1706,7 +1663,7 @@ static int uop_run(const risc86_uop_t *uop, int decode_time) static struct { int nr_uops; - const risc86_uop_t *uops[6]; + const p6_uop_t *uops[6]; /*Earliest time a uop can start. If the timestamp is -1, then the uop is part of a dependency chain and the start time is the completion time of the previous uop*/ @@ -1745,7 +1702,10 @@ void decode_flush_p6() /*Submit uops to execution units, and determine the latest completion time*/ for (c = 0; c < (decode_buffer.nr_uops); c++) { - start_timestamp = decode_buffer.earliest_start[c]; + if (decode_buffer.earliest_start[c] == -1) + start_timestamp = last_uop_timestamp; + else + start_timestamp = decode_buffer.earliest_start[c]; last_uop_timestamp = uop_run(decode_buffer.uops[c], start_timestamp); if (last_uop_timestamp > uop_timestamp) @@ -1819,7 +1779,7 @@ static int codegen_timing_instr_length(uint64_t deps, uint32_t fetchdat, int op_ return len; } -static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8) +static void decode_instruction(const macro_op_t *ins, uint64_t deps, uint32_t fetchdat, int op_32, int bit8) { uint32_t regmask_required; uint32_t regmask_modified; @@ -1855,10 +1815,8 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u } /*Simple decoders are limited to 7 bytes & 1 uOP*/ - if (decode_type == DECODE_SIMPLE && instr_length > 7) + if ((decode_type == DECODE_SIMPLE && instr_length > 7) || (decode_type == DECODE_SIMPLE && ins->nr_uops > 1)) decode_type = DECODE_COMPLEX; - else if (decode_type == DECODE_SIMPLE && ins->nr_uops > 1) - decode_type = DECODE_COMPLEX; switch (decode_type) { @@ -1901,7 +1859,10 @@ static void decode_instruction(const risc86_instruction_t *ins, uint64_t deps, u for (c = 0; c < ins->nr_uops; c++) { decode_buffer.uops[d] = &ins->uop[c]; - decode_buffer.earliest_start[d] = earliest_start; + if (c == 0) + decode_buffer.earliest_start[d] = earliest_start; + else + decode_buffer.earliest_start[d] = -1; d++; if ((d == 3) && (ins->nr_uops > 4)) /*Ins. with >4 uOPs require the use of special units only present on 3 translate PLAs*/ @@ -2006,7 +1967,7 @@ void codegen_timing_p6_prefix(uint8_t prefix, uint32_t fetchdat) void codegen_timing_p6_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc) { - const risc86_instruction_t **ins_table; + const macro_op_t **ins_table; uint64_t *deps; int mod3 = ((fetchdat & 0xc0) == 0xc0); int old_last_complete_timestamp = last_complete_timestamp; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 5cf520dbf..e06a20894 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -185,15 +185,15 @@ extern int machine_at_tg286m_init(const machine_t *); extern int machine_at_ama932j_init(const machine_t *); extern int machine_at_px286_init(const machine_t *); extern int machine_at_quadt286_init(const machine_t *); +extern int machine_at_mr286_init(const machine_t *); extern int machine_at_neat_init(const machine_t *); extern int machine_at_neat_ami_init(const machine_t *); extern int machine_at_goldstar386_init(const machine_t *); -extern int machine_at_micronics386_init(const machine_t *); - extern int machine_at_award286_init(const machine_t *); +extern int machine_at_gdc212m_init(const machine_t *); extern int machine_at_gw286ct_init(const machine_t *); extern int machine_at_super286tr_init(const machine_t *); extern int machine_at_spc4200p_init(const machine_t *); @@ -211,7 +211,9 @@ extern const device_t *at_commodore_sl386sx_get_device(void); /* m_at_386dx_486.c */ +extern int machine_at_acc386_init(const machine_t *); extern int machine_at_ecs386_init(const machine_t *); +extern int machine_at_micronics386_init(const machine_t *); extern int machine_at_pb410a_init(const machine_t *); @@ -235,7 +237,9 @@ extern int machine_at_r418_init(const machine_t *); extern int machine_at_ls486e_init(const machine_t *); extern int machine_at_4dps_init(const machine_t *); extern int machine_at_alfredo_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_486sp3g_init(const machine_t *); +#endif /* m_at_commodore.c */ extern int machine_at_cmdpc_init(const machine_t *); @@ -264,7 +268,6 @@ extern int machine_at_p54tp4xe_init(const machine_t *); extern int machine_at_endeavor_init(const machine_t *); extern int machine_at_zappa_init(const machine_t *); extern int machine_at_mb500n_init(const machine_t *); -extern int machine_at_president_init(const machine_t *); #if defined(DEV_BRANCH) && defined(USE_VECTRA54) extern int machine_at_vectra54_init(const machine_t *); #endif @@ -275,6 +278,7 @@ extern const device_t *at_endeavor_get_device(void); #endif /* m_at_socket7_s7.c */ +extern int machine_at_chariot_init(const machine_t *); extern int machine_at_thor_init(const machine_t *); #if defined(DEV_BRANCH) && defined(USE_MRTHOR) extern int machine_at_mrthor_init(const machine_t *); @@ -297,15 +301,23 @@ extern int machine_at_i430vx_init(const machine_t *); extern int machine_at_brio80xx_init(const machine_t *); extern int machine_at_pb680_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_p55xb2_init(const machine_t *); +#endif extern int machine_at_tx97_init(const machine_t *); extern int machine_at_ym430tx_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_586t2_init(const machine_t *); extern int machine_at_807ds_init(const machine_t *); +#endif extern int machine_at_p5mms98_init(const machine_t *); -extern int machine_at_tx100_init(const machine_t *); +extern int machine_at_ficva502_init(const machine_t *); + +extern int machine_at_ficpa2012_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_advanceii_init(const machine_t *); +#endif #ifdef EMU_DEVICE_H extern const device_t *at_pb640_get_device(void); @@ -320,7 +332,6 @@ extern int machine_at_686nx_init(const machine_t *); extern int machine_at_mb600n_init(const machine_t *); extern int machine_at_8500ttc_init(const machine_t *); extern int machine_at_m6mi_init(const machine_t *); -extern int machine_at_vs440fx_init(const machine_t *); #ifdef EMU_DEVICE_H extern void machine_at_p65up5_common_init(const machine_t *, const device_t *northbridge); #endif @@ -330,11 +341,15 @@ extern int machine_at_p65up5_cp6nd_init(const machine_t *); extern int machine_at_p65up5_cpknd_init(const machine_t *); extern int machine_at_p6kfx_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) extern int machine_at_6bxc_init(const machine_t *); +#endif extern int machine_at_p2bls_init(const machine_t *); extern int machine_at_p3bf_init(const machine_t *); extern int machine_at_bf6_init(const machine_t *); -extern int machine_at_borapro_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(NO_SIO) +extern int machine_at_tsunamiatx_init(const machine_t *); +#endif /* m_at_socket370.c */ extern int machine_at_cubx_init(const machine_t *); diff --git a/src/include/86box/vid_svga.h b/src/include/86box/vid_svga.h index d1495ebbd..acdea041c 100644 --- a/src/include/86box/vid_svga.h +++ b/src/include/86box/vid_svga.h @@ -72,7 +72,7 @@ typedef struct svga_t vram_mask, charseta, charsetb, adv_flags, ma_latch, - ma, maback, + ca_adj, ma, maback, write_bank, read_bank, extra_banks[2], banked_mask, @@ -117,6 +117,7 @@ typedef struct svga_t /*Called at the start of vertical sync*/ void (*vsync_callback)(struct svga_t *svga); + uint32_t (*translate_address)(uint32_t addr, void *p); /*If set then another device is driving the monitor output and the SVGA card should not attempt to display anything */ int override; @@ -132,7 +133,10 @@ typedef struct svga_t plane_mask, writemask, colourcompare, colournocare, dac_mask, dac_status, - ksc5601_sbyte_mask; + ksc5601_sbyte_mask, ksc5601_udc_area_msb[2]; + + int ksc5601_swap_mode; + uint16_t ksc5601_english_font_type; int vertical_linedbl; diff --git a/src/include/86box/video.h b/src/include/86box/video.h index ecc4242e2..fb0c33b08 100644 --- a/src/include/86box/video.h +++ b/src/include/86box/video.h @@ -212,6 +212,7 @@ extern const device_t ati28800_wonderxl24_device; #endif /* Cirrus Logic CL-GD 54xx */ +extern const device_t gd5401_isa_device; extern const device_t gd5402_isa_device; extern const device_t gd5402_onboard_device; extern const device_t gd5420_isa_device; @@ -245,6 +246,7 @@ extern const device_t compaq_cga_2_device; extern const device_t et4000_isa_device; extern const device_t et4000k_isa_device; extern const device_t et4000k_tg286_isa_device; +extern const device_t et4000_kasan_isa_device; extern const device_t et4000_mca_device; /* Tseng ET4000-W32p */ diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index c1ccd5d39..ddc349033 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -38,6 +38,25 @@ #include <86box/video.h> #include <86box/machine.h> +int +machine_at_mr286_init(const machine_t *model) +{ + int ret; + + ret = bios_load_interleaved(L"roms/machines/mr286/V000B200-1", + L"roms/machines/mr286/V000B200-2", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_ide_init(model); + device_add(&keyboard_at_device); + device_add(&fdc_at_device); + device_add(&headland_device); + + return ret; +} static void machine_at_headland_common_init(int ht386) @@ -120,26 +139,6 @@ machine_at_ama932j_init(const machine_t *model) return ret; } -int -machine_at_px286_init(const machine_t *model) -{ - int ret; - - ret = bios_load_interleaved(L"roms/machines/px286/286-Headland-LO.BIN", - L"roms/machines/px286/286-Headland-HI.BIN", - 0x000f0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_ide_init(model); - device_add(&keyboard_at_device); - device_add(&fdc_at_device); - device_add(&headland_device); - - return ret; -} - int machine_at_quadt286_init(const machine_t *model) { @@ -201,6 +200,26 @@ machine_at_neat_ami_init(const machine_t *model) return ret; } +int +machine_at_px286_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/px286/KENITEC.BIN", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + device_add(&keyboard_at_device); + device_add(&fdc_at_device); + device_add(&neat_device); + + return ret; +} + + int machine_at_goldstar386_init(const machine_t *model) { @@ -282,6 +301,21 @@ machine_at_award286_init(const machine_t *model) return ret; } +int +machine_at_gdc212m_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/gdc212m/gdc212m_72h.bin", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_scat_init(model, 0); + + return ret; +} int machine_at_gw286ct_init(const machine_t *model) diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 3832ddc21..8cb014f2b 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -39,9 +39,30 @@ #include <86box/hdc.h> #include <86box/video.h> #include <86box/intel_flash.h> +#include <86box/sst_flash.h> #include <86box/intel_sio.h> +#include <86box/scsi_ncr53c8xx.h> #include <86box/machine.h> +int +machine_at_acc386_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/acc386/acc386.BIN", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + device_add(&acc2168_device); + device_add(&keyboard_at_ami_device); + device_add(&fdc_at_device); + + return ret; +} + int machine_at_ecs386_init(const machine_t *model) { @@ -408,7 +429,7 @@ machine_at_alfredo_init(const machine_t *model) return ret; } - +#if defined(DEV_BRANCH) && defined(NO_SIO) int machine_at_486sp3g_init(const machine_t *model) { @@ -432,12 +453,14 @@ machine_at_486sp3g_init(const machine_t *model) pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */ pci_register_slot(0x07, PCI_CARD_SCSI, 1, 2, 3, 4); /* 07 = SCSI */ pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&keyboard_ps2_pci_device); + device_add(&keyboard_ps2_ami_pci_device); /* Uses the AMIKEY KBC */ device_add(&sio_device); /* Site says it has a ZB, but the BIOS is designed for an IB. */ - device_add(&pc87306_device); - device_add(&intel_flash_bxt_ami_device); + device_add(&pc87306_device); /*PC87332*/ + device_add(&sst_flash_29ee010_device); + device_add(&ncr53c810_pci_device); device_add(&i420zx_device); return ret; } +#endif diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index 37c8868e6..83de82447 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -274,17 +274,16 @@ machine_at_bf6_init(const machine_t *model) return ret; } +#if defined(DEV_BRANCH) && defined(NO_SIO) int -machine_at_borapro_init(const machine_t *model) +machine_at_tsunamiatx_init(const machine_t *model) { - //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 - //MIGHT REQUIRE MORE EXCESSIVE TESTING! - //Reports emmersive amounts of RAM like few Intel OEM boards - //we have. + //AMI 440BX Board. Requires the PC87309 and + //doesn't like the i686 CPU's int ret; - ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", + ret = bios_load_linear(L"roms/machines/tsunamiatx/bx46200f.rom", 0x000c0000, 262144, 0); if (bios_only || !ret) @@ -294,18 +293,20 @@ machine_at_borapro_init(const machine_t *model) pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3); pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); + device_add(&i440bx_device); device_add(&piix4e_device); - device_add(&w83977ef_device); + device_add(&pc87306_device); //PC87309 device_add(&keyboard_ps2_ami_pci_device); device_add(&intel_flash_bxt_device); spd_register(SPD_TYPE_SDRAM, 0x3, 256); return ret; } +#endif \ No newline at end of file diff --git a/src/machine/m_at_socket370.c b/src/machine/m_at_socket370.c index 009999f07..871b3cc6b 100644 --- a/src/machine/m_at_socket370.c +++ b/src/machine/m_at_socket370.c @@ -140,7 +140,7 @@ machine_at_63a_init(const machine_t *model) difference between to chipsets other than the name. */ int ret; - ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", + ret = bios_load_linear(L"roms/machines/63a1/63a-q3.bin", 0x000c0000, 262144, 0); if (bios_only || !ret) @@ -198,4 +198,3 @@ machine_at_apas3_init(const machine_t *model) return ret; } - diff --git a/src/machine/m_at_socket4_5.c b/src/machine/m_at_socket4_5.c index a73cba1d9..59e237567 100644 --- a/src/machine/m_at_socket4_5.c +++ b/src/machine/m_at_socket4_5.c @@ -351,37 +351,6 @@ machine_at_mb500n_init(const machine_t *model) return ret; } - -int -machine_at_president_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/president/bios.bin", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&i430fx_device); - device_add(&piix_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83877f_president_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - - #if defined(DEV_BRANCH) && defined(USE_VECTRA54) int machine_at_vectra54_init(const machine_t *model) diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index d18132a49..053401723 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -45,6 +45,35 @@ #include "cpu.h" #include <86box/machine.h> +int +machine_at_chariot_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/chariot/P5IV183.ROM", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 2, 1); + pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 3, 2, 1); + + device_add(&i430fx_device); + device_add(&piix_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&pc87306_device); + device_add(&intel_flash_bxt_device); + + return ret; +} static void machine_at_thor_common_init(const machine_t *model, int mr) @@ -136,7 +165,6 @@ machine_at_pb640_init(const machine_t *model) return ret; } - const device_t * at_pb640_get_device(void) { @@ -877,13 +905,12 @@ machine_at_p5mms98_init(const machine_t *model) return ret; } -#if defined(DEV_BRANCH) && defined(NO_SIO) int -machine_at_tx100_init(const machine_t *model) +machine_at_ficva502_init(const machine_t *model) { int ret; - ret = bios_load_linear(L"roms/machines/tx100/T100108E.rom", + ret = bios_load_linear(L"roms/machines/ficva502/VA502bp.BIN", 0x000e0000, 131072, 0); if (bios_only || !ret) @@ -900,14 +927,45 @@ machine_at_tx100_init(const machine_t *model) pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); device_add(&via_vpx_device); device_add(&via_vt82c586b_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&um8669f_device); //IT8661F + device_add(&keyboard_ps2_pci_device); + device_add(&fdc37c669_device); device_add(&sst_flash_29ee010_device); spd_register(SPD_TYPE_SDRAM, 0xF, 256); return ret; } +int +machine_at_ficpa2012_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/ficpa2012/113jb16.awd", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + device_add(&via_vp3_device); + device_add(&via_vt82c586b_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83877f_device); + device_add(&sst_flash_39sf010_device); + spd_register(SPD_TYPE_SDRAM, 0xF, 64); + + return ret; +} + +#if defined(DEV_BRANCH) && defined(NO_SIO) int machine_at_advanceii_init(const machine_t *model) { diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index dba53237b..fd7b5bcea 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -158,38 +158,6 @@ machine_at_m6mi_init(const machine_t *model) return ret; } -#if defined(DEV_BRANCH) && defined(NO_SIO) -int -machine_at_vs440fx_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear_combined2(L"roms/machines/vs440fx/1011CS1_.BIO", - L"roms/machines/vs440fx/1011CS1_.BI1", - L"roms/machines/vs440fx/1011CS1_.BI2", - L"roms/machines/vs440fx/1011CS1_.BI3", - L"roms/machines/vs440fx/1011CS1_.RCV", - 0x3a000, 128); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_ami_pci_device); - //device_add(&pc87307_device); - device_add(&pc87306_device); - device_add(&intel_flash_bxt_ami_device); - - return ret; -} -#endif - void machine_at_p65up5_common_init(const machine_t *model, const device_t *northbridge) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 2ce007f51..573cdfdd9 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -37,11 +37,13 @@ #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) #define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"Cyrix", cpus_6x863V}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S73VCH {{ "Intel", cpus_Pentium3V}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_SS7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip_SS7}, {"AMD", cpus_K56_SS7}, {"Cyrix", cpus_6x86SS7}, {"", NULL}} #else #define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S73VCH {{ "Intel", cpus_Pentium3V}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_SS7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip_SS7}, {"AMD", cpus_K56_SS7}, {"", NULL}, {"", NULL}} #endif @@ -49,11 +51,13 @@ #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) #define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x863V}, {"", NULL}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S73VCH {{ "Intel", cpus_Pentium3V}, {"", NULL }, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_SS7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip_SS7}, {"AMD", cpus_K56_SS7}, {"Cyrix", cpus_6x86SS7}, {"", NULL}} #else #define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S73V {{ "Intel", cpus_Pentium3V}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}} +#define MACHINE_CPUS_PENTIUM_S73VCH {{ "Intel", cpus_Pentium3V}, {"", NULL }, {"", NULL}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_S7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"", NULL}, {"", NULL}} #define MACHINE_CPUS_PENTIUM_SS7 {{ "Intel", cpus_Pentium}, {"IDT", cpus_WinChip_SS7}, {"AMD", cpus_K56_SS7}, {"", NULL}, {"", NULL}} #endif @@ -106,10 +110,12 @@ const machine_t machines[] = { { "[286 ISA] Award 286 clone", "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL }, { "[286 ISA] Phoenix 286 clone", "px286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_px286_init, NULL }, { "[286 ISA] Quadtel 286 clone", "quadt286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL }, + { "[286 ISA] MR 286 clone", "mr286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_mr286_init, NULL }, { "[286 ISA] Commodore PC 30 III", "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL }, { "[286 ISA] Compaq Portable II", "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL }, { "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device }, { "[286 ISA] GW-286CT GEAR", "gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL }, + { "[286 ISA] Goldstar GDC-212M", "gdc212m", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 512, 4096, 512, 127, machine_at_gdc212m_init, NULL }, { "[286 ISA] Hyundai Super-286TR", "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL }, { "[286 ISA] IBM AT", "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL }, { "[286 ISA] AMI IBM AT", "ibmatami", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibmatami_init, NULL }, @@ -153,7 +159,8 @@ const machine_t machines[] = { /* 386DX machines */ { "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device }, - { "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_ecs386_init, NULL }, + { "[386DX ISA] AMI 386DX clone", "acc386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_acc386_init, NULL }, + { "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 32, 1, 127, machine_at_ecs386_init, NULL }, { "[386DX ISA] Micronics 386 clone", "micronics386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_micronics386_init, NULL }, /* 386DX machines which utilize the VLB bus */ @@ -194,7 +201,9 @@ const machine_t machines[] = { #endif /* 486 machines which utilize the PCI bus */ +#if defined(DEV_BRANCH) && defined(NO_SIO) { "[486 PCI] ASUS PCI/I-486SP3G", "486sp3g", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_486sp3g_init, NULL }, +#endif { "[486 PCI] Intel Classic/PCI", "alfredo", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_alfredo_init, NULL }, { "[486 PCI] Lucky Star LS-486E", "ls486e", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_ls486e_init, NULL }, { "[486 PCI] Rise Computer R418", "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL }, @@ -208,7 +217,6 @@ const machine_t machines[] = { #endif { "[Socket 4 LX] Intel Premiere/PCI", "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL }, { "[Socket 4 LX] Micro Star 586MC1", "586mc1", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL }, - /* Socket 5 machines */ /* 430NX */ { "[Socket 5 NX] Intel Premiere/PCI II", "plato", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL }, @@ -222,11 +230,11 @@ const machine_t machines[] = { { "[Socket 5 FX] Intel Advanced/ZP", "zappa", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL }, { "[Socket 5 FX] NEC PowerMate V", "powermate_v", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_powermate_v_init, NULL }, { "[Socket 5 FX] PC Partner MB500N", "mb500n", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL }, - { "[Socket 5 FX] President Award 430FX PCI","president", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL }, /* Socket 7 machines */ /* 430FX */ { "[Socket 7-3V FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL }, + { "[Socket 7-3V FX] QDI Chariot", "chariot", MACHINE_CPUS_PENTIUM_S73VCH, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_chariot_init, NULL }, { "[Socket 7-3V FX] Intel Advanced/ATX", "thor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL }, { "[Socket 7-3V FX] Intel Advanced/EV", "endeavor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device }, #if defined(DEV_BRANCH) && defined(USE_MRTHOR) @@ -265,11 +273,13 @@ const machine_t machines[] = { #endif { "[Socket 7 TX] SuperMicro P5MMS98", "p5mms98", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p5mms98_init, NULL }, -#if defined(DEV_BRANCH) && defined(NO_SIO) + /* Apollo VPX */ - { "[Socket 7 VPX] Zida Tomato TX100", "tx100", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_tx100_init, NULL }, + { "[Socket 7 VPX] FIC VA-502", "ficva502", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ficva502_init, NULL }, /* Apollo VP3 */ + { "[Socket 7 VP3] FIC PA-2012", "ficpa2012", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_ficpa2012_init, NULL }, +#if defined(DEV_BRANCH) && defined(NO_SIO) { "[Socket 7 VP3] QDI Advance II", "advanceii", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_advanceii_init, NULL }, #endif @@ -284,9 +294,6 @@ const machine_t machines[] = { { "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_mb600n_init, NULL }, { "[Socket 8 FX] Biostar MB-8500ttc", "8500ttc", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_8500ttc_init, NULL }, { "[Socket 8 FX] Micronics M6MI", "m6mi", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_m6mi_init, NULL }, -#if defined(DEV_BRANCH) && defined(NO_SIO) - { "[Socket 8 FX] Intel VS440FX", "vs440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_vs440fx_init, NULL }, -#endif { "[Socket 8 FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cp6nd_init, NULL }, @@ -304,9 +311,9 @@ const machine_t machines[] = { { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, { "[Slot 1 BX] ASUS P3B-F", "p3bf", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p3bf_init, NULL }, { "[Slot 1 BX] ABit BF6", "bf6", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL }, - - /* 440ZX */ - { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, +#if defined(DEV_BRANCH) && defined(NO_SIO) + { "[Slot 1 BX] Tyan Tsunami ATX", "tsunamiatx", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_tsunamiatx_init, NULL }, +#endif /* PGA370 machines */ /* 440BX */ diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index 106e2bb87..0c4748505 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -273,7 +273,7 @@ static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_changeable = { 0, 0 }, { 0, 0 }, { GPMODE_CDROM_PAGE, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, - { 0x8E, 0xE, 0xFF, 0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + { 0x8E, 0xE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, { 0, 0 }, { 0, 0 }, { 0, 0 }, diff --git a/src/video/vid_ati28800.c b/src/video/vid_ati28800.c index 5ffcf14e8..3545cb69d 100644 --- a/src/video/vid_ati28800.c +++ b/src/video/vid_ati28800.c @@ -495,6 +495,10 @@ ati28800k_init(const device_t *info) ati28800->svga.miscout = 1; ati28800->svga.ksc5601_sbyte_mask = 0; + ati28800->svga.ksc5601_udc_area_msb[0] = 0xC9; + ati28800->svga.ksc5601_udc_area_msb[1] = 0xFE; + ati28800->svga.ksc5601_swap_mode = 0; + ati28800->svga.ksc5601_english_font_type = 0; ati_eeprom_load(&ati28800->eeprom, L"atikorvga.nvr", 0); diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index 7ac6ac8c1..f3f428f7e 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -36,6 +36,7 @@ #include <86box/vid_svga.h> #include <86box/vid_svga_render.h> +#define BIOS_GD5401_PATH L"roms/video/cirruslogic/avga1.rom" #define BIOS_GD5402_PATH L"roms/video/cirruslogic/avga2.rom" #define BIOS_GD5402_ONBOARD_PATH L"roms/video/machines/cbm_sl386sx25/Commodore386SX-25_AVGA2.bin" #define BIOS_GD5420_PATH L"roms/video/cirruslogic/5420.vbi" @@ -57,6 +58,7 @@ #define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb nitro64v.BIN" #define BIOS_GD5480_PATH L"roms/video/cirruslogic/clgd5480.rom" +#define CIRRUS_ID_CLGD5401 0x88 #define CIRRUS_ID_CLGD5402 0x89 #define CIRRUS_ID_CLGD5420 0x8a #define CIRRUS_ID_CLGD5422 0x8c @@ -2963,6 +2965,11 @@ static void gd54xx->has_bios = 1; switch (id) { + + case CIRRUS_ID_CLGD5401: + romfn = BIOS_GD5401_PATH; + break; + case CIRRUS_ID_CLGD5402: if (info->local & 0x200) romfn = BIOS_GD5402_ONBOARD_PATH; @@ -3154,6 +3161,12 @@ static void return gd54xx; } +static int +gd5401_available(void) +{ + return rom_present(BIOS_GD5401_PATH); +} + static int gd5402_available(void) { @@ -3376,6 +3389,19 @@ static const device_config_t gd5434_config[] = } }; +const device_t gd5401_isa_device = +{ + "Cirrus Logic GD-5401 (ACUMOS AVGA1)", + DEVICE_AT | DEVICE_ISA, + CIRRUS_ID_CLGD5401, + gd54xx_init, gd54xx_close, + NULL, + gd5401_available, + gd54xx_speed_changed, + gd54xx_force_redraw, + NULL, +}; + const device_t gd5402_isa_device = { "Cirrus Logic GD-5402 (ACUMOS AVGA2)", diff --git a/src/video/vid_et4000.c b/src/video/vid_et4000.c index a468ceb52..819dfa544 100644 --- a/src/video/vid_et4000.c +++ b/src/video/vid_et4000.c @@ -57,7 +57,8 @@ #define BIOS_ROM_PATH L"roms/video/et4000/et4000.bin" #define KOREAN_BIOS_ROM_PATH L"roms/video/et4000/tgkorvga.bin" #define KOREAN_FONT_ROM_PATH L"roms/video/et4000/tg_ksc5601.rom" - +#define KASAN_BIOS_ROM_PATH L"roms/video/et4000/et4000_kasan16.bin" +#define KASAN_FONT_ROM_PATH L"roms/video/et4000/kasan_ksc5601.rom" typedef struct { const char *name; @@ -78,6 +79,11 @@ typedef struct { int get_korean_font_enabled; int get_korean_font_index; uint16_t get_korean_font_base; + + uint8_t kasan_cfg_index; + uint8_t kasan_cfg_regs[16]; + uint16_t kasan_access_addr; + uint8_t kasan_font_data[4]; } et4000_t; @@ -95,6 +101,8 @@ static const uint8_t crtc_mask[0x40] = { static video_timings_t timing_et4000_isa = {VIDEO_ISA, 3, 3, 6, 5, 5, 10}; static video_timings_t timing_et4000_mca = {VIDEO_MCA, 4, 5, 10, 5, 5, 10}; +static void et4000_kasan_out(uint16_t addr, uint8_t val, void *p); +static uint8_t et4000_kasan_in(uint16_t addr, void *p); static uint8_t et4000_in(uint16_t addr, void *priv) @@ -393,62 +401,248 @@ et4000k_out(uint16_t addr, uint8_t val, void *priv) } } +static uint8_t +et4000_kasan_in(uint16_t addr, void *priv) +{ + et4000_t *et4000 = (et4000_t *)priv; + uint8_t val = 0xFF; + + if (addr == 0x258) { + val = et4000->kasan_cfg_index; + } else if (addr == 0x259) { + if (et4000->kasan_cfg_index >= 0xF0) { + val = et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0]; + if (et4000->kasan_cfg_index == 0xF4 && et4000->kasan_cfg_regs[0] & 0x20) + val |= 0x80; + } + } else if (addr >= et4000->kasan_access_addr && addr < et4000->kasan_access_addr + 8) { + switch (addr - ((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1]))) { + case 5: + if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[0] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[0] & 0x80)) + val = fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index]; + else if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[1] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[1] & 0x80)) + val = fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index]; + else + val = fontdatksc5601[et4000->get_korean_font_base].chr[et4000->get_korean_font_index]; + default: + break; + } + } else + val = et4000_in(addr, priv); + + return val; +} + +static void +et4000_kasan_out(uint16_t addr, uint8_t val, void *priv) +{ + et4000_t *et4000 = (et4000_t *)priv; + + if (addr == 0x258) { + et4000->kasan_cfg_index = val; + } else if (addr == 0x259) { + if (et4000->kasan_cfg_index >= 0xF0) { + switch (et4000->kasan_cfg_index - 0xF0) { + case 0: + if (et4000->kasan_cfg_regs[4] & 8) + val = (val & 0xFC) | (et4000->kasan_cfg_regs[0] & 3); + et4000->kasan_cfg_regs[0] = val; + et4000->svga.ksc5601_sbyte_mask = (val & 4) << 5; + svga_recalctimings(&et4000->svga); + break; + case 1: + case 2: + et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0] = val; + io_removehandler(et4000->kasan_access_addr, 0x0008, et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, et4000); + et4000->kasan_access_addr = (et4000->kasan_cfg_regs[2] << 8) | et4000->kasan_cfg_regs[1]; + io_sethandler(et4000->kasan_access_addr, 0x0008, et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, et4000); + break; + case 4: + if (et4000->kasan_cfg_regs[0] & 0x20) + val |= 0x80; + et4000->svga.ksc5601_swap_mode = (val & 4) >> 2; + et4000->kasan_cfg_regs[4] = val; + svga_recalctimings(&et4000->svga); + break; + case 5: + et4000->kasan_cfg_regs[5] = val; + et4000->svga.ksc5601_english_font_type = 0x100 | val; + case 6: + case 7: + et4000->svga.ksc5601_udc_area_msb[et4000->kasan_cfg_index - 0xF6] = val; + default: + et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0] = val; + svga_recalctimings(&et4000->svga); + break; + } + } + } else if (addr >= et4000->kasan_access_addr && addr < et4000->kasan_access_addr + 8) { + switch (addr - ((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1]))) { + case 0: + if (et4000->kasan_cfg_regs[0] & 2) { + et4000->get_korean_font_index = ((val & 1) << 4) | ((val & 0x1E) >> 1); + et4000->get_korean_font_base = (et4000->get_korean_font_base & ~7) | (val >> 5); + } + break; + case 1: + if (et4000->kasan_cfg_regs[0] & 2) + et4000->get_korean_font_base = (et4000->get_korean_font_base & ~0x7F8) | (val << 3); + break; + case 2: + if (et4000->kasan_cfg_regs[0] & 2) + et4000->get_korean_font_base = (et4000->get_korean_font_base & ~0x7F800) | ((val & 7) << 11); + break; + case 3: + case 4: + case 5: + if (et4000->kasan_cfg_regs[0] & 1) + et4000->kasan_font_data[addr - (((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1])) + 3)] = val; + break; + case 6: + if ((et4000->kasan_cfg_regs[0] & 1) && (et4000->kasan_font_data[3] & !(val & 0x80)) && (et4000->get_korean_font_base & 0x7F) >= 0x20 && (et4000->get_korean_font_base & 0x7F) < 0x7F) { + if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[0] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[0] & 0x80)) + fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = et4000->kasan_font_data[2]; + else if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[1] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[1] & 0x80)) + fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = et4000->kasan_font_data[2]; + } + et4000->kasan_font_data[3] = val; + break; + default: + break; + } + } else + et4000_out(addr, val, priv); +} + +uint32_t +get_et4000_addr(uint32_t addr, void *p) +{ + svga_t *svga = (svga_t *)p; + uint32_t nbank; + + switch (svga->crtc[0x37] & 0x0B) { + case 0x00: + case 0x01: + nbank = 0; + addr &= 0xFFFF; + break; + case 0x02: + nbank = (addr & 1) << 1; + addr = (addr >> 1) & 0xFFFF; + break; + case 0x03: + nbank = addr & 3; + addr = (addr >> 2) & 0xFFFF; + break; + case 0x08: + case 0x09: + nbank = 0; + addr &= 0x3FFFF; + break; + case 0x0A: + nbank = (addr & 1) << 1; + addr = (addr >> 1) & 0x3FFFF; + break; + case 0x0B: + nbank = addr & 3; + addr = (addr >> 2) & 0x3FFFF; + break; + default: + nbank = 0; + break; + } + + if (svga->vram_max >= 1024 * 1024) { + addr = (addr << 2) | (nbank & 3); + if ((svga->crtc[0x37] & 3) == 2) + addr >>= 1; + else if ((svga->crtc[0x37] & 3) < 2) + addr >>= 2; + } else if (svga->vram_max >= 512 * 1024) { + addr = (addr << 1) | ((nbank & 2) >> 1) | ((nbank & 1) << 19); + if ((svga->crtc[0x37] & 3) < 2) + addr >>= 1; + } else if(svga->vram_max >= 256 * 1024) + addr = addr | (nbank << 18); + else if (svga->vram_max > 128 * 1024) { + addr = (addr << 1) | ((nbank & 2) >> 1) | ((nbank & 1) << 17); + if ((svga->crtc[0x37] & 3) < 2) + addr >>= 1; + } else + addr = addr | (nbank << 16); + + return addr; +} static void et4000_recalctimings(svga_t *svga) { - et4000_t *dev = (et4000_t *)svga->p; + et4000_t *dev = (et4000_t *)svga->p; - svga->ma_latch |= (svga->crtc[0x33]&3)<<16; - if (svga->crtc[0x35] & 1) svga->vblankstart += 0x400; - if (svga->crtc[0x35] & 2) svga->vtotal += 0x400; - if (svga->crtc[0x35] & 4) svga->dispend += 0x400; - if (svga->crtc[0x35] & 8) svga->vsyncstart += 0x400; - if (svga->crtc[0x35] & 0x10) svga->split += 0x400; - if (!svga->rowoffset) svga->rowoffset = 0x100; - if (svga->crtc[0x3f] & 1) svga->htotal += 256; - if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1; + svga->ma_latch |= (svga->crtc[0x33] & 3) << 16; + if (svga->crtc[0x35] & 1) svga->vblankstart += 0x400; + if (svga->crtc[0x35] & 2) svga->vtotal += 0x400; + if (svga->crtc[0x35] & 4) svga->dispend += 0x400; + if (svga->crtc[0x35] & 8) svga->vsyncstart += 0x400; + if (svga->crtc[0x35] & 0x10) svga->split += 0x400; + if (!svga->rowoffset) svga->rowoffset = 0x100; + if (svga->crtc[0x3f] & 1) svga->htotal += 256; + if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1; - switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) { - case 0: - case 1: - break; + switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) { + case 0: + case 1: + break; + case 3: + svga->clock = (cpuclock * (double)(1ull << 32)) / 40000000.0; + break; + case 5: + svga->clock = (cpuclock * (double)(1ull << 32)) / 65000000.0; + break; + default: + svga->clock = (cpuclock * (double)(1ull << 32)) / 36000000.0; + break; + } + + switch (svga->bpp) { + case 15: + case 16: + svga->hdisp /= 2; + break; - case 3: - svga->clock = (cpuclock * (double)(1ull << 32)) / 40000000.0; - break; + case 24: + svga->hdisp /= 3; + break; + } - case 5: - svga->clock = (cpuclock * (double)(1ull << 32)) / 65000000.0; - break; - - default: - svga->clock = (cpuclock * (double)(1ull << 32)) / 36000000.0; - break; - } - - switch (svga->bpp) { - case 15: - case 16: - svga->hdisp /= 2; - break; - - case 24: - svga->hdisp /= 3; - break; - } - - if (dev->type == 2 || dev->type == 3) { -#if NOT_YET - if ((svga->render == svga_render_text_80) && ((svga->crtc[0x37] & 0x0A) == 0x0A)) { - if ((dev->port_32cb_val & 0xB4) == ((svga->crtc[0x37] & 3) == 2 ? 0xB4 : 0xB0)) { - svga->render = svga_render_text_80_ksc5601; + if (dev->type == 2 || dev->type == 3 || dev->type == 4) { + if ((svga->render == svga_render_text_80) && ((svga->crtc[0x37] & 0x0A) == 0x0A)) { + if (dev->port_32cb_val & 0x80) { + svga->ma_latch -= 2; + svga->ca_adj = -2; + } + if ((dev->port_32cb_val & 0xB4) == ((svga->crtc[0x37] & 3) == 2 ? 0xB4 : 0xB0)) { + svga->render = svga_render_text_80_ksc5601; + } } } -#endif - } } +static void +et4000_kasan_recalctimings(svga_t *svga) +{ + et4000_t *et4000 = (et4000_t *)svga->p; + + et4000_recalctimings(svga); + + if (svga->render == svga_render_text_80 && (et4000->kasan_cfg_regs[0] & 8)) { + svga->ma_latch -= 3 - (et4000->kasan_cfg_regs[3] >> 1); + svga->ca_adj = -(3 - (et4000->kasan_cfg_regs[0] >> 6)); + svga->hdisp -= (et4000->kasan_cfg_regs[3] >> 1) * ((svga->seqregs[1] & 1) ? 8 : 9); + if ((et4000->kasan_cfg_regs[0] & 3) == 0 && (et4000->kasan_cfg_regs[4] & 0x80) && ((svga->crtc[0x37] & 0x0B) == 0x0A)) + svga->render = svga_render_text_80_ksc5601; + } +} static uint8_t et4000_mca_read(int port, void *priv) @@ -484,6 +678,7 @@ et4000_init(const device_t *info) { const wchar_t *fn; et4000_t *dev; + int i; dev = (et4000_t *)malloc(sizeof(et4000_t)); memset(dev, 0x00, sizeof(et4000_t)); @@ -521,6 +716,10 @@ et4000_init(const device_t *info) dev->port_22cb_val = 0x60; dev->port_32cb_val = 0; dev->svga.ksc5601_sbyte_mask = 0x80; + dev->svga.ksc5601_udc_area_msb[0] = 0xC9; + dev->svga.ksc5601_udc_area_msb[1] = 0xFE; + dev->svga.ksc5601_swap_mode = 0; + dev->svga.ksc5601_english_font_type = 0; video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa); svga_init(info, &dev->svga, dev, dev->vram_size, et4000_recalctimings, et4000k_in, et4000k_out, @@ -536,6 +735,40 @@ et4000_init(const device_t *info) loadfont(KOREAN_FONT_ROM_PATH, 6); fn = KOREAN_BIOS_ROM_PATH; break; + case 4: /* Kasan ET4000 */ + dev->vram_size = device_get_config_int("memory") << 10; + dev->svga.ksc5601_sbyte_mask = 0; + dev->svga.ksc5601_udc_area_msb[0] = 0xC9; + dev->svga.ksc5601_udc_area_msb[1] = 0xFE; + dev->svga.ksc5601_swap_mode = 0; + dev->svga.ksc5601_english_font_type = 0x1FF; + dev->kasan_cfg_index = 0; + for (i=0; i<16; i++) + dev->kasan_cfg_regs[i] = 0; + for(i=0; i<4; i++) + dev->kasan_font_data[i] = 0; + dev->kasan_cfg_regs[1] = 0x50; + dev->kasan_cfg_regs[2] = 2; + dev->kasan_cfg_regs[3] = 6; + dev->kasan_cfg_regs[4] = 0x78; + dev->kasan_cfg_regs[5] = 0xFF; + dev->kasan_cfg_regs[6] = 0xC9; + dev->kasan_cfg_regs[7] = 0xFE; + dev->kasan_access_addr = 0x250; + video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa); + svga_init(info, &dev->svga, dev, dev->vram_size, + et4000_kasan_recalctimings, et4000_in, et4000_out, + NULL, NULL); + io_sethandler(0x03c0, 32, + et4000_in,NULL,NULL, et4000_out,NULL,NULL, dev); + io_sethandler(0x0250, 8, + et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, dev); + io_sethandler(0x0258, 2, + et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, dev); + loadfont(KASAN_FONT_ROM_PATH, 6); + fn = KASAN_BIOS_ROM_PATH; + break; + } dev->svga.ramdac = device_add(&sc1502x_ramdac_device); @@ -545,6 +778,8 @@ et4000_init(const device_t *info) rom_init(&dev->bios_rom, (wchar_t *) fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + dev->svga.translate_address = get_et4000_addr; + return(dev); } @@ -592,6 +827,12 @@ et4000k_available(void) rom_present(KOREAN_FONT_ROM_PATH); } +static int +et4000_kasan_available(void) +{ + return rom_present(KASAN_BIOS_ROM_PATH) && + rom_present(KASAN_FONT_ROM_PATH); +} static const device_config_t et4000_config[] = { @@ -660,3 +901,14 @@ const device_t et4000k_tg286_isa_device = { et4000_force_redraw, et4000_config }; + +const device_t et4000_kasan_isa_device = { + "Kasan Hangulmadang-16 VGA (Tseng Labs ET4000AX Korean)", + DEVICE_ISA, + 4, + et4000_init, et4000_close, NULL, + et4000_kasan_available, + et4000_speed_changed, + et4000_force_redraw, + et4000_config +}; diff --git a/src/video/vid_svga.c b/src/video/vid_svga.c index 0a21ad1a3..c0f51f858 100644 --- a/src/video/vid_svga.c +++ b/src/video/vid_svga.c @@ -445,7 +445,8 @@ svga_recalctimings(svga_t *svga) svga->interlace = 0; - svga->ma_latch = (svga->crtc[0xc] << 8) | svga->crtc[0xd]; + svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5); + svga->ca_adj = 0; svga->hdisp_time = svga->hdisp; svga->render = svga_render_blank; @@ -809,7 +810,7 @@ svga_poll(void *p) svga->ma = svga->maback = svga->ma_latch + (svga->rowoffset << 1); else svga->ma = svga->maback = svga->ma_latch; - svga->ca = (svga->crtc[0xe] << 8) | svga->crtc[0xf]; + svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj; svga->ma = (svga->ma << 2) + (skip << 2); svga->maback = (svga->maback << 2) + (skip << 2); @@ -911,6 +912,9 @@ svga_init(const device_t *info, svga_t *svga, void *p, int memsize, svga->dac_hwcursor.xsize = svga->dac_hwcursor.ysize = 32; svga->dac_hwcursor.yoff = 32; + + svga->translate_address = NULL; + svga->ksc5601_english_font_type = 0; if ((info->flags & DEVICE_PCI) || (info->flags & DEVICE_VLB)) { mem_mapping_add(&svga->mapping, 0xa0000, 0x20000, @@ -1036,6 +1040,9 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *p) addr &= svga->decode_mask; + if (svga->translate_address) + addr = svga->translate_address(addr, p); + if (addr >= svga->vram_max) return; @@ -1168,6 +1175,8 @@ svga_read_common(uint32_t addr, uint8_t linear, void *p) addr <<= 3; else if (svga->chain4 || svga->fb_only) { addr &= svga->decode_mask; + if (svga->translate_address) + addr = svga->translate_address(addr, p); if (addr >= svga->vram_max) return 0xff; return svga->vram[addr & svga->vram_mask]; @@ -1179,6 +1188,12 @@ svga_read_common(uint32_t addr, uint8_t linear, void *p) addr <<= 2; addr &= svga->decode_mask; + if (!linear) { + if (svga->translate_address) { + latch_addr = svga->translate_address(latch_addr, p); + addr = svga->translate_address(addr, p); + } + } /* standard VGA latched access */ if (latch_addr >= svga->vram_max) { @@ -1375,6 +1390,19 @@ svga_writew_common(uint32_t addr, uint16_t val, uint8_t linear, void *p) } addr &= svga->decode_mask; + if(svga->translate_address) { + uint32_t addr2 = svga->translate_address(addr, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = val & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + addr2 = svga->translate_address(addr+1, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + return; + } if (addr >= svga->vram_max) return; addr &= svga->vram_mask; @@ -1423,6 +1451,29 @@ svga_writel_common(uint32_t addr, uint32_t val, uint8_t linear, void *p) } addr &= svga->decode_mask; + if (svga->translate_address) { + uint32_t addr2 = svga->translate_address(addr, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = val & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + addr2 = svga->translate_address(addr+1, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + addr2 = svga->translate_address(addr+2, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = (val >> 16) & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + addr2 = svga->translate_address(addr+3, p); + if (addr2 < svga->vram_max) { + svga->vram[addr2 & svga->vram_mask] = (val >> 24) & 0xff; + svga->changedvram[addr2 >> 12] = changeframecount; + } + return; + } if (addr >= svga->vram_max) return; addr &= svga->vram_mask; @@ -1484,6 +1535,16 @@ svga_readw_common(uint32_t addr, uint8_t linear, void *p) } addr &= svga->decode_mask; + if (svga->translate_address) { + uint8_t val1 = 0xff, val2 = 0xff; + uint32_t addr2 = svga->translate_address(addr, p); + if (addr2 < svga->vram_max) + val1 = svga->vram[addr2 & svga->vram_mask]; + addr2 = svga->translate_address(addr+1, p); + if (addr2 < svga->vram_max) + val2 = svga->vram[addr2 & svga->vram_mask]; + return (val2 << 8) | val1; + } if (addr >= svga->vram_max) return 0xffff; @@ -1527,6 +1588,22 @@ svga_readl_common(uint32_t addr, uint8_t linear, void *p) } addr &= svga->decode_mask; + if (svga->translate_address) { + uint8_t val1 = 0xff, val2 = 0xff, val3 = 0xff, val4 = 0xff; + uint32_t addr2 = svga->translate_address(addr, p); + if (addr2 < svga->vram_max) + val1 = svga->vram[addr2 & svga->vram_mask]; + addr2 = svga->translate_address(addr+1, p); + if (addr2 < svga->vram_max) + val2 = svga->vram[addr2 & svga->vram_mask]; + addr2 = svga->translate_address(addr+2, p); + if (addr2 < svga->vram_max) + val3 = svga->vram[addr2 & svga->vram_mask]; + addr2 = svga->translate_address(addr+3, p); + if (addr2 < svga->vram_max) + val4 = svga->vram[addr2 & svga->vram_mask]; + return (val4 << 24) | (val3 << 16) | (val2 << 8) | val1; + } if (addr >= svga->vram_max) return 0xffffffff; diff --git a/src/video/vid_svga_render.c b/src/video/vid_svga_render.c index 11605fec4..30b274067 100644 --- a/src/video/vid_svga_render.c +++ b/src/video/vid_svga_render.c @@ -258,17 +258,24 @@ svga_render_text_80_ksc5601(svga_t *svga) } if ((x + xinc) < svga->hdisp && (chr & (nextchr | svga->ksc5601_sbyte_mask) & 0x80)) { - if (((chr == 0xc9) || (chr == 0xfe)) && ((nextchr > 0xa0) && (nextchr < 0xff))) - dat = fontdatksc5601_user[((chr == 0xfe) ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc]; - else if (nextchr & 0x80) + if ((chr == svga->ksc5601_udc_area_msb[0] || chr == svga->ksc5601_udc_area_msb[1]) && (nextchr > 0xa0 && nextchr < 0xff)) + dat = fontdatksc5601_user[(chr == svga->ksc5601_udc_area_msb[1] ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc]; + else if (nextchr & 0x80) { + if (svga->ksc5601_swap_mode == 1 && (nextchr > 0xa0 && nextchr < 0xff)) { + if(chr >= 0x80 && chr < 0x99) chr += 0x30; + else if(chr >= 0xB0 && chr < 0xC9) chr -= 0x30; + } dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)].chr[svga->sc]; - else + } else dat = 0xff; } else { if (attr & 8) charaddr = svga->charsetb + (chr * 128); else charaddr = svga->charseta + (chr * 128); - dat = svga->vram[charaddr + (svga->sc << 2)]; + if ((svga->ksc5601_english_font_type >> 8) == 1) + dat = fontdatksc5601[((svga->ksc5601_english_font_type & 0x7F) << 7) | (chr >> 1)].chr[((chr & 1) << 4) | svga->sc]; + else + dat = svga->vram[charaddr + (svga->sc << 2)]; } if (svga->seqregs[1] & 1) { @@ -301,8 +308,8 @@ svga_render_text_80_ksc5601(svga_t *svga) } } - if (((chr == 0xc9) || (chr == 0xfe)) && ((nextchr > 0xa0) && (nextchr < 0xff))) - dat = fontdatksc5601_user[(chr == 0xfe ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc + 16]; + if ((chr == svga->ksc5601_udc_area_msb[0] || chr == svga->ksc5601_udc_area_msb[1]) && (nextchr > 0xa0 && nextchr < 0xff)) + dat = fontdatksc5601_user[(chr == svga->ksc5601_udc_area_msb[1] ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc + 16]; else if(nextchr & 0x80) dat = fontdatksc5601[((chr & 0x7f) << 7) | (nextchr & 0x7F)].chr[svga->sc + 16]; else diff --git a/src/video/vid_table.c b/src/video/vid_table.c index f1f10835b..acff552ea 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -68,6 +68,7 @@ video_cards[] = { #endif { "[ISA] CGA", "cga", &cga_device }, { "[ISA] Chips & Technologies SuperEGA", "superega", &sega_device }, + { "[ISA] Cirrus Logic CL-GD 5401", "cl_gd5401_isa", &gd5401_isa_device }, { "[ISA] Cirrus Logic CL-GD 5402", "cl_gd5402_isa", &gd5402_isa_device }, { "[ISA] Cirrus Logic CL-GD 5420", "cl_gd5420_isa", &gd5420_isa_device }, #if defined(DEV_BRANCH) && defined(USE_CL5422) @@ -86,6 +87,7 @@ video_cards[] = { { "[ISA] Hercules Plus", "hercules_plus", &herculesplus_device }, { "[ISA] Hercules InColor", "incolor", &incolor_device }, { "[ISA] Image Manager 1024", "im1024", &im1024_device }, + { "[ISA] Kasan Hangulmadang-16 VGA (ET4000AX)", "kasan16vga", &et4000_kasan_isa_device }, { "[ISA] MDA", "mda", &mda_device }, { "[ISA] MDSI Genius", "genius", &genius_device }, { "[ISA] OAK OTI-037C", "oti037c", &oti037c_device },