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Applied the remaining mainline PCem commits.

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This commit is contained in:
OBattler
2017-07-15 14:01:19 +02:00
parent 713bce1205
commit 2dbce95fde
7 changed files with 381 additions and 334 deletions
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290
src/scat.c
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@@ -1,64 +1,35 @@
/* Copyright holders: Greatpsycho
see COPYING for more details
*/
/*This is the chipset used in the Award 286 clone model*/
#include "ibm.h"
#include "cpu/cpu.h"
#include "CPU/cpu.h"
#include "io.h"
#include "mem.h"
#include "device.h"
#include "model.h"
#define SCAT_DMA_WAIT_STATE_CONTROL 0x01
#define SCAT_VERSION 0x40
#define SCAT_CLOCK_CONTROL 0x41
#define SCAT_PERIPHERAL_CONTROL 0x44
#define SCAT_MISCELLANEOUS_STATUS 0x45
#define SCAT_POWER_MANAGEMENT 0x46
#define SCAT_ROM_ENABLE 0x48
#define SCAT_RAM_WRITE_PROTECT 0x49
#define SCAT_SHADOW_RAM_ENABLE_1 0x4A
#define SCAT_SHADOW_RAM_ENABLE_2 0x4B
#define SCAT_SHADOW_RAM_ENABLE_3 0x4C
#define SCAT_DRAM_CONFIGURATION 0x4D
#define SCAT_EXTENDED_BOUNDARY 0x4E
#define SCAT_EMS_CONTROL 0x4F
typedef struct {
uint8_t regs_2x8;
uint8_t regs_2x9;
} scat_t;
#include "scat.h"
#include "CPU/x86.h"
#include "CPU/cpu.h"
static uint8_t scat_regs[256];
static int scat_index;
static uint8_t scat_port_92 = 0;
static uint8_t scat_ems_reg_2xA = 0;
static mem_mapping_t scat_mapping[32];
static mem_mapping_t scat_high_mapping[16];
static scat_t scat_stat[32];
static uint32_t scat_xms_bound;
static mem_mapping_t scat_shadowram_mapping;
static mem_mapping_t scat_512k_clip_mapping;
static mem_mapping_t scat_4000_9FFF_mapping[24];
static mem_mapping_t scat_A000_BFFF_mapping;
uint8_t scat_read(uint16_t port, void *priv);
void scat_write(uint16_t port, uint8_t val, void *priv);
static void scat_shadow_state_update(void)
void scat_shadow_state_update()
{
int i, val;
for (i = 0; i < 24; i++)
{
if((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1)
{
val = MEM_READ_INTERNAL;
ram_mapped_addr[i + 40] |= 1;
}
else
{
val = MEM_READ_EXTERNAL;
ram_mapped_addr[i + 40] &= ~1;
}
val = ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
if (i < 8)
{
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
@@ -74,14 +45,13 @@ static void scat_shadow_state_update(void)
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
}
}
mem_set_mem_state((i + 40) << 14, 0x4000, val);
mem_set_mem_state((i + 40) << 14, 0x4000, val);
}
flushmmucache();
}
static void scat_set_xms_bound(uint8_t val)
void scat_set_xms_bound(uint8_t val)
{
uint32_t max_xms_size = (mem_size >= 16384) ? 0xFC0000 : mem_size << 10;
@@ -155,8 +125,7 @@ static void scat_set_xms_bound(uint8_t val)
}
}
static uint32_t get_scat_addr(uint32_t addr, scat_t *p)
uint32_t get_scat_addr(uint32_t addr, scat_t *p)
{
if (p && (scat_regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
{
@@ -170,8 +139,33 @@ static uint32_t get_scat_addr(uint32_t addr, scat_t *p)
return addr;
}
void scat_set_global_EMS_state(int state)
{
int i;
uint32_t base_addr, virt_addr;
static void scat_write(uint16_t port, uint8_t val, void *priv)
for(i=0; i<32; i++)
{
base_addr = (i + 16) << 14;
if(i >= 24)
base_addr += 0x30000;
if(state && (scat_stat[i].regs_2x9 & 0x80))
{
virt_addr = get_scat_addr(base_addr, &scat_stat[i]);
if(i < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[i]);
mem_mapping_set_exec(&scat_mapping[i], ram + virt_addr);
mem_mapping_enable(&scat_mapping[i]);
}
else
{
mem_mapping_set_exec(&scat_mapping[i], ram + base_addr);
mem_mapping_disable(&scat_mapping[i]);
if(i < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
}
}
void scat_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t scat_reg_valid = 0, scat_shadow_update = 0, index;
uint32_t base_addr, virt_addr;
@@ -187,11 +181,32 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
{
case SCAT_CLOCK_CONTROL:
case SCAT_PERIPHERAL_CONTROL:
scat_reg_valid = 1;
break;
case SCAT_EMS_CONTROL:
if(val & 0x40)
{
if(val & 1)
{
io_sethandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
else
{
io_sethandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
}
else
{
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
scat_set_global_EMS_state(val & 0x80);
scat_reg_valid = 1;
break;
case SCAT_POWER_MANAGEMENT:
val &= 0x40; /* TODO - Only use AUX parity disable bit for this version. Other bits should be implemented later. */
val &= 0x40;
scat_reg_valid = 1;
break;
case SCAT_DRAM_CONFIGURATION:
@@ -212,6 +227,10 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
}
}
flushmmucache();
cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
cpu_update_waitstates();
scat_reg_valid = 1;
break;
case SCAT_EXTENDED_BOUNDARY:
@@ -235,7 +254,6 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
scat_regs[scat_index] = val;
if (scat_shadow_update)
scat_shadow_state_update();
pclog("Write SCAT Register %02X to %02X at %04X:%04X\n", scat_index, val, CS, cpu_state.pc);
break;
case 0x92:
@@ -247,7 +265,7 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
if ((~scat_port_92 & val) & 1)
{
softresetx86();
cpu_set_edx();
cpu_set_edx();
}
scat_port_92 = val;
break;
@@ -255,17 +273,11 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
if((scat_regs[SCAT_EMS_CONTROL] & 0x80) && (scat_stat[index].regs_2x9 & 0x80))
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
@@ -273,25 +285,29 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
ram_mapped_addr[base_addr >> 14] &= 1;
if (val & 0x80)
if (scat_regs[SCAT_EMS_CONTROL] & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
if (val & 0x80)
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(index < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
mem_mapping_enable(&scat_mapping[index]);
}
else
{
mem_mapping_set_exec(&scat_mapping[index], ram + base_addr);
mem_mapping_disable(&scat_mapping[index]);
if(index < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[index]);
}
flushmmucache();
}
else
{
pclog("Unmap page %d(address %06X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -302,7 +318,6 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
@@ -310,17 +325,11 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
if((scat_regs[SCAT_EMS_CONTROL] & 0x80) && (scat_stat[index].regs_2x9 & 0x80))
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
@@ -328,24 +337,31 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
if (index >= 24)
base_addr += 0x30000;
if (val & 0x80)
if (scat_regs[SCAT_EMS_CONTROL] & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
if (val & 0x80)
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(index < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
mem_mapping_enable(&scat_mapping[index]);
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
}
else
{
mem_mapping_set_exec(&scat_mapping[index], ram + base_addr);
mem_mapping_disable(&scat_mapping[index]);
if(index < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[index]);
pclog("Unmap page %d(address %05X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
}
else
{
pclog("Unmap page %d(address %05X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -356,15 +372,13 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
}
}
static uint8_t scat_read(uint16_t port, void *priv)
uint8_t scat_read(uint16_t port, void *priv)
{
uint8_t val = 0xff, index;
switch (port)
@@ -375,11 +389,13 @@ static uint8_t scat_read(uint16_t port, void *priv)
case SCAT_MISCELLANEOUS_STATUS:
val = (scat_regs[scat_index] & 0xbf) | ((mem_a20_key & 2) << 5);
break;
case SCAT_DRAM_CONFIGURATION:
val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
break;
default:
val = scat_regs[scat_index];
break;
}
pclog("Read SCAT Register %02X at %04X:%04X\n", scat_index, CS, cpu_state.pc);
break;
case 0x92:
@@ -389,7 +405,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@@ -397,7 +412,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@@ -405,7 +419,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;
@@ -413,7 +426,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@@ -421,7 +433,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@@ -429,7 +440,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;
@@ -437,8 +447,7 @@ static uint8_t scat_read(uint16_t port, void *priv)
return val;
}
static uint8_t mem_read_scatems(uint32_t addr, void *priv)
uint8_t mem_read_scatems(uint32_t addr, void *priv)
{
uint8_t val = 0xff;
scat_t *stat = (scat_t *)priv;
@@ -450,34 +459,7 @@ static uint8_t mem_read_scatems(uint32_t addr, void *priv)
return val;
}
static uint16_t mem_read_scatemsw(uint32_t addr, void *priv)
{
uint16_t val = 0xffff;
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
val = mem_read_ramw(addr, priv);
return val;
}
static uint32_t mem_read_scatemsl(uint32_t addr, void *priv)
{
uint32_t val = 0xffffffff;
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
val = mem_read_raml(addr, priv);
return val;
}
static void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
@@ -486,46 +468,18 @@ static void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
mem_write_ram(addr, val, priv);
}
static void mem_write_scatemsw(uint32_t addr, uint16_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
mem_write_ramw(addr, val, priv);
}
static void mem_write_scatemsl(uint32_t addr, uint32_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
mem_write_raml(addr, val, priv);
}
void scat_init(void)
void scat_init()
{
int i;
io_sethandler(0x0022, 0x0002, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
for (i = 0; i < 256; i++)
{
scat_regs[i] = 0xff;
}
for (i = 0; i < 64; i++)
{
ram_mapped_addr[i] = 0;
}
scat_regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
scat_regs[SCAT_VERSION] = 10;
scat_regs[SCAT_CLOCK_CONTROL] = 2;
@@ -537,17 +491,34 @@ void scat_init(void)
scat_regs[SCAT_SHADOW_RAM_ENABLE_1] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_2] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_3] = 0;
scat_regs[SCAT_DRAM_CONFIGURATION] = 2;
scat_regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12;
scat_regs[SCAT_EXTENDED_BOUNDARY] = 0;
scat_regs[SCAT_EMS_CONTROL] = 0;
mem_mapping_set_addr(&ram_low_mapping, 0, 0x40000);
for (i = 0; i < 24; i++)
{
if(mem_size > 256 + (i << 4))
{
mem_mapping_add(&scat_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0x40000 + (i << 14), MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
}
mem_mapping_add(&scat_A000_BFFF_mapping, 0xA0000, 0x20000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_A000_BFFF_mapping);
for (i = 0; i < 32; i++)
{
scat_stat[i].regs_2x8 = 0xff;
scat_stat[i].regs_2x9 = 0x03;
mem_mapping_add(&scat_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + ((i + (i >= 24 ? 28 : 16)) << 14), 0, &scat_stat[i]);
mem_mapping_disable(&scat_mapping[i]);
}
/* TODO - Only normal CPU accessing address FF0000 to FFFFFF mapped to ROM. Normal CPU accessing address FC0000 to FEFFFF map to ROM should be implemented later. */
for(i=4;i<10;i++) isram[i] = 0;
for (i = 12; i < 16; i++)
{
mem_mapping_add(&scat_high_mapping[i], (i << 14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (i << 14), 0, NULL);
@@ -555,14 +526,11 @@ void scat_init(void)
if (mem_size == 1024)
{
mem_mapping_add(&scat_shadowram_mapping, 0x100000, 0x60000, mem_read_scatems, mem_read_scatemsw, mem_read_scatemsl, mem_write_scatems, mem_write_scatemsw, mem_write_scatemsl, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&scat_shadowram_mapping, 0x100000, 0x60000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
}
/* Need to RAM 512kb clipping emulation if only 256KB or 64KB modules installed in memory bank.
TODO - 512KB clipping should be applied all RAM refer. */
mem_mapping_add(&scat_512k_clip_mapping, 0x80000, 0x20000, mem_read_scatems, mem_read_scatemsw, mem_read_scatemsl, mem_write_scatems, mem_write_scatemsw, mem_write_scatemsl, ram, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&scat_512k_clip_mapping, 0x80000, 0x20000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_disable(&scat_512k_clip_mapping);
/* --- */
scat_set_xms_bound(0);
scat_shadow_state_update();