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VIA southbridge fixes, including dynamic SMBus clock

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This commit is contained in:
RichardG867
2021-07-08 18:54:31 -03:00
parent 0297243a50
commit 2eba22295a
5 changed files with 142 additions and 44 deletions
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16
src/device/smbus_piix4.c
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@@ -313,8 +313,8 @@ unknown_protocol:
if (dev->next_stat) { /* schedule dispatch of any pending status register update */
dev->stat = 0x01; /* raise HOST_BUSY while waiting */
timer_disable(&dev->response_timer);
/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * 60us period measured on real VIA 686B */
timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * 60 * TIMER_USEC);
/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * bit period in usecs */
timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * dev->bit_period * TIMER_USEC);
}
}
@@ -343,6 +343,16 @@ smbus_piix4_remap(smbus_piix4_t *dev, uint16_t new_io_base, uint8_t enable)
}
void
smbus_piix4_setclock(smbus_piix4_t *dev, int clock)
{
dev->clock = clock;
/* Set the bit period in usecs. */
dev->bit_period = 1000000.0 / dev->clock;
}
static void *
smbus_piix4_init(const device_t *info)
{
@@ -356,6 +366,8 @@ smbus_piix4_init(const device_t *info)
timer_add(&dev->response_timer, smbus_piix4_response, dev, 0);
smbus_piix4_setclock(dev, 16384); /* default to 16.384 KHz */
return dev;
}