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Preliminary 186 emulation.

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Added MCA variant of the ET4000 VGA card.
Added NE/2 Netware card.
Corrected timings of the NCR 5380-based cards.
Added the WD8003E (8-bit ISA), WD8013EBT (16-bit ISA) and WD8013EP/A
(MCA) network cards.
This commit is contained in:
TC1995
2018-07-19 16:01:31 +02:00
parent cf79b98628
commit 2fecef0741
17 changed files with 3382 additions and 645 deletions
Download Patch File Download Diff File Expand all files Collapse all files

141
src/cpu/808x.c
View File

@@ -881,19 +881,70 @@ void rep(int fv)
cycles-=2;
goto startrep;
break;
case 0x6E: /*REP OUTSB*/
if (c>0)
{
temp2=readmemb(ds+SI);
outb(DX,temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
case 0x6C: /*186+ REP INSB*/
if (is186)
{
if (c>0)
{
temp2=inb(DX);
writememb(ds+SI, temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0x6D: /*186+ REP INSW*/
if (is186)
{
if (c>0)
{
tempw2=inw(DX);
writememw(ds, SI, tempw2);
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0x6E: /*186+ REP OUTSB*/
if (is186)
{
if (c>0)
{
temp2=readmemb(ds+SI);
outb(DX,temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0x6F: /*186+ REP OUTSW*/
if (is186)
{
if (c>0)
{
tempw2=readmemw(ds,SI);
outw(DX,tempw2);
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0xA4: /*REP MOVSB*/
while (c>0 && !IRQTEST)
{
@@ -2282,7 +2333,50 @@ void execx86(int cycs)
cycles-=((cpu_mod==3)?4:14);
break;
case 0xC8: /*RETF alias*/
case 0xC8: /*186+ ENTER*/
if (is186)
{
int count;
tempw=readmemw(ss,SP);
tempw2=readmemw(ss,(SP+2)&0xFFFF);
tempw3=CS;
tempw4=cpu_state.pc;
if (cpu_state.ssegs) ss=oldss;
count=geteaw();
if (count > 0)
{
while (--count)
{
cpu_state.pc=tempw;
loadcs(tempw2);
cycles-=4;
}
writememw(ss,(SP-2)&0xFFFF,tempw3);
writememw(ss,((SP-4)&0xFFFF),tempw4);
cycles-=5;
}
cpu_state.last_ea = SP;
SP-=getword();
cycles-=10;
FETCHCLEAR();
}
else /*RETF alias*/
{
tempw=getword();
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);
loadcs(readmemw(ss,SP+2));
SP+=4;
SP+=tempw;
cycles-=33;
FETCHCLEAR();
}
break;
case 0xCA: /*RETF*/
tempw=getword();
if (cpu_state.ssegs) ss=oldss;
@@ -2293,7 +2387,26 @@ void execx86(int cycs)
cycles-=33;
FETCHCLEAR();
break;
case 0xC9: /*RETF alias*/
case 0xC9:
if (is186) /*186+ LEAVE*/
{
if (cpu_state.ssegs) ss=oldss;
cpu_state.regs[opcode&7].w=readmemw(ss,(SP-2)&0xFFFF);
cpu_state.last_ea = SP;
cycles-=4;
}
else /*RETF alias*/
{
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);
loadcs(readmemw(ss,SP+2));
SP+=4;
cycles-=34;
FETCHCLEAR();
}
break;
case 0xCB: /*RETF*/
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);

5
src/cpu/cpu.c
View File

@@ -132,7 +132,8 @@ int cpu_waitstates;
int cpu_cache_int_enabled, cpu_cache_ext_enabled;
int cpu_pci_speed;
int is286,
int is186,
is286,
is386,
is486,
cpu_iscyrix,
@@ -243,6 +244,7 @@ cpu_set(void)
CPUID = cpu_s->cpuid_model;
cpuspeed = cpu_s->speed;
is8086 = (cpu_s->cpu_type > CPU_8088);
is186 = (cpu_s->cpu_type == CPU_186);
is286 = (cpu_s->cpu_type >= CPU_286);
is386 = (cpu_s->cpu_type >= CPU_386SX);
israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD);
@@ -395,6 +397,7 @@ cpu_set(void)
{
case CPU_8088:
case CPU_8086:
case CPU_186:
break;
case CPU_286:

60
src/cpu/cpu.h
View File

@@ -24,42 +24,43 @@
#define CPU_8088 0 /* 808x class CPUs */
#define CPU_8086 1
#define CPU_286 2 /* 286 class CPUs */
#define CPU_386SX 3 /* 386 class CPUs */
#define CPU_386DX 4
#define CPU_RAPIDCAD 5
#define CPU_486SLC 6
#define CPU_486DLC 7
#define CPU_i486SX 8 /* 486 class CPUs */
#define CPU_Am486SX 9
#define CPU_Cx486S 10
#define CPU_i486DX 11
#define CPU_Am486DX 12
#define CPU_Cx486DX 13
#define CPU_iDX4 14
#define CPU_Cx5x86 15
#define CPU_WINCHIP 16 /* 586 class CPUs */
#define CPU_PENTIUM 17
#define CPU_PENTIUMMMX 18
#define CPU_Cx6x86 19
#define CPU_Cx6x86MX 20
#define CPU_Cx6x86L 21
#define CPU_CxGX1 22
#define CPU_186 2
#define CPU_286 3 /* 286 class CPUs */
#define CPU_386SX 4 /* 386 class CPUs */
#define CPU_386DX 5
#define CPU_RAPIDCAD 6
#define CPU_486SLC 7
#define CPU_486DLC 8
#define CPU_i486SX 9 /* 486 class CPUs */
#define CPU_Am486SX 10
#define CPU_Cx486S 11
#define CPU_i486DX 12
#define CPU_Am486DX 13
#define CPU_Cx486DX 14
#define CPU_iDX4 15
#define CPU_Cx5x86 16
#define CPU_WINCHIP 17 /* 586 class CPUs */
#define CPU_PENTIUM 18
#define CPU_PENTIUMMMX 19
#define CPU_Cx6x86 20
#define CPU_Cx6x86MX 21
#define CPU_Cx6x86L 22
#define CPU_CxGX1 23
#ifdef DEV_BRANCH
#ifdef USE_AMD_K
#define CPU_K5 23
#define CPU_5K86 24
#define CPU_K6 25
#define CPU_K5 24
#define CPU_5K86 25
#define CPU_K6 26
#endif
#endif
#ifdef DEV_BRANCH
#ifdef USE_I686
#define CPU_PENTIUMPRO 26 /* 686 class CPUs */
#define CPU_PENTIUMPRO 27 /* 686 class CPUs */
#if 0
# define CPU_PENTIUM2 27
# define CPU_PENTIUM2D 28
# define CPU_PENTIUM2 28
# define CPU_PENTIUM2D 29
#else
# define CPU_PENTIUM2D 27
# define CPU_PENTIUM2D 28
#endif
#endif
#endif
@@ -91,6 +92,7 @@ typedef struct {
extern CPU cpus_8088[];
extern CPU cpus_8086[];
extern CPU cpus_186[];
extern CPU cpus_286[];
extern CPU cpus_i386SX[];
extern CPU cpus_i386DX[];
@@ -315,7 +317,7 @@ extern int cpu_multi;
extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is286, is386, is486;
extern int is8086, is186, is286, is386, is486;
extern int is_rapidcad, is_pentium;
extern int hasfpu;
extern int cpu_hasrdtsc;

19
src/cpu/cpu_table.c
View File

@@ -29,7 +29,7 @@
* 16 = 180 MHz
* 17 = 200 MHz
*
* Version: @(#)cpu_table.c 1.0.5 2018/07/17
* Version: @(#)cpu_table.c 1.0.4 2018/02/18
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
@@ -54,12 +54,10 @@ CPU cpus_8088[] = {
/*8088 standard*/
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
#if 0
{"8088/7.16", CPU_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
#endif
{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 2},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
@@ -88,6 +86,19 @@ CPU cpus_8086[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
CPU cpus_186[] = {
/*80186 standard*/
{"80186/7.16", CPU_186, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"80186/8", CPU_186, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"80186/9.54", CPU_186, 1, 4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"80186/10", CPU_186, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"80186/12", CPU_186, 3, 12000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"80186/16", CPU_186, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 2},
{"80186/20", CPU_186, 5, 20000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 3},
{"80186/25", CPU_186, 6, 25000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 3},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
CPU cpus_pc1512[] = {
/*8086 Amstrad*/
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},