diff --git a/src/chipset/82c100.c b/src/chipset/82c100.c index 8b2259374..fc3441b47 100644 --- a/src/chipset/82c100.c +++ b/src/chipset/82c100.c @@ -30,76 +30,70 @@ #include <86box/rom.h> #include <86box/chipset.h> - typedef struct { - int enabled; - uint32_t virt, phys; + int enabled; + uint32_t virt, phys; } ems_page_t; - typedef struct { - uint8_t index, access; - uint16_t ems_io_base; - uint32_t ems_window_base; - uint8_t ems_page_regs[4], - regs[256]; - ems_page_t ems_pages[4]; - mem_mapping_t ems_mappings[4]; + uint8_t index, access; + uint16_t ems_io_base; + uint32_t ems_window_base; + uint8_t ems_page_regs[4], + regs[256]; + ems_page_t ems_pages[4]; + mem_mapping_t ems_mappings[4]; } ct_82c100_t; - #ifdef ENABLE_CT_82C100_LOG int ct_82c100_do_log = ENABLE_CT82C100_LOG; - static void ct_82c100_log(const char *fmt, ...) { va_list ap; if (ct_82c100_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define ct_82c100_log(fmt, ...) +# define ct_82c100_log(fmt, ...) #endif - static void ct_82c100_ems_pages_recalc(ct_82c100_t *dev) { - int i; + int i; uint32_t page_base; for (i = 0; i < 4; i++) { - page_base = dev->ems_window_base + (i << 14); - if ((i == 1) || (i == 2)) - page_base ^= 0xc000; - if (dev->ems_page_regs[i] & 0x80) { - dev->ems_pages[i].virt = page_base; - dev->ems_pages[i].phys = 0xa0000 + (((uint32_t) (dev->ems_page_regs[i] & 0x7f)) << 14); - ct_82c100_log("Enabling EMS page %i: %08X-%08X -> %08X-%08X\n", i, - dev->ems_pages[i].virt, dev->ems_pages[i].virt + 0x00003fff, - dev->ems_pages[i].phys, dev->ems_pages[i].phys + 0x00003fff); - mem_mapping_set_addr(&(dev->ems_mappings[i]), dev->ems_pages[i].virt, 0x4000); - mem_mapping_set_exec(&(dev->ems_mappings[i]), &(ram[dev->ems_pages[i].phys])); - mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } else { - ct_82c100_log("Disabling EMS page %i\n", i); - mem_mapping_disable(&(dev->ems_mappings[i])); - mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } + page_base = dev->ems_window_base + (i << 14); + if ((i == 1) || (i == 2)) + page_base ^= 0xc000; + if (dev->ems_page_regs[i] & 0x80) { + dev->ems_pages[i].virt = page_base; + dev->ems_pages[i].phys = 0xa0000 + (((uint32_t) (dev->ems_page_regs[i] & 0x7f)) << 14); + ct_82c100_log("Enabling EMS page %i: %08X-%08X -> %08X-%08X\n", i, + dev->ems_pages[i].virt, dev->ems_pages[i].virt + 0x00003fff, + dev->ems_pages[i].phys, dev->ems_pages[i].phys + 0x00003fff); + mem_mapping_set_addr(&(dev->ems_mappings[i]), dev->ems_pages[i].virt, 0x4000); + mem_mapping_set_exec(&(dev->ems_mappings[i]), &(ram[dev->ems_pages[i].phys])); + mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } else { + ct_82c100_log("Disabling EMS page %i\n", i); + mem_mapping_disable(&(dev->ems_mappings[i])); + mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } } flushmmucache_nopc(); } - static void ct_82c100_ems_out(uint16_t port, uint8_t val, void *priv) { @@ -110,36 +104,34 @@ ct_82c100_ems_out(uint16_t port, uint8_t val, void *priv) ct_82c100_ems_pages_recalc(dev); } - static uint8_t ct_82c100_ems_in(uint16_t port, void *priv) { ct_82c100_t *dev = (ct_82c100_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; ret = dev->ems_page_regs[port >> 14]; return ret; } - static void ct_82c100_ems_update(ct_82c100_t *dev) { int i; for (i = 0; i < 4; i++) { - ct_82c100_log("Disabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14)); - io_handler(0, dev->ems_io_base + (i << 14), 1, - ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev); + ct_82c100_log("Disabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14)); + io_handler(0, dev->ems_io_base + (i << 14), 1, + ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev); } dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0); for (i = 0; i < 4; i++) { - ct_82c100_log("Enabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14)); - io_handler(1, dev->ems_io_base + (i << 14), 1, - ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev); + ct_82c100_log("Enabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14)); + io_handler(1, dev->ems_io_base + (i << 14), 1, + ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev); } dev->ems_window_base = 0xc0000 + (((uint32_t) (dev->regs[0x4c] & 0x0f)) << 14); @@ -147,7 +139,6 @@ ct_82c100_ems_update(ct_82c100_t *dev) ct_82c100_ems_pages_recalc(dev); } - static void ct_82c100_reset(void *priv) { @@ -161,7 +152,7 @@ ct_82c100_reset(void *priv) dev->index = dev->access = 0x00; /* INTERNAL CONFIGURATION/CONTROL REGISTERS */ - dev->regs[0x40] = 0x01; /* Defaults to 8086/V30 mode. */ + dev->regs[0x40] = 0x01; /* Defaults to 8086/V30 mode. */ dev->regs[0x43] = 0x30; dev->regs[0x48] = 0x01; @@ -171,188 +162,183 @@ ct_82c100_reset(void *priv) /* ADDITIONAL I/O REGISTERS */ } - static void ct_82c100_out(uint16_t port, uint8_t val, void *priv) { ct_82c100_t *dev = (ct_82c100_t *) priv; if (port == 0x0022) { - dev->index = val; - dev->access = 1; + dev->index = val; + dev->access = 1; } else if (port == 0x0023) { - if (dev->access) { - switch (dev->index) { - /* INTERNAL CONFIGURATION/CONTROL REGISTERS */ - case 0x40: - dev->regs[0x40] = val & 0xc7; - /* TODO: Clock stuff - needs CPU speed change functionality that's - going to be implemented in 86box v4.0. - Bit 0 is 0 for 8088/V20 and 1 for 8086/V30. */ - break; - case 0x41: - dev->regs[0x41] = val & 0xed; - /* TODO: Where is the Software Reset Function that's enabled by - setting bit 6 to 1? */ - break; - case 0x42: - dev->regs[0x42] = val & 0x01; - break; - case 0x43: - dev->regs[0x43] = val; - break; - case 0x44: - dev->regs[0x44] = val; - custom_nmi_vector = (custom_nmi_vector & 0xffffff00) | ((uint32_t) val); - break; - case 0x45: - dev->regs[0x45] = val; - custom_nmi_vector = (custom_nmi_vector & 0xffff00ff) | (((uint32_t) val) << 8); - break; - case 0x46: - dev->regs[0x46] = val; - custom_nmi_vector = (custom_nmi_vector & 0xff00ffff) | (((uint32_t) val) << 16); - break; - case 0x47: - dev->regs[0x47] = val; - custom_nmi_vector = (custom_nmi_vector & 0x00ffffff) | (((uint32_t) val) << 24); - break; - case 0x48: case 0x49: - dev->regs[dev->index] = val; - break; - case 0x4b: - dev->regs[0x4b] = val; - use_custom_nmi_vector = !!(val & 0x40); - break; - case 0x4c: - ct_82c100_log("CS4C: %02X\n", val); - dev->regs[0x4c] = val; - ct_82c100_ems_update(dev); - break; - } - dev->access = 0; - } + if (dev->access) { + switch (dev->index) { + /* INTERNAL CONFIGURATION/CONTROL REGISTERS */ + case 0x40: + dev->regs[0x40] = val & 0xc7; + /* TODO: Clock stuff - needs CPU speed change functionality that's + going to be implemented in 86box v4.0. + Bit 0 is 0 for 8088/V20 and 1 for 8086/V30. */ + break; + case 0x41: + dev->regs[0x41] = val & 0xed; + /* TODO: Where is the Software Reset Function that's enabled by + setting bit 6 to 1? */ + break; + case 0x42: + dev->regs[0x42] = val & 0x01; + break; + case 0x43: + dev->regs[0x43] = val; + break; + case 0x44: + dev->regs[0x44] = val; + custom_nmi_vector = (custom_nmi_vector & 0xffffff00) | ((uint32_t) val); + break; + case 0x45: + dev->regs[0x45] = val; + custom_nmi_vector = (custom_nmi_vector & 0xffff00ff) | (((uint32_t) val) << 8); + break; + case 0x46: + dev->regs[0x46] = val; + custom_nmi_vector = (custom_nmi_vector & 0xff00ffff) | (((uint32_t) val) << 16); + break; + case 0x47: + dev->regs[0x47] = val; + custom_nmi_vector = (custom_nmi_vector & 0x00ffffff) | (((uint32_t) val) << 24); + break; + case 0x48: + case 0x49: + dev->regs[dev->index] = val; + break; + case 0x4b: + dev->regs[0x4b] = val; + use_custom_nmi_vector = !!(val & 0x40); + break; + case 0x4c: + ct_82c100_log("CS4C: %02X\n", val); + dev->regs[0x4c] = val; + ct_82c100_ems_update(dev); + break; + } + dev->access = 0; + } } else if (port == 0x72) - dev->regs[0x72] = val & 0x7e; + dev->regs[0x72] = val & 0x7e; else if (port == 0x7e) - dev->regs[0x7e] = val; + dev->regs[0x7e] = val; else if (port == 0x7f) { - /* Bit 3 is Software Controlled Reset, asserted if set. Will be - done in the feature/machine_and_kb branch using hardresetx86(). */ - dev->regs[0x7f] = val; - if ((dev->regs[0x41] & 0x40) && (val & 0x08)) { - softresetx86(); - cpu_set_edx(); - ct_82c100_reset(dev); - } + /* Bit 3 is Software Controlled Reset, asserted if set. Will be + done in the feature/machine_and_kb branch using hardresetx86(). */ + dev->regs[0x7f] = val; + if ((dev->regs[0x41] & 0x40) && (val & 0x08)) { + softresetx86(); + cpu_set_edx(); + ct_82c100_reset(dev); + } } } - static uint8_t ct_82c100_in(uint16_t port, void *priv) { ct_82c100_t *dev = (ct_82c100_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (port == 0x0022) - ret = dev->index; + ret = dev->index; else if (port == 0x0023) { - if (dev->access) { - switch (dev->index) { - /* INTERNAL CONFIGURATION/CONTROL REGISTERS */ - case 0x40 ... 0x49: - case 0x4b: case 0x4c: - ret = dev->regs[dev->index]; - break; - } - dev->access = 0; - } + if (dev->access) { + switch (dev->index) { + /* INTERNAL CONFIGURATION/CONTROL REGISTERS */ + case 0x40 ... 0x49: + case 0x4b: + case 0x4c: + ret = dev->regs[dev->index]; + break; + } + dev->access = 0; + } } else if (port == 0x72) - ret = dev->regs[0x72]; + ret = dev->regs[0x72]; else if (port == 0x7e) - ret = dev->regs[0x7e]; + ret = dev->regs[0x7e]; else if (port == 0x7f) - ret = dev->regs[0x7f]; + ret = dev->regs[0x7f]; return ret; } - static uint8_t mem_read_emsb(uint32_t addr, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - uint8_t ret = 0xff; + ems_page_t *page = (ems_page_t *) priv; + uint8_t ret = 0xff; #ifdef ENABLE_CT_82C100_LOG uint32_t old_addr = addr; #endif addr = addr - page->virt + page->phys; - if (addr < ((uint32_t)mem_size << 10)) - ret = ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + ret = ram[addr]; ct_82c100_log("mem_read_emsb(%08X = %08X): %02X\n", old_addr, addr, ret); return ret; } - static uint16_t mem_read_emsw(uint32_t addr, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - uint16_t ret = 0xffff; + ems_page_t *page = (ems_page_t *) priv; + uint16_t ret = 0xffff; #ifdef ENABLE_CT_82C100_LOG uint32_t old_addr = addr; #endif addr = addr - page->virt + page->phys; - if (addr < ((uint32_t)mem_size << 10)) - ret = *(uint16_t *)&ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + ret = *(uint16_t *) &ram[addr]; ct_82c100_log("mem_read_emsw(%08X = %08X): %04X\n", old_addr, addr, ret); return ret; } - static void mem_write_emsb(uint32_t addr, uint8_t val, void *priv) { - ems_page_t *page = (ems_page_t *)priv; + ems_page_t *page = (ems_page_t *) priv; #ifdef ENABLE_CT_82C100_LOG uint32_t old_addr = addr; #endif addr = addr - page->virt + page->phys; - if (addr < ((uint32_t)mem_size << 10)) - ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + ram[addr] = val; ct_82c100_log("mem_write_emsb(%08X = %08X, %02X)\n", old_addr, addr, val); } - static void mem_write_emsw(uint32_t addr, uint16_t val, void *priv) { - ems_page_t *page = (ems_page_t *)priv; + ems_page_t *page = (ems_page_t *) priv; #ifdef ENABLE_CT_82C100_LOG uint32_t old_addr = addr; #endif addr = addr - page->virt + page->phys; - if (addr < ((uint32_t)mem_size << 10)) - *(uint16_t *)&ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + *(uint16_t *) &ram[addr] = val; ct_82c100_log("mem_write_emsw(%08X = %08X, %04X)\n", old_addr, addr, val); } - static void ct_82c100_close(void *priv) { @@ -361,51 +347,49 @@ ct_82c100_close(void *priv) free(dev); } - static void * ct_82c100_init(const device_t *info) { ct_82c100_t *dev; - uint32_t i; + uint32_t i; - dev = (ct_82c100_t *)malloc(sizeof(ct_82c100_t)); + dev = (ct_82c100_t *) malloc(sizeof(ct_82c100_t)); memset(dev, 0x00, sizeof(ct_82c100_t)); ct_82c100_reset(dev); io_sethandler(0x0022, 2, - ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); + ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); io_sethandler(0x0072, 1, - ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); + ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); io_sethandler(0x007e, 2, - ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); + ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev); for (i = 0; i < 4; i++) { - mem_mapping_add(&(dev->ems_mappings[i]), (i + 28) << 14, 0x04000, - mem_read_emsb, mem_read_emsw, NULL, - mem_write_emsb, mem_write_emsw, NULL, - ram + 0xa0000 + (i << 14), MEM_MAPPING_INTERNAL, &dev->ems_pages[i]); - mem_mapping_disable(&(dev->ems_mappings[i])); + mem_mapping_add(&(dev->ems_mappings[i]), (i + 28) << 14, 0x04000, + mem_read_emsb, mem_read_emsw, NULL, + mem_write_emsb, mem_write_emsw, NULL, + ram + 0xa0000 + (i << 14), MEM_MAPPING_INTERNAL, &dev->ems_pages[i]); + mem_mapping_disable(&(dev->ems_mappings[i])); } mem_mapping_disable(&ram_mid_mapping); device_add(&port_92_device); - return(dev); + return (dev); } - const device_t ct_82c100_device = { - .name = "C&T 82C100", + .name = "C&T 82C100", .internal_name = "ct_82c100", - .flags = 0, - .local = 0, - .init = ct_82c100_init, - .close = ct_82c100_close, - .reset = ct_82c100_reset, + .flags = 0, + .local = 0, + .init = ct_82c100_init, + .close = ct_82c100_close, + .reset = ct_82c100_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/acc2168.c b/src/chipset/acc2168.c index 9b8865784..aa3921d71 100644 --- a/src/chipset/acc2168.c +++ b/src/chipset/acc2168.c @@ -32,11 +32,11 @@ #include <86box/port_92.h> #include <86box/chipset.h> -#define ENABLED_SHADOW (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) +#define ENABLED_SHADOW (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) #define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) -#define SHADOW_ADDR ((i <= 1) ? (0xc0000 + (i << 15)) : (0xd0000 + ((i - 2) << 16))) -#define SHADOW_SIZE ((i <= 1) ? 0x8000 : 0x10000) -#define SHADOW_RECALC ((dev->regs[0x02] & (1 << i)) ? ENABLED_SHADOW : DISABLED_SHADOW) +#define SHADOW_ADDR ((i <= 1) ? (0xc0000 + (i << 15)) : (0xd0000 + ((i - 2) << 16))) +#define SHADOW_SIZE ((i <= 1) ? 0x8000 : 0x10000) +#define SHADOW_RECALC ((dev->regs[0x02] & (1 << i)) ? ENABLED_SHADOW : DISABLED_SHADOW) #ifdef ENABLE_ACC2168_LOG int acc2168_do_log = ENABLE_ACC2168_LOG; @@ -46,17 +46,16 @@ acc2168_log(const char *fmt, ...) va_list ap; if (acc2168_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define acc2168_log(fmt, ...) +# define acc2168_log(fmt, ...) #endif -typedef struct acc2168_t -{ +typedef struct acc2168_t { uint8_t reg_idx, regs[256]; } acc2168_t; @@ -70,104 +69,101 @@ acc2168_shadow_recalc(acc2168_t *dev) static void acc2168_write(uint16_t addr, uint8_t val, void *p) { - acc2168_t *dev = (acc2168_t *)p; + acc2168_t *dev = (acc2168_t *) p; - switch (addr) - { - case 0xf2: - dev->reg_idx = val; - break; - case 0xf3: - acc2168_log("ACC2168: dev->regs[%02x] = %02x\n", dev->reg_idx, val); - switch (dev->reg_idx) - { - case 0x00: - dev->regs[dev->reg_idx] = val; + switch (addr) { + case 0xf2: + dev->reg_idx = val; break; + case 0xf3: + acc2168_log("ACC2168: dev->regs[%02x] = %02x\n", dev->reg_idx, val); + switch (dev->reg_idx) { + case 0x00: + dev->regs[dev->reg_idx] = val; + break; - case 0x01: - dev->regs[dev->reg_idx] = val & 0xd3; - cpu_update_waitstates(); + case 0x01: + dev->regs[dev->reg_idx] = val & 0xd3; + cpu_update_waitstates(); + break; + + case 0x02: + dev->regs[dev->reg_idx] = val & 0x7f; + acc2168_shadow_recalc(dev); + break; + + case 0x03: + dev->regs[dev->reg_idx] = val & 0x1f; + break; + + case 0x04: + dev->regs[dev->reg_idx] = val; + cpu_cache_ext_enabled = !!(val & 0x01); + cpu_update_waitstates(); + break; + + case 0x05: + dev->regs[dev->reg_idx] = val & 0xf3; + break; + + case 0x06: + case 0x07: + dev->regs[dev->reg_idx] = val & 0x1f; + break; + + case 0x08: + dev->regs[dev->reg_idx] = val & 0x0f; + break; + + case 0x09: + dev->regs[dev->reg_idx] = val & 0x03; + break; + + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + case 0x10: + case 0x11: + dev->regs[dev->reg_idx] = val; + break; + + case 0x12: + dev->regs[dev->reg_idx] = val & 0xbb; + break; + + case 0x18: + dev->regs[dev->reg_idx] = val & 0x77; + break; + + case 0x19: + dev->regs[dev->reg_idx] = val & 0xfb; + break; + + case 0x1a: + dev->regs[dev->reg_idx] = val; + cpu_cache_int_enabled = !(val & 0x40); + cpu_update_waitstates(); + break; + + case 0x1b: + dev->regs[dev->reg_idx] = val & 0xef; + break; + + default: /* ACC 2168 has way more registers which we haven't documented */ + dev->regs[dev->reg_idx] = val; + break; + } break; - - case 0x02: - dev->regs[dev->reg_idx] = val & 0x7f; - acc2168_shadow_recalc(dev); - break; - - case 0x03: - dev->regs[dev->reg_idx] = val & 0x1f; - break; - - case 0x04: - dev->regs[dev->reg_idx] = val; - cpu_cache_ext_enabled = !!(val & 0x01); - cpu_update_waitstates(); - break; - - case 0x05: - dev->regs[dev->reg_idx] = val & 0xf3; - break; - - case 0x06: - case 0x07: - dev->regs[dev->reg_idx] = val & 0x1f; - break; - - case 0x08: - dev->regs[dev->reg_idx] = val & 0x0f; - break; - - case 0x09: - dev->regs[dev->reg_idx] = val & 0x03; - break; - - case 0x0a: - case 0x0b: - case 0x0c: - case 0x0d: - case 0x0e: - case 0x0f: - case 0x10: - case 0x11: - dev->regs[dev->reg_idx] = val; - break; - - case 0x12: - dev->regs[dev->reg_idx] = val & 0xbb; - break; - - case 0x18: - dev->regs[dev->reg_idx] = val & 0x77; - break; - - case 0x19: - dev->regs[dev->reg_idx] = val & 0xfb; - break; - - case 0x1a: - dev->regs[dev->reg_idx] = val; - cpu_cache_int_enabled = !(val & 0x40); - cpu_update_waitstates(); - break; - - case 0x1b: - dev->regs[dev->reg_idx] = val & 0xef; - break; - - default: /* ACC 2168 has way more registers which we haven't documented */ - dev->regs[dev->reg_idx] = val; - break; - - } - break; } } static uint8_t acc2168_read(uint16_t addr, void *p) { - acc2168_t *dev = (acc2168_t *)p; + acc2168_t *dev = (acc2168_t *) p; return (addr == 0xf3) ? dev->regs[dev->reg_idx] : dev->reg_idx; } @@ -175,7 +171,7 @@ acc2168_read(uint16_t addr, void *p) static void acc2168_close(void *priv) { - acc2168_t *dev = (acc2168_t *)priv; + acc2168_t *dev = (acc2168_t *) priv; free(dev); } @@ -183,7 +179,7 @@ acc2168_close(void *priv) static void * acc2168_init(const device_t *info) { - acc2168_t *dev = (acc2168_t *)malloc(sizeof(acc2168_t)); + acc2168_t *dev = (acc2168_t *) malloc(sizeof(acc2168_t)); memset(dev, 0, sizeof(acc2168_t)); device_add(&port_92_device); @@ -193,15 +189,15 @@ acc2168_init(const device_t *info) } const device_t acc2168_device = { - .name = "ACC 2046/2168", + .name = "ACC 2046/2168", .internal_name = "acc2168", - .flags = 0, - .local = 0, - .init = acc2168_init, - .close = acc2168_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = acc2168_init, + .close = acc2168_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1429.c b/src/chipset/ali1429.c index 468ed4f00..68ffd9fe0 100644 --- a/src/chipset/ali1429.c +++ b/src/chipset/ali1429.c @@ -64,12 +64,12 @@ Register 20h: Bits 2-1-0: Bus Clock Speed 0 0 0: 7.1519Mhz (ATCLK2) - 0 0 1: CLK2IN/4 - 0 1 0: CLK2IN/5 - 0 1 1: CLK2IN/6 - 1 0 0: CLK2IN/8 - 1 0 1: CLK2IN/10 - 1 1 0: CLK2IN/12 + 0 0 1: CLK2IN/4 + 0 1 0: CLK2IN/5 + 0 1 1: CLK2IN/6 + 1 0 0: CLK2IN/8 + 1 0 1: CLK2IN/10 + 1 1 0: CLK2IN/12 */ @@ -94,13 +94,11 @@ #include <86box/smram.h> #include <86box/chipset.h> -#define GREEN dev->is_g /* Is G Variant */ - +#define GREEN dev->is_g /* Is G Variant */ #ifdef ENABLE_ALI1429_LOG int ali1429_do_log = ENABLE_ALI1429_LOG; - static void ali1429_log(const char *fmt, ...) { @@ -113,27 +111,25 @@ ali1429_log(const char *fmt, ...) } } #else -#define ali1429_log(fmt, ...) +# define ali1429_log(fmt, ...) #endif - typedef struct { - uint8_t is_g, index, cfg_locked, reg_57h, - regs[90]; + uint8_t is_g, index, cfg_locked, reg_57h, + regs[90]; } ali1429_t; - static void ali1429_shadow_recalc(ali1429_t *dev) { uint32_t base, i, can_write, can_read; - shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01); + shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01); shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02); can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; for (i = 0; i < 8; i++) { base = 0xc0000 + (i << 15); @@ -147,147 +143,149 @@ ali1429_shadow_recalc(ali1429_t *dev) flushmmucache_nopc(); } - static void ali1429_write(uint16_t addr, uint8_t val, void *priv) { - ali1429_t *dev = (ali1429_t *)priv; + ali1429_t *dev = (ali1429_t *) priv; switch (addr) { - case 0x22: - dev->index = val; - break; + case 0x22: + dev->index = val; + break; - case 0x23: + case 0x23: #ifdef ENABLE_ALI1429_LOG - if (dev->index != 0x03) - ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val); + if (dev->index != 0x03) + ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val); #endif - if (dev->index == 0x03) - dev->cfg_locked = !(val == 0xc5); + if (dev->index == 0x03) + dev->cfg_locked = !(val == 0xc5); - if (!dev->cfg_locked) { - /* Common M1429 Registers */ - switch (dev->index) { - case 0x10: case 0x11: - dev->regs[dev->index] = val; - break; + if (!dev->cfg_locked) { + /* Common M1429 Registers */ + switch (dev->index) { + case 0x10: + case 0x11: + dev->regs[dev->index] = val; + break; - case 0x12: - dev->regs[dev->index] = val; - if(val & 4) - mem_remap_top(128); - else - mem_remap_top(0); - break; + case 0x12: + dev->regs[dev->index] = val; + if (val & 4) + mem_remap_top(128); + else + mem_remap_top(0); + break; - case 0x13: case 0x14: - dev->regs[dev->index] = val; - ali1429_shadow_recalc(dev); - break; + case 0x13: + case 0x14: + dev->regs[dev->index] = val; + ali1429_shadow_recalc(dev); + break; - case 0x15: case 0x16: - case 0x17: - dev->regs[dev->index] = val; - break; + case 0x15: + case 0x16: + case 0x17: + dev->regs[dev->index] = val; + break; - case 0x18: - dev->regs[dev->index] = (val & 0x8f) | 0x20; - cpu_cache_ext_enabled = !!(val & 2); - cpu_update_waitstates(); - break; + case 0x18: + dev->regs[dev->index] = (val & 0x8f) | 0x20; + cpu_cache_ext_enabled = !!(val & 2); + cpu_update_waitstates(); + break; - case 0x19: case 0x1a: - case 0x1e: - dev->regs[dev->index] = val; - break; + case 0x19: + case 0x1a: + case 0x1e: + dev->regs[dev->index] = val; + break; - case 0x20: - dev->regs[dev->index] = val; + case 0x20: + dev->regs[dev->index] = val; - switch(val & 7) { - case 0: case 7: /* Illegal */ - cpu_set_isa_speed(7159091); - break; + switch (val & 7) { + case 0: + case 7: /* Illegal */ + cpu_set_isa_speed(7159091); + break; - case 1: - cpu_set_isa_speed(cpu_busspeed / 4); - break; + case 1: + cpu_set_isa_speed(cpu_busspeed / 4); + break; - case 2: - cpu_set_isa_speed(cpu_busspeed / 5); - break; + case 2: + cpu_set_isa_speed(cpu_busspeed / 5); + break; - case 3: - cpu_set_isa_speed(cpu_busspeed / 6); - break; + case 3: + cpu_set_isa_speed(cpu_busspeed / 6); + break; - case 4: - cpu_set_isa_speed(cpu_busspeed / 8); - break; + case 4: + cpu_set_isa_speed(cpu_busspeed / 8); + break; - case 5: - cpu_set_isa_speed(cpu_busspeed / 10); - break; + case 5: + cpu_set_isa_speed(cpu_busspeed / 10); + break; - case 6: - cpu_set_isa_speed(cpu_busspeed / 12); - break; - } - break; + case 6: + cpu_set_isa_speed(cpu_busspeed / 12); + break; + } + break; - case 0x21 ... 0x27: - dev->regs[dev->index] = val; - break; - } + case 0x21 ... 0x27: + dev->regs[dev->index] = val; + break; + } - /* M1429G Only Registers */ - if (GREEN) { - switch (dev->index) { - case 0x30 ... 0x41: - case 0x43: case 0x45: - case 0x4a: - dev->regs[dev->index] = val; - break; + /* M1429G Only Registers */ + if (GREEN) { + switch (dev->index) { + case 0x30 ... 0x41: + case 0x43: + case 0x45: + case 0x4a: + dev->regs[dev->index] = val; + break; - case 0x57: - dev->reg_57h = val; - break; - } - } - } - break; + case 0x57: + dev->reg_57h = val; + break; + } + } + } + break; } } - static uint8_t ali1429_read(uint16_t addr, void *priv) { - ali1429_t *dev = (ali1429_t *)priv; - uint8_t ret = 0xff; + ali1429_t *dev = (ali1429_t *) priv; + uint8_t ret = 0xff; if ((addr == 0x23) && (dev->index >= 0x10) && (dev->index <= 0x4a)) - ret = dev->regs[dev->index]; + ret = dev->regs[dev->index]; else if ((addr == 0x23) && (dev->index == 0x57)) - ret = dev->reg_57h; + ret = dev->reg_57h; else if (addr == 0x22) - ret = dev->index; + ret = dev->index; return ret; } - static void ali1429_close(void *priv) { - ali1429_t *dev = (ali1429_t *)priv; + ali1429_t *dev = (ali1429_t *) priv; free(dev); } - static void ali1429_defaults(ali1429_t *dev) { @@ -306,28 +304,27 @@ ali1429_defaults(ali1429_t *dev) /* M1429G Default Registers */ if (GREEN) { - dev->regs[0x31] = 0x88; - dev->regs[0x32] = 0xc0; - dev->regs[0x38] = 0xe5; - dev->regs[0x40] = 0xe3; - dev->regs[0x41] = 2; - dev->regs[0x45] = 0x80; + dev->regs[0x31] = 0x88; + dev->regs[0x32] = 0xc0; + dev->regs[0x38] = 0xe5; + dev->regs[0x40] = 0xe3; + dev->regs[0x41] = 2; + dev->regs[0x45] = 0x80; } } - static void * ali1429_init(const device_t *info) { - ali1429_t *dev = (ali1429_t *)malloc(sizeof(ali1429_t)); + ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t)); memset(dev, 0, sizeof(ali1429_t)); dev->cfg_locked = 1; - GREEN = info->local; + GREEN = info->local; /* M1429 Ports: - 22h Index Port - 23h Data Port + 22h Index Port + 23h Data Port */ io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); @@ -339,29 +336,29 @@ ali1429_init(const device_t *info) } const device_t ali1429_device = { - .name = "ALi M1429", + .name = "ALi M1429", .internal_name = "ali1429", - .flags = 0, - .local = 0, - .init = ali1429_init, - .close = ali1429_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = ali1429_init, + .close = ali1429_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t ali1429g_device = { - .name = "ALi M1429G", + .name = "ALi M1429G", .internal_name = "ali1429g", - .flags = 0, - .local = 1, - .init = ali1429_init, - .close = ali1429_close, - .reset = NULL, + .flags = 0, + .local = 1, + .init = ali1429_init, + .close = ali1429_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1489.c b/src/chipset/ali1489.c index da6ff39cc..c71b3e46d 100644 --- a/src/chipset/ali1489.c +++ b/src/chipset/ali1489.c @@ -40,10 +40,8 @@ #include <86box/chipset.h> - #define DEFINE_SHADOW_PROCEDURE (((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)) -#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) - +#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) #ifdef ENABLE_ALI1489_LOG int ali1489_do_log = ENABLE_ALI1489_LOG; @@ -52,30 +50,26 @@ ali1489_log(const char *fmt, ...) { va_list ap; - if (ali1489_do_log) - { + if (ali1489_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define ali1489_log(fmt, ...) +# define ali1489_log(fmt, ...) #endif - typedef struct { - uint8_t index, ide_index, ide_chip_id, pci_slot, - regs[256], pci_conf[256], ide_regs[256]; + uint8_t index, ide_index, ide_chip_id, pci_slot, + regs[256], pci_conf[256], ide_regs[256]; - port_92_t * port_92; - smram_t * smram; + port_92_t *port_92; + smram_t *smram; } ali1489_t; - -static void ali1489_ide_handler(ali1489_t *dev); - +static void ali1489_ide_handler(ali1489_t *dev); static void ali1489_shadow_recalc(ali1489_t *dev) @@ -85,33 +79,32 @@ ali1489_shadow_recalc(ali1489_t *dev) shadowbios = shadowbios_write = 0; for (i = 0; i < 8; i++) { - if (dev->regs[0x13] & (1 << i)) { - ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n", - 0xc0000 + (i << 14), 0xc3fff + (i << 14), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20)); - mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DEFINE_SHADOW_PROCEDURE); - } else { - ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xc0000 + (i << 14), 0xc3fff + (i << 14)); - mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DISABLED_SHADOW); - } + if (dev->regs[0x13] & (1 << i)) { + ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n", + 0xc0000 + (i << 14), 0xc3fff + (i << 14), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20)); + mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DEFINE_SHADOW_PROCEDURE); + } else { + ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xc0000 + (i << 14), 0xc3fff + (i << 14)); + mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DISABLED_SHADOW); + } } for (i = 0; i < 4; i++) { if (dev->regs[0x14] & (1 << i)) { - ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n", - 0xe0000 + (i << 15), 0xe7fff + (i << 15), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20)); - mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DEFINE_SHADOW_PROCEDURE); - shadowbios |= !!(dev->regs[0x14] & 0x10); - shadowbios_write |= !!(dev->regs[0x14] & 0x20); + ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n", + 0xe0000 + (i << 15), 0xe7fff + (i << 15), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20)); + mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DEFINE_SHADOW_PROCEDURE); + shadowbios |= !!(dev->regs[0x14] & 0x10); + shadowbios_write |= !!(dev->regs[0x14] & 0x20); } else { - ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xe0000 + (i << 15), 0xe7fff + (i << 15)); - mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DISABLED_SHADOW); - } + ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xe0000 + (i << 15), 0xe7fff + (i << 15)); + mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DISABLED_SHADOW); + } } flushmmucache_nopc(); } - static void ali1489_smram_recalc(ali1489_t *dev) { @@ -120,27 +113,26 @@ ali1489_smram_recalc(ali1489_t *dev) smram_disable(dev->smram); switch (dev->regs[0x19] & 0x30) { - case 0x10: - smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1); - break; - case 0x20: - smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), 1); - break; - case 0x30: - if ((dev->regs[0x35] & 0xc0) == 0x80) - smram_enable(dev->smram, 0x68000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1); - else - smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1); - break; + case 0x10: + smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1); + break; + case 0x20: + smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), 1); + break; + case 0x30: + if ((dev->regs[0x35] & 0xc0) == 0x80) + smram_enable(dev->smram, 0x68000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1); + else + smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1); + break; } if ((dev->regs[0x19] & 0x31) == 0x11) { - /* If SMRAM is enabled and bit 0 is set, code still goes to DRAM. */ - mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); + /* If SMRAM is enabled and bit 0 is set, code still goes to DRAM. */ + mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); } } - static void ali1489_defaults(ali1489_t *dev) { @@ -197,9 +189,9 @@ ali1489_defaults(ali1489_t *dev) picintc(1 << 10); picintc(1 << 15); - nmi = 0; + nmi = 0; smi_line = 0; - in_smm = 0; + in_smm = 0; pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); @@ -209,214 +201,212 @@ ali1489_defaults(ali1489_t *dev) ali1489_ide_handler(dev); } - static void ali1489_write(uint16_t addr, uint8_t val, void *priv) { - ali1489_t *dev = (ali1489_t *)priv; - uint8_t old, irq; + ali1489_t *dev = (ali1489_t *) priv; + uint8_t old, irq; const uint8_t irq_array[16] = { 0, 3, 4, 7, 0, 0, 0, 0, 9, 10, 5, 6, 11, 12, 14, 15 }; switch (addr) { - case 0x22: - dev->index = val; - break; - case 0x23: - /* Check if the configuration registers are unlocked */ - if (dev->regs[0x03] == 0xc5) { - switch (dev->index) { - case 0x03: /* Lock Register */ - case 0x10: /* DRAM Configuration Register I */ - case 0x11: /* DRAM Configuration Register II */ - case 0x12: /* ROM Function Register */ - dev->regs[dev->index] = val; - break; + case 0x22: + dev->index = val; + break; + case 0x23: + /* Check if the configuration registers are unlocked */ + if (dev->regs[0x03] == 0xc5) { + switch (dev->index) { + case 0x03: /* Lock Register */ + case 0x10: /* DRAM Configuration Register I */ + case 0x11: /* DRAM Configuration Register II */ + case 0x12: /* ROM Function Register */ + dev->regs[dev->index] = val; + break; - case 0x13: /* Shadow Region Register */ - case 0x14: /* Shadow Control Register */ - if (dev->index == 0x14) - dev->regs[dev->index] = (val & 0xbf); - else - dev->regs[dev->index] = val; + case 0x13: /* Shadow Region Register */ + case 0x14: /* Shadow Control Register */ + if (dev->index == 0x14) + dev->regs[dev->index] = (val & 0xbf); + else + dev->regs[dev->index] = val; - ali1489_shadow_recalc(dev); - ali1489_smram_recalc(dev); - break; + ali1489_shadow_recalc(dev); + ali1489_smram_recalc(dev); + break; - case 0x15: /* Cycle Check Point Control Register */ - dev->regs[dev->index] = (val & 0xf1); - break; + case 0x15: /* Cycle Check Point Control Register */ + dev->regs[dev->index] = (val & 0xf1); + break; - case 0x16: /* Cache Control Register I */ - dev->regs[dev->index] = val; - cpu_cache_int_enabled = (val & 0x01); - cpu_cache_ext_enabled = (val & 0x02); - cpu_update_waitstates(); - break; - case 0x17: /* Cache Control Register II */ - dev->regs[dev->index] = val; - break; + case 0x16: /* Cache Control Register I */ + dev->regs[dev->index] = val; + cpu_cache_int_enabled = (val & 0x01); + cpu_cache_ext_enabled = (val & 0x02); + cpu_update_waitstates(); + break; + case 0x17: /* Cache Control Register II */ + dev->regs[dev->index] = val; + break; - case 0x19: /* SMM Control Register */ - dev->regs[dev->index] = val; - ali1489_smram_recalc(dev); - break; + case 0x19: /* SMM Control Register */ + dev->regs[dev->index] = val; + ali1489_smram_recalc(dev); + break; - case 0x1a: /* EDO DRAM Configuration Register */ - case 0x1b: /* DRAM Timing Control Register */ - dev->regs[dev->index] = val; - break; - case 0x1c: /* Memory Data Buffer Direction Control Register */ - dev->regs[dev->index] = val & 0x1f; - break; + case 0x1a: /* EDO DRAM Configuration Register */ + case 0x1b: /* DRAM Timing Control Register */ + dev->regs[dev->index] = val; + break; + case 0x1c: /* Memory Data Buffer Direction Control Register */ + dev->regs[dev->index] = val & 0x1f; + break; - case 0x1e: /* Linear Wrapped Burst Order Mode Control Register */ - dev->regs[dev->index] = (val & 0x40); - break; + case 0x1e: /* Linear Wrapped Burst Order Mode Control Register */ + dev->regs[dev->index] = (val & 0x40); + break; - case 0x20: /* CPU to PCI Buffer Control Register */ - dev->regs[dev->index] = val; - break; - case 0x21: /* DEVSELJ Check Point Setting Register */ - dev->regs[dev->index] = (val & 0xbb) | 0x04; - break; - case 0x22: /* PCI to CPU W/R Buffer Configuration Register */ - dev->regs[dev->index] = (val & 0xfd); - break; + case 0x20: /* CPU to PCI Buffer Control Register */ + dev->regs[dev->index] = val; + break; + case 0x21: /* DEVSELJ Check Point Setting Register */ + dev->regs[dev->index] = (val & 0xbb) | 0x04; + break; + case 0x22: /* PCI to CPU W/R Buffer Configuration Register */ + dev->regs[dev->index] = (val & 0xfd); + break; - case 0x25: /* GP/MEM Address Definition Register I */ - case 0x26: /* GP/MEM Address Definition Register II */ - case 0x27: /* GP/MEM Address Definition Register III */ - dev->regs[dev->index] = val; - break; - case 0x28: /* PCI Arbiter Control Register */ - dev->regs[dev->index] = val & 0x3f; - break; + case 0x25: /* GP/MEM Address Definition Register I */ + case 0x26: /* GP/MEM Address Definition Register II */ + case 0x27: /* GP/MEM Address Definition Register III */ + dev->regs[dev->index] = val; + break; + case 0x28: /* PCI Arbiter Control Register */ + dev->regs[dev->index] = val & 0x3f; + break; - case 0x29: /* System Clock Register */ - dev->regs[dev->index] = val; + case 0x29: /* System Clock Register */ + dev->regs[dev->index] = val; - port_92_remove(dev->port_92); - if (val & 0x10) - port_92_add(dev->port_92); - break; + port_92_remove(dev->port_92); + if (val & 0x10) + port_92_add(dev->port_92); + break; - case 0x2a: /* I/O Recovery Register */ - dev->regs[dev->index] = val; - break; + case 0x2a: /* I/O Recovery Register */ + dev->regs[dev->index] = val; + break; - case 0x2b: /* Turbo Function Register */ - dev->regs[dev->index] = (val & 0xbf) | 0x40; - break; + case 0x2b: /* Turbo Function Register */ + dev->regs[dev->index] = (val & 0xbf) | 0x40; + break; - case 0x30: /* Power Management Unit Control Register */ - old = dev->regs[dev->index]; - dev->regs[dev->index] = val; + case 0x30: /* Power Management Unit Control Register */ + old = dev->regs[dev->index]; + dev->regs[dev->index] = val; - if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) { - switch (dev->regs[0x35] & 0x30) { - case 0x00: - smi_raise(); - break; - case 0x10: - nmi_raise(); - break; - case 0x20: - picint(1 << 15); - break; - case 0x30: - picint(1 << 10); - break; - } - dev->regs[0x35] |= 0x0e; - } else if (!(val & 0x10)) - dev->regs[0x35] &= ~0x0f; - break; + if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) { + switch (dev->regs[0x35] & 0x30) { + case 0x00: + smi_raise(); + break; + case 0x10: + nmi_raise(); + break; + case 0x20: + picint(1 << 15); + break; + case 0x30: + picint(1 << 10); + break; + } + dev->regs[0x35] |= 0x0e; + } else if (!(val & 0x10)) + dev->regs[0x35] &= ~0x0f; + break; - case 0x31: /* Mode Timer Monitoring Events Selection Register I */ - case 0x32: /* Mode Timer Monitoring Events Selection Register II */ - case 0x33: /* SMI Triggered Events Selection Register I */ - case 0x34: /* SMI Triggered Events Selection Register II */ - dev->regs[dev->index] = val; - break; + case 0x31: /* Mode Timer Monitoring Events Selection Register I */ + case 0x32: /* Mode Timer Monitoring Events Selection Register II */ + case 0x33: /* SMI Triggered Events Selection Register I */ + case 0x34: /* SMI Triggered Events Selection Register II */ + dev->regs[dev->index] = val; + break; - case 0x35: /* SMI Status Register */ - dev->regs[dev->index] = (dev->regs[dev->index] & 0x0f) | (val & 0xf0); - break; + case 0x35: /* SMI Status Register */ + dev->regs[dev->index] = (dev->regs[dev->index] & 0x0f) | (val & 0xf0); + break; - case 0x36: /* IRQ Channel Group Selected Control Register I */ - dev->regs[dev->index] = (val & 0xe5); - break; - case 0x37: /* IRQ Channel Group Selected Control Register II */ - dev->regs[dev->index] = (val & 0xef); - break; + case 0x36: /* IRQ Channel Group Selected Control Register I */ + dev->regs[dev->index] = (val & 0xe5); + break; + case 0x37: /* IRQ Channel Group Selected Control Register II */ + dev->regs[dev->index] = (val & 0xef); + break; - case 0x38: /* DRQ Channel Selected Control Register */ - case 0x39: /* Mode Timer Setting Register */ - case 0x3a: /* Input_device Timer Setting Register */ - case 0x3b: /* GP/MEM Timer Setting Register */ - case 0x3c: /* LED Flash Control Register */ - dev->regs[dev->index] = val; - break; + case 0x38: /* DRQ Channel Selected Control Register */ + case 0x39: /* Mode Timer Setting Register */ + case 0x3a: /* Input_device Timer Setting Register */ + case 0x3b: /* GP/MEM Timer Setting Register */ + case 0x3c: /* LED Flash Control Register */ + dev->regs[dev->index] = val; + break; - case 0x3d: /* Miscellaneous Register I */ - dev->regs[dev->index] = (val & 0x07); - break; + case 0x3d: /* Miscellaneous Register I */ + dev->regs[dev->index] = (val & 0x07); + break; - case 0x40: /* Clock Generator Control Feature Register */ - dev->regs[dev->index] = (val & 0x3f); - break; - case 0x41: /* Power Control Output Register */ - dev->regs[dev->index] = val; - break; + case 0x40: /* Clock Generator Control Feature Register */ + dev->regs[dev->index] = (val & 0x3f); + break; + case 0x41: /* Power Control Output Register */ + dev->regs[dev->index] = val; + break; - case 0x42: /* PCI INTx Routing Table Mapping Register I */ - irq = irq_array[val & 0x0f]; - pci_set_irq_routing(PCI_INTA, (irq != 0) ? irq : PCI_IRQ_DISABLED); - irq = irq_array[(val & 0xf0) >> 4]; - pci_set_irq_routing(PCI_INTB, (irq != 0) ? irq : PCI_IRQ_DISABLED); - break; + case 0x42: /* PCI INTx Routing Table Mapping Register I */ + irq = irq_array[val & 0x0f]; + pci_set_irq_routing(PCI_INTA, (irq != 0) ? irq : PCI_IRQ_DISABLED); + irq = irq_array[(val & 0xf0) >> 4]; + pci_set_irq_routing(PCI_INTB, (irq != 0) ? irq : PCI_IRQ_DISABLED); + break; - case 0x43: /* PCI INTx Routing Table Mapping Register II */ - irq = irq_array[val & 0x0f]; - pci_set_irq_routing(PCI_INTC, (irq != 0) ? irq : PCI_IRQ_DISABLED); - irq = irq_array[(val & 0xf0) >> 4]; - pci_set_irq_routing(PCI_INTD, (irq != 0) ? irq : PCI_IRQ_DISABLED); - break; + case 0x43: /* PCI INTx Routing Table Mapping Register II */ + irq = irq_array[val & 0x0f]; + pci_set_irq_routing(PCI_INTC, (irq != 0) ? irq : PCI_IRQ_DISABLED); + irq = irq_array[(val & 0xf0) >> 4]; + pci_set_irq_routing(PCI_INTD, (irq != 0) ? irq : PCI_IRQ_DISABLED); + break; - case 0x44: /* PCI INTx Sensitivity Register */ - /* TODO: When doing the IRQ and PCI IRQ rewrite, bits 0 to 3 toggle edge/level output. */ - dev->regs[dev->index] = val; - break; - } + case 0x44: /* PCI INTx Sensitivity Register */ + /* TODO: When doing the IRQ and PCI IRQ rewrite, bits 0 to 3 toggle edge/level output. */ + dev->regs[dev->index] = val; + break; + } - if (dev->index != 0x03) { - ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val); - } - } else if (dev->index == 0x03) - dev->regs[dev->index] = val; + if (dev->index != 0x03) { + ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val); + } + } else if (dev->index == 0x03) + dev->regs[dev->index] = val; - break; + break; } } - static uint8_t ali1489_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; - ali1489_t *dev = (ali1489_t *)priv; + uint8_t ret = 0xff; + ali1489_t *dev = (ali1489_t *) priv; switch (addr) { - case 0x23: - /* Avoid conflict with Cyrix CPU registers */ - if (((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix) - ret = 0xff; - else if (dev->index == 0x3f) - ret = inb(0x70); - else - ret = dev->regs[dev->index]; - break; + case 0x23: + /* Avoid conflict with Cyrix CPU registers */ + if (((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix) + ret = 0xff; + else if (dev->index == 0x3f) + ret = inb(0x70); + else + ret = dev->regs[dev->index]; + break; } ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret); @@ -424,155 +414,147 @@ ali1489_read(uint16_t addr, void *priv) return ret; } - static void ali1489_pci_write(int func, int addr, uint8_t val, void *priv) { - ali1489_t *dev = (ali1489_t *)priv; + ali1489_t *dev = (ali1489_t *) priv; ali1489_log("M1489-PCI: dev->pci_conf[%02x] = %02x\n", addr, val); switch (addr) { - /* Dummy PCI Config */ - case 0x04: - dev->pci_conf[0x04] = val & 0x7f; - break; + /* Dummy PCI Config */ + case 0x04: + dev->pci_conf[0x04] = val & 0x7f; + break; - /* Dummy PCI Status */ - case 0x07: - dev->pci_conf[0x07] &= ~(val & 0xb8); - break; + /* Dummy PCI Status */ + case 0x07: + dev->pci_conf[0x07] &= ~(val & 0xb8); + break; } } - static uint8_t ali1489_pci_read(int func, int addr, void *priv) { - ali1489_t *dev = (ali1489_t *)priv; - uint8_t ret = 0xff; + ali1489_t *dev = (ali1489_t *) priv; + uint8_t ret = 0xff; ret = dev->pci_conf[addr]; ali1489_log("M1489-PCI: dev->pci_conf[%02x] (%02x)\n", addr, ret); return ret; } - static void ali1489_ide_handler(ali1489_t *dev) { ide_pri_disable(); ide_sec_disable(); if (dev->ide_regs[0x01] & 0x01) { - ide_pri_enable(); - if (!(dev->ide_regs[0x35] & 0x40)) - ide_sec_enable(); + ide_pri_enable(); + if (!(dev->ide_regs[0x35] & 0x40)) + ide_sec_enable(); } } - static void ali1489_ide_write(uint16_t addr, uint8_t val, void *priv) { - ali1489_t *dev = (ali1489_t *)priv; + ali1489_t *dev = (ali1489_t *) priv; - switch (addr) - { - case 0xf4: /* Usually it writes 30h here */ - dev->ide_chip_id = val; - break; + switch (addr) { + case 0xf4: /* Usually it writes 30h here */ + dev->ide_chip_id = val; + break; - case 0xf8: - dev->ide_index = val; - break; + case 0xf8: + dev->ide_index = val; + break; - case 0xfc: - if (dev->ide_chip_id != 0x30) - break; + case 0xfc: + if (dev->ide_chip_id != 0x30) + break; - switch(dev->ide_index) { - case 0x01: /* IDE Configuration Register */ - dev->ide_regs[dev->ide_index] = val & 0x8f; - ali1489_ide_handler(dev); - break; - case 0x02: /* DBA Data Byte Cative Count for IDE-1 */ - case 0x03: /* D0RA Disk 0 Read Active Count for IDE-1 */ - case 0x04: /* D0WA Disk 0 Write Active Count for IDE-1 */ - case 0x05: /* D1RA Disk 1 Read Active Count for IDE-1 */ - case 0x06: /* D1WA Disk 1 Write Active Count for IDE-1 */ - case 0x25: /* DBR Data Byte Recovery Count for IDE-1 */ - case 0x26: /* D0RR Disk 0 Read Byte Recovery Count for IDE-1 */ - case 0x27: /* D0WR Disk 0 Write Byte Recovery Count for IDE-1 */ - case 0x28: /* D1RR Disk 1 Read Byte Recovery Count for IDE-1 */ - case 0x29: /* D1WR Disk 1 Write Byte Recovery Count for IDE-1 */ - case 0x2a: /* DBA Data Byte Cative Count for IDE-2 */ - case 0x2b: /* D0RA Disk 0 Read Active Count for IDE-2 */ - case 0x2c: /* D0WA Disk 0 Write Active Count for IDE-2 */ - case 0x2d: /* D1RA Disk 1 Read Active Count for IDE-2 */ - case 0x2e: /* D1WA Disk 1 Write Active Count for IDE-2 */ - case 0x2f: /* DBR Data Byte Recovery Count for IDE-2 */ - case 0x30: /* D0RR Disk 0 Read Byte Recovery Count for IDE-2 */ - case 0x31: /* D0WR Disk 0 Write Byte Recovery Count for IDE-2 */ - case 0x32: /* D1RR Disk 1 Read Byte Recovery Count for IDE-2 */ - case 0x33: /* D1WR Disk 1 Write Byte Recovery Count for IDE-2 */ - dev->ide_regs[dev->ide_index] = val & 0x1f; - break; - case 0x07: /* Buffer Mode Register 1 */ - dev->ide_regs[dev->ide_index] = val; - break; - case 0x09: /* IDEPE1 IDE Port Enable Register 1 */ - dev->ide_regs[dev->ide_index] = val & 0xc3; - break; - case 0x0a: /* Buffer Mode Register 2 */ - dev->ide_regs[dev->ide_index] = val & 0x4f; - break; - case 0x0b: /* IDE Channel 1 Disk 0 Sector Byte Count Register 1 */ - case 0x0d: /* IDE Channel 1 Disk 1 Sector Byte Count Register 1 */ - case 0x0f: /* IDE Channel 2 Disk 0 Sector Byte Count Register 1 */ - case 0x11: /* IDE Channel 2 Disk 1 Sector Byte Count Register 1 */ - dev->ide_regs[dev->ide_index] = val & 0x03; - break; - case 0x0c: /* IDE Channel 1 Disk 0 Sector Byte Count Register 2 */ - case 0x0e: /* IDE Channel 1 Disk 1 Sector Byte Count Register 2 */ - case 0x10: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */ - case 0x12: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */ - dev->ide_regs[dev->ide_index] = val & 0x1f; - break; - case 0x35: /* IDEPE3 IDE Port Enable Register 3 */ - dev->ide_regs[dev->ide_index] = val; - ali1489_ide_handler(dev); - break; - } - break; + switch (dev->ide_index) { + case 0x01: /* IDE Configuration Register */ + dev->ide_regs[dev->ide_index] = val & 0x8f; + ali1489_ide_handler(dev); + break; + case 0x02: /* DBA Data Byte Cative Count for IDE-1 */ + case 0x03: /* D0RA Disk 0 Read Active Count for IDE-1 */ + case 0x04: /* D0WA Disk 0 Write Active Count for IDE-1 */ + case 0x05: /* D1RA Disk 1 Read Active Count for IDE-1 */ + case 0x06: /* D1WA Disk 1 Write Active Count for IDE-1 */ + case 0x25: /* DBR Data Byte Recovery Count for IDE-1 */ + case 0x26: /* D0RR Disk 0 Read Byte Recovery Count for IDE-1 */ + case 0x27: /* D0WR Disk 0 Write Byte Recovery Count for IDE-1 */ + case 0x28: /* D1RR Disk 1 Read Byte Recovery Count for IDE-1 */ + case 0x29: /* D1WR Disk 1 Write Byte Recovery Count for IDE-1 */ + case 0x2a: /* DBA Data Byte Cative Count for IDE-2 */ + case 0x2b: /* D0RA Disk 0 Read Active Count for IDE-2 */ + case 0x2c: /* D0WA Disk 0 Write Active Count for IDE-2 */ + case 0x2d: /* D1RA Disk 1 Read Active Count for IDE-2 */ + case 0x2e: /* D1WA Disk 1 Write Active Count for IDE-2 */ + case 0x2f: /* DBR Data Byte Recovery Count for IDE-2 */ + case 0x30: /* D0RR Disk 0 Read Byte Recovery Count for IDE-2 */ + case 0x31: /* D0WR Disk 0 Write Byte Recovery Count for IDE-2 */ + case 0x32: /* D1RR Disk 1 Read Byte Recovery Count for IDE-2 */ + case 0x33: /* D1WR Disk 1 Write Byte Recovery Count for IDE-2 */ + dev->ide_regs[dev->ide_index] = val & 0x1f; + break; + case 0x07: /* Buffer Mode Register 1 */ + dev->ide_regs[dev->ide_index] = val; + break; + case 0x09: /* IDEPE1 IDE Port Enable Register 1 */ + dev->ide_regs[dev->ide_index] = val & 0xc3; + break; + case 0x0a: /* Buffer Mode Register 2 */ + dev->ide_regs[dev->ide_index] = val & 0x4f; + break; + case 0x0b: /* IDE Channel 1 Disk 0 Sector Byte Count Register 1 */ + case 0x0d: /* IDE Channel 1 Disk 1 Sector Byte Count Register 1 */ + case 0x0f: /* IDE Channel 2 Disk 0 Sector Byte Count Register 1 */ + case 0x11: /* IDE Channel 2 Disk 1 Sector Byte Count Register 1 */ + dev->ide_regs[dev->ide_index] = val & 0x03; + break; + case 0x0c: /* IDE Channel 1 Disk 0 Sector Byte Count Register 2 */ + case 0x0e: /* IDE Channel 1 Disk 1 Sector Byte Count Register 2 */ + case 0x10: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */ + case 0x12: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */ + dev->ide_regs[dev->ide_index] = val & 0x1f; + break; + case 0x35: /* IDEPE3 IDE Port Enable Register 3 */ + dev->ide_regs[dev->ide_index] = val; + ali1489_ide_handler(dev); + break; + } + break; } } - static uint8_t ali1489_ide_read(uint16_t addr, void *priv) { - ali1489_t *dev = (ali1489_t *)priv; - uint8_t ret = 0xff; + ali1489_t *dev = (ali1489_t *) priv; + uint8_t ret = 0xff; - switch (addr) - { - case 0xf4: - ret = dev->ide_chip_id; - break; - case 0xfc: - ret = dev->ide_regs[dev->ide_index]; - ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret); - break; + switch (addr) { + case 0xf4: + ret = dev->ide_chip_id; + break; + case 0xfc: + ret = dev->ide_regs[dev->ide_index]; + ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret); + break; } return ret; } - static void ali1489_reset(void *priv) { - ali1489_t *dev = (ali1489_t *)priv; + ali1489_t *dev = (ali1489_t *) priv; pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); @@ -582,21 +564,19 @@ ali1489_reset(void *priv) ali1489_defaults(dev); } - static void ali1489_close(void *priv) { - ali1489_t *dev = (ali1489_t *)priv; + ali1489_t *dev = (ali1489_t *) priv; smram_del(dev->smram); free(dev); } - static void * ali1489_init(const device_t *info) { - ali1489_t *dev = (ali1489_t *)malloc(sizeof(ali1489_t)); + ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t)); memset(dev, 0, sizeof(ali1489_t)); /* M1487/M1489 @@ -619,7 +599,7 @@ ali1489_init(const device_t *info) device_add(&ide_pci_2ch_device); dev->port_92 = device_add(&port_92_pci_device); - dev->smram = smram_add(); + dev->smram = smram_add(); ali1489_defaults(dev); @@ -627,15 +607,15 @@ ali1489_init(const device_t *info) } const device_t ali1489_device = { - .name = "ALi M1489", + .name = "ALi M1489", .internal_name = "ali1489", - .flags = 0, - .local = 0, - .init = ali1489_init, - .close = ali1489_close, - .reset = ali1489_reset, + .flags = 0, + .local = 0, + .init = ali1489_init, + .close = ali1489_close, + .reset = ali1489_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1531.c b/src/chipset/ali1531.c index 350ec146f..bf157953d 100644 --- a/src/chipset/ali1531.c +++ b/src/chipset/ali1531.c @@ -34,15 +34,12 @@ #include <86box/chipset.h> - -typedef struct ali1531_t -{ +typedef struct ali1531_t { uint8_t pci_conf[256]; smram_t *smram; } ali1531_t; - #ifdef ENABLE_ALI1531_LOG int ali1531_do_log = ENABLE_ALI1531_LOG; static void @@ -50,262 +47,263 @@ ali1531_log(const char *fmt, ...) { va_list ap; - if (ali1531_do_log) - { + if (ali1531_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define ali1531_log(fmt, ...) +# define ali1531_log(fmt, ...) #endif - static void ali1531_smram_recalc(uint8_t val, ali1531_t *dev) { smram_disable_all(); if (val & 1) { - switch (val & 0x0c) { - case 0x00: - ali1531_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02); - break; - case 0x04: - ali1531_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); - break; - case 0x08: - ali1531_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02); - break; - } + switch (val & 0x0c) { + case 0x00: + ali1531_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02); + break; + case 0x04: + ali1531_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); + break; + case 0x08: + ali1531_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02); + break; + } } flushmmucache_nopc(); } - static void ali1531_shadow_recalc(int cur_reg, ali1531_t *dev) { - int i, bit, r_reg, w_reg; + int i, bit, r_reg, w_reg; uint32_t base, flags = 0; shadowbios = shadowbios_write = 0; for (i = 0; i < 16; i++) { - base = 0x000c0000 + (i << 14); - bit = i & 7; - r_reg = 0x4c + (i >> 3); - w_reg = 0x4e + (i >> 3); + base = 0x000c0000 + (i << 14); + bit = i & 7; + r_reg = 0x4c + (i >> 3); + w_reg = 0x4e + (i >> 3); - flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); + flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); - if (base >= 0x000e0000) { - if (dev->pci_conf[r_reg] & (1 << bit)) - shadowbios |= 1; - if (dev->pci_conf[w_reg] & (1 << bit)) - shadowbios_write |= 1; - } + if (base >= 0x000e0000) { + if (dev->pci_conf[r_reg] & (1 << bit)) + shadowbios |= 1; + if (dev->pci_conf[w_reg] & (1 << bit)) + shadowbios_write |= 1; + } - ali1531_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, - (dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E'); + ali1531_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, + (dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E'); mem_set_mem_state_both(base, 0x00004000, flags); } flushmmucache_nopc(); } - static void ali1531_write(int func, int addr, uint8_t val, void *priv) { - ali1531_t *dev = (ali1531_t *)priv; + ali1531_t *dev = (ali1531_t *) priv; switch (addr) { - case 0x04: - dev->pci_conf[addr] = val; - break; - case 0x05: - dev->pci_conf[addr] = val & 0x01; - break; + case 0x04: + dev->pci_conf[addr] = val; + break; + case 0x05: + dev->pci_conf[addr] = val & 0x01; + break; - case 0x07: - dev->pci_conf[addr] &= ~(val & 0xf8); - break; + case 0x07: + dev->pci_conf[addr] &= ~(val & 0xf8); + break; - case 0x0d: - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x0d: + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x2c: /* Subsystem Vendor ID */ - case 0x2d: - case 0x2e: - case 0x2f: - if (dev->pci_conf[0x70] & 0x08) - dev->pci_conf[addr] = val; - break; + case 0x2c: /* Subsystem Vendor ID */ + case 0x2d: + case 0x2e: + case 0x2f: + if (dev->pci_conf[0x70] & 0x08) + dev->pci_conf[addr] = val; + break; - case 0x40: - dev->pci_conf[addr] = val & 0xf1; - break; + case 0x40: + dev->pci_conf[addr] = val & 0xf1; + break; - case 0x41: - dev->pci_conf[addr] = (val & 0xd6) | 0x08; - break; + case 0x41: + dev->pci_conf[addr] = (val & 0xd6) | 0x08; + break; - case 0x42: /* L2 Cache */ - dev->pci_conf[addr] = val & 0xf7; - cpu_cache_ext_enabled = !!(val & 1); - cpu_update_waitstates(); - break; + case 0x42: /* L2 Cache */ + dev->pci_conf[addr] = val & 0xf7; + cpu_cache_ext_enabled = !!(val & 1); + cpu_update_waitstates(); + break; - case 0x43: /* L1 Cache */ - dev->pci_conf[addr] = val; - cpu_cache_int_enabled = !!(val & 1); - cpu_update_waitstates(); - break; + case 0x43: /* L1 Cache */ + dev->pci_conf[addr] = val; + cpu_cache_int_enabled = !!(val & 1); + cpu_update_waitstates(); + break; - case 0x44: - dev->pci_conf[addr] = val; - break; - case 0x45: - dev->pci_conf[addr] = val; - break; + case 0x44: + dev->pci_conf[addr] = val; + break; + case 0x45: + dev->pci_conf[addr] = val; + break; - case 0x46: - dev->pci_conf[addr] = val; - break; + case 0x46: + dev->pci_conf[addr] = val; + break; - case 0x47: - dev->pci_conf[addr] = val & 0xfc; + case 0x47: + dev->pci_conf[addr] = val & 0xfc; - if (mem_size > 0xe00000) - mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + if (mem_size > 0xe00000) + mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - if (mem_size > 0xf00000) - mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + if (mem_size > 0xf00000) + mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); - mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); + mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - flushmmucache_nopc(); - break; + flushmmucache_nopc(); + break; - case 0x48: /* SMRAM */ - dev->pci_conf[addr] = val; - ali1531_smram_recalc(val, dev); - break; + case 0x48: /* SMRAM */ + dev->pci_conf[addr] = val; + ali1531_smram_recalc(val, dev); + break; - case 0x49: - dev->pci_conf[addr] = val & 0x73; - break; + case 0x49: + dev->pci_conf[addr] = val & 0x73; + break; - case 0x4a: - dev->pci_conf[addr] = val; - break; + case 0x4a: + dev->pci_conf[addr] = val; + break; - case 0x4c ... 0x4f: /* Shadow RAM */ - dev->pci_conf[addr] = val; - ali1531_shadow_recalc(val, dev); - break; + case 0x4c ... 0x4f: /* Shadow RAM */ + dev->pci_conf[addr] = val; + ali1531_shadow_recalc(val, dev); + break; - case 0x50: case 0x51: case 0x52: case 0x54: - case 0x55: case 0x56: - dev->pci_conf[addr] = val; - break; + case 0x50: + case 0x51: + case 0x52: + case 0x54: + case 0x55: + case 0x56: + dev->pci_conf[addr] = val; + break; - case 0x57: /* H2PO */ - dev->pci_conf[addr] = val & 0x60; - /* Find where the Shut-down Special cycle is initiated. */ - // if (!(val & 0x20)) - // outb(0x92, 0x01); - break; + case 0x57: /* H2PO */ + dev->pci_conf[addr] = val & 0x60; + /* Find where the Shut-down Special cycle is initiated. */ + // if (!(val & 0x20)) + // outb(0x92, 0x01); + break; - case 0x58: - dev->pci_conf[addr] = val & 0x86; - break; + case 0x58: + dev->pci_conf[addr] = val & 0x86; + break; - case 0x59: case 0x5a: - case 0x5c: - dev->pci_conf[addr] = val; - break; + case 0x59: + case 0x5a: + case 0x5c: + dev->pci_conf[addr] = val; + break; - case 0x5b: - dev->pci_conf[addr] = val & 0x4f; - break; + case 0x5b: + dev->pci_conf[addr] = val & 0x4f; + break; - case 0x5d: - dev->pci_conf[addr] = val & 0x53; - break; + case 0x5d: + dev->pci_conf[addr] = val & 0x53; + break; - case 0x5f: - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x5f: + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x60 ... 0x6f: /* DRB's */ - dev->pci_conf[addr] = val; - spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1); - break; + case 0x60 ... 0x6f: /* DRB's */ + dev->pci_conf[addr] = val; + spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1); + break; - case 0x70: case 0x71: - dev->pci_conf[addr] = val; - break; + case 0x70: + case 0x71: + dev->pci_conf[addr] = val; + break; - case 0x72: - dev->pci_conf[addr] = val & 0x0f; - break; + case 0x72: + dev->pci_conf[addr] = val & 0x0f; + break; - case 0x74: - dev->pci_conf[addr] = val & 0x2b; - break; + case 0x74: + dev->pci_conf[addr] = val & 0x2b; + break; - case 0x76: case 0x77: - dev->pci_conf[addr] = val; - break; + case 0x76: + case 0x77: + dev->pci_conf[addr] = val; + break; - case 0x80: - dev->pci_conf[addr] = val & 0x84; - break; + case 0x80: + dev->pci_conf[addr] = val & 0x84; + break; - case 0x81: - dev->pci_conf[addr] = val & 0x81; - break; + case 0x81: + dev->pci_conf[addr] = val & 0x81; + break; - case 0x83: - dev->pci_conf[addr] = val & 0x10; - break; + case 0x83: + dev->pci_conf[addr] = val & 0x10; + break; } } - static uint8_t ali1531_read(int func, int addr, void *priv) { - ali1531_t *dev = (ali1531_t *)priv; - uint8_t ret = 0xff; + ali1531_t *dev = (ali1531_t *) priv; + uint8_t ret = 0xff; ret = dev->pci_conf[addr]; return ret; } - static void ali1531_reset(void *priv) { - ali1531_t *dev = (ali1531_t *)priv; - int i; + ali1531_t *dev = (ali1531_t *) priv; + int i; /* Default Registers */ dev->pci_conf[0x00] = 0xb9; @@ -342,29 +340,27 @@ ali1531_reset(void *priv) ali1531_write(0, 0x48, 0x00, dev); for (i = 0; i < 4; i++) - ali1531_write(0, 0x4c + i, 0x00, dev); + ali1531_write(0, 0x4c + i, 0x00, dev); for (i = 0; i < 16; i += 2) { - ali1531_write(0, 0x60 + i, 0x08, dev); - ali1531_write(0, 0x61 + i, 0x40, dev); + ali1531_write(0, 0x60 + i, 0x08, dev); + ali1531_write(0, 0x61 + i, 0x40, dev); } } - static void ali1531_close(void *priv) { - ali1531_t *dev = (ali1531_t *)priv; + ali1531_t *dev = (ali1531_t *) priv; smram_del(dev->smram); free(dev); } - static void * ali1531_init(const device_t *info) { - ali1531_t *dev = (ali1531_t *)malloc(sizeof(ali1531_t)); + ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t)); memset(dev, 0, sizeof(ali1531_t)); pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev); @@ -377,15 +373,15 @@ ali1531_init(const device_t *info) } const device_t ali1531_device = { - .name = "ALi M1531 CPU-to-PCI Bridge", + .name = "ALi M1531 CPU-to-PCI Bridge", .internal_name = "ali1531", - .flags = DEVICE_PCI, - .local = 0, - .init = ali1531_init, - .close = ali1531_close, - .reset = ali1531_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = ali1531_init, + .close = ali1531_close, + .reset = ali1531_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1541.c b/src/chipset/ali1541.c index 097726106..4882ba717 100644 --- a/src/chipset/ali1541.c +++ b/src/chipset/ali1541.c @@ -31,16 +31,13 @@ #include <86box/chipset.h> +typedef struct ali1541_t { + uint8_t pci_conf[256]; -typedef struct ali1541_t -{ - uint8_t pci_conf[256]; - - smram_t * smram; - void * agp_bridge; + smram_t *smram; + void *agp_bridge; } ali1541_t; - #ifdef ENABLE_ALI1541_LOG int ali1541_do_log = ENABLE_ALI1541_LOG; static void @@ -48,518 +45,519 @@ ali1541_log(const char *fmt, ...) { va_list ap; - if (ali1541_do_log) - { + if (ali1541_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define ali1541_log(fmt, ...) +# define ali1541_log(fmt, ...) #endif - static void ali1541_smram_recalc(uint8_t val, ali1541_t *dev) { smram_disable_all(); if (val & 1) { - switch (val & 0x0c) { - case 0x00: - ali1541_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02); - break; - case 0x04: - ali1541_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); - break; - case 0x08: - ali1541_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2); - smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1); - if (val & 0x10) - mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02); - break; - } + switch (val & 0x0c) { + case 0x00: + ali1541_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02); + break; + case 0x04: + ali1541_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); + break; + case 0x08: + ali1541_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2); + smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1); + if (val & 0x10) + mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02); + break; + } } flushmmucache_nopc(); } - static void ali1541_shadow_recalc(int cur_reg, ali1541_t *dev) { - int i, bit, r_reg, w_reg; + int i, bit, r_reg, w_reg; uint32_t base, flags = 0; shadowbios = shadowbios_write = 0; for (i = 0; i < 16; i++) { - base = 0x000c0000 + (i << 14); - bit = i & 7; - r_reg = 0x56 + (i >> 3); - w_reg = 0x58 + (i >> 3); + base = 0x000c0000 + (i << 14); + bit = i & 7; + r_reg = 0x56 + (i >> 3); + w_reg = 0x58 + (i >> 3); - flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); + flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); - if (base >= 0x000e0000) { - if (dev->pci_conf[r_reg] & (1 << bit)) - shadowbios |= 1; - if (dev->pci_conf[w_reg] & (1 << bit)) - shadowbios_write |= 1; - } + if (base >= 0x000e0000) { + if (dev->pci_conf[r_reg] & (1 << bit)) + shadowbios |= 1; + if (dev->pci_conf[w_reg] & (1 << bit)) + shadowbios_write |= 1; + } - ali1541_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, - (dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E'); + ali1541_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, + (dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E'); mem_set_mem_state_both(base, 0x00004000, flags); } flushmmucache_nopc(); } - static void ali1541_mask_bar(ali1541_t *dev) { uint32_t bar, mask; switch (dev->pci_conf[0xbc] & 0x0f) { - case 0x00: - default: - mask = 0x00000000; - break; - case 0x01: - mask = 0xfff00000; - break; - case 0x02: - mask = 0xffe00000; - break; - case 0x03: - mask = 0xffc00000; - break; - case 0x04: - mask = 0xff800000; - break; - case 0x06: - mask = 0xff000000; - break; - case 0x07: - mask = 0xfe000000; - break; - case 0x08: - mask = 0xfc000000; - break; - case 0x09: - mask = 0xf8000000; - break; - case 0x0a: - mask = 0xf0000000; - break; + case 0x00: + default: + mask = 0x00000000; + break; + case 0x01: + mask = 0xfff00000; + break; + case 0x02: + mask = 0xffe00000; + break; + case 0x03: + mask = 0xffc00000; + break; + case 0x04: + mask = 0xff800000; + break; + case 0x06: + mask = 0xff000000; + break; + case 0x07: + mask = 0xfe000000; + break; + case 0x08: + mask = 0xfc000000; + break; + case 0x09: + mask = 0xf8000000; + break; + case 0x0a: + mask = 0xf0000000; + break; } - bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask; + bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask; dev->pci_conf[0x12] = (bar >> 16) & 0xff; dev->pci_conf[0x13] = (bar >> 24) & 0xff; } - static void ali1541_write(int func, int addr, uint8_t val, void *priv) { - ali1541_t *dev = (ali1541_t *)priv; + ali1541_t *dev = (ali1541_t *) priv; switch (addr) { - case 0x04: - dev->pci_conf[addr] = val; - break; - case 0x05: - dev->pci_conf[addr] = val & 0x01; - break; - - case 0x07: - dev->pci_conf[addr] &= ~(val & 0xf8); - break; - - case 0x0d: - dev->pci_conf[addr] = val & 0xf8; - break; - - case 0x12: - dev->pci_conf[0x12] = (val & 0xc0); - ali1541_mask_bar(dev); - break; - case 0x13: - dev->pci_conf[0x13] = val; - ali1541_mask_bar(dev); - break; - - case 0x2c: /* Subsystem Vendor ID */ - case 0x2d: - case 0x2e: - case 0x2f: - if (dev->pci_conf[0x90] & 0x01) - dev->pci_conf[addr] = val; - break; - - case 0x34: - if (dev->pci_conf[0x90] & 0x02) - dev->pci_conf[addr] = val; - break; - - case 0x40: - dev->pci_conf[addr] = val & 0x7f; - break; - - case 0x41: - dev->pci_conf[addr] = val & 0x7f; - break; - - case 0x42: /* L2 Cache */ - dev->pci_conf[addr] = val; - cpu_cache_ext_enabled = !!(val & 1); - cpu_update_waitstates(); - break; - - case 0x43: /* PLCTL-Pipe Line Control */ - dev->pci_conf[addr] = val & 0xf7; - break; - - case 0x44: - dev->pci_conf[addr] = val; - break; - case 0x45: - dev->pci_conf[addr] = val; - break; - case 0x46: - dev->pci_conf[addr] = val & 0xf0; - break; - case 0x47: - dev->pci_conf[addr] = val; - break; - - case 0x48: - dev->pci_conf[addr] = val; - break; - case 0x49: - dev->pci_conf[addr] = val; - break; - - case 0x4a: - dev->pci_conf[addr] = val & 0xf8; - break; - - case 0x4b: - dev->pci_conf[addr] = val; - break; - - case 0x4c: - dev->pci_conf[addr] = val; - break; - case 0x4d: - dev->pci_conf[addr] = val; - break; - - case 0x4e: - dev->pci_conf[addr] = val; - break; - case 0x4f: - dev->pci_conf[addr] = val; - break; - - case 0x50: - dev->pci_conf[addr] = val & 0x71; - break; - - case 0x51: - dev->pci_conf[addr] = val; - break; - - case 0x52: - dev->pci_conf[addr] = val; - break; - - case 0x53: - dev->pci_conf[addr] = val; - break; - - case 0x54: - dev->pci_conf[addr] = val & 0x3c; - - if (mem_size > 0xe00000) - mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - - if (mem_size > 0xf00000) - mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - - mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); - mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); - - flushmmucache_nopc(); - break; - - case 0x55: /* SMRAM */ - dev->pci_conf[addr] = val & 0x1f; - ali1541_smram_recalc(val, dev); - break; - - case 0x56 ... 0x59: /* Shadow RAM */ - dev->pci_conf[addr] = val; - ali1541_shadow_recalc(val, dev); - break; - - case 0x5a: case 0x5b: - dev->pci_conf[addr] = val; - break; - - case 0x5c: - dev->pci_conf[addr] = val; - break; - - case 0x5d: - dev->pci_conf[addr] = val & 0x17; - break; - - case 0x5e: - dev->pci_conf[addr] = val; - break; - - case 0x5f: - dev->pci_conf[addr] = val & 0xc1; - break; - - case 0x60 ... 0x6f: /* DRB's */ - dev->pci_conf[addr] = val; - spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1); - break; - - case 0x70: - dev->pci_conf[addr] = val; - break; - - case 0x71: - dev->pci_conf[addr] = val; - break; - - case 0x72: - dev->pci_conf[addr] = val & 0xc7; - break; - - case 0x73: - dev->pci_conf[addr] = val & 0x1f; - break; - - case 0x84: case 0x85: - dev->pci_conf[addr] = val; - break; - - case 0x86: - dev->pci_conf[addr] = val & 0x0f; - break; - - case 0x87: /* H2PO */ - dev->pci_conf[addr] = val; - /* Find where the Shut-down Special cycle is initiated. */ - // if (!(val & 0x20)) - // outb(0x92, 0x01); - break; - - case 0x88: - dev->pci_conf[addr] = val; - break; - - case 0x89: - dev->pci_conf[addr] = val; - break; - - case 0x8a: - dev->pci_conf[addr] = val; - break; - - case 0x8b: - dev->pci_conf[addr] = val & 0x3f; - break; - - case 0x8c: - dev->pci_conf[addr] = val; - break; - - case 0x8d: - dev->pci_conf[addr] = val; - break; - - case 0x8e: - dev->pci_conf[addr] = val; - break; - - case 0x8f: - dev->pci_conf[addr] = val; - break; - - case 0x90: - dev->pci_conf[addr] = val; - pci_bridge_set_ctl(dev->agp_bridge, val); - break; - - case 0x91: - dev->pci_conf[addr] = val; - break; - - case 0xb4: - if (dev->pci_conf[0x90] & 0x01) - dev->pci_conf[addr] = val & 0x03; - break; - case 0xb5: - if (dev->pci_conf[0x90] & 0x01) - dev->pci_conf[addr] = val & 0x02; - break; - case 0xb7: - if (dev->pci_conf[0x90] & 0x01) - dev->pci_conf[addr] = val; - break; - - case 0xb8: - dev->pci_conf[addr] = val & 0x03; - break; - case 0xb9: - dev->pci_conf[addr] = val & 0x03; - break; - case 0xbb: - dev->pci_conf[addr] = val; - break; - - case 0xbc: - dev->pci_conf[addr] = val & 0x0f; - ali1541_mask_bar(dev); - break; - case 0xbd: - dev->pci_conf[addr] = val & 0xf0; - break; - case 0xbe: case 0xbf: - dev->pci_conf[addr] = val; - break; - - case 0xc0: - dev->pci_conf[addr] = val & 0x90; - break; - case 0xc1: case 0xc2: - case 0xc3: - dev->pci_conf[addr] = val; - break; - - case 0xc8: case 0xc9: - dev->pci_conf[addr] = val; - break; - - case 0xd1: - dev->pci_conf[addr] = val & 0xf1; - break; - case 0xd2: case 0xd3: - dev->pci_conf[addr] = val; - break; - - case 0xe0: case 0xe1: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val; - break; - case 0xe2: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val & 0x3f; - break; - case 0xe3: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val & 0xfe; - break; - - case 0xe4: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val & 0x03; - break; - case 0xe5: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val; - break; - - case 0xe6: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val & 0xc0; - break; - - case 0xe7: - if (dev->pci_conf[0x90] & 0x20) - dev->pci_conf[addr] = val; - break; - - case 0xe8: case 0xe9: - if (dev->pci_conf[0x90] & 0x04) - dev->pci_conf[addr] = val; - break; - - case 0xea: - dev->pci_conf[addr] = val & 0xcf; - break; - - case 0xeb: - dev->pci_conf[addr] = val & 0xcf; - break; - - case 0xec: - dev->pci_conf[addr] = val & 0x3f; - break; - - case 0xed: - dev->pci_conf[addr] = val; - break; - - case 0xee: - dev->pci_conf[addr] = val & 0x3e; - break; - case 0xef: - dev->pci_conf[addr] = val; - break; - - case 0xf3: - dev->pci_conf[addr] = val & 0x08; - break; - - case 0xf5: - dev->pci_conf[addr] = val; - break; - - case 0xf6: - dev->pci_conf[addr] = val; - break; - - case 0xf7: - dev->pci_conf[addr] = val & 0x43; - break; + case 0x04: + dev->pci_conf[addr] = val; + break; + case 0x05: + dev->pci_conf[addr] = val & 0x01; + break; + + case 0x07: + dev->pci_conf[addr] &= ~(val & 0xf8); + break; + + case 0x0d: + dev->pci_conf[addr] = val & 0xf8; + break; + + case 0x12: + dev->pci_conf[0x12] = (val & 0xc0); + ali1541_mask_bar(dev); + break; + case 0x13: + dev->pci_conf[0x13] = val; + ali1541_mask_bar(dev); + break; + + case 0x2c: /* Subsystem Vendor ID */ + case 0x2d: + case 0x2e: + case 0x2f: + if (dev->pci_conf[0x90] & 0x01) + dev->pci_conf[addr] = val; + break; + + case 0x34: + if (dev->pci_conf[0x90] & 0x02) + dev->pci_conf[addr] = val; + break; + + case 0x40: + dev->pci_conf[addr] = val & 0x7f; + break; + + case 0x41: + dev->pci_conf[addr] = val & 0x7f; + break; + + case 0x42: /* L2 Cache */ + dev->pci_conf[addr] = val; + cpu_cache_ext_enabled = !!(val & 1); + cpu_update_waitstates(); + break; + + case 0x43: /* PLCTL-Pipe Line Control */ + dev->pci_conf[addr] = val & 0xf7; + break; + + case 0x44: + dev->pci_conf[addr] = val; + break; + case 0x45: + dev->pci_conf[addr] = val; + break; + case 0x46: + dev->pci_conf[addr] = val & 0xf0; + break; + case 0x47: + dev->pci_conf[addr] = val; + break; + + case 0x48: + dev->pci_conf[addr] = val; + break; + case 0x49: + dev->pci_conf[addr] = val; + break; + + case 0x4a: + dev->pci_conf[addr] = val & 0xf8; + break; + + case 0x4b: + dev->pci_conf[addr] = val; + break; + + case 0x4c: + dev->pci_conf[addr] = val; + break; + case 0x4d: + dev->pci_conf[addr] = val; + break; + + case 0x4e: + dev->pci_conf[addr] = val; + break; + case 0x4f: + dev->pci_conf[addr] = val; + break; + + case 0x50: + dev->pci_conf[addr] = val & 0x71; + break; + + case 0x51: + dev->pci_conf[addr] = val; + break; + + case 0x52: + dev->pci_conf[addr] = val; + break; + + case 0x53: + dev->pci_conf[addr] = val; + break; + + case 0x54: + dev->pci_conf[addr] = val & 0x3c; + + if (mem_size > 0xe00000) + mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + + if (mem_size > 0xf00000) + mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + + mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); + mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + + flushmmucache_nopc(); + break; + + case 0x55: /* SMRAM */ + dev->pci_conf[addr] = val & 0x1f; + ali1541_smram_recalc(val, dev); + break; + + case 0x56 ... 0x59: /* Shadow RAM */ + dev->pci_conf[addr] = val; + ali1541_shadow_recalc(val, dev); + break; + + case 0x5a: + case 0x5b: + dev->pci_conf[addr] = val; + break; + + case 0x5c: + dev->pci_conf[addr] = val; + break; + + case 0x5d: + dev->pci_conf[addr] = val & 0x17; + break; + + case 0x5e: + dev->pci_conf[addr] = val; + break; + + case 0x5f: + dev->pci_conf[addr] = val & 0xc1; + break; + + case 0x60 ... 0x6f: /* DRB's */ + dev->pci_conf[addr] = val; + spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1); + break; + + case 0x70: + dev->pci_conf[addr] = val; + break; + + case 0x71: + dev->pci_conf[addr] = val; + break; + + case 0x72: + dev->pci_conf[addr] = val & 0xc7; + break; + + case 0x73: + dev->pci_conf[addr] = val & 0x1f; + break; + + case 0x84: + case 0x85: + dev->pci_conf[addr] = val; + break; + + case 0x86: + dev->pci_conf[addr] = val & 0x0f; + break; + + case 0x87: /* H2PO */ + dev->pci_conf[addr] = val; + /* Find where the Shut-down Special cycle is initiated. */ + // if (!(val & 0x20)) + // outb(0x92, 0x01); + break; + + case 0x88: + dev->pci_conf[addr] = val; + break; + + case 0x89: + dev->pci_conf[addr] = val; + break; + + case 0x8a: + dev->pci_conf[addr] = val; + break; + + case 0x8b: + dev->pci_conf[addr] = val & 0x3f; + break; + + case 0x8c: + dev->pci_conf[addr] = val; + break; + + case 0x8d: + dev->pci_conf[addr] = val; + break; + + case 0x8e: + dev->pci_conf[addr] = val; + break; + + case 0x8f: + dev->pci_conf[addr] = val; + break; + + case 0x90: + dev->pci_conf[addr] = val; + pci_bridge_set_ctl(dev->agp_bridge, val); + break; + + case 0x91: + dev->pci_conf[addr] = val; + break; + + case 0xb4: + if (dev->pci_conf[0x90] & 0x01) + dev->pci_conf[addr] = val & 0x03; + break; + case 0xb5: + if (dev->pci_conf[0x90] & 0x01) + dev->pci_conf[addr] = val & 0x02; + break; + case 0xb7: + if (dev->pci_conf[0x90] & 0x01) + dev->pci_conf[addr] = val; + break; + + case 0xb8: + dev->pci_conf[addr] = val & 0x03; + break; + case 0xb9: + dev->pci_conf[addr] = val & 0x03; + break; + case 0xbb: + dev->pci_conf[addr] = val; + break; + + case 0xbc: + dev->pci_conf[addr] = val & 0x0f; + ali1541_mask_bar(dev); + break; + case 0xbd: + dev->pci_conf[addr] = val & 0xf0; + break; + case 0xbe: + case 0xbf: + dev->pci_conf[addr] = val; + break; + + case 0xc0: + dev->pci_conf[addr] = val & 0x90; + break; + case 0xc1: + case 0xc2: + case 0xc3: + dev->pci_conf[addr] = val; + break; + + case 0xc8: + case 0xc9: + dev->pci_conf[addr] = val; + break; + + case 0xd1: + dev->pci_conf[addr] = val & 0xf1; + break; + case 0xd2: + case 0xd3: + dev->pci_conf[addr] = val; + break; + + case 0xe0: + case 0xe1: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val; + break; + case 0xe2: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val & 0x3f; + break; + case 0xe3: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val & 0xfe; + break; + + case 0xe4: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val & 0x03; + break; + case 0xe5: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val; + break; + + case 0xe6: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val & 0xc0; + break; + + case 0xe7: + if (dev->pci_conf[0x90] & 0x20) + dev->pci_conf[addr] = val; + break; + + case 0xe8: + case 0xe9: + if (dev->pci_conf[0x90] & 0x04) + dev->pci_conf[addr] = val; + break; + + case 0xea: + dev->pci_conf[addr] = val & 0xcf; + break; + + case 0xeb: + dev->pci_conf[addr] = val & 0xcf; + break; + + case 0xec: + dev->pci_conf[addr] = val & 0x3f; + break; + + case 0xed: + dev->pci_conf[addr] = val; + break; + + case 0xee: + dev->pci_conf[addr] = val & 0x3e; + break; + case 0xef: + dev->pci_conf[addr] = val; + break; + + case 0xf3: + dev->pci_conf[addr] = val & 0x08; + break; + + case 0xf5: + dev->pci_conf[addr] = val; + break; + + case 0xf6: + dev->pci_conf[addr] = val; + break; + + case 0xf7: + dev->pci_conf[addr] = val & 0x43; + break; } } - static uint8_t ali1541_read(int func, int addr, void *priv) { - ali1541_t *dev = (ali1541_t *)priv; - uint8_t ret = 0xff; + ali1541_t *dev = (ali1541_t *) priv; + uint8_t ret = 0xff; ret = dev->pci_conf[addr]; return ret; } - static void ali1541_reset(void *priv) { - ali1541_t *dev = (ali1541_t *)priv; - int i; + ali1541_t *dev = (ali1541_t *) priv; + int i; /* Default Registers */ dev->pci_conf[0x00] = 0xb9; @@ -603,31 +601,29 @@ ali1541_reset(void *priv) ali1541_write(0, 0x55, 0x00, dev); for (i = 0; i < 4; i++) - ali1541_write(0, 0x56 + i, 0x00, dev); + ali1541_write(0, 0x56 + i, 0x00, dev); ali1541_write(0, 0x60 + i, 0x07, dev); ali1541_write(0, 0x61 + i, 0x40, dev); for (i = 0; i < 14; i += 2) { - ali1541_write(0, 0x62 + i, 0x00, dev); - ali1541_write(0, 0x63 + i, 0x00, dev); + ali1541_write(0, 0x62 + i, 0x00, dev); + ali1541_write(0, 0x63 + i, 0x00, dev); } } - static void ali1541_close(void *priv) { - ali1541_t *dev = (ali1541_t *)priv; + ali1541_t *dev = (ali1541_t *) priv; smram_del(dev->smram); free(dev); } - static void * ali1541_init(const device_t *info) { - ali1541_t *dev = (ali1541_t *)malloc(sizeof(ali1541_t)); + ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t)); memset(dev, 0, sizeof(ali1541_t)); pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev); @@ -642,15 +638,15 @@ ali1541_init(const device_t *info) } const device_t ali1541_device = { - .name = "ALi M1541 CPU-to-PCI Bridge", + .name = "ALi M1541 CPU-to-PCI Bridge", .internal_name = "ali1541", - .flags = DEVICE_PCI, - .local = 0, - .init = ali1541_init, - .close = ali1541_close, - .reset = ali1541_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = ali1541_init, + .close = ali1541_close, + .reset = ali1541_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1543.c b/src/chipset/ali1543.c index bbbf7d705..04f3f70c8 100644 --- a/src/chipset/ali1543.c +++ b/src/chipset/ali1543.c @@ -46,22 +46,20 @@ #include <86box/chipset.h> +typedef struct ali1543_t { + uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256], + pci_slot, ide_slot, usb_slot, pmu_slot, usb_dev_enable, ide_dev_enable, + pmu_dev_enable, type; + int offset; -typedef struct ali1543_t -{ - uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256], - pci_slot, ide_slot, usb_slot, pmu_slot, usb_dev_enable, ide_dev_enable, - pmu_dev_enable, type; - int offset; - - apm_t * apm; - acpi_t * acpi; - ddma_t * ddma; - nvr_t * nvr; - port_92_t * port_92; - sff8038i_t * ide_controller[2]; - smbus_ali7101_t * smbus; - usb_t * usb; + apm_t *apm; + acpi_t *acpi; + ddma_t *ddma; + nvr_t *nvr; + port_92_t *port_92; + sff8038i_t *ide_controller[2]; + smbus_ali7101_t *smbus; + usb_t *usb; } ali1543_t; @@ -75,9 +73,8 @@ typedef struct ali1543_t - Code quality is abysmal and needs lot's of cleanup. */ -int ali1533_irq_routing[16] = { PCI_IRQ_DISABLED, 9, 3, 10, 4, 5, 7, 6, - 1, 11, PCI_IRQ_DISABLED, 12, PCI_IRQ_DISABLED, 14, PCI_IRQ_DISABLED, 15 }; - +int ali1533_irq_routing[16] = { PCI_IRQ_DISABLED, 9, 3, 10, 4, 5, 7, 6, + 1, 11, PCI_IRQ_DISABLED, 12, PCI_IRQ_DISABLED, 14, PCI_IRQ_DISABLED, 15 }; #ifdef ENABLE_ALI1543_LOG int ali1543_do_log = ENABLE_ALI1543_LOG; @@ -86,380 +83,384 @@ ali1543_log(const char *fmt, ...) { va_list ap; - if (ali1543_do_log) - { + if (ali1543_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define ali1543_log(fmt, ...) +# define ali1543_log(fmt, ...) #endif - static void ali1533_ddma_handler(ali1543_t *dev) { /* TODO: Find any documentation that actually explains the ALi southbridge DDMA mapping. */ } +static void ali5229_ide_handler(ali1543_t *dev); +static void ali5229_ide_irq_handler(ali1543_t *dev); -static void ali5229_ide_handler(ali1543_t *dev); -static void ali5229_ide_irq_handler(ali1543_t *dev); - -static void ali5229_write(int func, int addr, uint8_t val, void *priv); - -static void ali7101_write(int func, int addr, uint8_t val, void *priv); -static uint8_t ali7101_read(int func, int addr, void *priv); +static void ali5229_write(int func, int addr, uint8_t val, void *priv); +static void ali7101_write(int func, int addr, uint8_t val, void *priv); +static uint8_t ali7101_read(int func, int addr, void *priv); static void ali1533_write(int func, int addr, uint8_t val, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; - int irq; + ali1543_t *dev = (ali1543_t *) priv; + int irq; ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val); if (func > 0) - return; + return; switch (addr) { - case 0x04: /* Command Register */ - if (dev->type == 1) { - if (dev->pci_conf[0x5f] & 0x08) - dev->pci_conf[0x04] = val & 0x0f; - else - dev->pci_conf[0x04] = val; - } else { - if (!(dev->pci_conf[0x5f] & 0x08)) - dev->pci_conf[0x04] = val; - } - break; - case 0x05: /* Command Register */ - if (!(dev->pci_conf[0x5f] & 0x08)) - dev->pci_conf[0x04] = val & 0x03; - break; + case 0x04: /* Command Register */ + if (dev->type == 1) { + if (dev->pci_conf[0x5f] & 0x08) + dev->pci_conf[0x04] = val & 0x0f; + else + dev->pci_conf[0x04] = val; + } else { + if (!(dev->pci_conf[0x5f] & 0x08)) + dev->pci_conf[0x04] = val; + } + break; + case 0x05: /* Command Register */ + if (!(dev->pci_conf[0x5f] & 0x08)) + dev->pci_conf[0x04] = val & 0x03; + break; - case 0x07: /* Status Byte */ - dev->pci_conf[addr] &= ~(val & 0x30); - break; + case 0x07: /* Status Byte */ + dev->pci_conf[addr] &= ~(val & 0x30); + break; - case 0x2c: /* Subsystem Vendor ID */ - case 0x2d: - case 0x2e: - case 0x2f: - if (!(dev->pci_conf[0x74] & 0x40)) - dev->pci_conf[addr] = val; - break; + case 0x2c: /* Subsystem Vendor ID */ + case 0x2d: + case 0x2e: + case 0x2f: + if (!(dev->pci_conf[0x74] & 0x40)) + dev->pci_conf[addr] = val; + break; - case 0x40: - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x40: + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x41: - /* TODO: Bit 7 selects keyboard controller type: - 0 = AT, 1 = PS/2 */ - keyboard_at_set_mouse_scan((val & 0x40) ? 1 : 0); - dev->pci_conf[addr] = val & 0xbf; - break; + case 0x41: + /* TODO: Bit 7 selects keyboard controller type: + 0 = AT, 1 = PS/2 */ + keyboard_at_set_mouse_scan((val & 0x40) ? 1 : 0); + dev->pci_conf[addr] = val & 0xbf; + break; - case 0x42: /* ISA Bus Speed */ - dev->pci_conf[addr] = val & 0xcf; - switch (val & 7) { - case 0: - cpu_set_isa_speed(7159091); - break; - case 1: case 2: case 3: case 4: - case 5: case 6: - cpu_set_isa_pci_div((val & 7) + 1); - break; - } - break; + case 0x42: /* ISA Bus Speed */ + dev->pci_conf[addr] = val & 0xcf; + switch (val & 7) { + case 0: + cpu_set_isa_speed(7159091); + break; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + cpu_set_isa_pci_div((val & 7) + 1); + break; + } + break; - case 0x43: - dev->pci_conf[addr] = val; - if (val & 0x80) - port_92_add(dev->port_92); - else - port_92_remove(dev->port_92); - break; + case 0x43: + dev->pci_conf[addr] = val; + if (val & 0x80) + port_92_add(dev->port_92); + else + port_92_remove(dev->port_92); + break; - /* We're going to cheat a little bit here and use MIRQ's as a substitute for the ALi's INTAJ's, - as they work pretty much the same - specifically, we're going to use MIRQ2 and MIRQ3 for them, - as MIRQ0 and MIRQ1 map to the ALi's MBIRQ0 and MBIRQ1. */ - case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */ - dev->pci_conf[addr] = val & 0xdf; - soft_reset_pci = !!(val & 0x80); - sff_set_irq_level(dev->ide_controller[0], 0, !(val & 0x10)); - sff_set_irq_level(dev->ide_controller[1], 0, !(val & 0x10)); - ali1543_log("INTAJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); - pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[val & 0x0f]); - pci_set_mirq_routing(PCI_MIRQ2, ali1533_irq_routing[val & 0x0f]); - break; + /* We're going to cheat a little bit here and use MIRQ's as a substitute for the ALi's INTAJ's, + as they work pretty much the same - specifically, we're going to use MIRQ2 and MIRQ3 for them, + as MIRQ0 and MIRQ1 map to the ALi's MBIRQ0 and MBIRQ1. */ + case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */ + dev->pci_conf[addr] = val & 0xdf; + soft_reset_pci = !!(val & 0x80); + sff_set_irq_level(dev->ide_controller[0], 0, !(val & 0x10)); + sff_set_irq_level(dev->ide_controller[1], 0, !(val & 0x10)); + ali1543_log("INTAJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); + pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[val & 0x0f]); + pci_set_mirq_routing(PCI_MIRQ2, ali1533_irq_routing[val & 0x0f]); + break; - /* TODO: Implement a ROMCS# assertion bitmask for I/O ports. */ - case 0x45: /* DDMA Enable */ - dev->pci_conf[addr] = val & 0xcb; - ali1533_ddma_handler(dev); - break; + /* TODO: Implement a ROMCS# assertion bitmask for I/O ports. */ + case 0x45: /* DDMA Enable */ + dev->pci_conf[addr] = val & 0xcb; + ali1533_ddma_handler(dev); + break; - /* TODO: For 0x47, we need a way to obtain the memory state for an address - and toggle ROMCS#. */ - case 0x47: /* BIOS chip select control */ - dev->pci_conf[addr] = val; - break; + /* TODO: For 0x47, we need a way to obtain the memory state for an address + and toggle ROMCS#. */ + case 0x47: /* BIOS chip select control */ + dev->pci_conf[addr] = val; + break; - /* PCI IRQ Routing */ - case 0x48: case 0x49: case 0x4a: case 0x4b: - dev->pci_conf[addr] = val; + /* PCI IRQ Routing */ + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + dev->pci_conf[addr] = val; - pci_set_irq_routing(((addr & 0x03) << 1) + 2, ali1533_irq_routing[(val >> 4) & 0x0f]); - pci_set_irq_routing(((addr & 0x03) << 1) + 1, ali1533_irq_routing[val & 0x0f]); - break; + pci_set_irq_routing(((addr & 0x03) << 1) + 2, ali1533_irq_routing[(val >> 4) & 0x0f]); + pci_set_irq_routing(((addr & 0x03) << 1) + 1, ali1533_irq_routing[val & 0x0f]); + break; - case 0x4c: /* PCI INT to ISA Level to Edge transfer */ - dev->pci_conf[addr] = val; + case 0x4c: /* PCI INT to ISA Level to Edge transfer */ + dev->pci_conf[addr] = val; - for (irq = 1; irq < 9; irq++) - pci_set_irq_level(irq, !(val & (1 << (irq - 1)))); - break; + for (irq = 1; irq < 9; irq++) + pci_set_irq_level(irq, !(val & (1 << (irq - 1)))); + break; - case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */ - if (dev->type == 0) { - dev->pci_conf[addr] = val; + case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */ + if (dev->type == 0) { + dev->pci_conf[addr] = val; - ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]); - // pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]); - // pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); - } - break; + ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]); + // pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]); + // pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); + } + break; - /* I/O cycle posted-write first port definition */ - case 0x50: - dev->pci_conf[addr] = val; - break; - case 0x51: - dev->pci_conf[addr] = val & 0x8f; - break; + /* I/O cycle posted-write first port definition */ + case 0x50: + dev->pci_conf[addr] = val; + break; + case 0x51: + dev->pci_conf[addr] = val & 0x8f; + break; - /* I/O cycle posted-write second port definition */ - case 0x52: - dev->pci_conf[addr] = val; - break; - case 0x53: - if (dev->type == 1) - dev->pci_conf[addr] = val; - else - dev->pci_conf[addr] = val & 0xcf; - /* This actually enables/disables the USB *device* rather than the interface itself. */ - dev->usb_dev_enable = !(val & 0x40); - break; + /* I/O cycle posted-write second port definition */ + case 0x52: + dev->pci_conf[addr] = val; + break; + case 0x53: + if (dev->type == 1) + dev->pci_conf[addr] = val; + else + dev->pci_conf[addr] = val & 0xcf; + /* This actually enables/disables the USB *device* rather than the interface itself. */ + dev->usb_dev_enable = !(val & 0x40); + break; - /* Hardware setting status bits, read-only (register 0x54) */ + /* Hardware setting status bits, read-only (register 0x54) */ - /* Programmable chip select (pin PCSJ) address define */ - case 0x55: case 0x56: - dev->pci_conf[addr] = val; - break; - case 0x57: - if (dev->type == 1) - dev->pci_conf[addr] = val & 0xf0; - else - dev->pci_conf[addr] = val & 0xe0; - break; + /* Programmable chip select (pin PCSJ) address define */ + case 0x55: + case 0x56: + dev->pci_conf[addr] = val; + break; + case 0x57: + if (dev->type == 1) + dev->pci_conf[addr] = val & 0xf0; + else + dev->pci_conf[addr] = val & 0xe0; + break; - /* IDE interface control */ - case 0x58: - dev->pci_conf[addr] = val & 0x7f; - ali1543_log("PCI58: %02X\n", val); - dev->ide_dev_enable = !!(val & 0x40); - switch (val & 0x30) { - case 0x00: - dev->ide_slot = 0x10; /* A27 = slot 16 */ - break; - case 0x10: - dev->ide_slot = 0x0f; /* A26 = slot 15 */ - break; - case 0x20: - dev->ide_slot = 0x0e; /* A25 = slot 14 */ - break; - case 0x30: - dev->ide_slot = 0x0d; /* A24 = slot 13 */ - break; - } - pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_IDE, ((int) dev->ide_slot) + dev->offset); - ali1543_log("IDE slot = %02X (A%0i)\n", ((int) dev->ide_slot) + dev->offset, dev->ide_slot + 11); - ali5229_ide_irq_handler(dev); - break; + /* IDE interface control */ + case 0x58: + dev->pci_conf[addr] = val & 0x7f; + ali1543_log("PCI58: %02X\n", val); + dev->ide_dev_enable = !!(val & 0x40); + switch (val & 0x30) { + case 0x00: + dev->ide_slot = 0x10; /* A27 = slot 16 */ + break; + case 0x10: + dev->ide_slot = 0x0f; /* A26 = slot 15 */ + break; + case 0x20: + dev->ide_slot = 0x0e; /* A25 = slot 14 */ + break; + case 0x30: + dev->ide_slot = 0x0d; /* A24 = slot 13 */ + break; + } + pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_IDE, ((int) dev->ide_slot) + dev->offset); + ali1543_log("IDE slot = %02X (A%0i)\n", ((int) dev->ide_slot) + dev->offset, dev->ide_slot + 11); + ali5229_ide_irq_handler(dev); + break; - /* General Purpose input multiplexed pin(GPI) select */ - case 0x59: - dev->pci_conf[addr] = val & 0x0e; - break; + /* General Purpose input multiplexed pin(GPI) select */ + case 0x59: + dev->pci_conf[addr] = val & 0x0e; + break; - /* General Purpose output multiplexed pin(GPO) select low */ - case 0x5a: - dev->pci_conf[addr] = val & 0x0f; - break; - /* General Purpose output multiplexed pin(GPO) select high */ - case 0x5b: - dev->pci_conf[addr] = val & 0x02; - break; + /* General Purpose output multiplexed pin(GPO) select low */ + case 0x5a: + dev->pci_conf[addr] = val & 0x0f; + break; + /* General Purpose output multiplexed pin(GPO) select high */ + case 0x5b: + dev->pci_conf[addr] = val & 0x02; + break; - case 0x5c: - dev->pci_conf[addr] = val & 0x7f; - break; - case 0x5d: - dev->pci_conf[addr] = val & 0x02; - break; + case 0x5c: + dev->pci_conf[addr] = val & 0x7f; + break; + case 0x5d: + dev->pci_conf[addr] = val & 0x02; + break; - case 0x5e: - if (dev->type == 1) - dev->pci_conf[addr] = val & 0xe1; - else - dev->pci_conf[addr] = val & 0xe0; - break; + case 0x5e: + if (dev->type == 1) + dev->pci_conf[addr] = val & 0xe1; + else + dev->pci_conf[addr] = val & 0xe0; + break; - case 0x5f: - dev->pci_conf[addr] = val; - dev->pmu_dev_enable = !(val & 0x04); - break; + case 0x5f: + dev->pci_conf[addr] = val; + dev->pmu_dev_enable = !(val & 0x04); + break; - case 0x6c: /* Deleted - no idea what it used to do */ - dev->pci_conf[addr] = val; - break; + case 0x6c: /* Deleted - no idea what it used to do */ + dev->pci_conf[addr] = val; + break; - case 0x6d: - dev->pci_conf[addr] = val & 0xbf; - break; + case 0x6d: + dev->pci_conf[addr] = val & 0xbf; + break; - case 0x6e: case 0x70: - dev->pci_conf[addr] = val; - break; + case 0x6e: + case 0x70: + dev->pci_conf[addr] = val; + break; - case 0x71: - dev->pci_conf[addr] = val & 0xef; - break; + case 0x71: + dev->pci_conf[addr] = val & 0xef; + break; - case 0x72: - dev->pci_conf[addr] = val & 0xef; - switch (val & 0x0c) { - case 0x00: - dev->pmu_slot = 0x11; /* A28 = slot 17 */ - break; - case 0x04: - dev->pmu_slot = 0x12; /* A29 = slot 18 */ - break; - case 0x08: - dev->pmu_slot = 0x03; /* A14 = slot 03 */ - break; - case 0x0c: - dev->pmu_slot = 0x04; /* A15 = slot 04 */ - break; - } - pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_PMU, ((int) dev->pmu_slot) + dev->offset); - ali1543_log("PMU slot = %02X (A%0i)\n", ((int) dev->pmu_slot) + dev->offset, dev->pmu_slot + 11); - switch (val & 0x03) { - case 0x00: - dev->usb_slot = 0x14; /* A31 = slot 20 */ - break; - case 0x01: - dev->usb_slot = 0x13; /* A30 = slot 19 */ - break; - case 0x02: - dev->usb_slot = 0x02; /* A13 = slot 02 */ - break; - case 0x03: - dev->usb_slot = 0x01; /* A12 = slot 01 */ - break; - } - pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_USB, ((int) dev->usb_slot) + dev->offset); - ali1543_log("USB slot = %02X (A%0i)\n", ((int) dev->usb_slot) + dev->offset, dev->usb_slot + 11); - break; + case 0x72: + dev->pci_conf[addr] = val & 0xef; + switch (val & 0x0c) { + case 0x00: + dev->pmu_slot = 0x11; /* A28 = slot 17 */ + break; + case 0x04: + dev->pmu_slot = 0x12; /* A29 = slot 18 */ + break; + case 0x08: + dev->pmu_slot = 0x03; /* A14 = slot 03 */ + break; + case 0x0c: + dev->pmu_slot = 0x04; /* A15 = slot 04 */ + break; + } + pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_PMU, ((int) dev->pmu_slot) + dev->offset); + ali1543_log("PMU slot = %02X (A%0i)\n", ((int) dev->pmu_slot) + dev->offset, dev->pmu_slot + 11); + switch (val & 0x03) { + case 0x00: + dev->usb_slot = 0x14; /* A31 = slot 20 */ + break; + case 0x01: + dev->usb_slot = 0x13; /* A30 = slot 19 */ + break; + case 0x02: + dev->usb_slot = 0x02; /* A13 = slot 02 */ + break; + case 0x03: + dev->usb_slot = 0x01; /* A12 = slot 01 */ + break; + } + pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_USB, ((int) dev->usb_slot) + dev->offset); + ali1543_log("USB slot = %02X (A%0i)\n", ((int) dev->usb_slot) + dev->offset, dev->usb_slot + 11); + break; - case 0x73: /* DDMA Base Address */ - dev->pci_conf[addr] = val; - ali1533_ddma_handler(dev); - break; + case 0x73: /* DDMA Base Address */ + dev->pci_conf[addr] = val; + ali1533_ddma_handler(dev); + break; - case 0x74: /* USB IRQ Routing - we cheat and use MIRQ4 */ - dev->pci_conf[addr] = val & 0xdf; - /* TODO: MIRQ level/edge control - if bit 4 = 1, it's level */ - pci_set_mirq_routing(PCI_MIRQ4, ali1533_irq_routing[val & 0x0f]); - break; + case 0x74: /* USB IRQ Routing - we cheat and use MIRQ4 */ + dev->pci_conf[addr] = val & 0xdf; + /* TODO: MIRQ level/edge control - if bit 4 = 1, it's level */ + pci_set_mirq_routing(PCI_MIRQ4, ali1533_irq_routing[val & 0x0f]); + break; - case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */ - dev->pci_conf[addr] = val & 0x1f; - sff_set_irq_level(dev->ide_controller[0], 1, !(val & 0x10)); - sff_set_irq_level(dev->ide_controller[1], 1, !(val & 0x10)); - ali1543_log("INTBJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); - pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); - pci_set_mirq_routing(PCI_MIRQ3, ali1533_irq_routing[val & 0x0f]); - break; + case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */ + dev->pci_conf[addr] = val & 0x1f; + sff_set_irq_level(dev->ide_controller[0], 1, !(val & 0x10)); + sff_set_irq_level(dev->ide_controller[1], 1, !(val & 0x10)); + ali1543_log("INTBJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); + pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); + pci_set_mirq_routing(PCI_MIRQ3, ali1533_irq_routing[val & 0x0f]); + break; - case 0x76: /* PMU IRQ Routing - we cheat and use MIRQ5 */ - if (dev->type == 1) - dev->pci_conf[addr] = val & 0x9f; - else - dev->pci_conf[addr] = val & 0x1f; - acpi_set_mirq_is_level(dev->acpi, !!(val & 0x10)); - if ((dev->type == 1) && (val & 0x80)) - pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED); - else - pci_set_mirq_routing(PCI_MIRQ5, ali1533_irq_routing[val & 0x0f]); - /* TODO: Tell ACPI to use MIRQ5 */ - break; + case 0x76: /* PMU IRQ Routing - we cheat and use MIRQ5 */ + if (dev->type == 1) + dev->pci_conf[addr] = val & 0x9f; + else + dev->pci_conf[addr] = val & 0x1f; + acpi_set_mirq_is_level(dev->acpi, !!(val & 0x10)); + if ((dev->type == 1) && (val & 0x80)) + pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED); + else + pci_set_mirq_routing(PCI_MIRQ5, ali1533_irq_routing[val & 0x0f]); + /* TODO: Tell ACPI to use MIRQ5 */ + break; - case 0x77: /* SMBus IRQ Routing - we cheat and use MIRQ6 */ - dev->pci_conf[addr] = val & 0x1f; - pci_set_mirq_routing(PCI_MIRQ6, ali1533_irq_routing[val & 0x0f]); - break; + case 0x77: /* SMBus IRQ Routing - we cheat and use MIRQ6 */ + dev->pci_conf[addr] = val & 0x1f; + pci_set_mirq_routing(PCI_MIRQ6, ali1533_irq_routing[val & 0x0f]); + break; - case 0x78: - if (dev->type == 1) { - ali1543_log("PCI78 = %02X\n", val); - dev->pci_conf[addr] = val & 0x33; - } - break; + case 0x78: + if (dev->type == 1) { + ali1543_log("PCI78 = %02X\n", val); + dev->pci_conf[addr] = val & 0x33; + } + break; - case 0x7c ... 0xff: - if ((dev->type == 1) && !dev->pmu_dev_enable) { - dev->pmu_dev_enable = 1; - ali7101_write(func, addr, val, priv); - dev->pmu_dev_enable = 0; - } - break; + case 0x7c ... 0xff: + if ((dev->type == 1) && !dev->pmu_dev_enable) { + dev->pmu_dev_enable = 1; + ali7101_write(func, addr, val, priv); + dev->pmu_dev_enable = 0; + } + break; } } static uint8_t ali1533_read(int func, int addr, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; - uint8_t ret = 0xff; + ali1543_t *dev = (ali1543_t *) priv; + uint8_t ret = 0xff; if (func == 0) { - if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4))) - ret = 0x00; - else { - ret = dev->pci_conf[addr]; - if (addr == 0x41) - ret |= (keyboard_at_get_mouse_scan() << 2); - else if (addr == 0x58) - ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00); - else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) { - dev->pmu_dev_enable = 1; - ret = ali7101_read(func, addr, priv); - dev->pmu_dev_enable = 0; - } - } + if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4))) + ret = 0x00; + else { + ret = dev->pci_conf[addr]; + if (addr == 0x41) + ret |= (keyboard_at_get_mouse_scan() << 2); + else if (addr == 0x58) + ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00); + else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) { + dev->pmu_dev_enable = 1; + ret = ali7101_read(func, addr, priv); + dev->pmu_dev_enable = 0; + } + } } return ret; } - static void ali5229_ide_irq_handler(ali1543_t *dev) { @@ -467,85 +468,84 @@ ali5229_ide_irq_handler(ali1543_t *dev) int bit = 0; if (dev->ide_conf[0x52] & 0x10) { - ctl ^= 1; - ch ^= 1; - bit ^= 5; + ctl ^= 1; + ch ^= 1; + bit ^= 5; } if (dev->ide_conf[0x09] & (1 ^ bit)) { - /* Primary IDE is native. */ - ali1543_log("Primary IDE IRQ mode: Native, Native\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); + /* Primary IDE is native. */ + ali1543_log("Primary IDE IRQ mode: Native, Native\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); } else { - /* Primary IDE is legacy. */ - switch (dev->pci_conf[0x58] & 0x03) { - case 0x00: - /* SIRQI, SIRQII */ - ali1543_log("Primary IDE IRQ mode: SIRQI, SIRQII\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); - break; - case 0x01: - /* IRQ14, IRQ15 */ - ali1543_log("Primary IDE IRQ mode: IRQ14, IRQ15\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); - break; - case 0x02: - /* IRQ14, SIRQII */ - ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQII\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); - break; - case 0x03: - /* IRQ14, SIRQI */ - ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQI\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); - break; - } + /* Primary IDE is legacy. */ + switch (dev->pci_conf[0x58] & 0x03) { + case 0x00: + /* SIRQI, SIRQII */ + ali1543_log("Primary IDE IRQ mode: SIRQI, SIRQII\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); + break; + case 0x01: + /* IRQ14, IRQ15 */ + ali1543_log("Primary IDE IRQ mode: IRQ14, IRQ15\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); + break; + case 0x02: + /* IRQ14, SIRQII */ + ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQII\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); + break; + case 0x03: + /* IRQ14, SIRQI */ + ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQI\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); + break; + } } ctl ^= 1; if (dev->ide_conf[0x09] & (4 ^ bit)) { - /* Secondary IDE is native. */ - ali1543_log("Secondary IDE IRQ mode: Native, Native\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); + /* Secondary IDE is native. */ + ali1543_log("Secondary IDE IRQ mode: Native, Native\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); } else { - /* Secondary IDE is legacy. */ - switch (dev->pci_conf[0x58] & 0x03) { - case 0x00: - /* SIRQI, SIRQII */ - ali1543_log("Secondary IDE IRQ mode: SIRQI, SIRQII\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); - break; - case 0x01: - /* IRQ14, IRQ15 */ - ali1543_log("Secondary IDE IRQ mode: IRQ14, IRQ15\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); - break; - case 0x02: - /* IRQ14, SIRQII */ - ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQII\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); - break; - case 0x03: - /* IRQ14, SIRQI */ - ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQI\n"); - sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); - sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); - break; - } + /* Secondary IDE is legacy. */ + switch (dev->pci_conf[0x58] & 0x03) { + case 0x00: + /* SIRQI, SIRQII */ + ali1543_log("Secondary IDE IRQ mode: SIRQI, SIRQII\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); + break; + case 0x01: + /* IRQ14, IRQ15 */ + ali1543_log("Secondary IDE IRQ mode: IRQ14, IRQ15\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); + break; + case 0x02: + /* IRQ14, SIRQII */ + ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQII\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); + break; + case 0x03: + /* IRQ14, SIRQI */ + ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQI\n"); + sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); + sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); + break; + } } } - static void ali5229_ide_handler(ali1543_t *dev) { @@ -565,24 +565,24 @@ ali5229_ide_handler(ali1543_t *dev) /* Primary Channel Programming */ if (dev->ide_conf[0x52] & 0x10) { - current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_sec_addr : native_base_sec_addr; - current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_sec_addr : native_side_sec_addr; + current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_sec_addr : native_base_sec_addr; + current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_sec_addr : native_side_sec_addr; } else { - current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_pri_addr : native_base_pri_addr; - current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_pri_addr : native_side_pri_addr; + current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_pri_addr : native_base_pri_addr; + current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_pri_addr : native_side_pri_addr; } /* Secondary Channel Programming */ if (dev->ide_conf[0x52] & 0x10) { - current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_pri_addr : native_base_pri_addr; - current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_pri_addr : native_side_pri_addr; + current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_pri_addr : native_base_pri_addr; + current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_pri_addr : native_side_pri_addr; } else { - current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_sec_addr : native_base_sec_addr; - current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_sec_addr : native_side_sec_addr; + current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_sec_addr : native_base_sec_addr; + current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_sec_addr : native_side_sec_addr; } if (dev->ide_conf[0x52] & 0x10) - ch ^= 8; + ch ^= 8; ali1543_log("ali5229_ide_handler(): Disabling primary IDE...\n"); ide_pri_disable(); @@ -590,40 +590,39 @@ ali5229_ide_handler(ali1543_t *dev) ide_sec_disable(); if (dev->ide_conf[0x04] & 0x01) { - /* Primary Channel Setup */ - if ((dev->ide_conf[0x09] & 0x20) || (dev->ide_conf[0x4d] & 0x80)) { - ali1543_log("ali5229_ide_handler(): Primary IDE base now %04X...\n", current_pri_base); - ide_set_base(0, current_pri_base); - ali1543_log("ali5229_ide_handler(): Primary IDE side now %04X...\n", current_pri_side); - ide_set_side(0, current_pri_side); + /* Primary Channel Setup */ + if ((dev->ide_conf[0x09] & 0x20) || (dev->ide_conf[0x4d] & 0x80)) { + ali1543_log("ali5229_ide_handler(): Primary IDE base now %04X...\n", current_pri_base); + ide_set_base(0, current_pri_base); + ali1543_log("ali5229_ide_handler(): Primary IDE side now %04X...\n", current_pri_side); + ide_set_side(0, current_pri_side); - ali1543_log("ali5229_ide_handler(): Enabling primary IDE...\n"); - ide_pri_enable(); + ali1543_log("ali5229_ide_handler(): Enabling primary IDE...\n"); + ide_pri_enable(); - sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (0 ^ ch)); - ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side); - } + sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (0 ^ ch)); + ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side); + } - /* Secondary Channel Setup */ - if ((dev->ide_conf[0x09] & 0x10) || (dev->ide_conf[0x4d] & 0x80)) { - ali1543_log("ali5229_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base); - ide_set_base(1, current_sec_base); - ali1543_log("ali5229_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side); - ide_set_side(1, current_sec_side); + /* Secondary Channel Setup */ + if ((dev->ide_conf[0x09] & 0x10) || (dev->ide_conf[0x4d] & 0x80)) { + ali1543_log("ali5229_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base); + ide_set_base(1, current_sec_base); + ali1543_log("ali5229_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side); + ide_set_side(1, current_sec_side); - ali1543_log("ali5229_ide_handler(): Enabling secondary IDE...\n"); - ide_sec_enable(); + ali1543_log("ali5229_ide_handler(): Enabling secondary IDE...\n"); + ide_sec_enable(); - sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, (((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8))) + (8 ^ ch)); - ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side); - } + sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, (((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8))) + (8 ^ ch)); + ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side); + } } else { - sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); - sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8); + sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); + sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8); } } - static void ali5229_chip_reset(ali1543_t *dev) { @@ -660,11 +659,11 @@ ali5229_chip_reset(ali1543_t *dev) dev->ide_conf[0x78] = 0x21; if (dev->type == 1) { - dev->ide_conf[0x08] = 0xc1; - dev->ide_conf[0x43] = 0x00; - dev->ide_conf[0x4b] = 0x4a; - dev->ide_conf[0x4e] = 0xba; - dev->ide_conf[0x4f] = 0x1a; + dev->ide_conf[0x08] = 0xc1; + dev->ide_conf[0x43] = 0x00; + dev->ide_conf[0x4b] = 0x4a; + dev->ide_conf[0x4e] = 0xba; + dev->ide_conf[0x4f] = 0x1a; } ali5229_write(0, 0x04, 0x05, dev); @@ -692,715 +691,734 @@ ali5229_chip_reset(ali1543_t *dev) ali5229_ide_handler(dev); } - static void ali5229_write(int func, int addr, uint8_t val, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; + ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M5229: dev->ide_conf[%02x] = %02x\n", addr, val); if (func > 0) - return; + return; if (!dev->ide_dev_enable) - return; + return; switch (addr) { - case 0x04: /* COM - Command Register */ - ali1543_log("IDE04: %02X\n", val); - dev->ide_conf[addr] = val & 0x45; - ali5229_ide_handler(dev); - break; + case 0x04: /* COM - Command Register */ + ali1543_log("IDE04: %02X\n", val); + dev->ide_conf[addr] = val & 0x45; + ali5229_ide_handler(dev); + break; - case 0x05: - dev->ide_conf[addr] = val & 0x01; - break; + case 0x05: + dev->ide_conf[addr] = val & 0x01; + break; - case 0x07: - dev->ide_conf[addr] &= ~(val & 0xf1); - break; + case 0x07: + dev->ide_conf[addr] &= ~(val & 0xf1); + break; - case 0x09: /* Control */ - ali1543_log("IDE09: %02X\n", val); + case 0x09: /* Control */ + ali1543_log("IDE09: %02X\n", val); - if (dev->type == 1) { - val &= ~(dev->ide_conf[0x43]); - val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]); - } + if (dev->type == 1) { + val &= ~(dev->ide_conf[0x43]); + val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]); + } - if (dev->ide_conf[0x4d] & 0x80) - dev->ide_conf[addr] = (dev->ide_conf[addr] & 0xfa) | (val & 0x05); - else - dev->ide_conf[addr] = (dev->ide_conf[addr] & 0x8a) | (val & 0x75); - ali5229_ide_handler(dev); - ali5229_ide_irq_handler(dev); - break; + if (dev->ide_conf[0x4d] & 0x80) + dev->ide_conf[addr] = (dev->ide_conf[addr] & 0xfa) | (val & 0x05); + else + dev->ide_conf[addr] = (dev->ide_conf[addr] & 0x8a) | (val & 0x75); + ali5229_ide_handler(dev); + ali5229_ide_irq_handler(dev); + break; - /* Primary Base Address */ - case 0x10: case 0x11: case 0x14: case 0x15: - /* FALLTHROUGH */ + /* Primary Base Address */ + case 0x10: + case 0x11: + case 0x14: + case 0x15: + /* FALLTHROUGH */ - /* Secondary Base Address */ - case 0x18: case 0x19: case 0x1c: case 0x1d: - /* FALLTHROUGH */ + /* Secondary Base Address */ + case 0x18: + case 0x19: + case 0x1c: + case 0x1d: + /* FALLTHROUGH */ - /* Bus Mastering Base Address */ - case 0x20: case 0x21: case 0x22: case 0x23: - dev->ide_conf[addr] = val; - ali5229_ide_handler(dev); - break; + /* Bus Mastering Base Address */ + case 0x20: + case 0x21: + case 0x22: + case 0x23: + dev->ide_conf[addr] = val; + ali5229_ide_handler(dev); + break; - case 0x2c: /* Subsystem Vendor ID */ - case 0x2d: - case 0x2e: - case 0x2f: - if (!(dev->ide_conf[0x53] & 0x80)) - dev->ide_conf[addr] = val; - break; + case 0x2c: /* Subsystem Vendor ID */ + case 0x2d: + case 0x2e: + case 0x2f: + if (!(dev->ide_conf[0x53] & 0x80)) + dev->ide_conf[addr] = val; + break; - case 0x3c: /* Interrupt Line */ - case 0x3d: /* Interrupt Pin */ - dev->ide_conf[addr] = val; - break; + case 0x3c: /* Interrupt Line */ + case 0x3d: /* Interrupt Pin */ + dev->ide_conf[addr] = val; + break; - /* The machines don't touch anything beyond that point so we avoid any programming */ - case 0x43: - if (dev->type == 1) - dev->ide_conf[addr] = val & 0x7f; - break; + /* The machines don't touch anything beyond that point so we avoid any programming */ + case 0x43: + if (dev->type == 1) + dev->ide_conf[addr] = val & 0x7f; + break; - case 0x4b: - if (dev->type == 1) - dev->ide_conf[addr] = val; - break; + case 0x4b: + if (dev->type == 1) + dev->ide_conf[addr] = val; + break; - case 0x4d: - dev->ide_conf[addr] = val & 0x80; - ali5229_ide_handler(dev); - break; + case 0x4d: + dev->ide_conf[addr] = val & 0x80; + ali5229_ide_handler(dev); + break; - case 0x4f: - if (dev->type == 0) - dev->ide_conf[addr] = val & 0x3f; - break; + case 0x4f: + if (dev->type == 0) + dev->ide_conf[addr] = val & 0x3f; + break; - case 0x50: /* Configuration */ - ali1543_log("IDE50: %02X\n", val); - dev->ide_conf[addr] = val & 0x2b; - dev->ide_dev_enable = !!(val & 0x01); - break; + case 0x50: /* Configuration */ + ali1543_log("IDE50: %02X\n", val); + dev->ide_conf[addr] = val & 0x2b; + dev->ide_dev_enable = !!(val & 0x01); + break; - case 0x51: - dev->ide_conf[addr] = val & 0xf7; - if (val & 0x80) - ali5229_chip_reset(dev); - else if (val & 0x40) { - sff_bus_master_reset(dev->ide_controller[0], (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); - sff_bus_master_reset(dev->ide_controller[1], ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8); - } - break; + case 0x51: + dev->ide_conf[addr] = val & 0xf7; + if (val & 0x80) + ali5229_chip_reset(dev); + else if (val & 0x40) { + sff_bus_master_reset(dev->ide_controller[0], (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); + sff_bus_master_reset(dev->ide_controller[1], ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8); + } + break; - case 0x52: /* FCS - Flexible Channel Setting Register */ - dev->ide_conf[addr] = val; - ali5229_ide_handler(dev); - ali5229_ide_irq_handler(dev); - break; + case 0x52: /* FCS - Flexible Channel Setting Register */ + dev->ide_conf[addr] = val; + ali5229_ide_handler(dev); + ali5229_ide_irq_handler(dev); + break; - case 0x53: /* Subsystem Vendor ID */ - dev->ide_conf[addr] = val & 0x8b; - break; + case 0x53: /* Subsystem Vendor ID */ + dev->ide_conf[addr] = val & 0x8b; + break; - case 0x54: /* FIFO threshold of primary channel drive 0 and drive 1 */ - case 0x55: /* FIFO threshold of secondary channel drive 0 and drive 1 */ - case 0x56: /* Ultra DMA /33 setting for Primary drive 0 and drive 1 */ - case 0x57: /* Ultra DMA /33 setting for Secondary drive 0 and drive 1 */ - case 0x78: /* IDE clock's frequency (default value is 33 = 21H) */ - dev->ide_conf[addr] = val; - break; + case 0x54: /* FIFO threshold of primary channel drive 0 and drive 1 */ + case 0x55: /* FIFO threshold of secondary channel drive 0 and drive 1 */ + case 0x56: /* Ultra DMA /33 setting for Primary drive 0 and drive 1 */ + case 0x57: /* Ultra DMA /33 setting for Secondary drive 0 and drive 1 */ + case 0x78: /* IDE clock's frequency (default value is 33 = 21H) */ + dev->ide_conf[addr] = val; + break; - case 0x58: - dev->ide_conf[addr] = val & 3; - break; + case 0x58: + dev->ide_conf[addr] = val & 3; + break; - case 0x59: case 0x5a: - case 0x5b: - dev->ide_conf[addr] = val & 0x7f; - break; + case 0x59: + case 0x5a: + case 0x5b: + dev->ide_conf[addr] = val & 0x7f; + break; - case 0x5c: - dev->ide_conf[addr] = val & 3; - break; + case 0x5c: + dev->ide_conf[addr] = val & 3; + break; - case 0x5d: case 0x5e: - case 0x5f: - dev->ide_conf[addr] = val & 0x7f; - break; + case 0x5d: + case 0x5e: + case 0x5f: + dev->ide_conf[addr] = val & 0x7f; + break; } } - static uint8_t ali5229_read(int func, int addr, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; - uint8_t ret = 0xff; + ali1543_t *dev = (ali1543_t *) priv; + uint8_t ret = 0xff; if (dev->ide_dev_enable && (func == 0)) { - ret = dev->ide_conf[addr]; - if ((addr == 0x09) && !(dev->ide_conf[0x50] & 0x02)) - ret &= 0x0f; - else if (addr == 0x50) - ret = (ret & 0xfe) | (dev->ide_dev_enable ? 0x01 : 0x00); - else if (addr == 0x75) - ret = ide_read_ali_75(); - else if (addr == 0x76) - ret = ide_read_ali_76(); + ret = dev->ide_conf[addr]; + if ((addr == 0x09) && !(dev->ide_conf[0x50] & 0x02)) + ret &= 0x0f; + else if (addr == 0x50) + ret = (ret & 0xfe) | (dev->ide_dev_enable ? 0x01 : 0x00); + else if (addr == 0x75) + ret = ide_read_ali_75(); + else if (addr == 0x76) + ret = ide_read_ali_76(); } return ret; } - static void ali5237_write(int func, int addr, uint8_t val, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; + ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val); if (func > 0) - return; + return; if (!dev->usb_dev_enable) - return; + return; switch (addr) { - case 0x04: /* USB Enable */ - dev->usb_conf[addr] = val & 0x5f; - ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); - break; + case 0x04: /* USB Enable */ + dev->usb_conf[addr] = val & 0x5f; + ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); + break; - case 0x05: - dev->usb_conf[addr] = 0x01; - break; + case 0x05: + dev->usb_conf[addr] = 0x01; + break; - case 0x07: - dev->usb_conf[addr] &= ~(val & 0xc9); - break; + case 0x07: + dev->usb_conf[addr] &= ~(val & 0xc9); + break; - case 0x0c: /* Cache Line Size */ - case 0x0d: /* Latency Timer */ - case 0x3c: /* Interrupt Line Register */ + case 0x0c: /* Cache Line Size */ + case 0x0d: /* Latency Timer */ + case 0x3c: /* Interrupt Line Register */ - case 0x42: /* Test Mode Register */ - dev->usb_conf[addr] = val & 0x10; - break; - case 0x43: - if (dev->type == 1) - dev->usb_conf[addr] = val & 0x04; - break; + case 0x42: /* Test Mode Register */ + dev->usb_conf[addr] = val & 0x10; + break; + case 0x43: + if (dev->type == 1) + dev->usb_conf[addr] = val & 0x04; + break; - /* USB Base I/O */ - case 0x11: - dev->usb_conf[addr] = val & 0xf0; - ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); - break; - case 0x12: case 0x13: - dev->usb_conf[addr] = val; - ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); - break; + /* USB Base I/O */ + case 0x11: + dev->usb_conf[addr] = val & 0xf0; + ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); + break; + case 0x12: + case 0x13: + dev->usb_conf[addr] = val; + ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1); + break; - case 0x2c: /* Subsystem Vendor ID */ - case 0x2d: - case 0x2e: - case 0x2f: - if (!(dev->usb_conf[0x42] & 0x10)) - dev->usb_conf[addr] = val; - break; + case 0x2c: /* Subsystem Vendor ID */ + case 0x2d: + case 0x2e: + case 0x2f: + if (!(dev->usb_conf[0x42] & 0x10)) + dev->usb_conf[addr] = val; + break; } } - static uint8_t ali5237_read(int func, int addr, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; - uint8_t ret = 0xff; + ali1543_t *dev = (ali1543_t *) priv; + uint8_t ret = 0xff; if (dev->usb_dev_enable && (func == 0)) - ret = dev->usb_conf[addr]; + ret = dev->usb_conf[addr]; return ret; } - static void ali7101_write(int func, int addr, uint8_t val, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; + ali1543_t *dev = (ali1543_t *) priv; ali1543_log("M7101: dev->pmu_conf[%02x] = %02x\n", addr, val); if (func > 0) - return; + return; if (!dev->pmu_dev_enable) - return; + return; if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9)) - return; + return; switch (addr) { - case 0x04: /* Enable PMU */ - ali1543_log("PMU04: %02X\n", val); - dev->pmu_conf[addr] = val & 0x01; - if (!(dev->pmu_conf[0x5b] & 0x02)) - acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1); - if (!(dev->pmu_conf[0x5b] & 0x04)) { - if (dev->type == 1) - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); - else - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); - } - break; + case 0x04: /* Enable PMU */ + ali1543_log("PMU04: %02X\n", val); + dev->pmu_conf[addr] = val & 0x01; + if (!(dev->pmu_conf[0x5b] & 0x02)) + acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1); + if (!(dev->pmu_conf[0x5b] & 0x04)) { + if (dev->type == 1) + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); + else + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); + } + break; - /* PMU Base I/O */ - case 0x10: case 0x11: - if (!(dev->pmu_conf[0x5b] & 0x02)) { - if (addr == 0x10) - dev->pmu_conf[addr] = (val & 0xc0) | 1; - else if (addr == 0x11) - dev->pmu_conf[addr] = val; + /* PMU Base I/O */ + case 0x10: + case 0x11: + if (!(dev->pmu_conf[0x5b] & 0x02)) { + if (addr == 0x10) + dev->pmu_conf[addr] = (val & 0xc0) | 1; + else if (addr == 0x11) + dev->pmu_conf[addr] = val; - ali1543_log("New ACPI base address: %08X\n", (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0)); - acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1); - } - break; + ali1543_log("New ACPI base address: %08X\n", (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0)); + acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1); + } + break; - /* SMBus Base I/O */ - case 0x14: case 0x15: - if (!(dev->pmu_conf[0x5b] & 0x04)) { - if (addr == 0x14) { - if (dev->type == 1) - dev->pmu_conf[addr] = (val & 0xc0) | 1; - else - dev->pmu_conf[addr] = (val & 0xe0) | 1; - } else if (addr == 0x15) - dev->pmu_conf[addr] = val; + /* SMBus Base I/O */ + case 0x14: + case 0x15: + if (!(dev->pmu_conf[0x5b] & 0x04)) { + if (addr == 0x14) { + if (dev->type == 1) + dev->pmu_conf[addr] = (val & 0xc0) | 1; + else + dev->pmu_conf[addr] = (val & 0xe0) | 1; + } else if (addr == 0x15) + dev->pmu_conf[addr] = val; - if (dev->type == 1) { - ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0)); - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); - } else { - ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0)); - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); - } - } - break; + if (dev->type == 1) { + ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0)); + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); + } else { + ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0)); + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); + } + } + break; - /* Subsystem Vendor ID */ - case 0x2c: case 0x2d: case 0x2e: case 0x2f: - if (!(dev->pmu_conf[0xd8] & 0x08)) - dev->pmu_conf[addr] = val; - break; + /* Subsystem Vendor ID */ + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + if (!(dev->pmu_conf[0xd8] & 0x08)) + dev->pmu_conf[addr] = val; + break; - case 0x40: - dev->pmu_conf[addr] = val & 0x1f; - pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03)); - break; - case 0x41: - dev->pmu_conf[addr] = val & 0x10; - ali1543_log("PMU41: %02X\n", val); - apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); - break; + case 0x40: + dev->pmu_conf[addr] = val & 0x1f; + pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03)); + break; + case 0x41: + dev->pmu_conf[addr] = val & 0x10; + ali1543_log("PMU41: %02X\n", val); + apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); + break; - /* TODO: Is the status R/W or R/WC? */ - case 0x42: - dev->pmu_conf[addr] &= ~(val & 0x1f); - break; - case 0x43: - dev->pmu_conf[addr] &= ~(val & 0x10); - if (val & 0x10) - acpi_ali_soft_smi_status_write(dev->acpi, 0); - break; + /* TODO: Is the status R/W or R/WC? */ + case 0x42: + dev->pmu_conf[addr] &= ~(val & 0x1f); + break; + case 0x43: + dev->pmu_conf[addr] &= ~(val & 0x10); + if (val & 0x10) + acpi_ali_soft_smi_status_write(dev->acpi, 0); + break; - case 0x44: - dev->pmu_conf[addr] = val; - break; - case 0x45: - dev->pmu_conf[addr] = val & 0x9f; - break; - case 0x46: - dev->pmu_conf[addr] = val & 0x18; - break; + case 0x44: + dev->pmu_conf[addr] = val; + break; + case 0x45: + dev->pmu_conf[addr] = val & 0x9f; + break; + case 0x46: + dev->pmu_conf[addr] = val & 0x18; + break; - /* TODO: Is the status R/W or R/WC? */ - case 0x48: - dev->pmu_conf[addr] &= ~val; - break; - case 0x49: - dev->pmu_conf[addr] &= ~(val & 0x9f); - break; - case 0x4a: - dev->pmu_conf[addr] &= ~(val & 0x38); - break; + /* TODO: Is the status R/W or R/WC? */ + case 0x48: + dev->pmu_conf[addr] &= ~val; + break; + case 0x49: + dev->pmu_conf[addr] &= ~(val & 0x9f); + break; + case 0x4a: + dev->pmu_conf[addr] &= ~(val & 0x38); + break; - case 0x4c: - dev->pmu_conf[addr] = val & 5; - break; - case 0x4d: - dev->pmu_conf[addr] = val & 1; - break; + case 0x4c: + dev->pmu_conf[addr] = val & 5; + break; + case 0x4d: + dev->pmu_conf[addr] = val & 1; + break; - /* TODO: Is the status R/W or R/WC? */ - case 0x4e: - dev->pmu_conf[addr] &= ~(val & 5); - break; - case 0x4f: - dev->pmu_conf[addr] &= ~(val & 1); - break; + /* TODO: Is the status R/W or R/WC? */ + case 0x4e: + dev->pmu_conf[addr] &= ~(val & 5); + break; + case 0x4f: + dev->pmu_conf[addr] &= ~(val & 1); + break; - case 0x50: case 0x51: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - break; + case 0x50: + case 0x51: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + break; - case 0x52: case 0x53: - if (dev->type == 1) - dev->pmu_conf[addr] &= ~val; - break; + case 0x52: + case 0x53: + if (dev->type == 1) + dev->pmu_conf[addr] &= ~val; + break; - case 0x54: /* Standby timer */ - dev->pmu_conf[addr] = val; - break; - case 0x55: /* APM Timer */ - dev->pmu_conf[addr] = val & 0x7f; - break; - case 0x59: /* Global display timer. */ - dev->pmu_conf[addr] = val & 0x1f; - break; + case 0x54: /* Standby timer */ + dev->pmu_conf[addr] = val; + break; + case 0x55: /* APM Timer */ + dev->pmu_conf[addr] = val & 0x7f; + break; + case 0x59: /* Global display timer. */ + dev->pmu_conf[addr] = val & 0x1f; + break; - case 0x5b: /* ACPI/SMB Base I/O Control */ - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x87; - else - dev->pmu_conf[addr] = val & 0x7f; - break; + case 0x5b: /* ACPI/SMB Base I/O Control */ + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x87; + else + dev->pmu_conf[addr] = val & 0x7f; + break; - case 0x60: - dev->pmu_conf[addr] = val; - break; - case 0x61: - dev->pmu_conf[addr] = val & 0x13; - break; - case 0x62: - dev->pmu_conf[addr] = val & 0xf1; - break; - case 0x63: - dev->pmu_conf[addr] = val & 0x07; - break; + case 0x60: + dev->pmu_conf[addr] = val; + break; + case 0x61: + dev->pmu_conf[addr] = val & 0x13; + break; + case 0x62: + dev->pmu_conf[addr] = val & 0xf1; + break; + case 0x63: + dev->pmu_conf[addr] = val & 0x07; + break; - case 0x64: - dev->pmu_conf[addr] = val; - break; - case 0x65: - dev->pmu_conf[addr] = val & 0x11; - break; + case 0x64: + dev->pmu_conf[addr] = val; + break; + case 0x65: + dev->pmu_conf[addr] = val & 0x11; + break; - case 0x68: - dev->pmu_conf[addr] = val & 0x07; - break; + case 0x68: + dev->pmu_conf[addr] = val & 0x07; + break; - case 0x6c: case 0x6d: - dev->pmu_conf[addr] = val; - break; - case 0x6e: - dev->pmu_conf[addr] = val & 0xbf; - break; - case 0x6f: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x1e; - else - dev->pmu_conf[addr] = val & 0x1f; - break; + case 0x6c: + case 0x6d: + dev->pmu_conf[addr] = val; + break; + case 0x6e: + dev->pmu_conf[addr] = val & 0xbf; + break; + case 0x6f: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x1e; + else + dev->pmu_conf[addr] = val & 0x1f; + break; - case 0x70: - dev->pmu_conf[addr] = val; - break; - case 0x71: - dev->pmu_conf[addr] = val & 0x3f; - break; + case 0x70: + dev->pmu_conf[addr] = val; + break; + case 0x71: + dev->pmu_conf[addr] = val & 0x3f; + break; - case 0x72: - dev->pmu_conf[addr] = val & 0x0f; - break; + case 0x72: + dev->pmu_conf[addr] = val & 0x0f; + break; - /* TODO: Is the status R/W or R/WC? */ - case 0x74: - dev->pmu_conf[addr] &= ~(val & 0x33); - break; + /* TODO: Is the status R/W or R/WC? */ + case 0x74: + dev->pmu_conf[addr] &= ~(val & 0x33); + break; - case 0x75: - dev->pmu_conf[addr] = val; - break; + case 0x75: + dev->pmu_conf[addr] = val; + break; - case 0x76: - dev->pmu_conf[addr] = val & 0x7f; - break; + case 0x76: + dev->pmu_conf[addr] = val & 0x7f; + break; - case 0x77: - /* TODO: If bit 1 is clear, then status bit is set even if SMI is disabled. */ - dev->pmu_conf[addr] = val; - pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03)); - ali1543_log("PMU77: %02X\n", val); - apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); - break; + case 0x77: + /* TODO: If bit 1 is clear, then status bit is set even if SMI is disabled. */ + dev->pmu_conf[addr] = val; + pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03)); + ali1543_log("PMU77: %02X\n", val); + apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); + break; - case 0x78: - dev->pmu_conf[addr] = val; - break; - case 0x79: - dev->pmu_conf[addr] = val & 0x0f; - break; + case 0x78: + dev->pmu_conf[addr] = val; + break; + case 0x79: + dev->pmu_conf[addr] = val & 0x0f; + break; - case 0x7a: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x07; - else - dev->pmu_conf[addr] = val & 0x02; - break; + case 0x7a: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x07; + else + dev->pmu_conf[addr] = val & 0x02; + break; - case 0x7b: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - else - dev->pmu_conf[addr] = val & 0x7f; - break; + case 0x7b: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + else + dev->pmu_conf[addr] = val & 0x7f; + break; - case 0x7c ... 0x7f: - dev->pmu_conf[addr] = val; - break; + case 0x7c ... 0x7f: + dev->pmu_conf[addr] = val; + break; - case 0x81: - dev->pmu_conf[addr] = val & 0xf0; - break; + case 0x81: + dev->pmu_conf[addr] = val & 0xf0; + break; - case 0x82: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x01; - break; + case 0x82: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x01; + break; - case 0x84 ... 0x87: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - break; - case 0x88 ... 0x8b: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - break; + case 0x84 ... 0x87: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + break; + case 0x88 ... 0x8b: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + break; - case 0x8c: case 0x8d: - dev->pmu_conf[addr] = val & 0x0f; - break; + case 0x8c: + case 0x8d: + dev->pmu_conf[addr] = val & 0x0f; + break; - case 0x90: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x0f; - else - dev->pmu_conf[addr] = val & 0x01; - break; + case 0x90: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x0f; + else + dev->pmu_conf[addr] = val & 0x01; + break; - case 0x91: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x02; - break; + case 0x91: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x02; + break; - case 0x94: - dev->pmu_conf[addr] = val & 0xf0; - break; - case 0x95 ... 0x97: - dev->pmu_conf[addr] = val; - break; + case 0x94: + dev->pmu_conf[addr] = val & 0xf0; + break; + case 0x95 ... 0x97: + dev->pmu_conf[addr] = val; + break; - case 0x98: case 0x99: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - break; + case 0x98: + case 0x99: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + break; - case 0xa4: case 0xa5: - dev->pmu_conf[addr] = val; - break; + case 0xa4: + case 0xa5: + dev->pmu_conf[addr] = val; + break; - case 0xb2: - dev->pmu_conf[addr] = val & 0x01; - break; + case 0xb2: + dev->pmu_conf[addr] = val & 0x01; + break; - case 0xb3: - dev->pmu_conf[addr] = val & 0x7f; - break; + case 0xb3: + dev->pmu_conf[addr] = val & 0x7f; + break; - case 0xb4: - dev->pmu_conf[addr] = val & 0x7c; - break; + case 0xb4: + dev->pmu_conf[addr] = val & 0x7c; + break; - case 0xb5: case 0xb7: - dev->pmu_conf[addr] = val & 0x0f; - break; + case 0xb5: + case 0xb7: + dev->pmu_conf[addr] = val & 0x0f; + break; - case 0xb8: case 0xb9: - if (dev->type == 1) - dev->pmu_conf[addr] = val; - break; + case 0xb8: + case 0xb9: + if (dev->type == 1) + dev->pmu_conf[addr] = val; + break; - case 0xbc: - outb(0x70, val); - break; + case 0xbc: + outb(0x70, val); + break; - case 0xbd: - dev->pmu_conf[addr] = val & 0x0f; - acpi_set_timer32(dev->acpi, val & 0x04); - break; + case 0xbd: + dev->pmu_conf[addr] = val & 0x0f; + acpi_set_timer32(dev->acpi, val & 0x04); + break; - case 0xbe: - dev->pmu_conf[addr] = val & 0x03; - break; + case 0xbe: + dev->pmu_conf[addr] = val & 0x03; + break; - /* Continue Further Later */ - /* GPO Registers */ - case 0xc0: - dev->pmu_conf[addr] = val & 0x0f; - acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); - break; - case 0xc1: - dev->pmu_conf[addr] = val & 0x12; - acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); - break; - case 0xc2: - dev->pmu_conf[addr] = val & 0x1c; - acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); - break; - case 0xc3: - dev->pmu_conf[addr] = val & 0x06; - acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); - break; + /* Continue Further Later */ + /* GPO Registers */ + case 0xc0: + dev->pmu_conf[addr] = val & 0x0f; + acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); + break; + case 0xc1: + dev->pmu_conf[addr] = val & 0x12; + acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); + break; + case 0xc2: + dev->pmu_conf[addr] = val & 0x1c; + acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); + break; + case 0xc3: + dev->pmu_conf[addr] = val & 0x06; + acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00); + break; - case 0xc6: - dev->pmu_conf[addr] = val & 0x06; - break; + case 0xc6: + dev->pmu_conf[addr] = val & 0x06; + break; - case 0xc8: case 0xc9: - dev->pmu_conf[addr] = val & 0x01; - break; + case 0xc8: + case 0xc9: + dev->pmu_conf[addr] = val & 0x01; + break; - case 0xca: - /* TODO: Write to this port causes a beep. */ - dev->pmu_conf[addr] = val; - break; + case 0xca: + /* TODO: Write to this port causes a beep. */ + dev->pmu_conf[addr] = val; + break; - case 0xcc: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x1f; - break; - case 0xcd: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x33; - break; + case 0xcc: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x1f; + break; + case 0xcd: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x33; + break; - case 0xd4: - dev->pmu_conf[addr] = val & 0x01; - break; + case 0xd4: + dev->pmu_conf[addr] = val & 0x01; + break; - case 0xd8: - dev->pmu_conf[addr] = val & 0xfd; - break; - case 0xd9: - if (dev->type == 1) - dev->pmu_conf[addr] = val & 0x3f; - break; + case 0xd8: + dev->pmu_conf[addr] = val & 0xfd; + break; + case 0xd9: + if (dev->type == 1) + dev->pmu_conf[addr] = val & 0x3f; + break; - case 0xe0: - dev->pmu_conf[addr] = val & 0x03; - if (dev->type == 1) - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4))); - else - smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4))); - break; + case 0xe0: + dev->pmu_conf[addr] = val & 0x03; + if (dev->type == 1) + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4))); + else + smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4))); + break; - case 0xe1: - dev->pmu_conf[addr] = val; - break; + case 0xe1: + dev->pmu_conf[addr] = val; + break; - case 0xe2: - dev->pmu_conf[addr] = val & 0xf8; - break; + case 0xe2: + dev->pmu_conf[addr] = val & 0xf8; + break; - default: - dev->pmu_conf[addr] = val; - break; + default: + dev->pmu_conf[addr] = val; + break; } } - static uint8_t ali7101_read(int func, int addr, void *priv) { - ali1543_t *dev = (ali1543_t *)priv; - uint8_t ret = 0xff; + ali1543_t *dev = (ali1543_t *) priv; + uint8_t ret = 0xff; if (dev->pmu_dev_enable && (func == 0)) { - if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9)) - return 0xff; + if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9)) + return 0xff; - /* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */ - if (addr == 0x43) - ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00; - else if (addr == 0x7f) - ret = 0x80; - else if (addr == 0xbc) - ret = inb(0x70); - else - ret = dev->pmu_conf[addr]; + /* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */ + if (addr == 0x43) + ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00; + else if (addr == 0x7f) + ret = 0x80; + else if (addr == 0xbc) + ret = inb(0x70); + else + ret = dev->pmu_conf[addr]; - if (dev->pmu_conf[0x77] & 0x10) { - switch (addr) { - case 0x42: - dev->pmu_conf[addr] &= 0xe0; - break; - case 0x43: - dev->pmu_conf[addr] &= 0xef; - acpi_ali_soft_smi_status_write(dev->acpi, 0); - break; + if (dev->pmu_conf[0x77] & 0x10) { + switch (addr) { + case 0x42: + dev->pmu_conf[addr] &= 0xe0; + break; + case 0x43: + dev->pmu_conf[addr] &= 0xef; + acpi_ali_soft_smi_status_write(dev->acpi, 0); + break; - case 0x48: - dev->pmu_conf[addr] = 0x00; - break; - case 0x49: - dev->pmu_conf[addr] &= 0x60; - break; - case 0x4a: - dev->pmu_conf[addr] &= 0xc7; - break; + case 0x48: + dev->pmu_conf[addr] = 0x00; + break; + case 0x49: + dev->pmu_conf[addr] &= 0x60; + break; + case 0x4a: + dev->pmu_conf[addr] &= 0xc7; + break; - case 0x4e: - dev->pmu_conf[addr] &= 0xfa; - break; - case 0x4f: - dev->pmu_conf[addr] &= 0xfe; - break; + case 0x4e: + dev->pmu_conf[addr] &= 0xfa; + break; + case 0x4f: + dev->pmu_conf[addr] &= 0xfe; + break; - case 0x74: - dev->pmu_conf[addr] &= 0xcc; - break; - } - } + case 0x74: + dev->pmu_conf[addr] &= 0xcc; + break; + } + } } return ret; } - static void ali1543_reset(void *priv) { - ali1543_t *dev = (ali1543_t *)priv; + ali1543_t *dev = (ali1543_t *) priv; /* Temporarily enable everything. Register writes will disable the devices. */ dev->ide_dev_enable = 1; @@ -1474,7 +1492,7 @@ ali1543_reset(void *priv) dev->pci_conf[0x04] = 0x0f; dev->pci_conf[0x07] = 0x02; if (dev->type == 1) - dev->pci_conf[0x08] = 0xc0; + dev->pci_conf[0x08] = 0xc0; dev->pci_conf[0x0a] = 0x01; dev->pci_conf[0x0b] = 0x06; @@ -1492,20 +1510,18 @@ ali1543_reset(void *priv) unmask_a20_in_smm = 1; } - static void ali1543_close(void *priv) { - ali1543_t *dev = (ali1543_t *)priv; + ali1543_t *dev = (ali1543_t *) priv; free(dev); } - static void * ali1543_init(const device_t *info) { - ali1543_t *dev = (ali1543_t *)malloc(sizeof(ali1543_t)); + ali1543_t *dev = (ali1543_t *) malloc(sizeof(ali1543_t)); memset(dev, 0, sizeof(ali1543_t)); /* Device 02: M1533 Southbridge */ @@ -1522,7 +1538,7 @@ ali1543_init(const device_t *info) /* ACPI */ dev->acpi = device_add(&acpi_ali_device); - dev->nvr = device_add(&piix4_nvr_device); + dev->nvr = device_add(&piix4_nvr_device); /* DMA */ dma_alias_set(); @@ -1548,10 +1564,10 @@ ali1543_init(const device_t *info) /* USB */ dev->usb = device_add(&usb_device); - dev->type = info->local & 0xff; + dev->type = info->local & 0xff; dev->offset = (info->local >> 8) & 0x7f; if (info->local & 0x8000) - dev->offset = -dev->offset; + dev->offset = -dev->offset; pclog("Offset = %i\n", dev->offset); pci_enable_mirq(0); @@ -1571,30 +1587,30 @@ ali1543_init(const device_t *info) } const device_t ali1543_device = { - .name = "ALi M1543 Desktop South Bridge", + .name = "ALi M1543 Desktop South Bridge", .internal_name = "ali1543", - .flags = DEVICE_PCI, - .local = 0x8500, /* -5 slot offset, we can do this because we currently - have no case of M1543 non-C with a different offset */ - .init = ali1543_init, + .flags = DEVICE_PCI, + .local = 0x8500, /* -5 slot offset, we can do this because we currently + have no case of M1543 non-C with a different offset */ + .init = ali1543_init, .close = ali1543_close, .reset = ali1543_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t ali1543c_device = { - .name = "ALi M1543C Desktop South Bridge", + .name = "ALi M1543C Desktop South Bridge", .internal_name = "ali1543c", - .flags = DEVICE_PCI, - .local = 1, - .init = ali1543_init, - .close = ali1543_close, - .reset = ali1543_reset, + .flags = DEVICE_PCI, + .local = 1, + .init = ali1543_init, + .close = ali1543_close, + .reset = ali1543_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali1621.c b/src/chipset/ali1621.c index c234e65ce..5f5f5883c 100644 --- a/src/chipset/ali1621.c +++ b/src/chipset/ali1621.c @@ -31,15 +31,12 @@ #include <86box/chipset.h> +typedef struct ali1621_t { + uint8_t pci_conf[256]; -typedef struct ali1621_t -{ - uint8_t pci_conf[256]; - - smram_t * smram[2]; + smram_t *smram[2]; } ali1621_t; - #ifdef ENABLE_ALI1621_LOG int ali1621_do_log = ENABLE_ALI1621_LOG; static void @@ -47,51 +44,49 @@ ali1621_log(const char *fmt, ...) { va_list ap; - if (ali1621_do_log) - { + if (ali1621_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define ali1621_log(fmt, ...) +# define ali1621_log(fmt, ...) #endif - /* Table translated to a more sensible format: - Read cycles: - SMREN SMM Mode Code Data - 0 X X PCI PCI - 1 0 Close PCI PCI - 1 0 Lock PCI PCI - 1 0 Protect PCI PCI - 1 0 Open DRAM DRAM - 1 1 Open DRAM DRAM - 1 1 Protect DRAM DRAM - 1 1 Close DRAM PCI - 1 1 Lock DRAM PCI + Read cycles: + SMREN SMM Mode Code Data + 0 X X PCI PCI + 1 0 Close PCI PCI + 1 0 Lock PCI PCI + 1 0 Protect PCI PCI + 1 0 Open DRAM DRAM + 1 1 Open DRAM DRAM + 1 1 Protect DRAM DRAM + 1 1 Close DRAM PCI + 1 1 Lock DRAM PCI - Write cycles: - SMWEN SMM Mode Data - 0 X X PCI - 1 0 Close PCI - 1 0 Lock PCI - 1 0 Protect PCI - 1 0 Open DRAM - 1 1 Open DRAM - 1 1 Protect DRAM - 1 1 Close PCI - 1 1 Lock PCI + Write cycles: + SMWEN SMM Mode Data + 0 X X PCI + 1 0 Close PCI + 1 0 Lock PCI + 1 0 Protect PCI + 1 0 Open DRAM + 1 1 Open DRAM + 1 1 Protect DRAM + 1 1 Close PCI + 1 1 Lock PCI - Explanation of the modes based above: - If SM*EN = 0, SMRAM is entirely disabled, otherwise: - If mode is Close or Lock, then SMRAM always goes to PCI outside SMM, - and data to PCI, code to DRAM in SMM; - If mode is Protect, then SMRAM always goes to PCI outside SMM and - DRAM in SMM; - If mode is Open, then SMRAM always goes to DRAM. - Read and write are enabled separately. + Explanation of the modes based above: + If SM*EN = 0, SMRAM is entirely disabled, otherwise: + If mode is Close or Lock, then SMRAM always goes to PCI outside SMM, + and data to PCI, code to DRAM in SMM; + If mode is Protect, then SMRAM always goes to PCI outside SMM and + DRAM in SMM; + If mode is Open, then SMRAM always goes to DRAM. + Read and write are enabled separately. */ static void ali1621_smram_recalc(uint8_t val, ali1621_t *dev) @@ -101,486 +96,486 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev) smram_disable_all(); if (val & 0xc0) { - /* SMRAM 0: A0000-BFFFF */ - if (val & 0x80) { - access_smm = ACCESS_SMRAM_X; + /* SMRAM 0: A0000-BFFFF */ + if (val & 0x80) { + access_smm = ACCESS_SMRAM_X; - switch (val & 0x30) { - case 0x10: /* Open. */ - access_normal = ACCESS_SMRAM_RX; - /* FALLTHROUGH */ - case 0x30: /* Protect. */ - access_smm |= ACCESS_SMRAM_R; - break; - } - } + switch (val & 0x30) { + case 0x10: /* Open. */ + access_normal = ACCESS_SMRAM_RX; + /* FALLTHROUGH */ + case 0x30: /* Protect. */ + access_smm |= ACCESS_SMRAM_R; + break; + } + } - if (val & 0x40) switch (val & 0x30) { - case 0x10: /* Open. */ - access_normal |= ACCESS_SMRAM_W; - /* FALLTHROUGH */ - case 0x30: /* Protect. */ - access_smm |= ACCESS_SMRAM_W; - break; - } + if (val & 0x40) + switch (val & 0x30) { + case 0x10: /* Open. */ + access_normal |= ACCESS_SMRAM_W; + /* FALLTHROUGH */ + case 0x30: /* Protect. */ + access_smm |= ACCESS_SMRAM_W; + break; + } - smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30)); + smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30)); - mem_set_access(ACCESS_NORMAL, 3, 0xa0000, 0x20000, access_normal); - mem_set_access(ACCESS_SMM, 3, 0xa0000, 0x20000, access_smm); + mem_set_access(ACCESS_NORMAL, 3, 0xa0000, 0x20000, access_normal); + mem_set_access(ACCESS_SMM, 3, 0xa0000, 0x20000, access_smm); } if (val & 0x08) - smram_enable(dev->smram[1], 0x38000, 0xa8000, 0x08000, 0, 1); + smram_enable(dev->smram[1], 0x38000, 0xa8000, 0x08000, 0, 1); flushmmucache_nopc(); } - static void ali1621_shadow_recalc(int cur_reg, ali1621_t *dev) { - int i, r_bit, w_bit, reg; + int i, r_bit, w_bit, reg; uint32_t base, flags = 0; shadowbios = shadowbios_write = 0; /* C0000-EFFFF */ for (i = 0; i < 12; i++) { - base = 0x000c0000 + (i << 14); - r_bit = (i << 1) + 4; - reg = 0x84; - if (r_bit > 23) { - r_bit &= 7; - reg += 3; - } else if (r_bit > 15) { - r_bit &= 7; - reg += 2; - } else if (r_bit > 7) { - r_bit &= 7; - reg++; - } - w_bit = r_bit + 1; + base = 0x000c0000 + (i << 14); + r_bit = (i << 1) + 4; + reg = 0x84; + if (r_bit > 23) { + r_bit &= 7; + reg += 3; + } else if (r_bit > 15) { + r_bit &= 7; + reg += 2; + } else if (r_bit > 7) { + r_bit &= 7; + reg++; + } + w_bit = r_bit + 1; - flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); + flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); - if (base >= 0x000e0000) { - if (dev->pci_conf[reg] & (1 << r_bit)) - shadowbios |= 1; - if (dev->pci_conf[reg] & (1 << r_bit)) - shadowbios_write |= 1; - } + if (base >= 0x000e0000) { + if (dev->pci_conf[reg] & (1 << r_bit)) + shadowbios |= 1; + if (dev->pci_conf[reg] & (1 << r_bit)) + shadowbios_write |= 1; + } - ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, - (dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E'); + ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, + (dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E'); mem_set_mem_state_both(base, 0x00004000, flags); } /* F0000-FFFFF */ - base = 0x000f0000; + base = 0x000f0000; r_bit = 4; w_bit = 5; - reg = 0x87; + reg = 0x87; flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY); if (dev->pci_conf[reg] & (1 << r_bit)) - shadowbios |= 1; + shadowbios |= 1; if (dev->pci_conf[reg] & (1 << r_bit)) - shadowbios_write |= 1; + shadowbios_write |= 1; ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x0000ffff, - (dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E'); + (dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E'); mem_set_mem_state_both(base, 0x00010000, flags); flushmmucache_nopc(); } - static void ali1621_mask_bar(ali1621_t *dev) { uint32_t bar, mask; switch (dev->pci_conf[0xbc] & 0x0f) { - case 0x00: - default: - mask = 0x00000000; - break; - case 0x01: - mask = 0xfff00000; - break; - case 0x02: - mask = 0xffe00000; - break; - case 0x03: - mask = 0xffc00000; - break; - case 0x04: - mask = 0xff800000; - break; - case 0x06: - mask = 0xff000000; - break; - case 0x07: - mask = 0xfe000000; - break; - case 0x08: - mask = 0xfc000000; - break; - case 0x09: - mask = 0xf8000000; - break; - case 0x0a: - mask = 0xf0000000; - break; + case 0x00: + default: + mask = 0x00000000; + break; + case 0x01: + mask = 0xfff00000; + break; + case 0x02: + mask = 0xffe00000; + break; + case 0x03: + mask = 0xffc00000; + break; + case 0x04: + mask = 0xff800000; + break; + case 0x06: + mask = 0xff000000; + break; + case 0x07: + mask = 0xfe000000; + break; + case 0x08: + mask = 0xfc000000; + break; + case 0x09: + mask = 0xf8000000; + break; + case 0x0a: + mask = 0xf0000000; + break; } - bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask; + bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask; dev->pci_conf[0x12] = (bar >> 16) & 0xff; dev->pci_conf[0x13] = (bar >> 24) & 0xff; } - static void ali1621_write(int func, int addr, uint8_t val, void *priv) { - ali1621_t *dev = (ali1621_t *)priv; + ali1621_t *dev = (ali1621_t *) priv; switch (addr) { - case 0x04: - dev->pci_conf[addr] = val & 0x01; - break; - case 0x05: - dev->pci_conf[addr] = val & 0x01; - break; + case 0x04: + dev->pci_conf[addr] = val & 0x01; + break; + case 0x05: + dev->pci_conf[addr] = val & 0x01; + break; - case 0x07: - dev->pci_conf[addr] &= ~(val & 0xf0); - break; + case 0x07: + dev->pci_conf[addr] &= ~(val & 0xf0); + break; - case 0x0d: - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x0d: + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x12: - dev->pci_conf[0x12] = (val & 0xc0); - ali1621_mask_bar(dev); - break; - case 0x13: - dev->pci_conf[0x13] = val; - ali1621_mask_bar(dev); - break; + case 0x12: + dev->pci_conf[0x12] = (val & 0xc0); + ali1621_mask_bar(dev); + break; + case 0x13: + dev->pci_conf[0x13] = val; + ali1621_mask_bar(dev); + break; - case 0x34: - dev->pci_conf[addr] = val; - break; + case 0x34: + dev->pci_conf[addr] = val; + break; - case 0x40: - dev->pci_conf[addr] = val; - break; - case 0x41: - dev->pci_conf[addr] = val; - break; + case 0x40: + dev->pci_conf[addr] = val; + break; + case 0x41: + dev->pci_conf[addr] = val; + break; - case 0x42: - dev->pci_conf[addr] = val; - break; - case 0x43: - dev->pci_conf[addr] = val; - break; + case 0x42: + dev->pci_conf[addr] = val; + break; + case 0x43: + dev->pci_conf[addr] = val; + break; - case 0x44: - dev->pci_conf[addr] = val; - break; - case 0x45: - dev->pci_conf[addr] = val; - break; + case 0x44: + dev->pci_conf[addr] = val; + break; + case 0x45: + dev->pci_conf[addr] = val; + break; - case 0x46: - dev->pci_conf[addr] = val; - break; - case 0x47: - dev->pci_conf[addr] = val; - break; + case 0x46: + dev->pci_conf[addr] = val; + break; + case 0x47: + dev->pci_conf[addr] = val; + break; - case 0x48: - dev->pci_conf[addr] = val; - break; - case 0x49: - dev->pci_conf[addr] = val; - break; + case 0x48: + dev->pci_conf[addr] = val; + break; + case 0x49: + dev->pci_conf[addr] = val; + break; - case 0x4a: - dev->pci_conf[addr] = val; - break; + case 0x4a: + dev->pci_conf[addr] = val; + break; - case 0x4b: - dev->pci_conf[addr] = val & 0x0f; - break; + case 0x4b: + dev->pci_conf[addr] = val & 0x0f; + break; - case 0x4c: - dev->pci_conf[addr] = val; - break; + case 0x4c: + dev->pci_conf[addr] = val; + break; - case 0x4d: - dev->pci_conf[addr] = val; - break; + case 0x4d: + dev->pci_conf[addr] = val; + break; - case 0x4e: - dev->pci_conf[addr] = val; - break; - case 0x4f: - dev->pci_conf[addr] = val; - break; + case 0x4e: + dev->pci_conf[addr] = val; + break; + case 0x4f: + dev->pci_conf[addr] = val; + break; - case 0x50: - dev->pci_conf[addr] = val & 0xef; - break; + case 0x50: + dev->pci_conf[addr] = val & 0xef; + break; - case 0x51: - dev->pci_conf[addr] = val; - break; + case 0x51: + dev->pci_conf[addr] = val; + break; - case 0x52: - dev->pci_conf[addr] = val & 0x9f; - break; + case 0x52: + dev->pci_conf[addr] = val & 0x9f; + break; - case 0x53: - dev->pci_conf[addr] = val; - break; + case 0x53: + dev->pci_conf[addr] = val; + break; - case 0x54: - dev->pci_conf[addr] = val & 0xb4; - break; - case 0x55: - dev->pci_conf[addr] = val & 0x01; - break; + case 0x54: + dev->pci_conf[addr] = val & 0xb4; + break; + case 0x55: + dev->pci_conf[addr] = val & 0x01; + break; - case 0x56: - dev->pci_conf[addr] = val & 0x3f; - break; + case 0x56: + dev->pci_conf[addr] = val & 0x3f; + break; - case 0x57: - dev->pci_conf[addr] = val & 0x08; - break; + case 0x57: + dev->pci_conf[addr] = val & 0x08; + break; - case 0x58: - dev->pci_conf[addr] = val; - break; + case 0x58: + dev->pci_conf[addr] = val; + break; - case 0x59: - dev->pci_conf[addr] = val; - break; + case 0x59: + dev->pci_conf[addr] = val; + break; - case 0x5a: - dev->pci_conf[addr] = val; - break; + case 0x5a: + dev->pci_conf[addr] = val; + break; - case 0x5c: - dev->pci_conf[addr] = val & 0x01; - break; + case 0x5c: + dev->pci_conf[addr] = val & 0x01; + break; - case 0x60: - dev->pci_conf[addr] = val; - break; + case 0x60: + dev->pci_conf[addr] = val; + break; - case 0x61: - dev->pci_conf[addr] = val; - break; + case 0x61: + dev->pci_conf[addr] = val; + break; - case 0x62: - dev->pci_conf[addr] = val; - break; + case 0x62: + dev->pci_conf[addr] = val; + break; - case 0x63: - dev->pci_conf[addr] = val; - break; + case 0x63: + dev->pci_conf[addr] = val; + break; - case 0x64: - dev->pci_conf[addr] = val & 0xb7; - break; - case 0x65: - dev->pci_conf[addr] = val & 0x01; - break; + case 0x64: + dev->pci_conf[addr] = val & 0xb7; + break; + case 0x65: + dev->pci_conf[addr] = val & 0x01; + break; - case 0x66: - dev->pci_conf[addr] &= ~(val & 0x33); - break; + case 0x66: + dev->pci_conf[addr] &= ~(val & 0x33); + break; - case 0x67: - dev->pci_conf[addr] = val; - break; + case 0x67: + dev->pci_conf[addr] = val; + break; - case 0x68: - dev->pci_conf[addr] = val; - break; + case 0x68: + dev->pci_conf[addr] = val; + break; - case 0x69: - dev->pci_conf[addr] = val; - break; + case 0x69: + dev->pci_conf[addr] = val; + break; - case 0x6c ... 0x7b: - /* Bits 22:20 = DRAM Row size: - - 000: 4 MB; - - 001: 8 MB; - - 010: 16 MB; - - 011: 32 MB; - - 100: 64 MB; - - 101: 128 MB; - - 110: 256 MB; - - 111: Reserved. */ - dev->pci_conf[addr] = val; - spd_write_drbs_ali1621(dev->pci_conf, 0x6c, 0x7b); - break; + case 0x6c ... 0x7b: + /* Bits 22:20 = DRAM Row size: + - 000: 4 MB; + - 001: 8 MB; + - 010: 16 MB; + - 011: 32 MB; + - 100: 64 MB; + - 101: 128 MB; + - 110: 256 MB; + - 111: Reserved. */ + dev->pci_conf[addr] = val; + spd_write_drbs_ali1621(dev->pci_conf, 0x6c, 0x7b); + break; - case 0x7c ... 0x7f: - dev->pci_conf[addr] = val; - break; + case 0x7c ... 0x7f: + dev->pci_conf[addr] = val; + break; - case 0x80: - dev->pci_conf[addr] = val; - break; - case 0x81: - dev->pci_conf[addr] = val & 0xdf; - break; + case 0x80: + dev->pci_conf[addr] = val; + break; + case 0x81: + dev->pci_conf[addr] = val & 0xdf; + break; - case 0x82: - dev->pci_conf[addr] = val & 0xf7; - break; + case 0x82: + dev->pci_conf[addr] = val & 0xf7; + break; - case 0x83: - dev->pci_conf[addr] = val & 0xfc; - ali1621_smram_recalc(val & 0xfc, dev); - break; + case 0x83: + dev->pci_conf[addr] = val & 0xfc; + ali1621_smram_recalc(val & 0xfc, dev); + break; - case 0x84 ... 0x87: - if (addr == 0x87) - dev->pci_conf[addr] = val & 0x3f; - else - dev->pci_conf[addr] = val; - ali1621_shadow_recalc(val, dev); - break; + case 0x84 ... 0x87: + if (addr == 0x87) + dev->pci_conf[addr] = val & 0x3f; + else + dev->pci_conf[addr] = val; + ali1621_shadow_recalc(val, dev); + break; - case 0x88: case 0x89: - dev->pci_conf[addr] = val; - break; - case 0x8a: - dev->pci_conf[addr] = val & 0xc5; - break; - case 0x8b: - dev->pci_conf[addr] = val & 0xbf; - break; + case 0x88: + case 0x89: + dev->pci_conf[addr] = val; + break; + case 0x8a: + dev->pci_conf[addr] = val & 0xc5; + break; + case 0x8b: + dev->pci_conf[addr] = val & 0xbf; + break; - case 0x8c ... 0x8f: - dev->pci_conf[addr] = val; - break; + case 0x8c ... 0x8f: + dev->pci_conf[addr] = val; + break; - case 0x90: - dev->pci_conf[addr] = val; - break; - case 0x91: - dev->pci_conf[addr] = val & 0x07; - break; + case 0x90: + dev->pci_conf[addr] = val; + break; + case 0x91: + dev->pci_conf[addr] = val & 0x07; + break; - case 0x94 ... 0x97: - dev->pci_conf[addr] = val; - break; + case 0x94 ... 0x97: + dev->pci_conf[addr] = val; + break; - case 0x98 ... 0x9b: - dev->pci_conf[addr] = val; - break; + case 0x98 ... 0x9b: + dev->pci_conf[addr] = val; + break; - case 0x9c ... 0x9f: - dev->pci_conf[addr] = val; - break; + case 0x9c ... 0x9f: + dev->pci_conf[addr] = val; + break; - case 0xa0: case 0xa1: - dev->pci_conf[addr] = val; - break; + case 0xa0: + case 0xa1: + dev->pci_conf[addr] = val; + break; - case 0xbc: - dev->pci_conf[addr] = val & 0x0f; - ali1621_mask_bar(dev); - break; - case 0xbd: - dev->pci_conf[addr] = val & 0xf0; - break; - case 0xbe: case 0xbf: - dev->pci_conf[addr] = val; - break; + case 0xbc: + dev->pci_conf[addr] = val & 0x0f; + ali1621_mask_bar(dev); + break; + case 0xbd: + dev->pci_conf[addr] = val & 0xf0; + break; + case 0xbe: + case 0xbf: + dev->pci_conf[addr] = val; + break; - case 0xc0: - dev->pci_conf[addr] = val & 0xb1; - break; + case 0xc0: + dev->pci_conf[addr] = val & 0xb1; + break; - case 0xc4 ... 0xc7: - dev->pci_conf[addr] = val; - break; + case 0xc4 ... 0xc7: + dev->pci_conf[addr] = val; + break; - case 0xc8: - dev->pci_conf[addr] = val & 0x8c; - break; - case 0xc9: - dev->pci_conf[addr] = val; - break; - case 0xca: - dev->pci_conf[addr] = val & 0x7f; - break; - case 0xcb: - dev->pci_conf[addr] = val & 0x87; - break; + case 0xc8: + dev->pci_conf[addr] = val & 0x8c; + break; + case 0xc9: + dev->pci_conf[addr] = val; + break; + case 0xca: + dev->pci_conf[addr] = val & 0x7f; + break; + case 0xcb: + dev->pci_conf[addr] = val & 0x87; + break; - case 0xcc ... 0xcf: - dev->pci_conf[addr] = val; - break; + case 0xcc ... 0xcf: + dev->pci_conf[addr] = val; + break; - case 0xd0: - dev->pci_conf[addr] = val & 0x80; - break; - case 0xd2: - dev->pci_conf[addr] = val & 0x40; - break; - case 0xd3: - dev->pci_conf[addr] = val & 0xb0; - break; + case 0xd0: + dev->pci_conf[addr] = val & 0x80; + break; + case 0xd2: + dev->pci_conf[addr] = val & 0x40; + break; + case 0xd3: + dev->pci_conf[addr] = val & 0xb0; + break; - case 0xd4: - dev->pci_conf[addr] = val; - break; - case 0xd5: - dev->pci_conf[addr] = val & 0xef; - break; - case 0xd6: case 0xd7: - dev->pci_conf[addr] = val; - break; + case 0xd4: + dev->pci_conf[addr] = val; + break; + case 0xd5: + dev->pci_conf[addr] = val & 0xef; + break; + case 0xd6: + case 0xd7: + dev->pci_conf[addr] = val; + break; - case 0xf0 ... 0xff: - dev->pci_conf[addr] = val; - break; + case 0xf0 ... 0xff: + dev->pci_conf[addr] = val; + break; } } - static uint8_t ali1621_read(int func, int addr, void *priv) { - ali1621_t *dev = (ali1621_t *)priv; - uint8_t ret = 0xff; + ali1621_t *dev = (ali1621_t *) priv; + uint8_t ret = 0xff; ret = dev->pci_conf[addr]; return ret; } - static void ali1621_reset(void *priv) { - ali1621_t *dev = (ali1621_t *)priv; - int i; + ali1621_t *dev = (ali1621_t *) priv; + int i; /* Default Registers */ dev->pci_conf[0x00] = 0xb9; @@ -636,14 +631,13 @@ ali1621_reset(void *priv) ali1621_write(0, 0x83, 0x08, dev); for (i = 0; i < 4; i++) - ali1621_write(0, 0x84 + i, 0x00, dev); + ali1621_write(0, 0x84 + i, 0x00, dev); } - static void ali1621_close(void *priv) { - ali1621_t *dev = (ali1621_t *)priv; + ali1621_t *dev = (ali1621_t *) priv; smram_del(dev->smram[1]); smram_del(dev->smram[0]); @@ -651,11 +645,10 @@ ali1621_close(void *priv) free(dev); } - static void * ali1621_init(const device_t *info) { - ali1621_t *dev = (ali1621_t *)malloc(sizeof(ali1621_t)); + ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t)); memset(dev, 0, sizeof(ali1621_t)); pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev); @@ -671,15 +664,15 @@ ali1621_init(const device_t *info) } const device_t ali1621_device = { - .name = "ALi M1621 CPU-to-PCI Bridge", + .name = "ALi M1621 CPU-to-PCI Bridge", .internal_name = "ali1621", - .flags = DEVICE_PCI, - .local = 0, - .init = ali1621_init, - .close = ali1621_close, - .reset = ali1621_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = ali1621_init, + .close = ali1621_close, + .reset = ali1621_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ali6117.c b/src/chipset/ali6117.c index 612970e45..8f1b38627 100644 --- a/src/chipset/ali6117.c +++ b/src/chipset/ali6117.c @@ -35,18 +35,15 @@ #include <86box/hdc_ide.h> #include <86box/chipset.h> - -typedef struct ali6117_t -{ - uint32_t local; +typedef struct ali6117_t { + uint32_t local; /* Main registers (port 22h/23h) */ - uint8_t unlocked, mode; - uint8_t reg_offset; - uint8_t regs[256]; + uint8_t unlocked, mode; + uint8_t reg_offset; + uint8_t regs[256]; } ali6117_t; - /* Total size, Bank 0 size, Bank 1 size, Bank 2 size, Bank 3 size. */ static uint32_t ali6117_modes[32][5] = { { 1024, 512, 512, 0, 0 }, @@ -83,7 +80,6 @@ static uint32_t ali6117_modes[32][5] = { { 65536, 32768, 32768, 0, 0 } }; - #ifdef ENABLE_ALI6117_LOG int ali6117_do_log = ENABLE_ALI6117_LOG; @@ -93,108 +89,105 @@ ali6117_log(const char *fmt, ...) va_list ap; if (ali6117_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define ali6117_log(fmt, ...) +# define ali6117_log(fmt, ...) #endif - static void ali6117_recalcmapping(ali6117_t *dev) { - uint8_t reg, bitpair; + uint8_t reg, bitpair; uint32_t base, size; - int state; + int state; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; ali6117_log("ALI6117: Shadowing for A0000-BFFFF (reg 12 bit 1) = %s\n", (dev->regs[0x12] & 0x02) ? "on" : "off"); mem_set_mem_state(0xa0000, 0x20000, (dev->regs[0x12] & 0x02) ? (MEM_WRITE_INTERNAL | MEM_READ_INTERNAL) : (MEM_WRITE_EXTANY | MEM_READ_EXTANY)); for (reg = 0; reg <= 1; reg++) { - for (bitpair = 0; bitpair <= 3; bitpair++) { - size = 0x8000; - base = 0xc0000 + (size * ((reg * 4) + bitpair)); - ali6117_log("ALI6117: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x14 + reg, bitpair, 1 << ((bitpair * 2) + 1), 1 << (bitpair * 2)); + for (bitpair = 0; bitpair <= 3; bitpair++) { + size = 0x8000; + base = 0xc0000 + (size * ((reg * 4) + bitpair)); + ali6117_log("ALI6117: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x14 + reg, bitpair, 1 << ((bitpair * 2) + 1), 1 << (bitpair * 2)); - state = 0; - if (dev->regs[0x14 + reg] & (1 << ((bitpair * 2) + 1))) { - ali6117_log(" w on"); - state |= MEM_WRITE_INTERNAL; - if (base >= 0xe0000) - shadowbios_write |= 1; - } else { - ali6117_log(" w off"); - state |= MEM_WRITE_EXTANY; - } - if (dev->regs[0x14 + reg] & (1 << (bitpair * 2))) { - ali6117_log("; r on\n"); - state |= MEM_READ_INTERNAL; - if (base >= 0xe0000) - shadowbios |= 1; - } else { - ali6117_log("; r off\n"); - state |= MEM_READ_EXTANY; - } + state = 0; + if (dev->regs[0x14 + reg] & (1 << ((bitpair * 2) + 1))) { + ali6117_log(" w on"); + state |= MEM_WRITE_INTERNAL; + if (base >= 0xe0000) + shadowbios_write |= 1; + } else { + ali6117_log(" w off"); + state |= MEM_WRITE_EXTANY; + } + if (dev->regs[0x14 + reg] & (1 << (bitpair * 2))) { + ali6117_log("; r on\n"); + state |= MEM_READ_INTERNAL; + if (base >= 0xe0000) + shadowbios |= 1; + } else { + ali6117_log("; r off\n"); + state |= MEM_READ_EXTANY; + } - mem_set_mem_state(base, size, state); - } + mem_set_mem_state(base, size, state); + } } flushmmucache_nopc(); } - static void ali6117_bank_recalc(ali6117_t *dev) { - int i; + int i; uint32_t bank, addr; for (i = 0x00000000; i < (mem_size << 10); i += 4096) { - if ((i >= 0x000a0000) && (i < 0x00100000)) - continue; + if ((i >= 0x000a0000) && (i < 0x00100000)) + continue; - if (!is6117 && (i >= 0x00f00000) && (i < 0x01000000)) - continue; + if (!is6117 && (i >= 0x00f00000) && (i < 0x01000000)) + continue; - if (is6117 && (i >= 0x03f00000) && (i < 0x04000000)) - continue; + if (is6117 && (i >= 0x03f00000) && (i < 0x04000000)) + continue; - switch (dev->regs[0x10] & 0xf8) { - case 0xe8: - bank = (i >> 12) & 3; - addr = (i & 0xfff) | ((i >> 14) << 12); - ali6117_log("E8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024); - if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024)) - mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 0xf8: - bank = (i >> 12) & 1; - addr = (i & 0xfff) | ((i >> 13) << 12); - ali6117_log("F8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024); - if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024)) - mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - default: - mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } + switch (dev->regs[0x10] & 0xf8) { + case 0xe8: + bank = (i >> 12) & 3; + addr = (i & 0xfff) | ((i >> 14) << 12); + ali6117_log("E8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024); + if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024)) + mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 0xf8: + bank = (i >> 12) & 1; + addr = (i & 0xfff) | ((i >> 13) << 12); + ali6117_log("F8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024); + if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024)) + mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + default: + mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + } } flushmmucache(); } - static void ali6117_reg_write(uint16_t addr, uint8_t val, void *priv) { @@ -203,194 +196,202 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv) ali6117_log("ALI6117: reg_write(%04X, %02X)\n", addr, val); if (addr == 0x22) - dev->reg_offset = val; + dev->reg_offset = val; else if (dev->reg_offset == 0x13) - dev->unlocked = (val == 0xc5); + dev->unlocked = (val == 0xc5); else if (dev->unlocked) { - ali6117_log("ALI6117: regs[%02X] = %02X\n", dev->reg_offset, val); + ali6117_log("ALI6117: regs[%02X] = %02X\n", dev->reg_offset, val); - if (!(dev->local & 0x08) || (dev->reg_offset < 0x30)) switch (dev->reg_offset) { - case 0x30: case 0x34: case 0x35: case 0x3e: - case 0x3f: case 0x46: case 0x4c: case 0x6a: - case 0x73: - return; /* read-only registers */ + if (!(dev->local & 0x08) || (dev->reg_offset < 0x30)) + switch (dev->reg_offset) { + case 0x30: + case 0x34: + case 0x35: + case 0x3e: + case 0x3f: + case 0x46: + case 0x4c: + case 0x6a: + case 0x73: + return; /* read-only registers */ - case 0x10: - refresh_at_enable = !(val & 0x02) || !!(dev->regs[0x20] & 0x80); - dev->regs[dev->reg_offset] = val; + case 0x10: + refresh_at_enable = !(val & 0x02) || !!(dev->regs[0x20] & 0x80); + dev->regs[dev->reg_offset] = val; - if (dev->local != 0x8) { - if (val & 0x04) - mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - else - mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + if (dev->local != 0x8) { + if (val & 0x04) + mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + else + mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - ali6117_bank_recalc(dev); - } - break; + ali6117_bank_recalc(dev); + } + break; - case 0x12: - val &= 0xf7; - /* FALL-THROUGH */ + case 0x12: + val &= 0xf7; + /* FALL-THROUGH */ - case 0x14: case 0x15: - dev->regs[dev->reg_offset] = val; - ali6117_recalcmapping(dev); - break; + case 0x14: + case 0x15: + dev->regs[dev->reg_offset] = val; + ali6117_recalcmapping(dev); + break; - case 0x1e: - val &= 0x07; + case 0x1e: + val &= 0x07; - switch (val) { - /* Half PIT clock. */ - case 0x0: - cpu_set_isa_speed(7159091); - break; + switch (val) { + /* Half PIT clock. */ + case 0x0: + cpu_set_isa_speed(7159091); + break; - /* Divisors on the input clock PCLK2, which is double the CPU clock. */ - case 0x1: - cpu_set_isa_speed(cpu_busspeed / 1.5); - break; + /* Divisors on the input clock PCLK2, which is double the CPU clock. */ + case 0x1: + cpu_set_isa_speed(cpu_busspeed / 1.5); + break; - case 0x2: - cpu_set_isa_speed(cpu_busspeed / 2); - break; + case 0x2: + cpu_set_isa_speed(cpu_busspeed / 2); + break; - case 0x3: - cpu_set_isa_speed(cpu_busspeed / 2.5); - break; + case 0x3: + cpu_set_isa_speed(cpu_busspeed / 2.5); + break; - case 0x4: - cpu_set_isa_speed(cpu_busspeed / 3); - break; + case 0x4: + cpu_set_isa_speed(cpu_busspeed / 3); + break; - case 0x5: - cpu_set_isa_speed(cpu_busspeed / 4); - break; + case 0x5: + cpu_set_isa_speed(cpu_busspeed / 4); + break; - case 0x6: - cpu_set_isa_speed(cpu_busspeed / 5); - break; + case 0x6: + cpu_set_isa_speed(cpu_busspeed / 5); + break; - case 0x7: - cpu_set_isa_speed(cpu_busspeed / 6); - break; - } - break; + case 0x7: + cpu_set_isa_speed(cpu_busspeed / 6); + break; + } + break; - case 0x20: - val &= 0xbf; - refresh_at_enable = !(dev->regs[0x10] & 0x02) || !!(val & 0x80); - break; + case 0x20: + val &= 0xbf; + refresh_at_enable = !(dev->regs[0x10] & 0x02) || !!(val & 0x80); + break; - case 0x31: - /* TODO: fast gate A20 (bit 0) */ - val &= 0x21; - break; + case 0x31: + /* TODO: fast gate A20 (bit 0) */ + val &= 0x21; + break; - case 0x32: - val &= 0xc1; - break; + case 0x32: + val &= 0xc1; + break; - case 0x33: - val &= 0xfd; - break; + case 0x33: + val &= 0xfd; + break; - case 0x36: - val &= 0xf0; - val |= dev->regs[dev->reg_offset]; - break; + case 0x36: + val &= 0xf0; + val |= dev->regs[dev->reg_offset]; + break; - case 0x37: - val &= 0xf5; - break; + case 0x37: + val &= 0xf5; + break; - case 0x3c: - val &= 0x8f; - ide_pri_disable(); - ide_set_base(1, (val & 0x01) ? 0x170 : 0x1f0); - ide_set_side(1, (val & 0x01) ? 0x376 : 0x3f6); - ide_pri_enable(); - break; + case 0x3c: + val &= 0x8f; + ide_pri_disable(); + ide_set_base(1, (val & 0x01) ? 0x170 : 0x1f0); + ide_set_side(1, (val & 0x01) ? 0x376 : 0x3f6); + ide_pri_enable(); + break; - case 0x44: case 0x45: - val &= 0x3f; - break; + case 0x44: + case 0x45: + val &= 0x3f; + break; - case 0x4a: - val &= 0xfe; - break; + case 0x4a: + val &= 0xfe; + break; - case 0x55: - val &= 0x03; - break; + case 0x55: + val &= 0x03; + break; - case 0x56: - val &= 0xc7; - break; + case 0x56: + val &= 0xc7; + break; - case 0x58: - val &= 0xc3; - break; + case 0x58: + val &= 0xc3; + break; - case 0x59: - val &= 0x60; - break; + case 0x59: + val &= 0x60; + break; - case 0x5b: - val &= 0x1f; - break; + case 0x5b: + val &= 0x1f; + break; - case 0x64: - val &= 0xf7; - break; + case 0x64: + val &= 0xf7; + break; - case 0x66: - val &= 0xe3; - break; + case 0x66: + val &= 0xe3; + break; - case 0x67: - val &= 0xdf; - break; + case 0x67: + val &= 0xdf; + break; - case 0x69: - val &= 0x50; - break; + case 0x69: + val &= 0x50; + break; - case 0x6b: - val &= 0x7f; - break; + case 0x6b: + val &= 0x7f; + break; - case 0x6e: case 0x6f: - val &= 0x03; - break; + case 0x6e: + case 0x6f: + val &= 0x03; + break; - case 0x71: - val &= 0x1f; - break; - } + case 0x71: + val &= 0x1f; + break; + } - dev->regs[dev->reg_offset] = val; + dev->regs[dev->reg_offset] = val; } } - static uint8_t ali6117_reg_read(uint16_t addr, void *priv) { ali6117_t *dev = (ali6117_t *) priv; - uint8_t ret; + uint8_t ret; if (addr == 0x22) - ret = dev->reg_offset; + ret = dev->reg_offset; else - ret = dev->regs[dev->reg_offset]; + ret = dev->regs[dev->reg_offset]; ali6117_log("ALI6117: reg_read(%04X) = %02X\n", dev->reg_offset, ret); return ret; } - static void ali6117_reset(void *priv) { @@ -408,11 +409,11 @@ ali6117_reset(void *priv) dev->regs[0x1d] = 0xff; dev->regs[0x20] = 0x80; if (dev->local & 0x08) { - dev->regs[0x30] = 0x08; - dev->regs[0x31] = 0x01; - dev->regs[0x34] = 0x04; /* enable internal RTC */ - dev->regs[0x35] = 0x20; /* enable internal KBC */ - dev->regs[0x36] = dev->local & 0x07; /* M6117D ID */ + dev->regs[0x30] = 0x08; + dev->regs[0x31] = 0x01; + dev->regs[0x34] = 0x04; /* enable internal RTC */ + dev->regs[0x35] = 0x20; /* enable internal KBC */ + dev->regs[0x36] = dev->local & 0x07; /* M6117D ID */ } cpu_set_isa_speed(7159091); @@ -420,13 +421,12 @@ ali6117_reset(void *priv) refresh_at_enable = 1; if (dev->local != 0x8) { - /* On-board memory 15-16M is enabled by default. */ - mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - ali6117_bank_recalc(dev); + /* On-board memory 15-16M is enabled by default. */ + mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + ali6117_bank_recalc(dev); } } - static void ali6117_setup(ali6117_t *dev) { @@ -434,10 +434,9 @@ ali6117_setup(ali6117_t *dev) /* Main register interface */ io_sethandler(0x22, 2, - ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev); + ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev); } - static void ali6117_close(void *priv) { @@ -446,12 +445,11 @@ ali6117_close(void *priv) ali6117_log("ALI6117: close()\n"); io_removehandler(0x22, 2, - ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev); + ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev); free(dev); } - static void * ali6117_init(const device_t *info) { @@ -469,44 +467,44 @@ ali6117_init(const device_t *info) ali6117_setup(dev); for (i = 31; i >= 0; i--) { - if ((mem_size >= ali6117_modes[i][0]) && (ali6117_modes[i][0] > last_match)) { - last_match = ali6117_modes[i][0]; - dev->mode = i; - } + if ((mem_size >= ali6117_modes[i][0]) && (ali6117_modes[i][0] > last_match)) { + last_match = ali6117_modes[i][0]; + dev->mode = i; + } } ali6117_reset(dev); if (!(dev->local & 0x08)) - pic_elcr_io_handler(0); + pic_elcr_io_handler(0); return dev; } const device_t ali1217_device = { - .name = "ALi M1217", + .name = "ALi M1217", .internal_name = "ali1217", - .flags = DEVICE_AT, - .local = 0x8, - .init = ali6117_init, - .close = ali6117_close, - .reset = ali6117_reset, + .flags = DEVICE_AT, + .local = 0x8, + .init = ali6117_init, + .close = ali6117_close, + .reset = ali6117_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t ali6117d_device = { - .name = "ALi M6117D", + .name = "ALi M6117D", .internal_name = "ali6117d", - .flags = DEVICE_AT, - .local = 0x2, - .init = ali6117_init, - .close = ali6117_close, - .reset = ali6117_reset, + .flags = DEVICE_AT, + .local = 0x2, + .init = ali6117_init, + .close = ali6117_close, + .reset = ali6117_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/contaq_82c59x.c b/src/chipset/contaq_82c59x.c index 97c8716eb..b724cbf4b 100644 --- a/src/chipset/contaq_82c59x.c +++ b/src/chipset/contaq_82c59x.c @@ -29,7 +29,6 @@ #include <86box/smram.h> #include <86box/chipset.h> - #ifdef ENABLE_CONTAQ_82C59X_LOG int contaq_82c59x_do_log = ENABLE_CONTAQ_82C59X_LOG; @@ -38,274 +37,268 @@ contaq_82c59x_log(const char *fmt, ...) { va_list ap; - if (contaq_82c59x_do_log) - { + if (contaq_82c59x_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define contaq_82c59x_log(fmt, ...) +# define contaq_82c59x_log(fmt, ...) #endif - typedef struct { - uint32_t phys, virt; + uint32_t phys, virt; } mem_remapping_t; - typedef struct { - uint8_t index, green, - smi_status_set, - regs[256], smi_status[2]; + uint8_t index, green, + smi_status_set, + regs[256], smi_status[2]; - smram_t *smram[2]; + smram_t *smram[2]; } contaq_82c59x_t; - static void contaq_82c59x_isa_speed_recalc(contaq_82c59x_t *dev) { if (dev->regs[0x1c] & 0x02) - cpu_set_isa_speed(7159091); + cpu_set_isa_speed(7159091); else { - /* TODO: ISA clock dividers for 386 and alt. 486. */ - switch (dev->regs[0x10] & 0x03) { - case 0x00: - cpu_set_isa_speed(cpu_busspeed / 4); - break; - case 0x01: - cpu_set_isa_speed(cpu_busspeed / 6); - break; - case 0x02: - cpu_set_isa_speed(cpu_busspeed / 8); - break; - case 0x03: - cpu_set_isa_speed(cpu_busspeed / 5); - break; - } + /* TODO: ISA clock dividers for 386 and alt. 486. */ + switch (dev->regs[0x10] & 0x03) { + case 0x00: + cpu_set_isa_speed(cpu_busspeed / 4); + break; + case 0x01: + cpu_set_isa_speed(cpu_busspeed / 6); + break; + case 0x02: + cpu_set_isa_speed(cpu_busspeed / 8); + break; + case 0x03: + cpu_set_isa_speed(cpu_busspeed / 5); + break; + } } } - static void contaq_82c59x_shadow_recalc(contaq_82c59x_t *dev) { uint32_t i, base; - uint8_t bit; + uint8_t bit; shadowbios = shadowbios_write = 0; /* F0000-FFFFF */ if (dev->regs[0x15] & 0x80) { - shadowbios |= 1; - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + shadowbios |= 1; + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); } else { - shadowbios_write |= 1; - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + shadowbios_write |= 1; + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); } /* C0000-CFFFF */ if (dev->regs[0x15] & 0x01) - mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); else { - for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); - bit = 1 << (i + 2); - if (dev->regs[0x15] & bit) { - if (dev->regs[0x15] & 0x02) - mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); - else - mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); - } else - mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); - } + for (i = 0; i < 4; i++) { + base = 0xc0000 + (i << 14); + bit = 1 << (i + 2); + if (dev->regs[0x15] & bit) { + if (dev->regs[0x15] & 0x02) + mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); + else + mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); + } else + mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + } } if (dev->green) { - /* D0000-DFFFF */ - if (dev->regs[0x6e] & 0x01) - mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - else { - for (i = 0; i < 4; i++) { - base = 0xd0000 + (i << 14); - bit = 1 << (i + 2); - if (dev->regs[0x6e] & bit) { - if (dev->regs[0x6e] & 0x02) - mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); - else - mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } else - mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); - } - } + /* D0000-DFFFF */ + if (dev->regs[0x6e] & 0x01) + mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + else { + for (i = 0; i < 4; i++) { + base = 0xd0000 + (i << 14); + bit = 1 << (i + 2); + if (dev->regs[0x6e] & bit) { + if (dev->regs[0x6e] & 0x02) + mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); + else + mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } else + mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + } + } - /* E0000-EFFFF */ - if (dev->regs[0x6f] & 0x01) - mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - else { - for (i = 0; i < 4; i++) { - base = 0xe0000 + (i << 14); - bit = 1 << (i + 2); - if (dev->regs[0x6f] & bit) { - shadowbios |= 1; - if (dev->regs[0x6f] & 0x02) - mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); - else { - shadowbios_write |= 1; - mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - } else - mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); - } - } + /* E0000-EFFFF */ + if (dev->regs[0x6f] & 0x01) + mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + else { + for (i = 0; i < 4; i++) { + base = 0xe0000 + (i << 14); + bit = 1 << (i + 2); + if (dev->regs[0x6f] & bit) { + shadowbios |= 1; + if (dev->regs[0x6f] & 0x02) + mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); + else { + shadowbios_write |= 1; + mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + } else + mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + } + } } } - static void contaq_82c59x_smram_recalc(contaq_82c59x_t *dev) { smram_disable(dev->smram[1]); if (dev->regs[0x70] & 0x04) - smram_enable(dev->smram[1], 0x00040000, 0x000a0000, 0x00020000, 1, 1); + smram_enable(dev->smram[1], 0x00040000, 0x000a0000, 0x00020000, 1, 1); } - static void contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv) { - contaq_82c59x_t *dev = (contaq_82c59x_t *)priv; + contaq_82c59x_t *dev = (contaq_82c59x_t *) priv; switch (addr) { - case 0x22: - dev->index = val; - break; + case 0x22: + dev->index = val; + break; - case 0x23: - contaq_82c59x_log("Contaq 82C59x: dev->regs[%02x] = %02x\n", dev->index, val); + case 0x23: + contaq_82c59x_log("Contaq 82C59x: dev->regs[%02x] = %02x\n", dev->index, val); - if ((dev->index >= 0x60) && !dev->green) - return; + if ((dev->index >= 0x60) && !dev->green) + return; - switch (dev->index) { - /* Registers common to 82C596(A) and 82C597. */ - case 0x10: - dev->regs[dev->index] = val; - contaq_82c59x_isa_speed_recalc(dev); - break; + switch (dev->index) { + /* Registers common to 82C596(A) and 82C597. */ + case 0x10: + dev->regs[dev->index] = val; + contaq_82c59x_isa_speed_recalc(dev); + break; - case 0x11: - dev->regs[dev->index] = val; - cpu_cache_int_enabled = !!(val & 0x01); - cpu_update_waitstates(); - break; + case 0x11: + dev->regs[dev->index] = val; + cpu_cache_int_enabled = !!(val & 0x01); + cpu_update_waitstates(); + break; - case 0x12: case 0x13: - dev->regs[dev->index] = val; - break; + case 0x12: + case 0x13: + dev->regs[dev->index] = val; + break; - case 0x14: - dev->regs[dev->index] = val; - reset_on_hlt = !!(val & 0x80); - break; + case 0x14: + dev->regs[dev->index] = val; + reset_on_hlt = !!(val & 0x80); + break; - case 0x15: - dev->regs[dev->index] = val; - contaq_82c59x_shadow_recalc(dev); - break; + case 0x15: + dev->regs[dev->index] = val; + contaq_82c59x_shadow_recalc(dev); + break; - case 0x16 ... 0x1b: - dev->regs[dev->index] = val; - break; + case 0x16 ... 0x1b: + dev->regs[dev->index] = val; + break; - case 0x1c: - /* TODO: What's NPRST (generated if bit 3 is set)? */ - dev->regs[dev->index] = val; - contaq_82c59x_isa_speed_recalc(dev); - break; + case 0x1c: + /* TODO: What's NPRST (generated if bit 3 is set)? */ + dev->regs[dev->index] = val; + contaq_82c59x_isa_speed_recalc(dev); + break; - case 0x1d ... 0x1f: - dev->regs[dev->index] = val; - break; + case 0x1d ... 0x1f: + dev->regs[dev->index] = val; + break; - /* Green (82C597-specific) registers. */ - case 0x60 ... 0x63: - dev->regs[dev->index] = val; - break; + /* Green (82C597-specific) registers. */ + case 0x60 ... 0x63: + dev->regs[dev->index] = val; + break; - case 0x64: - dev->regs[dev->index] = val; - if (val & 0x80) { - if (dev->regs[0x65] & 0x80) - smi_raise(); - dev->smi_status[0] |= 0x10; - } - break; + case 0x64: + dev->regs[dev->index] = val; + if (val & 0x80) { + if (dev->regs[0x65] & 0x80) + smi_raise(); + dev->smi_status[0] |= 0x10; + } + break; - case 0x65 ... 0x69: - dev->regs[dev->index] = val; - break; + case 0x65 ... 0x69: + dev->regs[dev->index] = val; + break; - case 0x6a: - dev->regs[dev->index] = val; - dev->smi_status_set = !!(val & 0x80); - break; + case 0x6a: + dev->regs[dev->index] = val; + dev->smi_status_set = !!(val & 0x80); + break; - case 0x6b ... 0x6d: - dev->regs[dev->index] = val; - break; + case 0x6b ... 0x6d: + dev->regs[dev->index] = val; + break; - case 0x6e: case 0x6f: - dev->regs[dev->index] = val; - contaq_82c59x_shadow_recalc(dev); - break; + case 0x6e: + case 0x6f: + dev->regs[dev->index] = val; + contaq_82c59x_shadow_recalc(dev); + break; - case 0x70: - dev->regs[dev->index] = val; - contaq_82c59x_smram_recalc(dev); - break; + case 0x70: + dev->regs[dev->index] = val; + contaq_82c59x_smram_recalc(dev); + break; - case 0x71 ... 0x79: - dev->regs[dev->index] = val; - break; + case 0x71 ... 0x79: + dev->regs[dev->index] = val; + break; - case 0x7b: case 0x7c: - dev->regs[dev->index] = val; - break; - } - break; + case 0x7b: + case 0x7c: + dev->regs[dev->index] = val; + break; + } + break; } } - static uint8_t contaq_82c59x_read(uint16_t addr, void *priv) { - contaq_82c59x_t *dev = (contaq_82c59x_t *)priv; - uint8_t ret = 0xff; + contaq_82c59x_t *dev = (contaq_82c59x_t *) priv; + uint8_t ret = 0xff; if (addr == 0x23) { - if (dev->index == 0x6a) { - ret = dev->smi_status[dev->smi_status_set]; - /* I assume it's cleared on read. */ - dev->smi_status[dev->smi_status_set] = 0x00; - } else - ret = dev->regs[dev->index]; + if (dev->index == 0x6a) { + ret = dev->smi_status[dev->smi_status_set]; + /* I assume it's cleared on read. */ + dev->smi_status[dev->smi_status_set] = 0x00; + } else + ret = dev->regs[dev->index]; } return ret; } - static void contaq_82c59x_close(void *priv) { - contaq_82c59x_t *dev = (contaq_82c59x_t *)priv; + contaq_82c59x_t *dev = (contaq_82c59x_t *) priv; smram_del(dev->smram[1]); smram_del(dev->smram[0]); @@ -313,11 +306,10 @@ contaq_82c59x_close(void *priv) free(dev); } - static void * contaq_82c59x_init(const device_t *info) { - contaq_82c59x_t *dev = (contaq_82c59x_t *)malloc(sizeof(contaq_82c59x_t)); + contaq_82c59x_t *dev = (contaq_82c59x_t *) malloc(sizeof(contaq_82c59x_t)); memset(dev, 0x00, sizeof(contaq_82c59x_t)); dev->green = info->local; @@ -334,42 +326,42 @@ contaq_82c59x_init(const device_t *info) contaq_82c59x_shadow_recalc(dev); if (dev->green) { - /* SMRAM 0: Fixed A0000-BFFFF to A0000-BFFFF DRAM. */ - dev->smram[0] = smram_add(); - smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x00020000, 0, 1); + /* SMRAM 0: Fixed A0000-BFFFF to A0000-BFFFF DRAM. */ + dev->smram[0] = smram_add(); + smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x00020000, 0, 1); - /* SMRAM 1: Optional. */ - dev->smram[1] = smram_add(); - contaq_82c59x_smram_recalc(dev); + /* SMRAM 1: Optional. */ + dev->smram[1] = smram_add(); + contaq_82c59x_smram_recalc(dev); } return dev; } const device_t contaq_82c596a_device = { - .name = "Contaq 82C596A", + .name = "Contaq 82C596A", .internal_name = "contaq_82c596a", - .flags = 0, - .local = 0, - .init = contaq_82c59x_init, - .close = contaq_82c59x_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = contaq_82c59x_init, + .close = contaq_82c59x_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t contaq_82c597_device = { - .name = "Contaq 82C597", + .name = "Contaq 82C597", .internal_name = "contaq_82c597", - .flags = 0, - .local = 1, - .init = contaq_82c59x_init, - .close = contaq_82c59x_close, - .reset = NULL, + .flags = 0, + .local = 1, + .init = contaq_82c59x_init, + .close = contaq_82c59x_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/cs4031.c b/src/chipset/cs4031.c index d5970b048..6eddc8cad 100644 --- a/src/chipset/cs4031.c +++ b/src/chipset/cs4031.c @@ -46,107 +46,104 @@ cs4031_log(const char *fmt, ...) { va_list ap; - if (cs4031_do_log) - { + if (cs4031_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define cs4031_log(fmt, ...) +# define cs4031_log(fmt, ...) #endif -static void cs4031_shadow_recalc(cs4031_t *dev) +static void +cs4031_shadow_recalc(cs4031_t *dev) { mem_set_mem_state_both(0xa0000, 0x10000, (dev->regs[0x18] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xb0000, 0x10000, (dev->regs[0x18] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); - for (uint32_t i = 0; i < 7; i++) - { + for (uint32_t i = 0; i < 7; i++) { if (i < 4) mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); else mem_set_mem_state_both(0xd0000 + ((i - 4) << 16), 0x10000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); } - shadowbios = !!(dev->regs[0x19] & 0x40); + shadowbios = !!(dev->regs[0x19] & 0x40); shadowbios_write = !!(dev->regs[0x1a] & 0x40); } static void cs4031_write(uint16_t addr, uint8_t val, void *priv) { - cs4031_t *dev = (cs4031_t *)priv; + cs4031_t *dev = (cs4031_t *) priv; - switch (addr) - { - case 0x22: - dev->index = val; - break; - case 0x23: - cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val); - switch (dev->index) - { - case 0x05: - dev->regs[dev->index] = val & 0x3f; + switch (addr) { + case 0x22: + dev->index = val; break; + case 0x23: + cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val); + switch (dev->index) { + case 0x05: + dev->regs[dev->index] = val & 0x3f; + break; - case 0x06: - dev->regs[dev->index] = val & 0xbc; - break; + case 0x06: + dev->regs[dev->index] = val & 0xbc; + break; - case 0x07: - dev->regs[dev->index] = val & 0x0f; - break; + case 0x07: + dev->regs[dev->index] = val & 0x0f; + break; - case 0x10: - dev->regs[dev->index] = val & 0x3d; - break; + case 0x10: + dev->regs[dev->index] = val & 0x3d; + break; - case 0x11: - dev->regs[dev->index] = val & 0x8d; - break; + case 0x11: + dev->regs[dev->index] = val & 0x8d; + break; - case 0x12: - case 0x13: - dev->regs[dev->index] = val & 0x8d; - break; + case 0x12: + case 0x13: + dev->regs[dev->index] = val & 0x8d; + break; - case 0x14: - case 0x15: - case 0x16: - case 0x17: - dev->regs[dev->index] = val & 0x7f; - break; + case 0x14: + case 0x15: + case 0x16: + case 0x17: + dev->regs[dev->index] = val & 0x7f; + break; - case 0x18: - dev->regs[dev->index] = val & 0xf3; - cs4031_shadow_recalc(dev); - break; + case 0x18: + dev->regs[dev->index] = val & 0xf3; + cs4031_shadow_recalc(dev); + break; - case 0x19: - case 0x1a: - dev->regs[dev->index] = val & 0x7f; - cs4031_shadow_recalc(dev); - break; + case 0x19: + case 0x1a: + dev->regs[dev->index] = val & 0x7f; + cs4031_shadow_recalc(dev); + break; - case 0x1b: - dev->regs[dev->index] = val; - break; + case 0x1b: + dev->regs[dev->index] = val; + break; - case 0x1c: - dev->regs[dev->index] = val & 0xb3; - port_92_set_features(dev->port_92, val & 0x10, val & 0x20); + case 0x1c: + dev->regs[dev->index] = val & 0xb3; + port_92_set_features(dev->port_92, val & 0x10, val & 0x20); + break; + } break; - } - break; } } static uint8_t cs4031_read(uint16_t addr, void *priv) { - cs4031_t *dev = (cs4031_t *)priv; + cs4031_t *dev = (cs4031_t *) priv; return (addr == 0x23) ? dev->regs[dev->index] : 0xff; } @@ -154,7 +151,7 @@ cs4031_read(uint16_t addr, void *priv) static void cs4031_close(void *priv) { - cs4031_t *dev = (cs4031_t *)priv; + cs4031_t *dev = (cs4031_t *) priv; free(dev); } @@ -162,7 +159,7 @@ cs4031_close(void *priv) static void * cs4031_init(const device_t *info) { - cs4031_t *dev = (cs4031_t *)malloc(sizeof(cs4031_t)); + cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t)); memset(dev, 0, sizeof(cs4031_t)); dev->port_92 = device_add(&port_92_device); @@ -176,15 +173,15 @@ cs4031_init(const device_t *info) } const device_t cs4031_device = { - .name = "Chips & Technogies CS4031", + .name = "Chips & Technogies CS4031", .internal_name = "cs4031", - .flags = 0, - .local = 0, - .init = cs4031_init, - .close = cs4031_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = cs4031_init, + .close = cs4031_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/cs8230.c b/src/chipset/cs8230.c index f6a77cabc..0917a3c88 100644 --- a/src/chipset/cs8230.c +++ b/src/chipset/cs8230.c @@ -29,143 +29,153 @@ #include <86box/fdc.h> #include <86box/chipset.h> - typedef struct { - int idx; - uint8_t regs[256]; + int idx; + uint8_t regs[256]; } cs8230_t; - static void shadow_control(uint32_t addr, uint32_t size, int state) { switch (state) { - case 0x00: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - case 0x01: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 0x10: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 0x11: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; + case 0x00: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + case 0x01: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 0x10: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 0x11: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; } flushmmucache_nopc(); } - static void rethink_shadow_mappings(cs8230_t *cs8230) { int c; for (c = 0; c < 32; c++) { - /* Addresses 40000-bffff in 16k blocks */ - if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7))) - mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /* I/O channel */ - else - mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /* System board */ + /* Addresses 40000-bffff in 16k blocks */ + if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /* I/O channel */ + else + mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /* System board */ } for (c = 0; c < 16; c++) { - /* Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here */ - if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7))) - mem_set_mem_state(0xc0000 + (c << 14), 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /* I/O channel */ - else - shadow_control(0xc0000 + (c << 14), 0x4000, (cs8230->regs[9] >> (3 - (c >> 2))) & 0x11); + /* Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here */ + if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0xc0000 + (c << 14), 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /* I/O channel */ + else + shadow_control(0xc0000 + (c << 14), 0x4000, (cs8230->regs[9] >> (3 - (c >> 2))) & 0x11); } } - static uint8_t cs8230_read(uint16_t port, void *p) { cs8230_t *cs8230 = (cs8230_t *) p; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (port & 1) { - switch (cs8230->idx) { - case 0x04: /* 82C301 ID/version */ - ret = cs8230->regs[cs8230->idx] & ~0xe3; - break; + switch (cs8230->idx) { + case 0x04: /* 82C301 ID/version */ + ret = cs8230->regs[cs8230->idx] & ~0xe3; + break; - case 0x08: /* 82C302 ID/Version */ - ret = cs8230->regs[cs8230->idx] & ~0xe0; - break; + case 0x08: /* 82C302 ID/Version */ + ret = cs8230->regs[cs8230->idx] & ~0xe0; + break; - case 0x05: case 0x06: /* 82C301 registers */ - case 0x09: case 0x0a: case 0x0b: case 0x0c: /* 82C302 registers */ - case 0x0d: case 0x0e: case 0x0f: - case 0x10: case 0x11: case 0x12: case 0x13: - case 0x28: case 0x29: case 0x2a: - ret = cs8230->regs[cs8230->idx]; - break; - } + case 0x05: + case 0x06: /* 82C301 registers */ + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: /* 82C302 registers */ + case 0x0d: + case 0x0e: + case 0x0f: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x28: + case 0x29: + case 0x2a: + ret = cs8230->regs[cs8230->idx]; + break; + } } return ret; } - static void cs8230_write(uint16_t port, uint8_t val, void *p) { - cs8230_t *cs8230 = (cs8230_t *)p; + cs8230_t *cs8230 = (cs8230_t *) p; if (!(port & 1)) - cs8230->idx = val; + cs8230->idx = val; else { - cs8230->regs[cs8230->idx] = val; - switch (cs8230->idx) { - case 0x09: /* RAM/ROM Configuration in boot area */ - case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /* Address maps */ - rethink_shadow_mappings(cs8230); - break; - } + cs8230->regs[cs8230->idx] = val; + switch (cs8230->idx) { + case 0x09: /* RAM/ROM Configuration in boot area */ + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: /* Address maps */ + rethink_shadow_mappings(cs8230); + break; + } } } - static void cs8230_close(void *priv) { - cs8230_t *cs8230 = (cs8230_t *)priv; + cs8230_t *cs8230 = (cs8230_t *) priv; free(cs8230); } - static void -*cs8230_init(const device_t *info) + * + cs8230_init(const device_t *info) { - cs8230_t *cs8230 = (cs8230_t *)malloc(sizeof(cs8230_t)); + cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t)); memset(cs8230, 0, sizeof(cs8230_t)); io_sethandler(0x0022, 0x0002, cs8230_read, NULL, NULL, cs8230_write, NULL, NULL, cs8230); if (mem_size > 768) { - mem_mapping_set_addr(&ram_mid_mapping, 0xa0000, mem_size > 1024 ? 0x60000 : 0x20000 + (mem_size - 768) * 1024); - mem_mapping_set_exec(&ram_mid_mapping, ram + 0xa0000); + mem_mapping_set_addr(&ram_mid_mapping, 0xa0000, mem_size > 1024 ? 0x60000 : 0x20000 + (mem_size - 768) * 1024); + mem_mapping_set_exec(&ram_mid_mapping, ram + 0xa0000); } return cs8230; } const device_t cs8230_device = { - .name = "C&T CS8230 (386/AT)", + .name = "C&T CS8230 (386/AT)", .internal_name = "cs8230", - .flags = 0, - .local = 0, - .init = cs8230_init, - .close = cs8230_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = cs8230_init, + .close = cs8230_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/et6000.c b/src/chipset/et6000.c index 1d7541c7e..5aaa5bff9 100644 --- a/src/chipset/et6000.c +++ b/src/chipset/et6000.c @@ -45,18 +45,18 @@ et6000_log(const char *fmt, ...) { va_list ap; - if (et6000_do_log) - { + if (et6000_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define et6000_log(fmt, ...) +# define et6000_log(fmt, ...) #endif -static void et6000_shadow_control(int base, int size, int can_read, int can_write) +static void +et6000_shadow_control(int base, int size, int can_read, int can_write) { mem_set_mem_state_both(base, size, (can_read ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (can_write ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); flushmmucache_nopc(); @@ -65,57 +65,55 @@ static void et6000_shadow_control(int base, int size, int can_read, int can_writ static void et6000_write(uint16_t addr, uint8_t val, void *priv) { - et6000_t *dev = (et6000_t *)priv; + et6000_t *dev = (et6000_t *) priv; - switch (addr) - { - case 0x22: - dev->index = val; - break; - case 0x23: - switch (INDEX) - { - case 0: /* System Configuration Register */ - dev->regs[INDEX] = val & 0xdf; - et6000_shadow_control(0xa0000, 0x20000, val & 1, val & 1); - refresh_at_enable = !(val & 0x10); + switch (addr) { + case 0x22: + dev->index = val; break; + case 0x23: + switch (INDEX) { + case 0: /* System Configuration Register */ + dev->regs[INDEX] = val & 0xdf; + et6000_shadow_control(0xa0000, 0x20000, val & 1, val & 1); + refresh_at_enable = !(val & 0x10); + break; - case 1: /* CACHE Configuration and Non-Cacheable Block Size */ - dev->regs[INDEX] = val & 0xf0; - break; + case 1: /* CACHE Configuration and Non-Cacheable Block Size */ + dev->regs[INDEX] = val & 0xf0; + break; - case 2: /* Non-Cacheable Block Address Register */ - dev->regs[INDEX] = val & 0xfe; - break; + case 2: /* Non-Cacheable Block Address Register */ + dev->regs[INDEX] = val & 0xfe; + break; - case 3: /* DRAM Bank and Type Configuration Register */ - dev->regs[INDEX] = val; - break; + case 3: /* DRAM Bank and Type Configuration Register */ + dev->regs[INDEX] = val; + break; - case 4: /* DRAM Configuration Register */ - dev->regs[INDEX] = val; - et6000_shadow_control(0xc0000, 0x10000, (dev->regs[0x15] & 2) && (val & 0x20), (dev->regs[0x15] & 2) && (val & 0x20) && (dev->regs[0x15] & 1)); - et6000_shadow_control(0xd0000, 0x10000, (dev->regs[0x15] & 8) && (val & 0x20), (dev->regs[0x15] & 8) && (val & 0x20) && (dev->regs[0x15] & 4)); - break; + case 4: /* DRAM Configuration Register */ + dev->regs[INDEX] = val; + et6000_shadow_control(0xc0000, 0x10000, (dev->regs[0x15] & 2) && (val & 0x20), (dev->regs[0x15] & 2) && (val & 0x20) && (dev->regs[0x15] & 1)); + et6000_shadow_control(0xd0000, 0x10000, (dev->regs[0x15] & 8) && (val & 0x20), (dev->regs[0x15] & 8) && (val & 0x20) && (dev->regs[0x15] & 4)); + break; - case 5: /* Shadow RAM Configuration Register */ - dev->regs[INDEX] = val; - et6000_shadow_control(0xc0000, 0x10000, (val & 2) && (dev->regs[0x14] & 0x20), (val & 2) && (dev->regs[0x14] & 0x20) && (val & 1)); - et6000_shadow_control(0xd0000, 0x10000, (val & 8) && (dev->regs[0x14] & 0x20), (val & 8) && (dev->regs[0x14] & 0x20) && (val & 4)); - et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10)); - et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40)); + case 5: /* Shadow RAM Configuration Register */ + dev->regs[INDEX] = val; + et6000_shadow_control(0xc0000, 0x10000, (val & 2) && (dev->regs[0x14] & 0x20), (val & 2) && (dev->regs[0x14] & 0x20) && (val & 1)); + et6000_shadow_control(0xd0000, 0x10000, (val & 8) && (dev->regs[0x14] & 0x20), (val & 8) && (dev->regs[0x14] & 0x20) && (val & 4)); + et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10)); + et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40)); + break; + } + et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]); break; - } - et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]); - break; } } static uint8_t et6000_read(uint16_t addr, void *priv) { - et6000_t *dev = (et6000_t *)priv; + et6000_t *dev = (et6000_t *) priv; return ((addr == 0x23) && (INDEX >= 0) && (INDEX <= 5)) ? dev->regs[INDEX] : 0xff; } @@ -123,7 +121,7 @@ et6000_read(uint16_t addr, void *priv) static void et6000_close(void *priv) { - et6000_t *dev = (et6000_t *)priv; + et6000_t *dev = (et6000_t *) priv; free(dev); } @@ -131,7 +129,7 @@ et6000_close(void *priv) static void * et6000_init(const device_t *info) { - et6000_t *dev = (et6000_t *)malloc(sizeof(et6000_t)); + et6000_t *dev = (et6000_t *) malloc(sizeof(et6000_t)); memset(dev, 0, sizeof(et6000_t)); /* Port 92h */ @@ -149,15 +147,15 @@ et6000_init(const device_t *info) } const device_t et6000_device = { - .name = "ETEQ Cheetah ET6000", + .name = "ETEQ Cheetah ET6000", .internal_name = "et6000", - .flags = 0, - .local = 0, - .init = et6000_init, - .close = et6000_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = et6000_init, + .close = et6000_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/gc100.c b/src/chipset/gc100.c index 09df87856..9ff577a1e 100644 --- a/src/chipset/gc100.c +++ b/src/chipset/gc100.c @@ -41,13 +41,11 @@ #include <86box/io.h> #include <86box/video.h> - typedef struct { - uint8_t reg[0x10]; + uint8_t reg[0x10]; } gc100_t; - #ifdef ENABLE_GC100_LOG int gc100_do_log = ENABLE_GC100_LOG; @@ -59,22 +57,21 @@ gc100_log(const char *fmt, ...) if (gc100_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); - va_end(ap); + va_end(ap); } } #else -#define gc100_log(fmt, ...) +# define gc100_log(fmt, ...) #endif - static uint8_t get_fdd_switch_settings(void) { int i, fdd_count = 0; for (i = 0; i < FDD_NUM; i++) { - if (fdd_get_flags(i)) - fdd_count++; + if (fdd_get_flags(i)) + fdd_count++; } if (!fdd_count) @@ -83,71 +80,68 @@ get_fdd_switch_settings(void) return ((fdd_count - 1) << 6) | 0x01; } - static uint8_t get_videomode_switch_settings(void) { if (video_is_mda()) - return 0x30; + return 0x30; else if (video_is_cga()) - return 0x20; /* 0x10 would be 40x25 */ + return 0x20; /* 0x10 would be 40x25 */ else - return 0x00; + return 0x00; } - static void gc100_write(uint16_t port, uint8_t val, void *priv) { - gc100_t *dev = (gc100_t *) priv; + gc100_t *dev = (gc100_t *) priv; uint16_t addr = port & 0xf; dev->reg[addr] = val; switch (addr) { - /* addr 0x2 - * bits 5-7: not used - * bit 4: intenal memory wait states - * bits 2-3: external memory wait states - * bits 0-1: i/o access wait states - */ - case 2: - break; + /* addr 0x2 + * bits 5-7: not used + * bit 4: intenal memory wait states + * bits 2-3: external memory wait states + * bits 0-1: i/o access wait states + */ + case 2: + break; - /* addr 0x3 - * bits 1-7: not used - * bit 0: turbo 0 xt 1 - */ - case 3: - if (val & 1) - cpu_dynamic_switch(0); - else - cpu_dynamic_switch(cpu); - break; + /* addr 0x3 + * bits 1-7: not used + * bit 0: turbo 0 xt 1 + */ + case 3: + if (val & 1) + cpu_dynamic_switch(0); + else + cpu_dynamic_switch(cpu); + break; - /* addr 0x5 - * programmable dip-switches - * bits 6-7: floppy drive number - * bits 4-5: video mode - * bits 2-3: memory size - * bit 1: fpu - * bit 0: not used - */ + /* addr 0x5 + * programmable dip-switches + * bits 6-7: floppy drive number + * bits 4-5: video mode + * bits 2-3: memory size + * bit 1: fpu + * bit 0: not used + */ - /* addr 0x6 */ + /* addr 0x6 */ - /* addr 0x7 */ + /* addr 0x7 */ } gc100_log("GC100: Write %02x at %02x\n", val, port); } - static uint8_t gc100_read(uint16_t port, void *priv) { - gc100_t *dev = (gc100_t *) priv; - uint8_t ret = 0xff; + gc100_t *dev = (gc100_t *) priv; + uint8_t ret = 0xff; uint16_t addr = port & 0xf; ret = dev->reg[addr]; @@ -155,47 +149,46 @@ gc100_read(uint16_t port, void *priv) gc100_log("GC100: Read %02x at %02x\n", ret, port); switch (addr) { - /* addr 0x2 - * bits 5-7: not used - * bit 4: intenal memory wait states - * bits 2-3: external memory wait states - * bits 0-1: i/o access wait states - */ - case 0x2: - break; + /* addr 0x2 + * bits 5-7: not used + * bit 4: intenal memory wait states + * bits 2-3: external memory wait states + * bits 0-1: i/o access wait states + */ + case 0x2: + break; - /* addr 0x3 - * bits 1-7: not used - * bit 0: turbo 0 xt 1 - */ - case 0x3: - break; + /* addr 0x3 + * bits 1-7: not used + * bit 0: turbo 0 xt 1 + */ + case 0x3: + break; - /* addr 0x5 - * programmable dip-switches - * bits 6-7: floppy drive number - * bits 4-5: video mode - * bits 2-3: memory size - * bit 1: fpu - * bit 0: not used - */ - case 0x5: - ret = ret & 0x0c; - ret |= get_fdd_switch_settings(); - ret |= get_videomode_switch_settings(); - if (hasfpu) - ret |= 0x02; - break; + /* addr 0x5 + * programmable dip-switches + * bits 6-7: floppy drive number + * bits 4-5: video mode + * bits 2-3: memory size + * bit 1: fpu + * bit 0: not used + */ + case 0x5: + ret = ret & 0x0c; + ret |= get_fdd_switch_settings(); + ret |= get_videomode_switch_settings(); + if (hasfpu) + ret |= 0x02; + break; - /* addr 0x6 */ + /* addr 0x6 */ - /* addr 0x7 */ + /* addr 0x7 */ } return ret; } - static void gc100_close(void *priv) { @@ -204,7 +197,6 @@ gc100_close(void *priv) free(dev); } - static void * gc100_init(const device_t *info) { @@ -218,11 +210,11 @@ gc100_init(const device_t *info) dev->reg[0x7] = 0x0; if (info->local) { - /* GC100A */ + /* GC100A */ io_sethandler(0x0c2, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev); io_sethandler(0x0c5, 0x03, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev); } else { - /* GC100 */ + /* GC100 */ io_sethandler(0x022, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev); io_sethandler(0x025, 0x01, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev); } @@ -231,29 +223,29 @@ gc100_init(const device_t *info) } const device_t gc100_device = { - .name = "G2 GC100", + .name = "G2 GC100", .internal_name = "gc100", - .flags = 0, - .local = 0, - .init = gc100_init, - .close = gc100_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = gc100_init, + .close = gc100_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t gc100a_device = { - .name = "G2 GC100A", + .name = "G2 GC100A", .internal_name = "gc100a", - .flags = 0, - .local = 1, - .init = gc100_init, - .close = gc100_close, - .reset = NULL, + .flags = 0, + .local = 1, + .init = gc100_init, + .close = gc100_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/headland.c b/src/chipset/headland.c index 91f1658d8..9aa6b3fac 100644 --- a/src/chipset/headland.c +++ b/src/chipset/headland.c @@ -37,59 +37,54 @@ #include <86box/port_92.h> #include <86box/chipset.h> - enum { - HEADLAND_GC103 = 0x00, - HEADLAND_GC113 = 0x10, - HEADLAND_HT18_A = 0x11, - HEADLAND_HT18_B = 0x12, - HEADLAND_HT18_C = 0x18, + HEADLAND_GC103 = 0x00, + HEADLAND_GC113 = 0x10, + HEADLAND_HT18_A = 0x11, + HEADLAND_HT18_B = 0x12, + HEADLAND_HT18_C = 0x18, HEADLAND_HT21_C_D = 0x31, - HEADLAND_HT21_E = 0x32, + HEADLAND_HT21_E = 0x32, }; +#define HEADLAND_REV_MASK 0x0F -#define HEADLAND_REV_MASK 0x0F - -#define HEADLAND_HAS_CRI 0x10 +#define HEADLAND_HAS_CRI 0x10 #define HEADLAND_HAS_SLEEP 0x20 - typedef struct { - uint8_t valid, enabled; - uint16_t mr; - uint32_t virt_base; + uint8_t valid, enabled; + uint16_t mr; + uint32_t virt_base; - struct headland_t * headland; + struct headland_t *headland; } headland_mr_t; - typedef struct headland_t { - uint8_t revision; - uint8_t has_cri, has_sleep; + uint8_t revision; + uint8_t has_cri, has_sleep; - uint8_t cri; - uint8_t cr[7]; + uint8_t cri; + uint8_t cr[7]; - uint8_t indx; - uint8_t regs[256]; + uint8_t indx; + uint8_t regs[256]; - uint8_t ems_mar; + uint8_t ems_mar; - headland_mr_t null_mr, - ems_mr[64]; + headland_mr_t null_mr, + ems_mr[64]; - mem_mapping_t low_mapping; - mem_mapping_t ems_mapping[64]; - mem_mapping_t mid_mapping; - mem_mapping_t high_mapping; - mem_mapping_t shadow_mapping[2]; - mem_mapping_t upper_mapping[24]; + mem_mapping_t low_mapping; + mem_mapping_t ems_mapping[64]; + mem_mapping_t mid_mapping; + mem_mapping_t high_mapping; + mem_mapping_t shadow_mapping[2]; + mem_mapping_t upper_mapping[24]; } headland_t; - /* TODO - Headland chipset's memory address mapping emulation isn't fully implemented yet, - so memory configuration is hardcoded now. */ + so memory configuration is hardcoded now. */ static const int mem_conf_cr0[41] = { 0x00, 0x00, 0x20, 0x40, 0x60, 0xA0, 0x40, 0xE0, 0xA0, 0xC0, 0xE0, 0xE0, 0xC0, 0xE0, 0xE0, 0xE0, @@ -107,23 +102,22 @@ static const int mem_conf_cr1[41] = { 0x40 }; - static uint32_t get_addr(headland_t *dev, uint32_t addr, headland_mr_t *mr) { uint32_t bank_base[4], bank_shift[4], shift, other_shift, bank; if ((addr >= 0x0e0000) && (addr <= 0x0fffff)) - return addr; + return addr; else if ((addr >= 0xfe0000) && (addr <= 0xffffff)) - return addr & 0x0fffff; + return addr & 0x0fffff; if (dev->revision == 8) { - shift = (dev->cr[0] & 0x80) ? 21 : ((dev->cr[6] & 0x01) ? 23 : 19); - other_shift = (dev->cr[0] & 0x80) ? ((dev->cr[6] & 0x01) ? 19 : 23) : 21; + shift = (dev->cr[0] & 0x80) ? 21 : ((dev->cr[6] & 0x01) ? 23 : 19); + other_shift = (dev->cr[0] & 0x80) ? ((dev->cr[6] & 0x01) ? 19 : 23) : 21; } else { - shift = (dev->cr[0] & 0x80) ? 21 : 19; - other_shift = (dev->cr[0] & 0x80) ? 21 : 19; + shift = (dev->cr[0] & 0x80) ? 21 : 19; + other_shift = (dev->cr[0] & 0x80) ? 21 : 19; } /* Bank size = 1 << (bank shift + 2) . */ @@ -134,296 +128,288 @@ get_addr(headland_t *dev, uint32_t addr, headland_mr_t *mr) bank_base[2] = bank_base[1] + (1 << shift); if ((dev->revision > 0) && (dev->revision < 8) && (dev->cr[1] & 0x40)) { - bank_shift[2] = bank_shift[3] = other_shift; - bank_base[3] = bank_base[2] + (1 << other_shift); - /* First address after the memory is bank_base[3] + (1 << other_shift) */ + bank_shift[2] = bank_shift[3] = other_shift; + bank_base[3] = bank_base[2] + (1 << other_shift); + /* First address after the memory is bank_base[3] + (1 << other_shift) */ } else { - bank_shift[2] = bank_shift[3] = shift; - bank_base[3] = bank_base[2] + (1 << shift); - /* First address after the memory is bank_base[3] + (1 << shift) */ + bank_shift[2] = bank_shift[3] = shift; + bank_base[3] = bank_base[2] + (1 << shift); + /* First address after the memory is bank_base[3] + (1 << shift) */ } if (mr && mr->valid && (dev->cr[0] & 2) && (mr->mr & 0x200)) { - addr = (addr & 0x3fff) | ((mr->mr & 0x1F) << 14); + addr = (addr & 0x3fff) | ((mr->mr & 0x1F) << 14); - bank = (mr->mr >> 7) & 3; + bank = (mr->mr >> 7) & 3; - if (bank_shift[bank] >= 21) - addr |= (mr->mr & 0x060) << 14; + if (bank_shift[bank] >= 21) + addr |= (mr->mr & 0x060) << 14; - if ((dev->revision == 8) && (bank_shift[bank] == 23)) - addr |= (mr->mr & 0xc00) << 11; + if ((dev->revision == 8) && (bank_shift[bank] == 23)) + addr |= (mr->mr & 0xc00) << 11; - addr |= bank_base[(mr->mr >> 7) & 3]; + addr |= bank_base[(mr->mr >> 7) & 3]; } else if (((mr == NULL) || !mr->valid) && (mem_size >= 1024) && (addr >= 0x100000) && ((dev->cr[0] & 4) == 0)) - addr -= 0x60000; + addr -= 0x60000; return addr; } - static void hl_ems_disable(headland_t *dev, uint8_t mar, uint32_t base_addr, uint8_t indx) { - if (base_addr < ((uint32_t)mem_size << 10)) - mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + base_addr); + if (base_addr < ((uint32_t) mem_size << 10)) + mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + base_addr); else - mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL); + mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL); mem_mapping_disable(&dev->ems_mapping[mar & 0x3f]); if (indx < 24) { - mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_mapping_enable(&dev->upper_mapping[indx]); + mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_mapping_enable(&dev->upper_mapping[indx]); } else - mem_set_mem_state(base_addr, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state(base_addr, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); } - static void hl_ems_update(headland_t *dev, uint8_t mar) { uint32_t base_addr, virt_addr; - uint8_t indx = mar & 0x1f; + uint8_t indx = mar & 0x1f; base_addr = (indx + 16) << 14; if (indx >= 24) - base_addr += 0x20000; + base_addr += 0x20000; hl_ems_disable(dev, mar, base_addr, indx); - dev->ems_mr[mar & 0x3f].enabled = 0; + dev->ems_mr[mar & 0x3f].enabled = 0; dev->ems_mr[mar & 0x3f].virt_base = base_addr; if ((dev->cr[0] & 2) && ((dev->cr[0] & 1) == ((mar & 0x20) >> 5)) && (dev->ems_mr[mar & 0x3f].mr & 0x200)) { - mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - virt_addr = get_addr(dev, base_addr, &dev->ems_mr[mar & 0x3f]); - dev->ems_mr[mar & 0x3f].enabled = 1; - dev->ems_mr[mar & 0x3f].virt_base = virt_addr; - if (indx < 24) - mem_mapping_disable(&dev->upper_mapping[indx]); - if (virt_addr < ((uint32_t)mem_size << 10)) - mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + virt_addr); - else - mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL); - mem_mapping_enable(&dev->ems_mapping[mar & 0x3f]); + mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + virt_addr = get_addr(dev, base_addr, &dev->ems_mr[mar & 0x3f]); + dev->ems_mr[mar & 0x3f].enabled = 1; + dev->ems_mr[mar & 0x3f].virt_base = virt_addr; + if (indx < 24) + mem_mapping_disable(&dev->upper_mapping[indx]); + if (virt_addr < ((uint32_t) mem_size << 10)) + mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + virt_addr); + else + mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL); + mem_mapping_enable(&dev->ems_mapping[mar & 0x3f]); } flushmmucache(); } - static void set_global_EMS_state(headland_t *dev, int state) { int i; for (i = 0; i < 32; i++) { - hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20)); - hl_ems_update(dev, i | ((dev->cr[0] & 0x01) << 5)); - } + hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20)); + hl_ems_update(dev, i | ((dev->cr[0] & 0x01) << 5)); + } } - static void memmap_state_default(headland_t *dev, uint8_t ht_romcs) { mem_mapping_disable(&dev->mid_mapping); if (ht_romcs) - mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS); + mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS); else - mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); + mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS); mem_mapping_disable(&dev->shadow_mapping[0]); mem_mapping_disable(&dev->shadow_mapping[1]); } - static void memmap_state_update(headland_t *dev) { uint32_t addr; - int i; - uint8_t ht_cr0 = dev->cr[0]; - uint8_t ht_romcs = !(dev->cr[4] & 0x01); + int i; + uint8_t ht_cr0 = dev->cr[0]; + uint8_t ht_romcs = !(dev->cr[4] & 0x01); if (dev->revision <= 1) - ht_romcs = 1; + ht_romcs = 1; if (!(dev->cr[0] & 0x04)) - ht_cr0 &= ~0x18; + ht_cr0 &= ~0x18; for (i = 0; i < 24; i++) { - addr = get_addr(dev, 0x40000 + (i << 14), NULL); - mem_mapping_set_exec(&dev->upper_mapping[i], addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); + addr = get_addr(dev, 0x40000 + (i << 14), NULL); + mem_mapping_set_exec(&dev->upper_mapping[i], addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); } memmap_state_default(dev, ht_romcs); if (mem_size > 640) { - if (ht_cr0 & 0x04) { - mem_mapping_set_addr(&dev->mid_mapping, 0xA0000, 0x40000); - mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000); - mem_mapping_disable(&dev->mid_mapping); - if (mem_size > 1024) { - mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_mapping_set_addr(&dev->high_mapping, 0x100000, (mem_size - 1024) << 10); - mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000); - } - } else { - /* 1 MB - 1 MB + 384k: RAM pointing to A0000-FFFFF - 1 MB + 384k: Any ram pointing 1 MB onwards. */ - /* First, do the addresses above 1 MB. */ - mem_mapping_set_addr(&dev->mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10); - mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000); - if (mem_size > 1024) { - /* We have ram above 1 MB, we need to relocate that. */ - mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - mem_mapping_set_addr(&dev->high_mapping, 0x160000, (mem_size - 1024) << 10); - mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000); - } - } + if (ht_cr0 & 0x04) { + mem_mapping_set_addr(&dev->mid_mapping, 0xA0000, 0x40000); + mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000); + mem_mapping_disable(&dev->mid_mapping); + if (mem_size > 1024) { + mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_mapping_set_addr(&dev->high_mapping, 0x100000, (mem_size - 1024) << 10); + mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000); + } + } else { + /* 1 MB - 1 MB + 384k: RAM pointing to A0000-FFFFF + 1 MB + 384k: Any ram pointing 1 MB onwards. */ + /* First, do the addresses above 1 MB. */ + mem_mapping_set_addr(&dev->mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10); + mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000); + if (mem_size > 1024) { + /* We have ram above 1 MB, we need to relocate that. */ + mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_mapping_set_addr(&dev->high_mapping, 0x160000, (mem_size - 1024) << 10); + mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000); + } + } } switch (ht_cr0) { - case 0x18: - if ((mem_size << 10) > 0xe0000) { - mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + case 0x18: + if ((mem_size << 10) > 0xe0000) { + mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x20000); - mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000); - mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x20000); - mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000); - } else { - mem_mapping_disable(&dev->shadow_mapping[0]); - mem_mapping_disable(&dev->shadow_mapping[1]); - } - break; - case 0x10: - if ((mem_size << 10) > 0xf0000) { - mem_set_mem_state(0x0f0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_set_mem_state(0xff0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x20000); + mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000); + mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x20000); + mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000); + } else { + mem_mapping_disable(&dev->shadow_mapping[0]); + mem_mapping_disable(&dev->shadow_mapping[1]); + } + break; + case 0x10: + if ((mem_size << 10) > 0xf0000) { + mem_set_mem_state(0x0f0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_set_mem_state(0xff0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0f0000, 0x10000); - mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xf0000); - mem_mapping_set_addr(&dev->shadow_mapping[1], 0xff0000, 0x10000); - mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xf0000); - } else { - mem_mapping_disable(&dev->shadow_mapping[0]); - mem_mapping_disable(&dev->shadow_mapping[1]); - } - break; - case 0x08: - if ((mem_size << 10) > 0xe0000) { - mem_set_mem_state(0x0e0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_set_mem_state(0xfe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0f0000, 0x10000); + mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xf0000); + mem_mapping_set_addr(&dev->shadow_mapping[1], 0xff0000, 0x10000); + mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xf0000); + } else { + mem_mapping_disable(&dev->shadow_mapping[0]); + mem_mapping_disable(&dev->shadow_mapping[1]); + } + break; + case 0x08: + if ((mem_size << 10) > 0xe0000) { + mem_set_mem_state(0x0e0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_set_mem_state(0xfe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x10000); - mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000); - mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x10000); - mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000); - } else { - mem_mapping_disable(&dev->shadow_mapping[0]); - mem_mapping_disable(&dev->shadow_mapping[1]); - } - break; - case 0x00: - default: - mem_mapping_disable(&dev->shadow_mapping[0]); - mem_mapping_disable(&dev->shadow_mapping[1]); - break; + mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x10000); + mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000); + mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x10000); + mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000); + } else { + mem_mapping_disable(&dev->shadow_mapping[0]); + mem_mapping_disable(&dev->shadow_mapping[1]); + } + break; + case 0x00: + default: + mem_mapping_disable(&dev->shadow_mapping[0]); + mem_mapping_disable(&dev->shadow_mapping[1]); + break; } set_global_EMS_state(dev, ht_cr0 & 3); } - static void hl_write(uint16_t addr, uint8_t val, void *priv) { - headland_t *dev = (headland_t *)priv; + headland_t *dev = (headland_t *) priv; - switch(addr) { - case 0x01ec: - dev->ems_mr[dev->ems_mar & 0x3f].mr = val | 0xff00; - hl_ems_update(dev, dev->ems_mar & 0x3f); - if (dev->ems_mar & 0x80) - dev->ems_mar++; - break; + switch (addr) { + case 0x01ec: + dev->ems_mr[dev->ems_mar & 0x3f].mr = val | 0xff00; + hl_ems_update(dev, dev->ems_mar & 0x3f); + if (dev->ems_mar & 0x80) + dev->ems_mar++; + break; - case 0x01ed: - if (dev->has_cri) - dev->cri = val; - break; + case 0x01ed: + if (dev->has_cri) + dev->cri = val; + break; - case 0x01ee: - dev->ems_mar = val; - break; + case 0x01ee: + dev->ems_mar = val; + break; - case 0x01ef: - switch(dev->cri & 0x07) { - case 0: - dev->cr[0] = (val & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; - memmap_state_update(dev); - break; + case 0x01ef: + switch (dev->cri & 0x07) { + case 0: + dev->cr[0] = (val & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; + memmap_state_update(dev); + break; - case 1: - dev->cr[1] = (val & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; - memmap_state_update(dev); - break; + case 1: + dev->cr[1] = (val & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; + memmap_state_update(dev); + break; - case 2: - case 3: - dev->cr[dev->cri] = val; - memmap_state_update(dev); - break; + case 2: + case 3: + dev->cr[dev->cri] = val; + memmap_state_update(dev); + break; - case 5: - if (dev->has_sleep) - dev->cr[dev->cri] = val; - else - dev->cr[dev->cri] = val & 0x0f; - memmap_state_update(dev); - break; + case 5: + if (dev->has_sleep) + dev->cr[dev->cri] = val; + else + dev->cr[dev->cri] = val & 0x0f; + memmap_state_update(dev); + break; - case 4: - dev->cr[4] = (dev->cr[4] & 0xf0) | (val & 0x0f); - memmap_state_update(dev); - break; + case 4: + dev->cr[4] = (dev->cr[4] & 0xf0) | (val & 0x0f); + memmap_state_update(dev); + break; - case 6: - if (dev->revision == 8) { - dev->cr[dev->cri] = (val & 0xfe) | (mem_size > 8192 ? 1 : 0); - memmap_state_update(dev); - } - break; + case 6: + if (dev->revision == 8) { + dev->cr[dev->cri] = (val & 0xfe) | (mem_size > 8192 ? 1 : 0); + memmap_state_update(dev); + } + break; - default: - break; - } - break; + default: + break; + } + break; - default: - break; + default: + break; } } - static void hl_writew(uint16_t addr, uint16_t val, void *priv) { - headland_t *dev = (headland_t *)priv; + headland_t *dev = (headland_t *) priv; - switch(addr) { - case 0x01ec: - dev->ems_mr[dev->ems_mar & 0x3f].mr = val; - hl_ems_update(dev, dev->ems_mar & 0x3f); - if (dev->ems_mar & 0x80) - dev->ems_mar++; - break; + switch (addr) { + case 0x01ec: + dev->ems_mr[dev->ems_mar & 0x3f].mr = val; + hl_ems_update(dev, dev->ems_mar & 0x3f); + if (dev->ems_mar & 0x80) + dev->ems_mar++; + break; - default: - break; + default: + break; } } - static void hl_writel(uint16_t addr, uint32_t val, void *priv) { @@ -431,81 +417,78 @@ hl_writel(uint16_t addr, uint32_t val, void *priv) hl_writew(addr + 2, val >> 16, priv); } - static uint8_t hl_read(uint16_t addr, void *priv) { - headland_t *dev = (headland_t *)priv; - uint8_t ret = 0xff; + headland_t *dev = (headland_t *) priv; + uint8_t ret = 0xff; - switch(addr) { - case 0x01ec: - ret = (uint8_t)dev->ems_mr[dev->ems_mar & 0x3f].mr; - if (dev->ems_mar & 0x80) - dev->ems_mar++; - break; + switch (addr) { + case 0x01ec: + ret = (uint8_t) dev->ems_mr[dev->ems_mar & 0x3f].mr; + if (dev->ems_mar & 0x80) + dev->ems_mar++; + break; - case 0x01ed: - if (dev->has_cri) - ret = dev->cri; - break; + case 0x01ed: + if (dev->has_cri) + ret = dev->cri; + break; - case 0x01ee: - ret = dev->ems_mar; - break; + case 0x01ee: + ret = dev->ems_mar; + break; - case 0x01ef: - switch(dev->cri & 0x07) { - case 0: - ret = (dev->cr[0] & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; - break; + case 0x01ef: + switch (dev->cri & 0x07) { + case 0: + ret = (dev->cr[0] & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; + break; - case 1: - ret = (dev->cr[1] & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; - break; + case 1: + ret = (dev->cr[1] & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9]; + break; - case 6: - if (dev->revision == 8) - ret = (dev->cr[6] & 0xfe) | (mem_size > 8192 ? 1 : 0); - else - ret = 0; - break; + case 6: + if (dev->revision == 8) + ret = (dev->cr[6] & 0xfe) | (mem_size > 8192 ? 1 : 0); + else + ret = 0; + break; - default: - ret = dev->cr[dev->cri]; - break; - } - break; + default: + ret = dev->cr[dev->cri]; + break; + } + break; - default: - break; + default: + break; } return ret; } - static uint16_t hl_readw(uint16_t addr, void *priv) { - headland_t *dev = (headland_t *)priv; - uint16_t ret = 0xffff; + headland_t *dev = (headland_t *) priv; + uint16_t ret = 0xffff; - switch(addr) { - case 0x01ec: - ret = dev->ems_mr[dev->ems_mar & 0x3f].mr | ((dev->cr[4] & 0x80) ? 0xf000 : 0xfc00); - if (dev->ems_mar & 0x80) - dev->ems_mar++; - break; + switch (addr) { + case 0x01ec: + ret = dev->ems_mr[dev->ems_mar & 0x3f].mr | ((dev->cr[4] & 0x80) ? 0xf000 : 0xfc00); + if (dev->ems_mar & 0x80) + dev->ems_mar++; + break; - default: - break; + default: + break; } return ret; } - static uint32_t hl_readl(uint16_t addr, void *priv) { @@ -517,131 +500,123 @@ hl_readl(uint16_t addr, void *priv) return ret; } - static uint8_t mem_read_b(uint32_t addr, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; - uint8_t ret = 0xff; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; + uint8_t ret = 0xff; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - ret = ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + ret = ram[addr]; return ret; } - static uint16_t mem_read_w(uint32_t addr, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; - uint16_t ret = 0xffff; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; + uint16_t ret = 0xffff; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - ret = *(uint16_t *)&ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + ret = *(uint16_t *) &ram[addr]; return ret; } - static uint32_t mem_read_l(uint32_t addr, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; - uint32_t ret = 0xffffffff; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; + uint32_t ret = 0xffffffff; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - ret = *(uint32_t *)&ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + ret = *(uint32_t *) &ram[addr]; return ret; } - static void mem_write_b(uint32_t addr, uint8_t val, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + ram[addr] = val; } - static void mem_write_w(uint32_t addr, uint16_t val, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - *(uint16_t *)&ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + *(uint16_t *) &ram[addr] = val; } - static void mem_write_l(uint32_t addr, uint32_t val, void *priv) { - headland_mr_t *mr = (headland_mr_t *) priv; - headland_t *dev = mr->headland; + headland_mr_t *mr = (headland_mr_t *) priv; + headland_t *dev = mr->headland; addr = get_addr(dev, addr, mr); - if (addr < ((uint32_t)mem_size << 10)) - *(uint32_t *)&ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + *(uint32_t *) &ram[addr] = val; } - static void headland_close(void *priv) { - headland_t *dev = (headland_t *)priv; + headland_t *dev = (headland_t *) priv; free(dev); } - static void * headland_init(const device_t *info) { headland_t *dev; - int ht386 = 0; - uint32_t i; + int ht386 = 0; + uint32_t i; dev = (headland_t *) malloc(sizeof(headland_t)); memset(dev, 0x00, sizeof(headland_t)); - dev->has_cri = (info->local & HEADLAND_HAS_CRI); + dev->has_cri = (info->local & HEADLAND_HAS_CRI); dev->has_sleep = (info->local & HEADLAND_HAS_SLEEP); - dev->revision = info->local & HEADLAND_REV_MASK; + dev->revision = info->local & HEADLAND_REV_MASK; if (dev->revision > 0) - ht386 = 1; + ht386 = 1; dev->cr[0] = 0x04; dev->cr[4] = dev->revision << 4; - if (ht386) - device_add(&port_92_inv_device); + if (ht386) + device_add(&port_92_inv_device); io_sethandler(0x01ec, 4, - hl_read,hl_readw,hl_readl, hl_write,hl_writew,hl_writel, dev); + hl_read, hl_readw, hl_readl, hl_write, hl_writew, hl_writel, dev); - dev->null_mr.valid = 0; - dev->null_mr.mr = 0xff; + dev->null_mr.valid = 0; + dev->null_mr.mr = 0xff; dev->null_mr.headland = dev; for (i = 0; i < 64; i++) { - dev->ems_mr[i].valid = 1; - dev->ems_mr[i].mr = 0x00; - dev->ems_mr[i].headland = dev; + dev->ems_mr[i].valid = 1; + dev->ems_mr[i].mr = 0x00; + dev->ems_mr[i].headland = dev; } /* Turn off mem.c mappings. */ @@ -650,163 +625,162 @@ headland_init(const device_t *info) mem_mapping_disable(&ram_high_mapping); mem_mapping_add(&dev->low_mapping, 0, 0x40000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ram, MEM_MAPPING_INTERNAL, &dev->null_mr); + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ram, MEM_MAPPING_INTERNAL, &dev->null_mr); if (mem_size > 640) { - mem_mapping_add(&dev->mid_mapping, 0xa0000, 0x60000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ram + 0xa0000, MEM_MAPPING_INTERNAL, &dev->null_mr); - mem_mapping_disable(&dev->mid_mapping); + mem_mapping_add(&dev->mid_mapping, 0xa0000, 0x60000, + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ram + 0xa0000, MEM_MAPPING_INTERNAL, &dev->null_mr); + mem_mapping_disable(&dev->mid_mapping); } if (mem_size > 1024) { - mem_mapping_add(&dev->high_mapping, 0x100000, ((mem_size-1024)*1024), - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ram + 0x100000, MEM_MAPPING_INTERNAL, &dev->null_mr); - mem_mapping_enable(&dev->high_mapping); + mem_mapping_add(&dev->high_mapping, 0x100000, ((mem_size - 1024) * 1024), + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ram + 0x100000, MEM_MAPPING_INTERNAL, &dev->null_mr); + mem_mapping_enable(&dev->high_mapping); } for (i = 0; i < 24; i++) { - mem_mapping_add(&dev->upper_mapping[i], - 0x40000 + (i << 14), 0x4000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - mem_size > (256 + (i << 4)) ? (ram + 0x40000 + (i << 14)) : NULL, - MEM_MAPPING_INTERNAL, &dev->null_mr); - mem_mapping_enable(&dev->upper_mapping[i]); + mem_mapping_add(&dev->upper_mapping[i], + 0x40000 + (i << 14), 0x4000, + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + mem_size > (256 + (i << 4)) ? (ram + 0x40000 + (i << 14)) : NULL, + MEM_MAPPING_INTERNAL, &dev->null_mr); + mem_mapping_enable(&dev->upper_mapping[i]); } mem_mapping_add(&dev->shadow_mapping[0], - 0xe0000, 0x20000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL, - MEM_MAPPING_INTERNAL, &dev->null_mr); + 0xe0000, 0x20000, + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL, + MEM_MAPPING_INTERNAL, &dev->null_mr); mem_mapping_disable(&dev->shadow_mapping[0]); mem_mapping_add(&dev->shadow_mapping[1], - 0xfe0000, 0x20000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL, - MEM_MAPPING_INTERNAL, &dev->null_mr); + 0xfe0000, 0x20000, + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL, + MEM_MAPPING_INTERNAL, &dev->null_mr); mem_mapping_disable(&dev->shadow_mapping[1]); for (i = 0; i < 64; i++) { - dev->ems_mr[i].mr = 0x00; - mem_mapping_add(&dev->ems_mapping[i], - ((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000, - mem_read_b, mem_read_w, mem_read_l, - mem_write_b, mem_write_w, mem_write_l, - ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14), - MEM_MAPPING_INTERNAL, &dev->ems_mr[i]); - mem_mapping_disable(&dev->ems_mapping[i]); + dev->ems_mr[i].mr = 0x00; + mem_mapping_add(&dev->ems_mapping[i], + ((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000, + mem_read_b, mem_read_w, mem_read_l, + mem_write_b, mem_write_w, mem_write_l, + ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14), + MEM_MAPPING_INTERNAL, &dev->ems_mr[i]); + mem_mapping_disable(&dev->ems_mapping[i]); } memmap_state_update(dev); - return(dev); + return (dev); } - const device_t headland_gc10x_device = { - .name = "Headland GC101/102/103", + .name = "Headland GC101/102/103", .internal_name = "headland_gc10x", - .flags = 0, - .local = HEADLAND_GC103, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_GC103, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_gc113_device = { - .name = "Headland GC101/102/113", + .name = "Headland GC101/102/113", .internal_name = "headland_gc113", - .flags = 0, - .local = HEADLAND_GC113, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_GC113, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_ht18a_device = { - .name = "Headland HT18 Rev. A", + .name = "Headland HT18 Rev. A", .internal_name = "headland_ht18a", - .flags = 0, - .local = HEADLAND_HT18_A, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_HT18_A, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_ht18b_device = { - .name = "Headland HT18 Rev. B", + .name = "Headland HT18 Rev. B", .internal_name = "headland_ht18b", - .flags = 0, - .local = HEADLAND_HT18_B, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_HT18_B, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_ht18c_device = { - .name = "Headland HT18 Rev. C", + .name = "Headland HT18 Rev. C", .internal_name = "headland_ht18c", - .flags = 0, - .local = HEADLAND_HT18_C, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_HT18_C, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_ht21c_d_device = { - .name = "Headland HT21 Rev. C/D", + .name = "Headland HT21 Rev. C/D", .internal_name = "headland_ht21cd", - .flags = 0, - .local = HEADLAND_HT21_C_D, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_HT21_C_D, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t headland_ht21e_device = { - .name = "Headland HT21 Rev. E", + .name = "Headland HT21 Rev. E", .internal_name = "headland_ht21", - .flags = 0, - .local = HEADLAND_HT21_E, - .init = headland_init, - .close = headland_close, - .reset = NULL, + .flags = 0, + .local = HEADLAND_HT21_E, + .init = headland_init, + .close = headland_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/ims8848.c b/src/chipset/ims8848.c index 35b1ef62b..c4273b4fe 100644 --- a/src/chipset/ims8848.c +++ b/src/chipset/ims8848.c @@ -33,7 +33,6 @@ #include <86box/port_92.h> #include <86box/chipset.h> - /* IMS 884x Configuration Registers @@ -42,158 +41,152 @@ By: Tiseno100, Miran Grca(OBattler) Register 00h: - Bit 3: F0000-FFFFF Shadow Enable - Bit 2: E0000-EFFFF Shadow Enable - Bit 0: ???? + Bit 3: F0000-FFFFF Shadow Enable + Bit 2: E0000-EFFFF Shadow Enable + Bit 0: ???? Register 04h: - Bit 3: Cache Write Hit Wait State - Bit 2: Cache Read Hit Wait State + Bit 3: Cache Write Hit Wait State + Bit 2: Cache Read Hit Wait State Register 06h: - Bit 3: System BIOS Cacheable (1: Yes / 0: No) - Bit 1: Power Management Mode (1: IRQ / 0: SMI#) + Bit 3: System BIOS Cacheable (1: Yes / 0: No) + Bit 1: Power Management Mode (1: IRQ / 0: SMI#) Register 08h: - Bit 2: System BIOS Shadow Write (1: Enable / 0: Disable) - Bit 1: System BIOS Shadow Read? + Bit 2: System BIOS Shadow Write (1: Enable / 0: Disable) + Bit 1: System BIOS Shadow Read? Register 0Dh: - Bit 0: IO 100H-3FFH Idle Detect (1: Enable / 0: Disable) + Bit 0: IO 100H-3FFH Idle Detect (1: Enable / 0: Disable) Register 0Eh: - Bit 7: DMA & Local Bus Idle Detect (1: Enable / 0: Disable) - Bit 6: Floppy Disk Idle Detect (1: Enable / 0: Disable) - Bit 5: IDE Idle Detect (1: Enable / 0: Disable) - Bit 4: Serial Port Idle Detect (1: Enable / 0: Disable) - Bit 3: Parallel Port Idle Detect (1: Enable / 0: Disable) - Bit 2: Keyboard Idle Detect (1: Enable / 0: Disable) - Bit 1: Video Idle Detect (1: Enable / 0: Disable) + Bit 7: DMA & Local Bus Idle Detect (1: Enable / 0: Disable) + Bit 6: Floppy Disk Idle Detect (1: Enable / 0: Disable) + Bit 5: IDE Idle Detect (1: Enable / 0: Disable) + Bit 4: Serial Port Idle Detect (1: Enable / 0: Disable) + Bit 3: Parallel Port Idle Detect (1: Enable / 0: Disable) + Bit 2: Keyboard Idle Detect (1: Enable / 0: Disable) + Bit 1: Video Idle Detect (1: Enable / 0: Disable) Register 12h: - Bits 3-2: Power Saving Timer (00 = 1 MIN, 01 = 3 MIN, 10 = 5 MIN, 11 = 8 MIN) - Bit 1: Base Memory (1: 512KB / 0: 640KB) + Bits 3-2: Power Saving Timer (00 = 1 MIN, 01 = 3 MIN, 10 = 5 MIN, 11 = 8 MIN) + Bit 1: Base Memory (1: 512KB / 0: 640KB) Register 1Ah: - Bit 3: Cache Write Hit W/S For PCI (1: Enabled / 0: Disable) - Bit 2: Cache Read Hit W/S For PCI (1: Enabled / 0: Disable) - Bit 1: VESA Clock Skew (1: 4ns/6ns, 0: No Delay/2ns) + Bit 3: Cache Write Hit W/S For PCI (1: Enabled / 0: Disable) + Bit 2: Cache Read Hit W/S For PCI (1: Enabled / 0: Disable) + Bit 1: VESA Clock Skew (1: 4ns/6ns, 0: No Delay/2ns) Register 1Bh: - Bit 6: Enable SMRAM (always at 30000-4FFFF) in SMM - Bit 5: ???? - Bit 4: Software SMI# - Bit 3: DC000-DFFFF Shadow Enable - Bit 2: D8000-DBFFF Shadow Enable - Bit 1: D4000-D7FFF Shadow Enable - Bit 0: D0000-D3FFF Shadow Enable + Bit 6: Enable SMRAM (always at 30000-4FFFF) in SMM + Bit 5: ???? + Bit 4: Software SMI# + Bit 3: DC000-DFFFF Shadow Enable + Bit 2: D8000-DBFFF Shadow Enable + Bit 1: D4000-D7FFF Shadow Enable + Bit 0: D0000-D3FFF Shadow Enable Register 1Ch: - Bits 7-4: INTA IRQ routing (0 = disabled, 1 to F = IRQ) - Bit 3: CC000-CFFFF Shadow Enable - Bit 2: C8000-CBFFF Shadow Enable - Bit 1: C4000-C7FFF Shadow Enable - Bit 0: C0000-C3FFF Shadow Enable + Bits 7-4: INTA IRQ routing (0 = disabled, 1 to F = IRQ) + Bit 3: CC000-CFFFF Shadow Enable + Bit 2: C8000-CBFFF Shadow Enable + Bit 1: C4000-C7FFF Shadow Enable + Bit 0: C0000-C3FFF Shadow Enable Register 1Dh: - Bits 7-4: INTB IRQ routing (0 = disabled, 1 to F = IRQ) + Bits 7-4: INTB IRQ routing (0 = disabled, 1 to F = IRQ) Register 1Eh: - Bits 7-4: INTC IRQ routing (0 = disabled, 1 to F = IRQ) - Bit 1: C4000-C7FFF Cacheable - Bit 0: C0000-C3FFF Cacheable + Bits 7-4: INTC IRQ routing (0 = disabled, 1 to F = IRQ) + Bit 1: C4000-C7FFF Cacheable + Bit 0: C0000-C3FFF Cacheable Register 21h: - Bits 7-4: INTD IRQ routing (0 = disabled, 1 to F = IRQ) + Bits 7-4: INTD IRQ routing (0 = disabled, 1 to F = IRQ) Register 22h: - Bit 5: Local Bus Master #2 select (0 = VESA, 1 = PCI) - Bit 4: Local Bus Master #1 select (0 = VESA, 1 = PCI) - Bits 1-0: Internal HADS# Delay Always (00 = No Delay, 01 = 1 Clk, 10 = 2 Clks) + Bit 5: Local Bus Master #2 select (0 = VESA, 1 = PCI) + Bit 4: Local Bus Master #1 select (0 = VESA, 1 = PCI) + Bits 1-0: Internal HADS# Delay Always (00 = No Delay, 01 = 1 Clk, 10 = 2 Clks) Register 23h: - Bit 7: Seven Bits Tag (1: Enabled / 0: Disable) - Bit 3: Extend LBRDY#(VL Master) (1: Enabled / 0: Disable) - Bit 2: Sync LRDY#(VL Slave) (1: Enabled / 0: Disable) - Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable) + Bit 7: Seven Bits Tag (1: Enabled / 0: Disable) + Bit 3: Extend LBRDY#(VL Master) (1: Enabled / 0: Disable) + Bit 2: Sync LRDY#(VL Slave) (1: Enabled / 0: Disable) + Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable) */ typedef struct { - uint8_t idx, access_data, - regs[256], pci_conf[256]; + uint8_t idx, access_data, + regs[256], pci_conf[256]; - smram_t *smram; + smram_t *smram; } ims8848_t; - #ifdef ENABLE_IMS8848_LOG int ims8848_do_log = ENABLE_IMS8848_LOG; - static void ims8848_log(const char *fmt, ...) { va_list ap; if (ims8848_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define ims8848_log(fmt, ...) +# define ims8848_log(fmt, ...) #endif - /* Shadow write always enabled, 1B and 1C control C000-DFFF read. */ static void ims8848_recalc(ims8848_t *dev) { - int i, state_on; + int i, state_on; uint32_t base; ims8848_log("SHADOW: 00 = %02X, 08 = %02X, 1B = %02X, 1C = %02X\n", - dev->regs[0x00], dev->regs[0x08], dev->regs[0x1b], dev->regs[0x1c]); + dev->regs[0x00], dev->regs[0x08], dev->regs[0x1b], dev->regs[0x1c]); state_on = MEM_READ_INTERNAL; state_on |= (dev->regs[0x08] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; for (i = 0; i < 2; i++) { - base = 0xe0000 + (i << 16); - if (dev->regs[0x00] & (1 << (i + 2))) - mem_set_mem_state_both(base, 0x10000, state_on); - else - mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + base = 0xe0000 + (i << 16); + if (dev->regs[0x00] & (1 << (i + 2))) + mem_set_mem_state_both(base, 0x10000, state_on); + else + mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); } for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); - if (dev->regs[0x1c] & (1 << i)) - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + base = 0xc0000 + (i << 14); + if (dev->regs[0x1c] & (1 << i)) + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - base = 0xd0000 + (i << 14); - if (dev->regs[0x1b] & (1 << i)) - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + base = 0xd0000 + (i << 14); + if (dev->regs[0x1b] & (1 << i)) + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); } flushmmucache_nopc(); } - static void ims8848_base_memory(ims8848_t *dev) { /* We can use the proper mem_set_access to handle that. */ - mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x12] & 2) ? - (MEM_READ_DISABLED | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); + mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x12] & 2) ? (MEM_READ_DISABLED | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)); } - static void ims8848_smram(ims8848_t *dev) { @@ -202,137 +195,137 @@ ims8848_smram(ims8848_t *dev) smram_enable(dev->smram, 0x00030000, 0x00030000, 0x20000, dev->regs[0x1b] & 0x40, 1); } - static void ims8848_write(uint16_t addr, uint8_t val, void *priv) { ims8848_t *dev = (ims8848_t *) priv; - uint8_t old = dev->regs[dev->idx]; + uint8_t old = dev->regs[dev->idx]; switch (addr) { - case 0x22: - ims8848_log("[W] IDX = %02X\n", val); - dev->idx = val; - break; - case 0x23: - ims8848_log("[W] IDX IN = %02X\n", val); - if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0))) - dev->access_data = 1; - break; - case 0x24: - ims8848_log("[W] [%i] REG %02X = %02X\n", dev->access_data, dev->idx, val); - if (dev->access_data) { - dev->regs[dev->idx] = val; - switch (dev->idx) { - case 0x00: case 0x08: case 0x1b: case 0x1c: - /* Shadow RAM */ - ims8848_recalc(dev); - if (dev->idx == 0x1b) { - ims8848_smram(dev); - if (!(old & 0x10) && (val & 0x10)) - smi_raise(); - } else if (dev->idx == 0x1c) - pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); - break; + case 0x22: + ims8848_log("[W] IDX = %02X\n", val); + dev->idx = val; + break; + case 0x23: + ims8848_log("[W] IDX IN = %02X\n", val); + if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0))) + dev->access_data = 1; + break; + case 0x24: + ims8848_log("[W] [%i] REG %02X = %02X\n", dev->access_data, dev->idx, val); + if (dev->access_data) { + dev->regs[dev->idx] = val; + switch (dev->idx) { + case 0x00: + case 0x08: + case 0x1b: + case 0x1c: + /* Shadow RAM */ + ims8848_recalc(dev); + if (dev->idx == 0x1b) { + ims8848_smram(dev); + if (!(old & 0x10) && (val & 0x10)) + smi_raise(); + } else if (dev->idx == 0x1c) + pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); + break; - case 0x1d: case 0x1e: - pci_set_irq_routing(PCI_INTB + (dev->idx - 0x1d), (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); - break; - case 0x21: - pci_set_irq_routing(PCI_INTD, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); - break; + case 0x1d: + case 0x1e: + pci_set_irq_routing(PCI_INTB + (dev->idx - 0x1d), (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); + break; + case 0x21: + pci_set_irq_routing(PCI_INTD, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); + break; - case 0x12: - /* Base Memory */ - ims8848_base_memory(dev); - break; - } - dev->access_data = 0; - } - break; + case 0x12: + /* Base Memory */ + ims8848_base_memory(dev); + break; + } + dev->access_data = 0; + } + break; } } - static uint8_t ims8848_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; ims8848_t *dev = (ims8848_t *) priv; #ifdef ENABLE_IMS8848_LOG uint8_t old_ad = dev->access_data; #endif switch (addr) { - case 0x22: - ims8848_log("[R] IDX = %02X\n", ret); - ret = dev->idx; - break; - case 0x23: - ims8848_log("[R] IDX IN = %02X\n", ret); - ret = (dev->idx >> 4) | (dev->idx << 4); - break; - case 0x24: - if (dev->access_data) { - ret = dev->regs[dev->idx]; - dev->access_data = 0; - } - ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret); - break; + case 0x22: + ims8848_log("[R] IDX = %02X\n", ret); + ret = dev->idx; + break; + case 0x23: + ims8848_log("[R] IDX IN = %02X\n", ret); + ret = (dev->idx >> 4) | (dev->idx << 4); + break; + case 0x24: + if (dev->access_data) { + ret = dev->regs[dev->idx]; + dev->access_data = 0; + } + ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret); + break; } return ret; } - static void ims8849_pci_write(int func, int addr, uint8_t val, void *priv) { - ims8848_t *dev = (ims8848_t *)priv; + ims8848_t *dev = (ims8848_t *) priv; ims8848_log("IMS 884x-PCI: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80)); - if (func == 0) switch (addr) { - case 0x04: - dev->pci_conf[addr] = val; - break; + if (func == 0) + switch (addr) { + case 0x04: + dev->pci_conf[addr] = val; + break; - case 0x05: - dev->pci_conf[addr] = val & 3; - break; + case 0x05: + dev->pci_conf[addr] = val & 3; + break; - case 0x07: - dev->pci_conf[addr] &= val & 0xf7; - break; + case 0x07: + dev->pci_conf[addr] &= val & 0xf7; + break; - case 0x0c ... 0x0d: - dev->pci_conf[addr] = val; - break; + case 0x0c ... 0x0d: + dev->pci_conf[addr] = val; + break; - case 0x52 ... 0x55: - dev->pci_conf[addr] = val; - break; - } + case 0x52 ... 0x55: + dev->pci_conf[addr] = val; + break; + } } - static uint8_t ims8849_pci_read(int func, int addr, void *priv) { - ims8848_t *dev = (ims8848_t *)priv; - uint8_t ret = 0xff; + ims8848_t *dev = (ims8848_t *) priv; + uint8_t ret = 0xff; if (func == 0) - ret = dev->pci_conf[addr]; + ret = dev->pci_conf[addr]; return ret; } - static void ims8848_reset(void *priv) { - ims8848_t *dev = (ims8848_t *)priv; + ims8848_t *dev = (ims8848_t *) priv; memset(dev->regs, 0x00, sizeof(dev->regs)); memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf)); @@ -347,7 +340,7 @@ ims8848_reset(void *priv) dev->pci_conf[0x0b] = 0x06; - ims8848_recalc(dev); /* Shadow RAM Setup */ + ims8848_recalc(dev); /* Shadow RAM Setup */ ims8848_base_memory(dev); /* Base Memory Setup */ pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); @@ -358,7 +351,6 @@ ims8848_reset(void *priv) ims8848_smram(dev); } - static void ims8848_close(void *priv) { @@ -369,7 +361,6 @@ ims8848_close(void *priv) free(dev); } - static void * ims8848_init(const device_t *info) { @@ -379,12 +370,12 @@ ims8848_init(const device_t *info) device_add(&port_92_device); /* IMS 8848: - 22h Index - 23h Data Unlock - 24h Data + 22h Index + 23h Data Unlock + 24h Data IMS 8849: - PCI Device 0: IMS 8849 Dummy for compatibility reasons + PCI Device 0: IMS 8849 Dummy for compatibility reasons */ io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev); pci_add_card(PCI_ADD_NORTHBRIDGE, ims8849_pci_read, ims8849_pci_write, dev); @@ -401,15 +392,15 @@ ims8848_init(const device_t *info) } const device_t ims8848_device = { - .name = "IMS 8848/8849", + .name = "IMS 8848/8849", .internal_name = "ims8848", - .flags = 0, - .local = 0, - .init = ims8848_init, - .close = ims8848_close, - .reset = ims8848_reset, + .flags = 0, + .local = 0, + .init = ims8848_init, + .close = ims8848_close, + .reset = ims8848_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_420ex.c b/src/chipset/intel_420ex.c index 11c66b833..406aeb48a 100644 --- a/src/chipset/intel_420ex.c +++ b/src/chipset/intel_420ex.c @@ -36,72 +36,66 @@ #include <86box/chipset.h> #include <86box/spd.h> - -#define MEM_STATE_SHADOW_R 0x01 -#define MEM_STATE_SHADOW_W 0x02 -#define MEM_STATE_SMRAM 0x04 - +#define MEM_STATE_SHADOW_R 0x01 +#define MEM_STATE_SHADOW_W 0x02 +#define MEM_STATE_SMRAM 0x04 typedef struct { - uint8_t has_ide, smram_locked, - regs[256]; + uint8_t has_ide, smram_locked, + regs[256]; - uint16_t timer_base, - timer_latch; + uint16_t timer_base, + timer_latch; - smram_t *smram; + smram_t *smram; - double fast_off_period; + double fast_off_period; - pc_timer_t timer, fast_off_timer; + pc_timer_t timer, fast_off_timer; - apm_t * apm; - port_92_t * port_92; + apm_t *apm; + port_92_t *port_92; } i420ex_t; - #ifdef ENABLE_I420EX_LOG int i420ex_do_log = ENABLE_I420EX_LOG; - static void i420ex_log(const char *fmt, ...) { va_list ap; if (i420ex_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define i420ex_log(fmt, ...) +# define i420ex_log(fmt, ...) #endif - static void i420ex_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { - case 0: - mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 2: - mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 3: - mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; + case 0: + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 2: + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 3: + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; } flushmmucache_nopc(); } - static void i420ex_smram_handler_phase0(void) { @@ -109,7 +103,6 @@ i420ex_smram_handler_phase0(void) smram_disable_all(); } - static void i420ex_smram_handler_phase1(i420ex_t *dev) { @@ -119,244 +112,252 @@ i420ex_smram_handler_phase1(i420ex_t *dev) uint32_t size = 0x00010000; switch (regs[0x70] & 0x07) { - case 0: case 1: - default: - host_base = ram_base = 0x00000000; - size = 0x00000000; - break; - case 2: - host_base = 0x000a0000; - ram_base = 0x000a0000; - break; - case 3: - host_base = 0x000b0000; - ram_base = 0x000b0000; - break; - case 4: - host_base = 0x000c0000; - ram_base = 0x000a0000; - break; - case 5: - host_base = 0x000d0000; - ram_base = 0x000a0000; - break; - case 6: - host_base = 0x000e0000; - ram_base = 0x000a0000; - break; - case 7: - host_base = 0x000f0000; - ram_base = 0x000a0000; - break; + case 0: + case 1: + default: + host_base = ram_base = 0x00000000; + size = 0x00000000; + break; + case 2: + host_base = 0x000a0000; + ram_base = 0x000a0000; + break; + case 3: + host_base = 0x000b0000; + ram_base = 0x000b0000; + break; + case 4: + host_base = 0x000c0000; + ram_base = 0x000a0000; + break; + case 5: + host_base = 0x000d0000; + ram_base = 0x000a0000; + break; + case 6: + host_base = 0x000e0000; + ram_base = 0x000a0000; + break; + case 7: + host_base = 0x000f0000; + ram_base = 0x000a0000; + break; } smram_enable(dev->smram, host_base, ram_base, size, - (regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20)); + (regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20)); } - static void i420ex_write(int func, int addr, uint8_t val, void *priv) { i420ex_t *dev = (i420ex_t *) priv; if (func > 0) - return; + return; if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40)) - return; + return; switch (addr) { - case 0x05: - dev->regs[addr] = (val & 0x01); - break; + case 0x05: + dev->regs[addr] = (val & 0x01); + break; - case 0x07: - dev->regs[addr] &= ~(val & 0xf0); - break; + case 0x07: + dev->regs[addr] &= ~(val & 0xf0); + break; - case 0x40: - dev->regs[addr] = (val & 0x7f); - break; - case 0x44: - dev->regs[addr] = (val & 0x07); - break; - case 0x48: - dev->regs[addr] = (val & 0x3f); - if (dev->has_ide) { - ide_pri_disable(); - switch (val & 0x03) { - case 0x01: - ide_set_base(0, 0x01f0); - ide_set_side(0, 0x03f6); - ide_pri_enable(); - break; - case 0x02: - ide_set_base(0, 0x0170); - ide_set_side(0, 0x0376); - ide_pri_enable(); - break; - } - } - break; - case 0x49: case 0x53: - dev->regs[addr] = (val & 0x1f); - break; - case 0x4c: case 0x51: - case 0x57: - case 0x68: case 0x69: - dev->regs[addr] = val; - if (addr == 0x4c) { - dma_alias_remove(); - if (!(val & 0x80)) - dma_alias_set(); - } - break; - case 0x4d: - dev->regs[addr] = (dev->regs[addr] & 0xef) | (val & 0x10); - break; - case 0x4e: - dev->regs[addr] = (val & 0xf7); - break; - case 0x50: - dev->regs[addr] = (val & 0x0f); - break; - case 0x52: - dev->regs[addr] = (val & 0x7f); - break; - case 0x56: - dev->regs[addr] = (val & 0x3e); - break; - case 0x59: /* PAM0 */ - if ((dev->regs[0x59] ^ val) & 0xf0) { - i420ex_map(0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - dev->regs[0x59] = val & 0xf0; - break; - case 0x5a: /* PAM1 */ - if ((dev->regs[0x5a] ^ val) & 0x0f) - i420ex_map(0xc0000, 0x04000, val & 0xf); - if ((dev->regs[0x5a] ^ val) & 0xf0) - i420ex_map(0xc4000, 0x04000, val >> 4); - dev->regs[0x5a] = val; - break; - case 0x5b: /*PAM2 */ - if ((dev->regs[0x5b] ^ val) & 0x0f) - i420ex_map(0xc8000, 0x04000, val & 0xf); - if ((dev->regs[0x5b] ^ val) & 0xf0) - i420ex_map(0xcc000, 0x04000, val >> 4); - dev->regs[0x5b] = val; - break; - case 0x5c: /*PAM3 */ - if ((dev->regs[0x5c] ^ val) & 0x0f) - i420ex_map(0xd0000, 0x04000, val & 0xf); - if ((dev->regs[0x5c] ^ val) & 0xf0) - i420ex_map(0xd4000, 0x04000, val >> 4); - dev->regs[0x5c] = val; - break; - case 0x5d: /* PAM4 */ - if ((dev->regs[0x5d] ^ val) & 0x0f) - i420ex_map(0xd8000, 0x04000, val & 0xf); - if ((dev->regs[0x5d] ^ val) & 0xf0) - i420ex_map(0xdc000, 0x04000, val >> 4); - dev->regs[0x5d] = val; - break; - case 0x5e: /* PAM5 */ - if ((dev->regs[0x5e] ^ val) & 0x0f) - i420ex_map(0xe0000, 0x04000, val & 0xf); - if ((dev->regs[0x5e] ^ val) & 0xf0) - i420ex_map(0xe4000, 0x04000, val >> 4); - dev->regs[0x5e] = val; - break; - case 0x5f: /* PAM6 */ - if ((dev->regs[0x5f] ^ val) & 0x0f) - i420ex_map(0xe8000, 0x04000, val & 0xf); - if ((dev->regs[0x5f] ^ val) & 0xf0) - i420ex_map(0xec000, 0x04000, val >> 4); - dev->regs[0x5f] = val; - break; - case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: - spd_write_drbs(dev->regs, 0x60, 0x64, 1); - break; - case 0x66: case 0x67: - i420ex_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x01), val); - dev->regs[addr] = val & 0x8f; - if (val & 0x80) - pci_set_irq_routing(PCI_INTA + (addr & 0x01), PCI_IRQ_DISABLED); - else - pci_set_irq_routing(PCI_INTA + (addr & 0x01), val & 0xf); - break; - case 0x70: /* SMRAM */ - i420ex_smram_handler_phase0(); - if (dev->smram_locked) - dev->regs[0x70] = (dev->regs[0x70] & 0xdf) | (val & 0x20); - else { - dev->regs[0x70] = (dev->regs[0x70] & 0x88) | (val & 0x77); - dev->smram_locked = (val & 0x10); - if (dev->smram_locked) - dev->regs[0x70] &= 0xbf; - } - i420ex_smram_handler_phase1(dev); - break; - case 0xa0: - dev->regs[addr] = val & 0x1f; - apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80)); - switch ((val & 0x18) >> 3) { - case 0x00: - dev->fast_off_period = PCICLK * 32768.0 * 60000.0; - break; - case 0x01: - default: - dev->fast_off_period = 0.0; - break; - case 0x02: - dev->fast_off_period = PCICLK; - break; - case 0x03: - dev->fast_off_period = PCICLK * 32768.0; - break; - } - cpu_fast_off_count = cpu_fast_off_val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - break; - case 0xa2: - dev->regs[addr] = val & 0xff; - apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); - break; - case 0xaa: - dev->regs[addr] &= (val & 0xff); - break; - case 0xac: case 0xae: - dev->regs[addr] = val & 0xff; - break; - case 0xa4: - dev->regs[addr] = val & 0xfb; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr]; - break; - case 0xa5: - dev->regs[addr] = val; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8); - break; - case 0xa7: - dev->regs[addr] = val & 0xe0; - cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24); - break; - case 0xa8: - dev->regs[addr] = val & 0xff; - cpu_fast_off_val = val; - cpu_fast_off_count = val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - break; + case 0x40: + dev->regs[addr] = (val & 0x7f); + break; + case 0x44: + dev->regs[addr] = (val & 0x07); + break; + case 0x48: + dev->regs[addr] = (val & 0x3f); + if (dev->has_ide) { + ide_pri_disable(); + switch (val & 0x03) { + case 0x01: + ide_set_base(0, 0x01f0); + ide_set_side(0, 0x03f6); + ide_pri_enable(); + break; + case 0x02: + ide_set_base(0, 0x0170); + ide_set_side(0, 0x0376); + ide_pri_enable(); + break; + } + } + break; + case 0x49: + case 0x53: + dev->regs[addr] = (val & 0x1f); + break; + case 0x4c: + case 0x51: + case 0x57: + case 0x68: + case 0x69: + dev->regs[addr] = val; + if (addr == 0x4c) { + dma_alias_remove(); + if (!(val & 0x80)) + dma_alias_set(); + } + break; + case 0x4d: + dev->regs[addr] = (dev->regs[addr] & 0xef) | (val & 0x10); + break; + case 0x4e: + dev->regs[addr] = (val & 0xf7); + break; + case 0x50: + dev->regs[addr] = (val & 0x0f); + break; + case 0x52: + dev->regs[addr] = (val & 0x7f); + break; + case 0x56: + dev->regs[addr] = (val & 0x3e); + break; + case 0x59: /* PAM0 */ + if ((dev->regs[0x59] ^ val) & 0xf0) { + i420ex_map(0xf0000, 0x10000, val >> 4); + shadowbios = (val & 0x10); + } + dev->regs[0x59] = val & 0xf0; + break; + case 0x5a: /* PAM1 */ + if ((dev->regs[0x5a] ^ val) & 0x0f) + i420ex_map(0xc0000, 0x04000, val & 0xf); + if ((dev->regs[0x5a] ^ val) & 0xf0) + i420ex_map(0xc4000, 0x04000, val >> 4); + dev->regs[0x5a] = val; + break; + case 0x5b: /*PAM2 */ + if ((dev->regs[0x5b] ^ val) & 0x0f) + i420ex_map(0xc8000, 0x04000, val & 0xf); + if ((dev->regs[0x5b] ^ val) & 0xf0) + i420ex_map(0xcc000, 0x04000, val >> 4); + dev->regs[0x5b] = val; + break; + case 0x5c: /*PAM3 */ + if ((dev->regs[0x5c] ^ val) & 0x0f) + i420ex_map(0xd0000, 0x04000, val & 0xf); + if ((dev->regs[0x5c] ^ val) & 0xf0) + i420ex_map(0xd4000, 0x04000, val >> 4); + dev->regs[0x5c] = val; + break; + case 0x5d: /* PAM4 */ + if ((dev->regs[0x5d] ^ val) & 0x0f) + i420ex_map(0xd8000, 0x04000, val & 0xf); + if ((dev->regs[0x5d] ^ val) & 0xf0) + i420ex_map(0xdc000, 0x04000, val >> 4); + dev->regs[0x5d] = val; + break; + case 0x5e: /* PAM5 */ + if ((dev->regs[0x5e] ^ val) & 0x0f) + i420ex_map(0xe0000, 0x04000, val & 0xf); + if ((dev->regs[0x5e] ^ val) & 0xf0) + i420ex_map(0xe4000, 0x04000, val >> 4); + dev->regs[0x5e] = val; + break; + case 0x5f: /* PAM6 */ + if ((dev->regs[0x5f] ^ val) & 0x0f) + i420ex_map(0xe8000, 0x04000, val & 0xf); + if ((dev->regs[0x5f] ^ val) & 0xf0) + i420ex_map(0xec000, 0x04000, val >> 4); + dev->regs[0x5f] = val; + break; + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + spd_write_drbs(dev->regs, 0x60, 0x64, 1); + break; + case 0x66: + case 0x67: + i420ex_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x01), val); + dev->regs[addr] = val & 0x8f; + if (val & 0x80) + pci_set_irq_routing(PCI_INTA + (addr & 0x01), PCI_IRQ_DISABLED); + else + pci_set_irq_routing(PCI_INTA + (addr & 0x01), val & 0xf); + break; + case 0x70: /* SMRAM */ + i420ex_smram_handler_phase0(); + if (dev->smram_locked) + dev->regs[0x70] = (dev->regs[0x70] & 0xdf) | (val & 0x20); + else { + dev->regs[0x70] = (dev->regs[0x70] & 0x88) | (val & 0x77); + dev->smram_locked = (val & 0x10); + if (dev->smram_locked) + dev->regs[0x70] &= 0xbf; + } + i420ex_smram_handler_phase1(dev); + break; + case 0xa0: + dev->regs[addr] = val & 0x1f; + apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80)); + switch ((val & 0x18) >> 3) { + case 0x00: + dev->fast_off_period = PCICLK * 32768.0 * 60000.0; + break; + case 0x01: + default: + dev->fast_off_period = 0.0; + break; + case 0x02: + dev->fast_off_period = PCICLK; + break; + case 0x03: + dev->fast_off_period = PCICLK * 32768.0; + break; + } + cpu_fast_off_count = cpu_fast_off_val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + break; + case 0xa2: + dev->regs[addr] = val & 0xff; + apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); + break; + case 0xaa: + dev->regs[addr] &= (val & 0xff); + break; + case 0xac: + case 0xae: + dev->regs[addr] = val & 0xff; + break; + case 0xa4: + dev->regs[addr] = val & 0xfb; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr]; + break; + case 0xa5: + dev->regs[addr] = val; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8); + break; + case 0xa7: + dev->regs[addr] = val & 0xe0; + cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24); + break; + case 0xa8: + dev->regs[addr] = val & 0xff; + cpu_fast_off_val = val; + cpu_fast_off_count = val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + break; } } - static uint8_t i420ex_read(int func, int addr, void *priv) { i420ex_t *dev = (i420ex_t *) priv; - uint8_t ret; + uint8_t ret; ret = 0xff; @@ -366,7 +367,6 @@ i420ex_read(int func, int addr, void *priv) return ret; } - static void i420ex_reset_hard(void *priv) { @@ -374,8 +374,10 @@ i420ex_reset_hard(void *priv) memset(dev->regs, 0, 256); - dev->regs[0x00] = 0x86; dev->regs[0x01] = 0x80; /*Intel*/ - dev->regs[0x02] = 0x86; dev->regs[0x03] = 0x04; /*82378IB (I420EX)*/ + dev->regs[0x00] = 0x86; + dev->regs[0x01] = 0x80; /*Intel*/ + dev->regs[0x02] = 0x86; + dev->regs[0x03] = 0x04; /*82378IB (I420EX)*/ dev->regs[0x04] = 0x07; dev->regs[0x07] = 0x02; @@ -383,13 +385,14 @@ i420ex_reset_hard(void *priv) dev->regs[0x4e] = 0x03; /* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */ if (cpu_busspeed >= 33333333) - dev->regs[0x50] |= 0x02; + dev->regs[0x50] |= 0x02; dev->regs[0x51] = 0x80; dev->regs[0x60] = dev->regs[0x61] = dev->regs[0x62] = dev->regs[0x63] = dev->regs[0x64] = 0x01; - dev->regs[0x66] = 0x80; dev->regs[0x67] = 0x80; - dev->regs[0x69] = 0x02; - dev->regs[0xa0] = 0x08; - dev->regs[0xa8] = 0x0f; + dev->regs[0x66] = 0x80; + dev->regs[0x67] = 0x80; + dev->regs[0x69] = 0x02; + dev->regs[0xa0] = 0x08; + dev->regs[0xa8] = 0x0f; mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); @@ -398,20 +401,18 @@ i420ex_reset_hard(void *priv) pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); if (dev->has_ide) - ide_pri_disable(); + ide_pri_disable(); } - static void i420ex_apm_out(uint16_t port, uint8_t val, void *p) { i420ex_t *dev = (i420ex_t *) p; if (dev->apm->do_smi) - dev->regs[0xaa] |= 0x80; + dev->regs[0xaa] |= 0x80; } - static void i420ex_fast_off_count(void *priv) { @@ -423,22 +424,21 @@ i420ex_fast_off_count(void *priv) dev->regs[0xaa] |= 0x20; } - static void i420ex_reset(void *p) { i420ex_t *dev = (i420ex_t *) p; - int i; + int i; i420ex_write(0, 0x48, 0x00, p); for (i = 0; i < 7; i++) - i420ex_write(0, 0x59 + i, 0x00, p); + i420ex_write(0, 0x59 + i, 0x00, p); for (i = 0; i <= 4; i++) - i420ex_write(0, 0x60 + i, 0x01, p); + i420ex_write(0, 0x60 + i, 0x01, p); - dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */ + dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */ dev->smram_locked = 0; i420ex_write(0, 0x70, 0x00, p); @@ -454,38 +454,35 @@ i420ex_reset(void *p) i420ex_write(0, 0xa8, 0x0f, p); } - static void i420ex_close(void *p) { - i420ex_t *dev = (i420ex_t *)p; + i420ex_t *dev = (i420ex_t *) p; smram_del(dev->smram); free(dev); } - static void i420ex_speed_changed(void *priv) { i420ex_t *dev = (i420ex_t *) priv; - int te; + int te; te = timer_is_enabled(&dev->timer); timer_disable(&dev->timer); if (te) - timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); + timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); te = timer_is_enabled(&dev->fast_off_timer); timer_stop(&dev->fast_off_timer); if (te) - timer_on_auto(&dev->fast_off_timer, dev->fast_off_period); + timer_on_auto(&dev->fast_off_timer, dev->fast_off_period); } - static void * i420ex_init(const device_t *info) { @@ -502,7 +499,7 @@ i420ex_init(const device_t *info) cpu_fast_off_flags = 0x00000000; - cpu_fast_off_val = dev->regs[0xa8]; + cpu_fast_off_val = dev->regs[0xa8]; cpu_fast_off_count = cpu_fast_off_val + 1; cpu_register_fast_off_handler(&dev->fast_off_timer); @@ -523,29 +520,29 @@ i420ex_init(const device_t *info) } const device_t i420ex_device = { - .name = "Intel 82420EX", + .name = "Intel 82420EX", .internal_name = "i420ex", - .flags = DEVICE_PCI, - .local = 0x00, - .init = i420ex_init, - .close = i420ex_close, - .reset = i420ex_reset, + .flags = DEVICE_PCI, + .local = 0x00, + .init = i420ex_init, + .close = i420ex_close, + .reset = i420ex_reset, { .available = NULL }, .speed_changed = i420ex_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i420ex_ide_device = { - .name = "Intel 82420EX (With IDE)", + .name = "Intel 82420EX (With IDE)", .internal_name = "i420ex_ide", - .flags = DEVICE_PCI, - .local = 0x01, - .init = i420ex_init, - .close = i420ex_close, - .reset = i420ex_reset, + .flags = DEVICE_PCI, + .local = 0x01, + .init = i420ex_init, + .close = i420ex_close, + .reset = i420ex_reset, { .available = NULL }, .speed_changed = i420ex_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 49b8f3fc2..5ed236935 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -31,9 +31,7 @@ #include <86box/machine.h> #include <86box/agpgart.h> - -enum -{ +enum { INTEL_420TX, INTEL_420ZX, INTEL_430LX, @@ -52,160 +50,152 @@ enum typedef struct { - uint8_t pm2_cntrl, - smram_locked, max_drb, - drb_unit, drb_default; - uint8_t regs[256], regs_locked[256]; - uint8_t mem_state[256]; - int type; - smram_t *smram_low, *smram_high; + uint8_t pm2_cntrl, + smram_locked, max_drb, + drb_unit, drb_default; + uint8_t regs[256], regs_locked[256]; + uint8_t mem_state[256]; + int type; + smram_t *smram_low, *smram_high; agpgart_t *agpgart; - void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit); + void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit); } i4x0_t; - #ifdef ENABLE_I4X0_LOG int i4x0_do_log = ENABLE_I4X0_LOG; - static void i4x0_log(const char *fmt, ...) { va_list ap; if (i4x0_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define i4x0_log(fmt, ...) +# define i4x0_log(fmt, ...) #endif - static void i4x0_map(i4x0_t *dev, uint32_t addr, uint32_t size, int state) { - uint32_t base = addr >> 12; - int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY, - MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL }; + uint32_t base = addr >> 12; + int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY, + MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL }; state &= 3; if (dev->mem_state[base] != state) { - mem_set_mem_state_both(addr, size, states[state]); - dev->mem_state[base] = state; - flushmmucache_nopc(); + mem_set_mem_state_both(addr, size, states[state]); + dev->mem_state[base] = state; + flushmmucache_nopc(); } } - static void i4x0_smram_handler_phase0(i4x0_t *dev) { uint32_t tom = (mem_size << 10); - if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && - smram_enabled(dev->smram_high)) { - tom -= (1 << 20); - mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && smram_enabled(dev->smram_high)) { + tom -= (1 << 20); + mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); } /* Disable any active mappings. */ smram_disable_all(); } - static void i4x0_smram_handler_phase1(i4x0_t *dev) { - uint8_t *regs = (uint8_t *) dev->regs; - uint32_t tom = (mem_size << 10); - uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]); + uint8_t *regs = (uint8_t *) dev->regs; + uint32_t tom = (mem_size << 10); + uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]); uint8_t *ext_reg = (dev->type >= INTEL_440BX) ? &(regs[0x73]) : &(regs[0x71]); uint32_t s, base[2] = { 0x000a0000, 0x00000000 }; uint32_t size[2] = { 0x00010000, 0x00000000 }; if ((dev->type <= INTEL_420ZX) || (dev->type >= INTEL_430FX)) { - /* Set temporary bases and sizes. */ - if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && - (*ext_reg & 0x80)) { - base[0] = 0x100a0000; - size[0] = 0x00060000; - } else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) { - base[0] = 0x000c0000; - size[0] = 0x00010000; - } else { - base[0] = 0x000a0000; - size[0] = 0x00020000; - } + /* Set temporary bases and sizes. */ + if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && (*ext_reg & 0x80)) { + base[0] = 0x100a0000; + size[0] = 0x00060000; + } else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) { + base[0] = 0x000c0000; + size[0] = 0x00010000; + } else { + base[0] = 0x000a0000; + size[0] = 0x00020000; + } - if (*reg & 0x08) - smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0], - ((*reg & 0x78) == 0x48), (*reg & 0x08)); + if (*reg & 0x08) + smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0], + ((*reg & 0x78) == 0x48), (*reg & 0x08)); - if ((*reg & 0x28) == 0x28) { - /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but - code still goes to DRAM. */ - mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); - } + if ((*reg & 0x28) == 0x28) { + /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but + code still goes to DRAM. */ + mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); + } - /* TSEG mapping. */ - if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { - if ((*reg & 0x08) && (*ext_reg & 0x01)) { - size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03))); - tom -= size[1]; - base[1] = tom; - } else - base[1] = size[1] = 0x00000000; + /* TSEG mapping. */ + if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { + if ((*reg & 0x08) && (*ext_reg & 0x01)) { + size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03))); + tom -= size[1]; + base[1] = tom; + } else + base[1] = size[1] = 0x00000000; - if (size[1] != 0x00000000) { - smram_enable(dev->smram_high, base[1] + (1 << 28), base[1], size[1], - 0, 1); + if (size[1] != 0x00000000) { + smram_enable(dev->smram_high, base[1] + (1 << 28), base[1], size[1], + 0, 1); - mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } - } + mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } + } } else { - size[0] = 0x00010000; - switch (*reg & 0x03) { - case 0: - default: - base[0] = (mem_size << 10) - size[0]; - s = 1; - break; - case 1: - base[0] = size[0] = 0x00000000; - s = 1; - break; - case 2: - base[0] = 0x000a0000; - s = 0; - break; - case 3: - base[0] = 0x000b0000; - s = 0; - break; - } + size[0] = 0x00010000; + switch (*reg & 0x03) { + case 0: + default: + base[0] = (mem_size << 10) - size[0]; + s = 1; + break; + case 1: + base[0] = size[0] = 0x00000000; + s = 1; + break; + case 2: + base[0] = 0x000a0000; + s = 0; + break; + case 3: + base[0] = 0x000b0000; + s = 0; + break; + } - if (size[0] != 0x00000000) { - smram_enable(dev->smram_low, base[0], base[0], size[0], - (((*reg & 0x38) == 0x20) || s), 1); + if (size[0] != 0x00000000) { + smram_enable(dev->smram_low, base[0], base[0], size[0], + (((*reg & 0x38) == 0x20) || s), 1); - if (*reg & 0x10) { - /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but - code still goes to DRAM. */ - mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); - } - } + if (*reg & 0x10) { + /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but + code still goes to DRAM. */ + mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); + } + } } flushmmucache(); } - static void i4x0_mask_bar(uint8_t *regs, void *agpgart) { @@ -218,17 +208,16 @@ i4x0_mask_bar(uint8_t *regs, void *agpgart) regs[0x13] = (bar >> 24) & 0xff; if (!agpgart) - return; + return; /* Map aperture and GART. */ agpgart_set_aperture(agpgart, - bar, - ((uint32_t) (uint8_t) (~regs[0xb4] & 0x3f) + 1) << 22, - !!(regs[0x51] & 0x02)); + bar, + ((uint32_t) (uint8_t) (~regs[0xb4] & 0x3f) + 1) << 22, + !!(regs[0x51] & 0x02)); agpgart_set_gart(agpgart, (regs[0xb9] << 8) | (regs[0xba] << 16) | (regs[0xbb] << 24)); } - static uint8_t pm2_cntrl_read(uint16_t addr, void *p) { @@ -237,7 +226,6 @@ pm2_cntrl_read(uint16_t addr, void *p) return dev->pm2_cntrl & 0x01; } - static void pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) { @@ -246,1055 +234,1216 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) dev->pm2_cntrl = val & 0x01; } - static void i4x0_write(int func, int addr, uint8_t val, void *priv) { - i4x0_t *dev = (i4x0_t *) priv; - uint8_t *regs = (uint8_t *) dev->regs; + i4x0_t *dev = (i4x0_t *) priv; + uint8_t *regs = (uint8_t *) dev->regs; uint8_t *regs_l = (uint8_t *) dev->regs_locked; - int i; + int i; if (func > 0) - return; + return; - if (func == 0) switch (addr) { - case 0x04: /*Command register*/ - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: - case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX: - default: - regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42); - break; - case INTEL_430FX: case INTEL_430HX: case INTEL_430VX: case INTEL_430TX: - case INTEL_440FX: - regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02); - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x04] = val & 0x40; - break; - } - break; - case 0x05: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: - case INTEL_430HX: case INTEL_440FX: case INTEL_440BX: case INTEL_440GX: - case INTEL_440ZX: - regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01); - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x05] = val & 0x01; - break; - } - break; - case 0x07: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: - case INTEL_430HX: - default: - regs[0x07] &= ~(val & 0x70); - break; - case INTEL_430FX: case INTEL_430VX: - case INTEL_430TX: - regs[0x07] &= ~(val & 0x30); - break; - case INTEL_440FX: - regs[0x07] &= ~(val & 0xf9); - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x07] &= ~(val & 0xf1); - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x07] &= ~(val & 0xf0); - break; - } - break; - case 0x0d: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: - regs[0x0d] = (val & 0xf0); - break; - default: - regs[0x0d] = (val & 0xf8); - break; - } - break; - case 0x0f: - switch (dev->type) { - case INTEL_430FX: case INTEL_430HX: case INTEL_430VX: case INTEL_430TX: - regs[0x0f] = (val & 0x40); - break; - } - break; - case 0x12: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x12] = (val & 0xc0); - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; - case 0x13: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x13] = val; - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; - case 0x2c: case 0x2d: case 0x2e: case 0x2f: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - if (!regs_l[addr]) { - regs[addr] = val; - regs_l[addr] = 1; - } - break; - } - break; + if (func == 0) + switch (addr) { + case 0x04: /*Command register*/ + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + case INTEL_440BX: + case INTEL_440GX: + case INTEL_440ZX: + default: + regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42); + break; + case INTEL_430FX: + case INTEL_430HX: + case INTEL_430VX: + case INTEL_430TX: + case INTEL_440FX: + regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02); + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x04] = val & 0x40; + break; + } + break; + case 0x05: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + case INTEL_440BX: + case INTEL_440GX: + case INTEL_440ZX: + regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01); + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x05] = val & 0x01; + break; + } + break; + case 0x07: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + case INTEL_430HX: + default: + regs[0x07] &= ~(val & 0x70); + break; + case INTEL_430FX: + case INTEL_430VX: + case INTEL_430TX: + regs[0x07] &= ~(val & 0x30); + break; + case INTEL_440FX: + regs[0x07] &= ~(val & 0xf9); + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x07] &= ~(val & 0xf1); + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x07] &= ~(val & 0xf0); + break; + } + break; + case 0x0d: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[0x0d] = (val & 0xf0); + break; + default: + regs[0x0d] = (val & 0xf8); + break; + } + break; + case 0x0f: + switch (dev->type) { + case INTEL_430FX: + case INTEL_430HX: + case INTEL_430VX: + case INTEL_430TX: + regs[0x0f] = (val & 0x40); + break; + } + break; + case 0x12: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x12] = (val & 0xc0); + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; + case 0x13: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x13] = val; + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + if (!regs_l[addr]) { + regs[addr] = val; + regs_l[addr] = 1; + } + break; + } + break; - case 0x4f: - switch (dev->type) { - case INTEL_430HX: - regs[0x4f] = (val & 0x84); - break; - case INTEL_430VX: - regs[0x4f] = (val & 0x94); - break; - case INTEL_430TX: - regs[0x4f] = (val & 0x80); - break; - } - break; - case 0x50: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: default: - regs[0x50] = (val & 0xe5); - break; - case INTEL_430NX: - regs[0x50] = (val & 0xe7); - break; - case INTEL_430FX: - regs[0x50] = (val & 0xef); - break; - case INTEL_430HX: - regs[0x50] = (val & 0xf7); - break; - case INTEL_430VX: case INTEL_430TX: - regs[0x50] = (val & 0x08); - break; - case INTEL_440FX: - regs[0x50] = (val & 0xf4); - break; - case INTEL_440LX: - regs[0x50] = (val & 0x70); - break; - case INTEL_440EX: - regs[0x50] = (val & 0x20); - break; - case INTEL_440BX: - regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb); - break; - case INTEL_440GX: - regs[0x50] = (regs[0x50] & 0x04) | (val & 0xe8); - break; - case INTEL_440ZX: - regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb); - break; + case 0x4f: + switch (dev->type) { + case INTEL_430HX: + regs[0x4f] = (val & 0x84); + break; + case INTEL_430VX: + regs[0x4f] = (val & 0x94); + break; + case INTEL_430TX: + regs[0x4f] = (val & 0x80); + break; + } + break; + case 0x50: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + default: + regs[0x50] = (val & 0xe5); + break; + case INTEL_430NX: + regs[0x50] = (val & 0xe7); + break; + case INTEL_430FX: + regs[0x50] = (val & 0xef); + break; + case INTEL_430HX: + regs[0x50] = (val & 0xf7); + break; + case INTEL_430VX: + case INTEL_430TX: + regs[0x50] = (val & 0x08); + break; + case INTEL_440FX: + regs[0x50] = (val & 0xf4); + break; + case INTEL_440LX: + regs[0x50] = (val & 0x70); + break; + case INTEL_440EX: + regs[0x50] = (val & 0x20); + break; + case INTEL_440BX: + regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb); + break; + case INTEL_440GX: + regs[0x50] = (regs[0x50] & 0x04) | (val & 0xe8); + break; + case INTEL_440ZX: + regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb); + break; + } + break; + case 0x51: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[0x51] = (val & 0xc0); + break; + case INTEL_440FX: + regs[0x51] = (val & 0xc3); + break; + case INTEL_440LX: + regs[0x51] = (regs[0x51] & 0x40) | (val & 0x87); + i4x0_mask_bar(regs, dev->agpgart); + break; + case INTEL_440EX: + regs[0x51] = (val & 0x86); + i4x0_mask_bar(regs, dev->agpgart); + break; + case INTEL_440BX: + case INTEL_440ZX: + regs[0x51] = (regs[0x51] & 0x70) | (val & 0x8f); + i4x0_mask_bar(regs, dev->agpgart); + break; + case INTEL_440GX: + regs[0x51] = (regs[0x51] & 0xb0) | (val & 0x4f); + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; + case 0x52: /* Cache Control Register */ + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430FX: + case INTEL_430VX: + case INTEL_430TX: + default: + regs[0x52] = (val & 0xfb); + break; + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + regs[0x52] = val; + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x52] = val & 0x07; + break; + } + break; + case 0x53: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + regs[0x53] = val & 0x0b; + break; + case INTEL_430NX: + regs[0x53] = val & 0x0a; + break; + case INTEL_430VX: + case INTEL_430TX: + regs[0x53] = val & 0x3f; + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x53] = val & 0x60; + break; + case INTEL_440BX: + case INTEL_440GX: + /* Not applicable to 440ZX as that does not support ECC. */ + regs[0x53] = val; + break; + } + break; + case 0x54: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[0x54] = val & 0x07; + break; + case INTEL_430VX: + regs[0x54] = val & 0xd8; + break; + case INTEL_430TX: + regs[0x54] = val & 0xfa; + break; + case INTEL_440FX: + regs[0x54] = val & 0x82; + break; + } + break; + case 0x55: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + /* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has + this register. The mask is unknown, so write all bits. */ + regs[0x55] = val; + break; + case INTEL_430VX: + case INTEL_430TX: + regs[0x55] = val & 0x01; + break; + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + regs[0x55] = val; + break; + } + break; + case 0x56: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + /* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has + this register. The mask is unknown, so write all bits. */ + regs[0x56] = val; + break; + case INTEL_430HX: + regs[0x56] = val & 0x1f; + break; + case INTEL_430VX: + regs[0x56] = val & 0x77; + break; + case INTEL_430TX: + regs[0x56] = val & 0x76; + break; + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + regs[0x56] = val; + break; + } + break; + case 0x57: + switch (dev->type) { + /* On the 420TX and 420ZX, this is the SMRAM space register. */ + case INTEL_420TX: + case INTEL_420ZX: + i4x0_smram_handler_phase0(dev); + if (dev->smram_locked) + regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20); + else { + regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78); + dev->smram_locked = (val & 0x10); + if (dev->smram_locked) + regs[0x57] &= 0xbf; + } + i4x0_smram_handler_phase1(dev); + break; + case INTEL_430LX: + default: + regs[0x57] = val & 0x3f; + break; + case INTEL_430NX: + regs[0x57] = val; + break; + case INTEL_430FX: + case INTEL_430HX: + case INTEL_430VX: + regs[0x57] = val & 0xcf; + break; + case INTEL_430TX: + regs[0x57] = val & 0xdf; + break; + case INTEL_440FX: + regs[0x57] = val & 0x77; + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x57] = val & 0x37; + break; + case INTEL_440BX: + case INTEL_440GX: + regs[0x57] = val & 0x3f; + break; + case INTEL_440ZX: + regs[0x57] = val & 0x2f; + break; + } + break; + case 0x58: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + default: + regs[0x58] = val & 0x01; + break; + case INTEL_430NX: + case INTEL_440BX: + case INTEL_440ZX: + regs[0x58] = val & 0x03; + break; + case INTEL_430FX: + case INTEL_440FX: + regs[0x58] = val & 0x7f; + break; + case INTEL_430HX: + case INTEL_430VX: + case INTEL_440LX: + case INTEL_440EX: + regs[0x58] = val; + break; + case INTEL_430TX: + regs[0x58] = val & 0x7b; + break; + } + break; + case 0x59: /* PAM0 */ + if (dev->type <= INTEL_430NX) { + if ((regs[0x59] ^ val) & 0x0f) + i4x0_map(dev, 0x80000, 0x20000, val & 0x0f); + } + if ((regs[0x59] ^ val) & 0xf0) { + i4x0_map(dev, 0xf0000, 0x10000, val >> 4); + shadowbios = (val & 0x10); + } + if (dev->type > INTEL_430NX) + regs[0x59] = val & 0x70; + else + regs[0x59] = val & 0x77; + break; + case 0x5a: /* PAM1 */ + if ((regs[0x5a] ^ val) & 0x0f) + i4x0_map(dev, 0xc0000, 0x04000, val & 0xf); + if ((regs[0x5a] ^ val) & 0xf0) + i4x0_map(dev, 0xc4000, 0x04000, val >> 4); + regs[0x5a] = val & 0x77; + break; + case 0x5b: /*PAM2 */ + if ((regs[0x5b] ^ val) & 0x0f) + i4x0_map(dev, 0xc8000, 0x04000, val & 0xf); + if ((regs[0x5b] ^ val) & 0xf0) + i4x0_map(dev, 0xcc000, 0x04000, val >> 4); + regs[0x5b] = val & 0x77; + break; + case 0x5c: /*PAM3 */ + if ((regs[0x5c] ^ val) & 0x0f) + i4x0_map(dev, 0xd0000, 0x04000, val & 0xf); + if ((regs[0x5c] ^ val) & 0xf0) + i4x0_map(dev, 0xd4000, 0x04000, val >> 4); + regs[0x5c] = val & 0x77; + break; + case 0x5d: /* PAM4 */ + if ((regs[0x5d] ^ val) & 0x0f) + i4x0_map(dev, 0xd8000, 0x04000, val & 0xf); + if ((regs[0x5d] ^ val) & 0xf0) + i4x0_map(dev, 0xdc000, 0x04000, val >> 4); + regs[0x5d] = val & 0x77; + break; + case 0x5e: /* PAM5 */ + if ((regs[0x5e] ^ val) & 0x0f) + i4x0_map(dev, 0xe0000, 0x04000, val & 0xf); + if ((regs[0x5e] ^ val) & 0xf0) + i4x0_map(dev, 0xe4000, 0x04000, val >> 4); + regs[0x5e] = val & 0x77; + break; + case 0x5f: /* PAM6 */ + if ((regs[0x5f] ^ val) & 0x0f) + i4x0_map(dev, 0xe8000, 0x04000, val & 0xf); + if ((regs[0x5f] ^ val) & 0xf0) + i4x0_map(dev, 0xec000, 0x04000, val >> 4); + regs[0x5f] = val & 0x77; + break; + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + if ((addr & 0x7) <= dev->max_drb) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + default: + regs[addr] = val; + break; + case INTEL_430FX: + case INTEL_430VX: + regs[addr] = val & 0x3f; + break; + case INTEL_430TX: + regs[addr] = val & 0x7f; + break; + } + break; + case 0x65: + if ((addr & 0x7) <= dev->max_drb) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440GX: + case INTEL_440BX: + case INTEL_440ZX: + regs[addr] = val; + break; + case INTEL_430VX: + regs[addr] = val & 0x3f; + break; + case INTEL_430TX: + regs[addr] = val & 0x7f; + break; + } + break; + case 0x66: + if ((addr & 0x7) <= dev->max_drb) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440GX: + case INTEL_440BX: + case INTEL_440ZX: + regs[addr] = val; + break; + } + break; + case 0x67: + if ((addr & 0x7) <= dev->max_drb) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_430NX: + case INTEL_430HX: + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440GX: + case INTEL_440ZX: + regs[addr] = val; + break; + case INTEL_430VX: + regs[addr] = val & 0x11; + break; + case INTEL_430TX: + regs[addr] = val & 0xb7; + break; + } + break; + case 0x68: + if (dev->type == INTEL_430NX) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_430HX: + case INTEL_430VX: + case INTEL_430TX: + regs[0x68] = val; + break; + case INTEL_430FX: + regs[0x68] = val & 0x1f; + break; + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440GX: + regs[0x68] = val & 0xc0; + break; + case INTEL_440BX: + regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7); + break; + case INTEL_440ZX: + regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0); + break; + } + break; + case 0x69: + if (dev->type == INTEL_430NX) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_440BX: + case INTEL_440GX: + regs[0x69] = val; + break; + case INTEL_430VX: + regs[0x69] = val & 0x07; + break; + case INTEL_440ZX: + regs[0x69] = val & 0x3f; + break; + } + break; + case 0x6a: + case 0x6b: + if (dev->type == INTEL_430NX) { + dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); + break; + } + switch (dev->type) { + case INTEL_440BX: + case INTEL_440GX: + regs[addr] = val; + break; + case INTEL_440LX: + case INTEL_440EX: + if (addr == 0x6a) + regs[addr] = val & 0xef; + break; + case INTEL_440ZX: + if (addr == 0x6a) + regs[addr] = val & 0xfc; + else + regs[addr] = val & 0x33; + break; + } + break; + case 0x6c: + case 0x6d: + case 0x6e: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440GX: + if (addr != 0x6e) + regs[addr] = val; + break; + case INTEL_440ZX: + if (addr == 0x6c) + regs[addr] = val & 0x03; + else if (addr == 0x6d) + regs[addr] = val & 0xcf; + break; + } + break; + case 0x6f: + switch (dev->type) { + case INTEL_440LX: + regs[addr] = val; + break; + case INTEL_440EX: + regs[addr] = val & 0xcf; + break; + } + break; + case 0x70: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + regs[addr] = val & 0xc7; + break; + case INTEL_430NX: + regs[addr] = val; + break; + case INTEL_430VX: + case INTEL_430TX: + regs[addr] = val & 0xfc; + break; + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440EX: + regs[addr] = val & 0xf8; + break; + } + break; + case 0x71: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + regs[addr] = val & 0x4d; + break; + case INTEL_430TX: + if (!dev->smram_locked) { + i4x0_smram_handler_phase0(dev); + regs[0x71] = (regs[0x71] & 0x20) | (val & 0xdf); + i4x0_smram_handler_phase1(dev); + } + break; + case INTEL_440EX: + regs[addr] = val; + break; + case INTEL_440FX: + case INTEL_440LX: + regs[addr] = val & 0x1f; + break; + } + break; + case 0x72: /* SMRAM */ + if (dev->type <= INTEL_420ZX) + break; - } - break; - case 0x51: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: - regs[0x51] = (val & 0xc0); - break; - case INTEL_440FX: - regs[0x51] = (val & 0xc3); - break; - case INTEL_440LX: - regs[0x51] = (regs[0x51] & 0x40) | (val & 0x87); - i4x0_mask_bar(regs, dev->agpgart); - break; - case INTEL_440EX: - regs[0x51] = (val & 0x86); - i4x0_mask_bar(regs, dev->agpgart); - break; - case INTEL_440BX: case INTEL_440ZX: - regs[0x51] = (regs[0x51] & 0x70) | (val & 0x8f); - i4x0_mask_bar(regs, dev->agpgart); - break; - case INTEL_440GX: - regs[0x51] = (regs[0x51] & 0xb0) | (val & 0x4f); - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; - case 0x52: /* Cache Control Register */ - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430FX: - case INTEL_430VX: case INTEL_430TX: - default: - regs[0x52] = (val & 0xfb); - break; - case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: - regs[0x52] = val; - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x52] = val & 0x07; - break; - } - break; - case 0x53: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: - regs[0x53] = val & 0x0b; - break; - case INTEL_430NX: - regs[0x53] = val & 0x0a; - break; - case INTEL_430VX: case INTEL_430TX: - regs[0x53] = val & 0x3f; - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x53] = val & 0x60; - break; - case INTEL_440BX: case INTEL_440GX: - /* Not applicable to 440ZX as that does not support ECC. */ - regs[0x53] = val; - break; - } - break; - case 0x54: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - regs[0x54] = val & 0x07; - break; - case INTEL_430VX: - regs[0x54] = val & 0xd8; - break; - case INTEL_430TX: - regs[0x54] = val & 0xfa; - break; - case INTEL_440FX: - regs[0x54] = val & 0x82; - break; - } - break; - case 0x55: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - /* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has - this register. The mask is unknown, so write all bits. */ - regs[0x55] = val; - break; - case INTEL_430VX: case INTEL_430TX: - regs[0x55] = val & 0x01; - break; - case INTEL_440FX: case INTEL_440LX: - case INTEL_440EX: - regs[0x55] = val; - break; - } - break; - case 0x56: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - /* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has - this register. The mask is unknown, so write all bits. */ - regs[0x56] = val; - break; - case INTEL_430HX: - regs[0x56] = val & 0x1f; - break; - case INTEL_430VX: - regs[0x56] = val & 0x77; - break; - case INTEL_430TX: - regs[0x56] = val & 0x76; - break; - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - regs[0x56] = val; - break; - } - break; - case 0x57: - switch (dev->type) { - /* On the 420TX and 420ZX, this is the SMRAM space register. */ - case INTEL_420TX: case INTEL_420ZX: - i4x0_smram_handler_phase0(dev); - if (dev->smram_locked) - regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20); - else { - regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78); - dev->smram_locked = (val & 0x10); - if (dev->smram_locked) - regs[0x57] &= 0xbf; - } - i4x0_smram_handler_phase1(dev); - break; - case INTEL_430LX: default: - regs[0x57] = val & 0x3f; - break; - case INTEL_430NX: - regs[0x57] = val; - break; - case INTEL_430FX: case INTEL_430HX: - case INTEL_430VX: - regs[0x57] = val & 0xcf; - break; - case INTEL_430TX: - regs[0x57] = val & 0xdf; - break; - case INTEL_440FX: - regs[0x57] = val & 0x77; - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x57] = val & 0x37; - break; - case INTEL_440BX: case INTEL_440GX: - regs[0x57] = val & 0x3f; - break; - case INTEL_440ZX: - regs[0x57] = val & 0x2f; - break; - } - break; - case 0x58: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: default: - regs[0x58] = val & 0x01; - break; - case INTEL_430NX: - case INTEL_440BX: case INTEL_440ZX: - regs[0x58] = val & 0x03; - break; - case INTEL_430FX: case INTEL_440FX: - regs[0x58] = val & 0x7f; - break; - case INTEL_430HX: case INTEL_430VX: - case INTEL_440LX: case INTEL_440EX: - regs[0x58] = val; - break; - case INTEL_430TX: - regs[0x58] = val & 0x7b; - break; - } - break; - case 0x59: /* PAM0 */ - if (dev->type <= INTEL_430NX) { - if ((regs[0x59] ^ val) & 0x0f) - i4x0_map(dev, 0x80000, 0x20000, val & 0x0f); - } - if ((regs[0x59] ^ val) & 0xf0) { - i4x0_map(dev, 0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - if (dev->type > INTEL_430NX) - regs[0x59] = val & 0x70; - else - regs[0x59] = val & 0x77; - break; - case 0x5a: /* PAM1 */ - if ((regs[0x5a] ^ val) & 0x0f) - i4x0_map(dev, 0xc0000, 0x04000, val & 0xf); - if ((regs[0x5a] ^ val) & 0xf0) - i4x0_map(dev, 0xc4000, 0x04000, val >> 4); - regs[0x5a] = val & 0x77; - break; - case 0x5b: /*PAM2 */ - if ((regs[0x5b] ^ val) & 0x0f) - i4x0_map(dev, 0xc8000, 0x04000, val & 0xf); - if ((regs[0x5b] ^ val) & 0xf0) - i4x0_map(dev, 0xcc000, 0x04000, val >> 4); - regs[0x5b] = val & 0x77; - break; - case 0x5c: /*PAM3 */ - if ((regs[0x5c] ^ val) & 0x0f) - i4x0_map(dev, 0xd0000, 0x04000, val & 0xf); - if ((regs[0x5c] ^ val) & 0xf0) - i4x0_map(dev, 0xd4000, 0x04000, val >> 4); - regs[0x5c] = val & 0x77; - break; - case 0x5d: /* PAM4 */ - if ((regs[0x5d] ^ val) & 0x0f) - i4x0_map(dev, 0xd8000, 0x04000, val & 0xf); - if ((regs[0x5d] ^ val) & 0xf0) - i4x0_map(dev, 0xdc000, 0x04000, val >> 4); - regs[0x5d] = val & 0x77; - break; - case 0x5e: /* PAM5 */ - if ((regs[0x5e] ^ val) & 0x0f) - i4x0_map(dev, 0xe0000, 0x04000, val & 0xf); - if ((regs[0x5e] ^ val) & 0xf0) - i4x0_map(dev, 0xe4000, 0x04000, val >> 4); - regs[0x5e] = val & 0x77; - break; - case 0x5f: /* PAM6 */ - if ((regs[0x5f] ^ val) & 0x0f) - i4x0_map(dev, 0xe8000, 0x04000, val & 0xf); - if ((regs[0x5f] ^ val) & 0xf0) - i4x0_map(dev, 0xec000, 0x04000, val >> 4); - regs[0x5f] = val & 0x77; - break; - case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: - if ((addr & 0x7) <= dev->max_drb) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - case INTEL_430HX: - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - default: - regs[addr] = val; - break; - case INTEL_430FX: case INTEL_430VX: - regs[addr] = val & 0x3f; - break; - case INTEL_430TX: - regs[addr] = val & 0x7f; - break; - } - break; - case 0x65: - if ((addr & 0x7) <= dev->max_drb) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - case INTEL_430HX: - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - case INTEL_440GX: - case INTEL_440BX: case INTEL_440ZX: - regs[addr] = val; - break; - case INTEL_430VX: - regs[addr] = val & 0x3f; - break; - case INTEL_430TX: - regs[addr] = val & 0x7f; - break; - } - break; - case 0x66: - if ((addr & 0x7) <= dev->max_drb) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: case INTEL_440LX: - case INTEL_440EX: case INTEL_440GX: - case INTEL_440BX: case INTEL_440ZX: - regs[addr] = val; - break; - } - break; - case 0x67: - if ((addr & 0x7) <= dev->max_drb) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_430NX: case INTEL_430HX: - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440GX: - case INTEL_440ZX: - regs[addr] = val; - break; - case INTEL_430VX: - regs[addr] = val & 0x11; - break; - case INTEL_430TX: - regs[addr] = val & 0xb7; - break; - } - break; - case 0x68: - if (dev->type == INTEL_430NX) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_430HX: - case INTEL_430VX: case INTEL_430TX: - regs[0x68] = val; - break; - case INTEL_430FX: - regs[0x68] = val & 0x1f; - break; - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - case INTEL_440GX: - regs[0x68] = val & 0xc0; - break; - case INTEL_440BX: - regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7); - break; - case INTEL_440ZX: - regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0); - break; - } - break; - case 0x69: - if (dev->type == INTEL_430NX) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_440BX: case INTEL_440GX: - regs[0x69] = val; - break; - case INTEL_430VX: - regs[0x69] = val & 0x07; - break; - case INTEL_440ZX: - regs[0x69] = val & 0x3f; - break; - } - break; - case 0x6a: case 0x6b: - if (dev->type == INTEL_430NX) { - dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit); - break; - } - switch (dev->type) { - case INTEL_440BX: case INTEL_440GX: - regs[addr] = val; - break; - case INTEL_440LX: case INTEL_440EX: - if (addr == 0x6a) - regs[addr] = val & 0xef; - break; - case INTEL_440ZX: - if (addr == 0x6a) - regs[addr] = val & 0xfc; - else - regs[addr] = val & 0x33; - break; - } - break; - case 0x6c: case 0x6d: case 0x6e: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440GX: - if (addr != 0x6e) - regs[addr] = val; - break; - case INTEL_440ZX: - if (addr == 0x6c) - regs[addr] = val & 0x03; - else if (addr == 0x6d) - regs[addr] = val & 0xcf; - break; - } - break; - case 0x6f: - switch (dev->type) { - case INTEL_440LX: - regs[addr] = val; - break; - case INTEL_440EX: - regs[addr] = val & 0xcf; - break; - } - break; - case 0x70: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: - regs[addr] = val & 0xc7; - break; - case INTEL_430NX: - regs[addr] = val; - break; - case INTEL_430VX: case INTEL_430TX: - regs[addr] = val & 0xfc; - break; - case INTEL_440FX: - case INTEL_440LX: case INTEL_440EX: - regs[addr] = val & 0xf8; - break; - } - break; - case 0x71: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: - regs[addr] = val & 0x4d; - break; - case INTEL_430TX: - if (!dev->smram_locked) { - i4x0_smram_handler_phase0(dev); - regs[0x71] = (regs[0x71] & 0x20) | (val & 0xdf); - i4x0_smram_handler_phase1(dev); - } - break; - case INTEL_440EX: - regs[addr] = val; - break; - case INTEL_440FX: case INTEL_440LX: - regs[addr] = val & 0x1f; - break; - } - break; - case 0x72: /* SMRAM */ - if (dev->type <= INTEL_420ZX) - break; + i4x0_smram_handler_phase0(dev); + if (dev->type >= INTEL_430FX) { + if (dev->smram_locked) + regs[0x72] = (regs[0x72] & 0xdf) | (val & 0x20); + else { + if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX) || (dev->type == INTEL_440GX)) + regs[0x72] = (val & 0x7f); + else + regs[0x72] = (regs[0x72] & 0x87) | (val & 0x78); + dev->smram_locked = (val & 0x10); + if (dev->smram_locked) + regs[0x72] &= 0xbf; + } + } else { + if (dev->smram_locked) + regs[0x72] = (regs[0x72] & 0xef) | (val & 0x10); + else { + regs[0x72] = (regs[0x72] & 0xc0) | (val & 0x3f); + dev->smram_locked = (val & 0x08); + if (dev->smram_locked) + regs[0x72] &= 0xdf; + } + } + i4x0_smram_handler_phase1(dev); + break; + case 0x73: + switch (dev->type) { + case INTEL_430VX: + regs[0x73] = val & 0x03; + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + if (!dev->smram_locked) { + i4x0_smram_handler_phase0(dev); + regs[0x73] = (regs[0x73] & 0x38) | (val & 0xc7); + i4x0_smram_handler_phase1(dev); + } + break; + } + break; + case 0x74: + switch (dev->type) { + case INTEL_430VX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x74] = val; + break; + } + break; + case 0x75: + case 0x76: + case 0x7b: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[addr] = val; + } + break; + case 0x77: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + regs[0x77] = val & 0x03; + } + break; + case 0x78: + switch (dev->type) { + case INTEL_430VX: + regs[0x78] = val & 0xcf; + break; + case INTEL_440BX: + case INTEL_440ZX: + regs[0x78] = val & 0x0f; + break; + case INTEL_440GX: + regs[0x78] = val & 0x1f; + break; + } + break; + case 0x79: + switch (dev->type) { + case INTEL_430TX: + regs[0x79] = val & 0x74; + io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); + if (val & 0x40) + io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x79] = val; + break; + } + break; + case 0x7a: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5); + io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); + if (val & 0x40) + io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); + break; + } + break; + case 0x7c: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[0x7c] = val & 0x8f; + break; + case INTEL_440BX: + case INTEL_440GX: + case INTEL_440ZX: + regs[0x7c] = val & 0x1f; + break; + } + break; + case 0x7d: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[0x7d] = val & 0x32; + break; + } + break; + case 0x7e: + case 0x7f: + switch (dev->type) { + case INTEL_420TX: + case INTEL_420ZX: + case INTEL_430LX: + case INTEL_430NX: + regs[addr] = val; + break; + } + break; + case 0x80: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x80] &= ~(val & 0x03); + break; + } + break; + case 0x90: + switch (dev->type) { + case INTEL_430HX: + regs[0x90] = val & 0x87; + break; + case INTEL_440FX: + regs[0x90] = val & 0x1b; + break; + case INTEL_440LX: + regs[0x90] = val & 0xfb; + break; + case INTEL_440EX: + regs[0x90] = val & 0xf8; + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x90] = val; + break; + } + break; + case 0x91: + switch (dev->type) { + case INTEL_430HX: + case INTEL_440BX: + case INTEL_440FX: + case INTEL_440LX: + case INTEL_440GX: + /* Not applicable on 82443EX and 82443ZX. */ + regs[0x91] &= ~(val & 0x11); + break; + } + break; + case 0x92: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + regs[0x92] &= ~(val & 0x07); + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0x92] &= ~(val & 0x1f); + break; + } + break; + case 0x93: + switch (dev->type) { + case INTEL_440FX: + regs[0x93] = (val & 0x0f); + trc_write(0x0093, val & 0x06, NULL); + break; + case INTEL_440LX: + case INTEL_440EX: + regs[0x93] = (val & 0x0e); + trc_write(0x0093, val & 0x06, NULL); + break; + } + break; + case 0xa7: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + regs[0xa7] = val & 0x1f; + break; + } + break; + case 0xa8: + case 0xa9: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[addr] = (val & 0x03); + break; + } + break; + case 0xb0: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xb0] = (val & 0x80); + break; + } + break; + case 0xb1: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + regs[0xb1] = (val & 0x22); + break; + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xb1] = (val & 0xa0); + break; + } + break; + case 0xb4: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xb4] = (val & 0x3f); + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; + case 0xb9: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xb9] = (val & 0xf0); + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; - i4x0_smram_handler_phase0(dev); - if (dev->type >= INTEL_430FX) { - if (dev->smram_locked) - regs[0x72] = (regs[0x72] & 0xdf) | (val & 0x20); - else { - if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX) || - (dev->type == INTEL_440GX)) - regs[0x72] = (val & 0x7f); - else - regs[0x72] = (regs[0x72] & 0x87) | (val & 0x78); - dev->smram_locked = (val & 0x10); - if (dev->smram_locked) - regs[0x72] &= 0xbf; - } - } else { - if (dev->smram_locked) - regs[0x72] = (regs[0x72] & 0xef) | (val & 0x10); - else { - regs[0x72] = (regs[0x72] & 0xc0) | (val & 0x3f); - dev->smram_locked = (val & 0x08); - if (dev->smram_locked) - regs[0x72] &= 0xdf; - } - } - i4x0_smram_handler_phase1(dev); - break; - case 0x73: - switch (dev->type) { - case INTEL_430VX: - regs[0x73] = val & 0x03; - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - if (!dev->smram_locked) { - i4x0_smram_handler_phase0(dev); - regs[0x73] = (regs[0x73] & 0x38) | (val & 0xc7); - i4x0_smram_handler_phase1(dev); - } - break; - } - break; - case 0x74: - switch (dev->type) { - case INTEL_430VX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x74] = val; - break; - } - break; - case 0x75: case 0x76: - case 0x7b: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[addr] = val; - } - break; - case 0x77: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - regs[0x77] = val & 0x03; - } - break; - case 0x78: - switch (dev->type) { - case INTEL_430VX: - regs[0x78] = val & 0xcf; - break; - case INTEL_440BX: case INTEL_440ZX: - regs[0x78] = val & 0x0f; - break; - case INTEL_440GX: - regs[0x78] = val & 0x1f; - break; - } - break; - case 0x79: - switch (dev->type) { - case INTEL_430TX: - regs[0x79] = val & 0x74; - io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - if (val & 0x40) - io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x79] = val; - break; - } - break; - case 0x7a: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5); - io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - if (val & 0x40) - io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - break; - } - break; - case 0x7c: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - regs[0x7c] = val & 0x8f; - break; - case INTEL_440BX: case INTEL_440GX: - case INTEL_440ZX: - regs[0x7c] = val & 0x1f; - break; - } - break; - case 0x7d: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - regs[0x7d] = val & 0x32; - break; - } - break; - case 0x7e: case 0x7f: - switch (dev->type) { - case INTEL_420TX: case INTEL_420ZX: - case INTEL_430LX: case INTEL_430NX: - regs[addr] = val; - break; - } - break; - case 0x80: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x80] &= ~(val & 0x03); - break; - } - break; - case 0x90: - switch (dev->type) { - case INTEL_430HX: - regs[0x90] = val & 0x87; - break; - case INTEL_440FX: - regs[0x90] = val & 0x1b; - break; - case INTEL_440LX: - regs[0x90] = val & 0xfb; - break; - case INTEL_440EX: - regs[0x90] = val & 0xf8; - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x90] = val; - break; - } - break; - case 0x91: - switch (dev->type) { - case INTEL_430HX: case INTEL_440BX: - case INTEL_440FX: case INTEL_440LX: - case INTEL_440GX: - /* Not applicable on 82443EX and 82443ZX. */ - regs[0x91] &= ~(val & 0x11); - break; - } - break; - case 0x92: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - regs[0x92] &= ~(val & 0x07); - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0x92] &= ~(val & 0x1f); - break; - } - break; - case 0x93: - switch (dev->type) { - case INTEL_440FX: - regs[0x93] = (val & 0x0f); - trc_write(0x0093, val & 0x06, NULL); - break; - case INTEL_440LX: case INTEL_440EX: - regs[0x93] = (val & 0x0e); - trc_write(0x0093, val & 0x06, NULL); - break; - } - break; - case 0xa7: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - regs[0xa7] = val & 0x1f; - break; - } - break; - case 0xa8: case 0xa9: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[addr] = (val & 0x03); - break; - } - break; - case 0xb0: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xb0] = (val & 0x80); - break; - } - break; - case 0xb1: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - regs[0xb1] = (val & 0x22); - break; - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xb1] = (val & 0xa0); - break; - } - break; - case 0xb4: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xb4] = (val & 0x3f); - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; - case 0xb9: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xb9] = (val & 0xf0); - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; + case 0xba: + case 0xbb: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[addr] = val; + i4x0_mask_bar(regs, dev->agpgart); + break; + } + break; - case 0xba: case 0xbb: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[addr] = val; - i4x0_mask_bar(regs, dev->agpgart); - break; - } - break; + case 0xbc: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + regs[addr] = (val & 0xf8); + break; + } + break; - case 0xbc: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - regs[addr] = (val & 0xf8); - break; - } - break; + case 0xbd: + switch (dev->type) { + case INTEL_440LX: + case INTEL_440EX: + regs[addr] = (val & 0xf8); + break; + } + break; - case 0xbd: - switch (dev->type) { - case INTEL_440LX: case INTEL_440EX: - regs[addr] = (val & 0xf8); - break; - } - break; - - case 0xd0: case 0xd1: case 0xd2: case 0xd3: - case 0xd4: case 0xd5: case 0xd6: case 0xd7: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[addr] = val; - break; - } - break; - case 0xca: - switch (dev->type) { - case INTEL_440BX: case INTEL_440GX: - regs[addr] = val; - break; - case INTEL_440ZX: - regs[addr] = val & 0xe7; - break; - } - break; - case 0xcb: - switch (dev->type) { - case INTEL_440BX: case INTEL_440GX: - regs[addr] = val; - break; - case INTEL_440ZX: - regs[addr] = val & 0xa7; - break; - } - break; - case 0xcc: - switch (dev->type) { - case INTEL_440BX: case INTEL_440GX: - regs[0xcc] = (val & 0x7f); - break; - case INTEL_440ZX: - regs[0xcc] = (val & 0x58); - break; - } - break; - case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: - case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - if (!regs_l[addr]) - regs[addr] = val; - break; - } - break; - case 0xe5: case 0xed: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - if (!regs_l[addr]) - regs[addr] = (val & 0x3f); - break; - } - break; - case 0xe7: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xe7] = 0x80; - for (i = 0; i < 16; i++) - regs_l[0xe0 + i] = !!(val & 0x80); - if (!regs_l[0xe7]) { - regs[0xe7] |= (val & 0x7f); - } - break; - } - break; - case 0xf0: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xf0] = (val & 0xc0); - break; - } - break; - case 0xf1: - switch (dev->type) { - case INTEL_440BX: case INTEL_440ZX: - case INTEL_440GX: - regs[0xf1] = (val & 0x03); - break; - } - break; - } + case 0xd0: + case 0xd1: + case 0xd2: + case 0xd3: + case 0xd4: + case 0xd5: + case 0xd6: + case 0xd7: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[addr] = val; + break; + } + break; + case 0xca: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440GX: + regs[addr] = val; + break; + case INTEL_440ZX: + regs[addr] = val & 0xe7; + break; + } + break; + case 0xcb: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440GX: + regs[addr] = val; + break; + case INTEL_440ZX: + regs[addr] = val & 0xa7; + break; + } + break; + case 0xcc: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440GX: + regs[0xcc] = (val & 0x7f); + break; + case INTEL_440ZX: + regs[0xcc] = (val & 0x58); + break; + } + break; + case 0xe0: + case 0xe1: + case 0xe2: + case 0xe3: + case 0xe4: + case 0xe8: + case 0xe9: + case 0xea: + case 0xeb: + case 0xec: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + if (!regs_l[addr]) + regs[addr] = val; + break; + } + break; + case 0xe5: + case 0xed: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + if (!regs_l[addr]) + regs[addr] = (val & 0x3f); + break; + } + break; + case 0xe7: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xe7] = 0x80; + for (i = 0; i < 16; i++) + regs_l[0xe0 + i] = !!(val & 0x80); + if (!regs_l[0xe7]) { + regs[0xe7] |= (val & 0x7f); + } + break; + } + break; + case 0xf0: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xf0] = (val & 0xc0); + break; + } + break; + case 0xf1: + switch (dev->type) { + case INTEL_440BX: + case INTEL_440ZX: + case INTEL_440GX: + regs[0xf1] = (val & 0x03); + break; + } + break; + } } - static uint8_t i4x0_read(int func, int addr, void *priv) { - i4x0_t *dev = (i4x0_t *) priv; - uint8_t ret = 0xff; + i4x0_t *dev = (i4x0_t *) priv; + uint8_t ret = 0xff; uint8_t *regs = (uint8_t *) dev->regs; if (func == 0) { - ret = regs[addr]; - /* Special behavior for 440FX register 0x93 which is basically TRC in PCI space - with the addition of bits 3 and 0. */ - if ((func == 0) && (addr == 0x93) && - ((dev->type == INTEL_440FX) || (dev->type == INTEL_440LX) || - (dev->type == INTEL_440EX))) - ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06); + ret = regs[addr]; + /* Special behavior for 440FX register 0x93 which is basically TRC in PCI space + with the addition of bits 3 and 0. */ + if ((func == 0) && (addr == 0x93) && ((dev->type == INTEL_440FX) || (dev->type == INTEL_440LX) || (dev->type == INTEL_440EX))) + ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06); } return ret; } - static void i4x0_reset(void *priv) { - i4x0_t *dev = (i4x0_t *)priv; - int i; + i4x0_t *dev = (i4x0_t *) priv; + int i; - if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || - (dev->type == INTEL_440ZX)) - memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t)); + if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) + memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t)); if (dev->type >= INTEL_430FX) - i4x0_write(0, 0x59, 0x00, priv); + i4x0_write(0, 0x59, 0x00, priv); else - i4x0_write(0, 0x59, 0x0f, priv); + i4x0_write(0, 0x59, 0x0f, priv); for (i = 0; i < 6; i++) - i4x0_write(0, 0x5a + i, 0x00, priv); + i4x0_write(0, 0x5a + i, 0x00, priv); for (i = 0; i <= dev->max_drb; i++) - i4x0_write(0, 0x60 + i, dev->drb_default, priv); + i4x0_write(0, 0x60 + i, dev->drb_default, priv); if (dev->type >= INTEL_430FX) { - dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x72, 0x02, priv); + dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */ + i4x0_write(0, 0x72, 0x02, priv); } else if (dev->type >= INTEL_430LX) { - dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x72, 0x00, priv); + dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */ + i4x0_write(0, 0x72, 0x00, priv); } else { - dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */ - i4x0_write(0, 0x57, 0x02, priv); + dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */ + i4x0_write(0, 0x57, 0x02, priv); } if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { - i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, - (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv); + i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, + (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv); } } - static void i4x0_close(void *p) { - i4x0_t *dev = (i4x0_t *)p; + i4x0_t *dev = (i4x0_t *) p; smram_del(dev->smram_high); smram_del(dev->smram_low); @@ -1302,303 +1451,318 @@ i4x0_close(void *p) free(dev); } - static void -*i4x0_init(const device_t *info) + * + i4x0_init(const device_t *info) { - i4x0_t *dev = (i4x0_t *) malloc(sizeof(i4x0_t)); + i4x0_t *dev = (i4x0_t *) malloc(sizeof(i4x0_t)); uint8_t *regs; memset(dev, 0, sizeof(i4x0_t)); - dev->smram_low = smram_add(); + dev->smram_low = smram_add(); dev->smram_high = smram_add(); dev->type = info->local & 0xff; regs = (uint8_t *) dev->regs; - regs[0x00] = 0x86; regs[0x01] = 0x80; /*Intel*/ + regs[0x00] = 0x86; + regs[0x01] = 0x80; /*Intel*/ dev->write_drbs = spd_write_drbs; switch (dev->type) { - case INTEL_420TX: - case INTEL_420ZX: - regs[0x02] = 0x83; regs[0x03] = 0x04; /* 82424TX/ZX */ - regs[0x06] = 0x40; - regs[0x08] = (dev->type == INTEL_420ZX) ? 0x01 : 0x00; - regs[0x0d] = 0x20; - /* According to information from FreeBSD 3.x source code: - 0x00 = 486DX, 0x20 = 486SX, 0x40 = 486DX2 or 486DX4, 0x80 = Pentium OverDrive. */ - if (!(hasfpu) && (cpu_multi == 1)) - regs[0x50] = 0x20; - else if (!(hasfpu) && (cpu_multi == 2)) - regs[0x50] = 0x60; /* Guess based on the SX, DX, and DX2 values. */ - else if (hasfpu && (cpu_multi == 1)) - regs[0x50] = 0x00; - else if (hasfpu && (cpu_multi >= 2) && !(cpu_s->cpu_type == CPU_P24T)) - regs[0x50] = 0x40; - else - regs[0x50] = 0x80; /* Pentium OverDrive. */ - /* According to information from FreeBSD 3.x source code: - 00 = 25 MHz, 01 = 33 MHz. */ - if (cpu_busspeed > 25000000) - regs[0x50] |= 0x01; - regs[0x51] = 0x80; - /* According to information from FreeBSD 3.x source code: - 0x00 = None, 0x01 = 64 kB, 0x41 = 128 kB, 0x81 = 256 kB, 0xc1 = 512 kB, - If bit 0 is set, then if bit 2 is also set, the cache is write back, - otherwise it's write through. */ - regs[0x52] = 0xc3; /* 512 kB writeback cache */ - regs[0x57] = 0x31; - regs[0x59] = 0x0f; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02; - dev->max_drb = 3; - dev->drb_unit = 4; - dev->drb_default = 0x02; - break; - case INTEL_430LX: - regs[0x02] = 0xa3; regs[0x03] = 0x04; /* 82434LX/NX */ - regs[0x06] = 0x40; - regs[0x08] = 0x03; - regs[0x0d] = 0x20; - regs[0x50] = 0x82; - if (cpu_busspeed <= 60000000) - regs[0x50] |= 0x00; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x50] |= 0x01; - regs[0x51] = 0x80; - regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */ - regs[0x59] = 0x0f; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02; - dev->max_drb = 5; - dev->drb_unit = 1; - dev->drb_default = 0x02; - break; - case INTEL_430NX: - regs[0x02] = 0xa3; regs[0x03] = 0x04; /* 82434LX/NX */ - regs[0x06] = 0x40; - regs[0x08] = 0x11; - regs[0x0d] = 0x20; - regs[0x50] = 0x80; - if (cpu_busspeed <= 50000000) - regs[0x50] |= 0x01; - else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - regs[0x50] |= 0x02; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x50] |= 0x03; - regs[0x51] = 0x80; - regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */ - regs[0x57] = 0x31; - regs[0x59] = 0x0f; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; - dev->max_drb = 7; - dev->drb_unit = 1; - dev->drb_default = 0x02; - dev->write_drbs = spd_write_drbs_with_ext; - break; - case INTEL_430FX: - regs[0x02] = 0x2d; regs[0x03] = 0x12; /* SB82437FX-66 */ - regs[0x08] = (info->local >> 8) & 0xff; - regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ - if (cpu_busspeed <= 50000000) - regs[0x57] |= 0x01; - else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - regs[0x57] |= 0x02; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x57] |= 0x03; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02; - regs[0x72] = 0x02; - dev->max_drb = 4; - dev->drb_unit = 4; - dev->drb_default = 0x02; - break; - case INTEL_430HX: - regs[0x02] = 0x50; regs[0x03] = 0x12; /* 82439HX */ - regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ - if (cpu_busspeed <= 50000000) - regs[0x57] |= 0x01; - else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - regs[0x57] |= 0x02; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x57] |= 0x03; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; - regs[0x72] = 0x02; - dev->max_drb = 7; - dev->drb_unit = 4; - dev->drb_default = 0x02; - break; - case INTEL_430VX: - regs[0x02] = 0x30; regs[0x03] = 0x70; /* 82437VX */ - regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ - regs[0x53] = 0x14; - regs[0x56] = 0x52; - if (cpu_busspeed <= 50000000) - regs[0x57] |= 0x01; - else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - regs[0x57] |= 0x02; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x57] |= 0x03; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02; - regs[0x67] = 0x11; - regs[0x69] = 0x03; - regs[0x70] = 0x20; - regs[0x72] = 0x02; - regs[0x74] = 0x0e; - regs[0x78] = 0x23; - dev->max_drb = 4; - dev->drb_unit = 4; - dev->drb_default = 0x02; - break; - case INTEL_430TX: - regs[0x02] = 0x00; regs[0x03] = 0x71; /* 82439TX */ - regs[0x08] = 0x01; - regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ - regs[0x53] = 0x14; - regs[0x56] = 0x52; - regs[0x57] = 0x01; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = 0x02; - if (cpu_busspeed <= 60000000) - regs[0x67] |= 0x00; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x67] |= 0x80; - regs[0x70] = 0x20; - regs[0x72] = 0x02; - dev->max_drb = 5; - dev->drb_unit = 4; - dev->drb_default = 0x02; - break; - case INTEL_440FX: - regs[0x02] = 0x37; regs[0x03] = 0x12; /* 82441FX */ - regs[0x08] = 0x02; - if (cpu_busspeed <= 60000000) - regs[0x51] |= 0x01; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x51] |= 0x02; - regs[0x53] = 0x80; - regs[0x57] = 0x01; - regs[0x58] = 0x10; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; - regs[0x71] = 0x10; - regs[0x72] = 0x02; - dev->max_drb = 7; - dev->drb_unit = 8; - dev->drb_default = 0x02; - break; - case INTEL_440LX: - regs[0x02] = 0x80; regs[0x03] = 0x71; /* 82443LX */ - regs[0x08] = 0x03; - regs[0x06] = 0x90; - regs[0x10] = 0x08; - regs[0x34] = 0xa0; - if (cpu_busspeed <= 60000000) - regs[0x51] |= 0x40; - else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) - regs[0x51] |= 0x00; - regs[0x53] = 0x83; - regs[0x57] = 0x01; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; - regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55; - regs[0x72] = 0x02; - regs[0xa0] = 0x02; - regs[0xa2] = 0x10; - regs[0xa4] = 0x03; - regs[0xa5] = 0x02; - regs[0xa7] = 0x1f; - dev->max_drb = 7; - dev->drb_unit = 8; - dev->drb_default = 0x01; - break; - case INTEL_440EX: - regs[0x02] = 0x80; regs[0x03] = 0x71; /* 82443EX. Same Vendor ID as 440LX */ - regs[0x08] = 0x03; - regs[0x06] = 0x90; - regs[0x10] = 0x08; - regs[0x34] = 0xa0; - regs[0x51] = 0x80; - regs[0x53] = 0x83; - regs[0x57] = 0x01; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; - regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55; - regs[0x72] = 0x02; - regs[0xa0] = 0x02; - regs[0xa2] = 0x10; - regs[0xa4] = 0x03; - regs[0xa5] = 0x02; - regs[0xa7] = 0x1f; - dev->max_drb = 7; - dev->drb_unit = 8; - dev->drb_default = 0x01; - break; - case INTEL_440BX: case INTEL_440ZX: - regs[0x7a] = (info->local >> 8) & 0xff; + case INTEL_420TX: + case INTEL_420ZX: + regs[0x02] = 0x83; + regs[0x03] = 0x04; /* 82424TX/ZX */ + regs[0x06] = 0x40; + regs[0x08] = (dev->type == INTEL_420ZX) ? 0x01 : 0x00; + regs[0x0d] = 0x20; + /* According to information from FreeBSD 3.x source code: + 0x00 = 486DX, 0x20 = 486SX, 0x40 = 486DX2 or 486DX4, 0x80 = Pentium OverDrive. */ + if (!(hasfpu) && (cpu_multi == 1)) + regs[0x50] = 0x20; + else if (!(hasfpu) && (cpu_multi == 2)) + regs[0x50] = 0x60; /* Guess based on the SX, DX, and DX2 values. */ + else if (hasfpu && (cpu_multi == 1)) + regs[0x50] = 0x00; + else if (hasfpu && (cpu_multi >= 2) && !(cpu_s->cpu_type == CPU_P24T)) + regs[0x50] = 0x40; + else + regs[0x50] = 0x80; /* Pentium OverDrive. */ + /* According to information from FreeBSD 3.x source code: + 00 = 25 MHz, 01 = 33 MHz. */ + if (cpu_busspeed > 25000000) + regs[0x50] |= 0x01; + regs[0x51] = 0x80; + /* According to information from FreeBSD 3.x source code: + 0x00 = None, 0x01 = 64 kB, 0x41 = 128 kB, 0x81 = 256 kB, 0xc1 = 512 kB, + If bit 0 is set, then if bit 2 is also set, the cache is write back, + otherwise it's write through. */ + regs[0x52] = 0xc3; /* 512 kB writeback cache */ + regs[0x57] = 0x31; + regs[0x59] = 0x0f; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02; + dev->max_drb = 3; + dev->drb_unit = 4; + dev->drb_default = 0x02; + break; + case INTEL_430LX: + regs[0x02] = 0xa3; + regs[0x03] = 0x04; /* 82434LX/NX */ + regs[0x06] = 0x40; + regs[0x08] = 0x03; + regs[0x0d] = 0x20; + regs[0x50] = 0x82; + if (cpu_busspeed <= 60000000) + regs[0x50] |= 0x00; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x50] |= 0x01; + regs[0x51] = 0x80; + regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */ + regs[0x59] = 0x0f; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02; + dev->max_drb = 5; + dev->drb_unit = 1; + dev->drb_default = 0x02; + break; + case INTEL_430NX: + regs[0x02] = 0xa3; + regs[0x03] = 0x04; /* 82434LX/NX */ + regs[0x06] = 0x40; + regs[0x08] = 0x11; + regs[0x0d] = 0x20; + regs[0x50] = 0x80; + if (cpu_busspeed <= 50000000) + regs[0x50] |= 0x01; + else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) + regs[0x50] |= 0x02; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x50] |= 0x03; + regs[0x51] = 0x80; + regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */ + regs[0x57] = 0x31; + regs[0x59] = 0x0f; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; + dev->max_drb = 7; + dev->drb_unit = 1; + dev->drb_default = 0x02; + dev->write_drbs = spd_write_drbs_with_ext; + break; + case INTEL_430FX: + regs[0x02] = 0x2d; + regs[0x03] = 0x12; /* SB82437FX-66 */ + regs[0x08] = (info->local >> 8) & 0xff; + regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ + if (cpu_busspeed <= 50000000) + regs[0x57] |= 0x01; + else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) + regs[0x57] |= 0x02; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x57] |= 0x03; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02; + regs[0x72] = 0x02; + dev->max_drb = 4; + dev->drb_unit = 4; + dev->drb_default = 0x02; + break; + case INTEL_430HX: + regs[0x02] = 0x50; + regs[0x03] = 0x12; /* 82439HX */ + regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ + if (cpu_busspeed <= 50000000) + regs[0x57] |= 0x01; + else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) + regs[0x57] |= 0x02; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x57] |= 0x03; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; + regs[0x72] = 0x02; + dev->max_drb = 7; + dev->drb_unit = 4; + dev->drb_default = 0x02; + break; + case INTEL_430VX: + regs[0x02] = 0x30; + regs[0x03] = 0x70; /* 82437VX */ + regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ + regs[0x53] = 0x14; + regs[0x56] = 0x52; + if (cpu_busspeed <= 50000000) + regs[0x57] |= 0x01; + else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) + regs[0x57] |= 0x02; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x57] |= 0x03; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02; + regs[0x67] = 0x11; + regs[0x69] = 0x03; + regs[0x70] = 0x20; + regs[0x72] = 0x02; + regs[0x74] = 0x0e; + regs[0x78] = 0x23; + dev->max_drb = 4; + dev->drb_unit = 4; + dev->drb_default = 0x02; + break; + case INTEL_430TX: + regs[0x02] = 0x00; + regs[0x03] = 0x71; /* 82439TX */ + regs[0x08] = 0x01; + regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */ + regs[0x53] = 0x14; + regs[0x56] = 0x52; + regs[0x57] = 0x01; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = 0x02; + if (cpu_busspeed <= 60000000) + regs[0x67] |= 0x00; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x67] |= 0x80; + regs[0x70] = 0x20; + regs[0x72] = 0x02; + dev->max_drb = 5; + dev->drb_unit = 4; + dev->drb_default = 0x02; + break; + case INTEL_440FX: + regs[0x02] = 0x37; + regs[0x03] = 0x12; /* 82441FX */ + regs[0x08] = 0x02; + if (cpu_busspeed <= 60000000) + regs[0x51] |= 0x01; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x51] |= 0x02; + regs[0x53] = 0x80; + regs[0x57] = 0x01; + regs[0x58] = 0x10; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02; + regs[0x71] = 0x10; + regs[0x72] = 0x02; + dev->max_drb = 7; + dev->drb_unit = 8; + dev->drb_default = 0x02; + break; + case INTEL_440LX: + regs[0x02] = 0x80; + regs[0x03] = 0x71; /* 82443LX */ + regs[0x08] = 0x03; + regs[0x06] = 0x90; + regs[0x10] = 0x08; + regs[0x34] = 0xa0; + if (cpu_busspeed <= 60000000) + regs[0x51] |= 0x40; + else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667)) + regs[0x51] |= 0x00; + regs[0x53] = 0x83; + regs[0x57] = 0x01; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; + regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55; + regs[0x72] = 0x02; + regs[0xa0] = 0x02; + regs[0xa2] = 0x10; + regs[0xa4] = 0x03; + regs[0xa5] = 0x02; + regs[0xa7] = 0x1f; + dev->max_drb = 7; + dev->drb_unit = 8; + dev->drb_default = 0x01; + break; + case INTEL_440EX: + regs[0x02] = 0x80; + regs[0x03] = 0x71; /* 82443EX. Same Vendor ID as 440LX */ + regs[0x08] = 0x03; + regs[0x06] = 0x90; + regs[0x10] = 0x08; + regs[0x34] = 0xa0; + regs[0x51] = 0x80; + regs[0x53] = 0x83; + regs[0x57] = 0x01; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; + regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55; + regs[0x72] = 0x02; + regs[0xa0] = 0x02; + regs[0xa2] = 0x10; + regs[0xa4] = 0x03; + regs[0xa5] = 0x02; + regs[0xa7] = 0x1f; + dev->max_drb = 7; + dev->drb_unit = 8; + dev->drb_default = 0x01; + break; + case INTEL_440BX: + case INTEL_440ZX: + regs[0x7a] = (info->local >> 8) & 0xff; - regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */ - regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; - regs[0x08] = (regs[0x7a] & 0x02) ? 0x03 : 0x02; - regs[0x10] = 0x08; - regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0; - if (cpu_busspeed <= 66666667) - regs[0x51] |= 0x20; - else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000)) - regs[0x51] |= 0x00; - regs[0x57] = 0x28; /* 4 DIMMs, SDRAM */ - regs[0x58] = 0x03; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; - regs[0x72] = 0x02; - regs[0x73] = 0x38; - regs[0x7b] = 0x38; - regs[0x90] = 0x80; - regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02; - regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; - regs[0xa4] = 0x03; - regs[0xa5] = 0x02; - regs[0xa7] = 0x1f; - dev->max_drb = 7; - dev->drb_unit = 8; - dev->drb_default = 0x01; - break; - case INTEL_440GX: - regs[0x7a] = (info->local >> 8) & 0xff; + regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; + regs[0x03] = 0x71; /* 82443BX */ + regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; + regs[0x08] = (regs[0x7a] & 0x02) ? 0x03 : 0x02; + regs[0x10] = 0x08; + regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0; + if (cpu_busspeed <= 66666667) + regs[0x51] |= 0x20; + else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000)) + regs[0x51] |= 0x00; + regs[0x57] = 0x28; /* 4 DIMMs, SDRAM */ + regs[0x58] = 0x03; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; + regs[0x72] = 0x02; + regs[0x73] = 0x38; + regs[0x7b] = 0x38; + regs[0x90] = 0x80; + regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02; + regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; + regs[0xa4] = 0x03; + regs[0xa5] = 0x02; + regs[0xa7] = 0x1f; + dev->max_drb = 7; + dev->drb_unit = 8; + dev->drb_default = 0x01; + break; + case INTEL_440GX: + regs[0x7a] = (info->local >> 8) & 0xff; - regs[0x02] = (regs[0x7a] & 0x02) ? 0xa2 : 0xa0; regs[0x03] = 0x71; /* 82443GX */ - regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; - regs[0x10] = 0x08; - regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0; - regs[0x57] = 0x28; - regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; - regs[0x72] = 0x02; - regs[0x73] = 0x38; - regs[0x7b] = 0x38; - regs[0x90] = 0x80; - regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02; - regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; - regs[0xa4] = 0x03; - regs[0xa5] = 0x02; - regs[0xa7] = 0x1f; - dev->max_drb = 7; - dev->drb_unit = 8; - dev->drb_default = 0x01; - break; + regs[0x02] = (regs[0x7a] & 0x02) ? 0xa2 : 0xa0; + regs[0x03] = 0x71; /* 82443GX */ + regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; + regs[0x10] = 0x08; + regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0; + regs[0x57] = 0x28; + regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01; + regs[0x72] = 0x02; + regs[0x73] = 0x38; + regs[0x7b] = 0x38; + regs[0x90] = 0x80; + regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02; + regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; + regs[0xa4] = 0x03; + regs[0xa5] = 0x02; + regs[0xa7] = 0x1f; + dev->max_drb = 7; + dev->drb_unit = 8; + dev->drb_default = 0x01; + break; } - regs[0x04] = 0x06; regs[0x07] = 0x02; + regs[0x04] = 0x06; + regs[0x07] = 0x02; regs[0x0b] = 0x06; if (dev->type >= INTEL_440FX) { - cpu_cache_ext_enabled = 1; - cpu_update_waitstates(); + cpu_cache_ext_enabled = 1; + cpu_update_waitstates(); } /* Out-of-spec PCI and AGP clocks with overclocked bus. */ if ((dev->type <= INTEL_440FX) && (cpu_busspeed >= 66666666)) - cpu_set_pci_speed(cpu_busspeed / 2); + cpu_set_pci_speed(cpu_busspeed / 2); if ((dev->type >= INTEL_440BX) && (cpu_busspeed >= 100000000)) - cpu_set_agp_speed(cpu_busspeed / 1.5); + cpu_set_agp_speed(cpu_busspeed / 1.5); else if (dev->type >= INTEL_440LX) - cpu_set_agp_speed(cpu_busspeed); + cpu_set_agp_speed(cpu_busspeed); i4x0_write(regs[0x59], 0x59, 0x00, dev); i4x0_write(regs[0x5a], 0x5a, 0x00, dev); @@ -1609,250 +1773,250 @@ static void i4x0_write(regs[0x5f], 0x5f, 0x00, dev); if (dev->type >= INTEL_430FX) - i4x0_write(0, 0x72, 0x02, dev); + i4x0_write(0, 0x72, 0x02, dev); else if (dev->type >= INTEL_430LX) - i4x0_write(0, 0x72, 0x00, dev); + i4x0_write(0, 0x72, 0x00, dev); else - i4x0_write(0, 0x57, 0x02, dev); + i4x0_write(0, 0x57, 0x02, dev); if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { - i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, - (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev); + i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, + (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev); } pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev); if ((dev->type >= INTEL_440BX) && !(regs[0x7a] & 0x02)) { - device_add((dev->type == INTEL_440GX) ? &i440gx_agp_device : &i440bx_agp_device); - dev->agpgart = device_add(&agpgart_device); + device_add((dev->type == INTEL_440GX) ? &i440gx_agp_device : &i440bx_agp_device); + dev->agpgart = device_add(&agpgart_device); } else if (dev->type >= INTEL_440LX) { - device_add(&i440lx_agp_device); - dev->agpgart = device_add(&agpgart_device); + device_add(&i440lx_agp_device); + dev->agpgart = device_add(&agpgart_device); } return dev; } const device_t i420tx_device = { - .name = "Intel 82424TX", + .name = "Intel 82424TX", .internal_name = "i420tx", - .flags = DEVICE_PCI, - .local = INTEL_420TX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_420TX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i420zx_device = { - .name = "Intel 82424ZX", + .name = "Intel 82424ZX", .internal_name = "i420zx", - .flags = DEVICE_PCI, - .local = INTEL_420ZX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_420ZX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430lx_device = { - .name = "Intel 82434LX", + .name = "Intel 82434LX", .internal_name = "i430lx", - .flags = DEVICE_PCI, - .local = INTEL_430LX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430LX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430nx_device = { - .name = "Intel 82434NX", + .name = "Intel 82434NX", .internal_name = "i430nx", - .flags = DEVICE_PCI, - .local = INTEL_430NX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430NX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430fx_device = { - .name = "Intel SB82437FX-66", + .name = "Intel SB82437FX-66", .internal_name = "i430fx", - .flags = DEVICE_PCI, - .local = INTEL_430FX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430FX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430fx_rev02_device = { - .name = "Intel SB82437FX-66 (Rev. 02)", + .name = "Intel SB82437FX-66 (Rev. 02)", .internal_name = "i430fx_rev02", - .flags = DEVICE_PCI, - .local = 0x0200 | INTEL_430FX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = 0x0200 | INTEL_430FX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430hx_device = { - .name = "Intel 82439HX", + .name = "Intel 82439HX", .internal_name = "i430hx", - .flags = DEVICE_PCI, - .local = INTEL_430HX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430HX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430vx_device = { - .name = "Intel 82437VX", + .name = "Intel 82437VX", .internal_name = "i430vx", - .flags = DEVICE_PCI, - .local = INTEL_430VX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430VX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i430tx_device = { - .name = "Intel 82439TX", + .name = "Intel 82439TX", .internal_name = "i430tx", - .flags = DEVICE_PCI, - .local = INTEL_430TX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_430TX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440fx_device = { - .name = "Intel 82441FX", + .name = "Intel 82441FX", .internal_name = "i440fx", - .flags = DEVICE_PCI, - .local = INTEL_440FX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_440FX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440lx_device = { - .name = "Intel 82443LX", + .name = "Intel 82443LX", .internal_name = "i440lx", - .flags = DEVICE_PCI, - .local = INTEL_440LX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_440LX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440ex_device = { - .name = "Intel 82443EX", + .name = "Intel 82443EX", .internal_name = "i440ex", - .flags = DEVICE_PCI, - .local = INTEL_440EX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = INTEL_440EX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440bx_device = { - .name = "Intel 82443BX", + .name = "Intel 82443BX", .internal_name = "i440bx", - .flags = DEVICE_PCI, - .local = 0x8000 | INTEL_440BX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = 0x8000 | INTEL_440BX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440bx_no_agp_device = { - .name = "Intel 82443BX", + .name = "Intel 82443BX", .internal_name = "i440bx_no_agp", - .flags = DEVICE_PCI, - .local = 0x8200 | INTEL_440BX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = 0x8200 | INTEL_440BX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440gx_device = { - .name = "Intel 82443GX", + .name = "Intel 82443GX", .internal_name = "i440gx", - .flags = DEVICE_PCI, - .local = 0x8000 | INTEL_440GX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = 0x8000 | INTEL_440GX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t i440zx_device = { - .name = "Intel 82443ZX", + .name = "Intel 82443ZX", .internal_name = "i440zx", - .flags = DEVICE_PCI, - .local = 0x8000 | INTEL_440ZX, - .init = i4x0_init, - .close = i4x0_close, - .reset = i4x0_reset, + .flags = DEVICE_PCI, + .local = 0x8000 | INTEL_440ZX, + .init = i4x0_init, + .close = i4x0_close, + .reset = i4x0_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 2c018d3ef..96f0cad2c 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -29,19 +29,19 @@ /* Shadow capabilities */ #define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) -#define ENABLED_SHADOW ((LOCK_STATUS) ? RO_SHADOW : RW_SHADOW) -#define RW_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) -#define RO_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) +#define ENABLED_SHADOW ((LOCK_STATUS) ? RO_SHADOW : RW_SHADOW) +#define RW_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) +#define RO_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) /* Granularity Register Enable & Recalc */ #define EXTENDED_GRANULARITY_ENABLED (dev->regs[0x2c] & 0x01) -#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i + 8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW) +#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i + 8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW) /* R/W operator for the Video RAM region */ #define DETERMINE_VIDEO_RAM_WRITE_ACCESS ((dev->regs[0x22] & (0x08 << 8)) ? RW_SHADOW : RO_SHADOW) /* Base System 512/640KB switch */ -#define ENABLE_TOP_128KB (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) +#define ENABLE_TOP_128KB (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) #define DISABLE_TOP_128KB (MEM_READ_EXTANY | MEM_WRITE_EXTANY) /* ROM size determination */ @@ -70,75 +70,69 @@ intel_82335_log(const char *fmt, ...) { va_list ap; - if (intel_82335_do_log) - { + if (intel_82335_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define intel_82335_log(fmt, ...) +# define intel_82335_log(fmt, ...) #endif static void intel_82335_write(uint16_t addr, uint16_t val, void *priv) { - intel_82335_t *dev = (intel_82335_t *)priv; - uint32_t romsize = 0, base = 0, i = 0, rc1_remap = 0, rc2_remap = 0; + intel_82335_t *dev = (intel_82335_t *) priv; + uint32_t romsize = 0, base = 0, i = 0, rc1_remap = 0, rc2_remap = 0; dev->regs[addr] = val; - if (!dev->cfg_locked) - { + if (!dev->cfg_locked) { intel_82335_log("Register %02x: Write %04x\n", addr, val); - switch (addr) - { - case 0x22: /* Memory Controller */ + switch (addr) { + case 0x22: /* Memory Controller */ - /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ - romsize = ROM_SIZE; + /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ + romsize = ROM_SIZE; - if (!EXTENDED_GRANULARITY_ENABLED) - { - shadowbios = !!(dev->regs[0x22] & 0x01); - shadowbios_write = !!(dev->regs[0x22] & 0x01); + if (!EXTENDED_GRANULARITY_ENABLED) { + shadowbios = !!(dev->regs[0x22] & 0x01); + shadowbios_write = !!(dev->regs[0x22] & 0x01); - /* Base System 512/640KB set */ - mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); + /* Base System 512/640KB set */ + mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); - /* Video RAM shadow*/ - mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); + /* Video RAM shadow*/ + mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); - /* Option ROM shadow */ - mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW); + /* Option ROM shadow */ + mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW); - /* System ROM shadow */ - mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW); - } - break; - - case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */ - case 0x26: - rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0; - rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0; - mem_remap_top(rc1_remap + rc2_remap); - break; - - case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ - if (EXTENDED_GRANULARITY_ENABLED) - { - for (i = 0; i < 8; i++) - { - base = 0xc0000 + (i << 15); - shadowbios = (dev->regs[0x2e] & (1 << (i + 8))) && (base == romsize); - shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); - mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC); + /* System ROM shadow */ + mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW); } break; - } + + case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */ + case 0x26: + rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0; + rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0; + mem_remap_top(rc1_remap + rc2_remap); + break; + + case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ + if (EXTENDED_GRANULARITY_ENABLED) { + for (i = 0; i < 8; i++) { + base = 0xc0000 + (i << 15); + shadowbios = (dev->regs[0x2e] & (1 << (i + 8))) && (base == romsize); + shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); + mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC); + } + break; + } } } @@ -149,7 +143,7 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) static uint16_t intel_82335_read(uint16_t addr, void *priv) { - intel_82335_t *dev = (intel_82335_t *)priv; + intel_82335_t *dev = (intel_82335_t *) priv; intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]); @@ -159,7 +153,7 @@ intel_82335_read(uint16_t addr, void *priv) static void intel_82335_close(void *priv) { - intel_82335_t *dev = (intel_82335_t *)priv; + intel_82335_t *dev = (intel_82335_t *) priv; free(dev); } @@ -167,7 +161,7 @@ intel_82335_close(void *priv) static void * intel_82335_init(const device_t *info) { - intel_82335_t *dev = (intel_82335_t *)malloc(sizeof(intel_82335_t)); + intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t)); memset(dev, 0, sizeof(intel_82335_t)); memset(dev->regs, 0, sizeof(dev->regs)); @@ -197,15 +191,15 @@ intel_82335_init(const device_t *info) } const device_t intel_82335_device = { - .name = "Intel 82335", + .name = "Intel 82335", .internal_name = "intel_82335", - .flags = 0, - .local = 0, - .init = intel_82335_init, - .close = intel_82335_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = intel_82335_init, + .close = intel_82335_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_i450kx.c b/src/chipset/intel_i450kx.c index ad92218f8..a6cecf915 100644 --- a/src/chipset/intel_i450kx.c +++ b/src/chipset/intel_i450kx.c @@ -38,7 +38,6 @@ i450GX is way more popular of an option but needs more stuff. #include <86box/spd.h> #include <86box/chipset.h> - #ifdef ENABLE_450KX_LOG int i450kx_do_log = ENABLE_450KX_LOG; static void @@ -46,48 +45,44 @@ i450kx_log(const char *fmt, ...) { va_list ap; - if (i450kx_do_log) - { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + if (i450kx_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define i450kx_log(fmt, ...) +# define i450kx_log(fmt, ...) #endif - /* TODO: Finish the bus index stuff. */ typedef struct i450kx_t { - smram_t * smram[2]; + smram_t *smram[2]; - uint8_t pb_pci_conf[256], mc_pci_conf[256]; - uint8_t mem_state[2][256]; + uint8_t pb_pci_conf[256], mc_pci_conf[256]; + uint8_t mem_state[2][256]; - uint8_t bus_index; + uint8_t bus_index; } i450kx_t; - static void i450kx_map(i450kx_t *dev, int bus, uint32_t addr, uint32_t size, int state) { - uint32_t base = addr >> 12; - int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY, - MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL }; + uint32_t base = addr >> 12; + int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY, + MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL }; state &= 3; if (dev->mem_state[bus][base] != state) { - if (bus) - mem_set_mem_state_bus_both(addr, size, states[state]); - else - mem_set_mem_state_cpu_both(addr, size, states[state]); - dev->mem_state[bus][base] = state; - flushmmucache_nopc(); + if (bus) + mem_set_mem_state_bus_both(addr, size, states[state]); + else + mem_set_mem_state_cpu_both(addr, size, states[state]); + dev->mem_state[bus][base] = state; + flushmmucache_nopc(); } } - static void i450kx_smram_recalc(i450kx_t *dev, int bus) { @@ -100,16 +95,15 @@ i450kx_smram_recalc(i450kx_t *dev, int bus) size = (((uint32_t) ((regs[0xbb] >> 4) & 0x0f)) << 16) + 0x00010000; if ((addr != 0x00000000) && !!(regs[0x57] & 0x08)) { - if (bus) - smram_enable_ex(dev->smram[bus], addr, addr, size, 0, !!(regs[0x57] & 8), 0, 1); - else - smram_enable_ex(dev->smram[bus], addr, addr, size, !!(regs[0x57] & 8), 0, 1, 0); + if (bus) + smram_enable_ex(dev->smram[bus], addr, addr, size, 0, !!(regs[0x57] & 8), 0, 1); + else + smram_enable_ex(dev->smram[bus], addr, addr, size, !!(regs[0x57] & 8), 0, 1, 0); } flushmmucache(); } - static void i450kx_vid_buf_recalc(i450kx_t *dev, int bus) { @@ -119,269 +113,273 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus) int state = (regs[0x58] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY); if (bus) - mem_set_mem_state_bus_both(0x000a0000, 0x00020000, state); + mem_set_mem_state_bus_both(0x000a0000, 0x00020000, state); else - mem_set_mem_state_cpu_both(0x000a0000, 0x00020000, state); + mem_set_mem_state_cpu_both(0x000a0000, 0x00020000, state); flushmmucache_nopc(); } - static void pb_write(int func, int addr, uint8_t val, void *priv) { - i450kx_t *dev = (i450kx_t *)priv; + i450kx_t *dev = (i450kx_t *) priv; // pclog("i450KX-PB: [W] dev->pb_pci_conf[%02X] = %02X POST: %02X\n", addr, val, inb(0x80)); i450kx_log("i450KX-PB: [W] dev->pb_pci_conf[%02X] = %02X POST: %02X\n", addr, val, inb(0x80)); - if (func == 0) switch (addr) { - case 0x04: - dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x04) | (val & 0x53); - break; - case 0x05: - dev->pb_pci_conf[addr] = val & 0x01; - break; + if (func == 0) + switch (addr) { + case 0x04: + dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x04) | (val & 0x53); + break; + case 0x05: + dev->pb_pci_conf[addr] = val & 0x01; + break; - case 0x07: - dev->pb_pci_conf[addr] &= ~(val & 0xf9); - break; + case 0x07: + dev->pb_pci_conf[addr] &= ~(val & 0xf9); + break; - case 0x0d: - dev->pb_pci_conf[addr] = val; - break; + case 0x0d: + dev->pb_pci_conf[addr] = val; + break; - case 0x0f: - dev->pb_pci_conf[addr] = val & 0xcf; - break; + case 0x0f: + dev->pb_pci_conf[addr] = val & 0xcf; + break; - case 0x40: case 0x41: - dev->pb_pci_conf[addr] = val; - break; - case 0x43: - dev->pb_pci_conf[addr] = val & 0x80; - break; + case 0x40: + case 0x41: + dev->pb_pci_conf[addr] = val; + break; + case 0x43: + dev->pb_pci_conf[addr] = val & 0x80; + break; - case 0x48: - dev->pb_pci_conf[addr] = val & 0x06; - break; + case 0x48: + dev->pb_pci_conf[addr] = val & 0x06; + break; - case 0x4a: case 0x4b: - dev->pb_pci_conf[addr] = val; - // if (addr == 0x4a) - // pci_remap_bus(dev->bus_index, val); - break; + case 0x4a: + case 0x4b: + dev->pb_pci_conf[addr] = val; + // if (addr == 0x4a) + // pci_remap_bus(dev->bus_index, val); + break; - case 0x4c: - dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x01) | (val & 0xd8); - break; + case 0x4c: + dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x01) | (val & 0xd8); + break; - case 0x51: - dev->pb_pci_conf[addr] = val; - break; + case 0x51: + dev->pb_pci_conf[addr] = val; + break; - case 0x53: - dev->pb_pci_conf[addr] = val & 0x02; - break; + case 0x53: + dev->pb_pci_conf[addr] = val & 0x02; + break; - case 0x54: - dev->pb_pci_conf[addr] = val & 0x7b; - break; - case 0x55: - dev->pb_pci_conf[addr] = val & 0x03; - break; + case 0x54: + dev->pb_pci_conf[addr] = val & 0x7b; + break; + case 0x55: + dev->pb_pci_conf[addr] = val & 0x03; + break; - case 0x57: - dev->pb_pci_conf[addr] = val & 0x08; - i450kx_smram_recalc(dev, 1); - break; + case 0x57: + dev->pb_pci_conf[addr] = val & 0x08; + i450kx_smram_recalc(dev, 1); + break; - case 0x58: - dev->pb_pci_conf[addr] = val & 0x02; - i450kx_vid_buf_recalc(dev, 1); - break; + case 0x58: + dev->pb_pci_conf[addr] = val & 0x02; + i450kx_vid_buf_recalc(dev, 1); + break; - case 0x59: /* PAM0 */ - if ((dev->pb_pci_conf[0x59] ^ val) & 0x0f) - i450kx_map(dev, 1, 0x80000, 0x20000, val & 0x0f); - if ((dev->pb_pci_conf[0x59] ^ val) & 0xf0) { - i450kx_map(dev, 1, 0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - dev->pb_pci_conf[0x59] = val & 0x33; - break; - case 0x5a: /* PAM1 */ - if ((dev->pb_pci_conf[0x5a] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xc0000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5a] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xc4000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5a] = val & 0x33; - break; - case 0x5b: /*PAM2 */ - if ((dev->pb_pci_conf[0x5b] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xc8000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5b] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xcc000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5b] = val & 0x33; - break; - case 0x5c: /*PAM3 */ - if ((dev->pb_pci_conf[0x5c] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xd0000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5c] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xd4000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5c] = val & 0x33; - break; - case 0x5d: /* PAM4 */ - if ((dev->pb_pci_conf[0x5d] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xd8000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5d] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xdc000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5d] = val & 0x33; - break; - case 0x5e: /* PAM5 */ - if ((dev->pb_pci_conf[0x5e] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xe0000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5e] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xe4000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5e] = val & 0x33; - break; - case 0x5f: /* PAM6 */ - if ((dev->pb_pci_conf[0x5f] ^ val) & 0x0f) - i450kx_map(dev, 1, 0xe8000, 0x04000, val & 0xf); - if ((dev->pb_pci_conf[0x5f] ^ val) & 0xf0) - i450kx_map(dev, 1, 0xec000, 0x04000, val >> 4); - dev->pb_pci_conf[0x5f] = val & 0x33; - break; + case 0x59: /* PAM0 */ + if ((dev->pb_pci_conf[0x59] ^ val) & 0x0f) + i450kx_map(dev, 1, 0x80000, 0x20000, val & 0x0f); + if ((dev->pb_pci_conf[0x59] ^ val) & 0xf0) { + i450kx_map(dev, 1, 0xf0000, 0x10000, val >> 4); + shadowbios = (val & 0x10); + } + dev->pb_pci_conf[0x59] = val & 0x33; + break; + case 0x5a: /* PAM1 */ + if ((dev->pb_pci_conf[0x5a] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xc0000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5a] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xc4000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5a] = val & 0x33; + break; + case 0x5b: /*PAM2 */ + if ((dev->pb_pci_conf[0x5b] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xc8000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5b] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xcc000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5b] = val & 0x33; + break; + case 0x5c: /*PAM3 */ + if ((dev->pb_pci_conf[0x5c] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xd0000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5c] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xd4000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5c] = val & 0x33; + break; + case 0x5d: /* PAM4 */ + if ((dev->pb_pci_conf[0x5d] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xd8000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5d] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xdc000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5d] = val & 0x33; + break; + case 0x5e: /* PAM5 */ + if ((dev->pb_pci_conf[0x5e] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xe0000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5e] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xe4000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5e] = val & 0x33; + break; + case 0x5f: /* PAM6 */ + if ((dev->pb_pci_conf[0x5f] ^ val) & 0x0f) + i450kx_map(dev, 1, 0xe8000, 0x04000, val & 0xf); + if ((dev->pb_pci_conf[0x5f] ^ val) & 0xf0) + i450kx_map(dev, 1, 0xec000, 0x04000, val >> 4); + dev->pb_pci_conf[0x5f] = val & 0x33; + break; - case 0x70: - dev->pb_pci_conf[addr] = val & 0xf8; - break; + case 0x70: + dev->pb_pci_conf[addr] = val & 0xf8; + break; - case 0x71: - dev->pb_pci_conf[addr] = val & 0x71; - break; + case 0x71: + dev->pb_pci_conf[addr] = val & 0x71; + break; - case 0x78: - dev->pb_pci_conf[addr] = val & 0xf0; - break; - case 0x79: - dev->pb_pci_conf[addr] = val & 0xfc; - break; - case 0x7a: - dev->pb_pci_conf[addr] = val; - break; - case 0x7b: - dev->pb_pci_conf[addr] = val & 0x0f; - break; + case 0x78: + dev->pb_pci_conf[addr] = val & 0xf0; + break; + case 0x79: + dev->pb_pci_conf[addr] = val & 0xfc; + break; + case 0x7a: + dev->pb_pci_conf[addr] = val; + break; + case 0x7b: + dev->pb_pci_conf[addr] = val & 0x0f; + break; - case 0x7c: - dev->pb_pci_conf[addr] = val & 0x9f; - break; - case 0x7d: - dev->pb_pci_conf[addr] = val & 0x1a; - break; - case 0x7e: - dev->pb_pci_conf[addr] = val & 0xf0; - break; - case 0x7f: - dev->pb_pci_conf[addr] = val; - break; + case 0x7c: + dev->pb_pci_conf[addr] = val & 0x9f; + break; + case 0x7d: + dev->pb_pci_conf[addr] = val & 0x1a; + break; + case 0x7e: + dev->pb_pci_conf[addr] = val & 0xf0; + break; + case 0x7f: + dev->pb_pci_conf[addr] = val; + break; - case 0x88: case 0x89: - dev->pb_pci_conf[addr] = val; - break; - case 0x8b: - dev->pb_pci_conf[addr] = val & 0x80; - break; - case 0x8c: case 0x8d: - dev->pb_pci_conf[addr] = val; - break; + case 0x88: + case 0x89: + dev->pb_pci_conf[addr] = val; + break; + case 0x8b: + dev->pb_pci_conf[addr] = val & 0x80; + break; + case 0x8c: + case 0x8d: + dev->pb_pci_conf[addr] = val; + break; - case 0x9c: - dev->pb_pci_conf[addr] = val & 0x01; - break; + case 0x9c: + dev->pb_pci_conf[addr] = val & 0x01; + break; - case 0xa4: - dev->pb_pci_conf[addr] = val & 0xf8; - break; - case 0xa5: case 0xa6: - dev->pb_pci_conf[addr] = val; - break; - case 0xa7: - dev->pb_pci_conf[addr] = val & 0x0f; - break; + case 0xa4: + dev->pb_pci_conf[addr] = val & 0xf8; + break; + case 0xa5: + case 0xa6: + dev->pb_pci_conf[addr] = val; + break; + case 0xa7: + dev->pb_pci_conf[addr] = val & 0x0f; + break; - case 0xb0: - dev->pb_pci_conf[addr] = val & 0xe0; - break; - case 0xb1: - dev->pb_pci_conf[addr] = val & /*0x1a*/ 0x1f; - break; + case 0xb0: + dev->pb_pci_conf[addr] = val & 0xe0; + break; + case 0xb1: + dev->pb_pci_conf[addr] = val & /*0x1a*/ 0x1f; + break; - case 0xb4: - dev->pb_pci_conf[addr] = val & 0xe0; - break; - case 0xb5: - dev->pb_pci_conf[addr] = val & 0x1f; - break; + case 0xb4: + dev->pb_pci_conf[addr] = val & 0xe0; + break; + case 0xb5: + dev->pb_pci_conf[addr] = val & 0x1f; + break; - case 0xb8: case 0xb9: - dev->pb_pci_conf[addr] = val; - i450kx_smram_recalc(dev, 1); - break; - case 0xbb: - dev->pb_pci_conf[addr] = val & 0xf0; - i450kx_smram_recalc(dev, 1); - break; + case 0xb8: + case 0xb9: + dev->pb_pci_conf[addr] = val; + i450kx_smram_recalc(dev, 1); + break; + case 0xbb: + dev->pb_pci_conf[addr] = val & 0xf0; + i450kx_smram_recalc(dev, 1); + break; - case 0xbc: - dev->pb_pci_conf[addr] = val & 0x11; - break; + case 0xbc: + dev->pb_pci_conf[addr] = val & 0x11; + break; - case 0xc0: - dev->pb_pci_conf[addr] = val & 0xdf; - break; - case 0xc1: - dev->pb_pci_conf[addr] = val & 0x3f; - break; + case 0xc0: + dev->pb_pci_conf[addr] = val & 0xdf; + break; + case 0xc1: + dev->pb_pci_conf[addr] = val & 0x3f; + break; - case 0xc4: - dev->pb_pci_conf[addr] &= ~(val & 0x0f); - break; - case 0xc5: - dev->pb_pci_conf[addr] &= ~(val & 0x0a); - break; - case 0xc6: - dev->pb_pci_conf[addr] &= ~(val & 0x1f); - break; + case 0xc4: + dev->pb_pci_conf[addr] &= ~(val & 0x0f); + break; + case 0xc5: + dev->pb_pci_conf[addr] &= ~(val & 0x0a); + break; + case 0xc6: + dev->pb_pci_conf[addr] &= ~(val & 0x1f); + break; - case 0xc8: - dev->pb_pci_conf[addr] = val & 0x1f; - break; + case 0xc8: + dev->pb_pci_conf[addr] = val & 0x1f; + break; - case 0xca: - case 0xcb: - dev->pb_pci_conf[addr] = val; - break; - } + case 0xca: + case 0xcb: + dev->pb_pci_conf[addr] = val; + break; + } } - static uint8_t pb_read(int func, int addr, void *priv) { - i450kx_t *dev = (i450kx_t *)priv; - uint8_t ret = 0xff; + i450kx_t *dev = (i450kx_t *) priv; + uint8_t ret = 0xff; if (func == 0) - ret = dev->pb_pci_conf[addr]; + ret = dev->pb_pci_conf[addr]; // pclog("i450KX-PB: [R] dev->pb_pci_conf[%02X] = %02X POST: %02X\n", addr, ret, inb(0x80)); return ret; } - /* A way to use spd_write_drbs_interlaved() and convert the output to what we need. */ static void mc_fill_drbs(i450kx_t *dev) @@ -390,227 +388,229 @@ mc_fill_drbs(i450kx_t *dev) spd_write_drbs_interleaved(dev->mc_pci_conf, 0x60, 0x6f, 4); for (i = 0x60; i <= 0x6f; i++) { - if (i & 0x01) - dev->mc_pci_conf[i] = 0x00; - else - dev->mc_pci_conf[i] &= 0x7f; + if (i & 0x01) + dev->mc_pci_conf[i] = 0x00; + else + dev->mc_pci_conf[i] &= 0x7f; } } - static void mc_write(int func, int addr, uint8_t val, void *priv) { - i450kx_t *dev = (i450kx_t *)priv; + i450kx_t *dev = (i450kx_t *) priv; // pclog("i450KX-MC: [W] dev->mc_pci_conf[%02X] = %02X POST: %02X\n", addr, val, inb(0x80)); i450kx_log("i450KX-MC: [W] dev->mc_pci_conf[%02X] = %02X POST: %02X\n", addr, val, inb(0x80)); - if (func == 0) switch (addr) { - case 0x4c: - dev->mc_pci_conf[addr] = val & 0xdf; - break; - case 0x4d: - dev->mc_pci_conf[addr] = val & 0xff; - break; + if (func == 0) + switch (addr) { + case 0x4c: + dev->mc_pci_conf[addr] = val & 0xdf; + break; + case 0x4d: + dev->mc_pci_conf[addr] = val & 0xff; + break; - case 0x57: - dev->mc_pci_conf[addr] = val & 0x08; - i450kx_smram_recalc(dev, 0); - break; + case 0x57: + dev->mc_pci_conf[addr] = val & 0x08; + i450kx_smram_recalc(dev, 0); + break; - case 0x58: - dev->mc_pci_conf[addr] = val & 0x02; - i450kx_vid_buf_recalc(dev, 0); - break; + case 0x58: + dev->mc_pci_conf[addr] = val & 0x02; + i450kx_vid_buf_recalc(dev, 0); + break; - case 0x59: /* PAM0 */ - if ((dev->mc_pci_conf[0x59] ^ val) & 0x0f) - i450kx_map(dev, 0, 0x80000, 0x20000, val & 0x0f); - if ((dev->mc_pci_conf[0x59] ^ val) & 0xf0) { - i450kx_map(dev, 0, 0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - dev->mc_pci_conf[0x59] = val & 0x33; - break; - case 0x5a: /* PAM1 */ - if ((dev->mc_pci_conf[0x5a] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xc0000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5a] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xc4000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5a] = val & 0x33; - break; - case 0x5b: /*PAM2 */ - if ((dev->mc_pci_conf[0x5b] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xc8000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5b] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xcc000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5b] = val & 0x33; - break; - case 0x5c: /*PAM3 */ - if ((dev->mc_pci_conf[0x5c] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xd0000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5c] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xd4000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5c] = val & 0x33; - break; - case 0x5d: /* PAM4 */ - if ((dev->mc_pci_conf[0x5d] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xd8000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5d] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xdc000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5d] = val & 0x33; - break; - case 0x5e: /* PAM5 */ - if ((dev->mc_pci_conf[0x5e] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xe0000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5e] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xe4000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5e] = val & 0x33; - break; - case 0x5f: /* PAM6 */ - if ((dev->mc_pci_conf[0x5f] ^ val) & 0x0f) - i450kx_map(dev, 0, 0xe8000, 0x04000, val & 0xf); - if ((dev->mc_pci_conf[0x5f] ^ val) & 0xf0) - i450kx_map(dev, 0, 0xec000, 0x04000, val >> 4); - dev->mc_pci_conf[0x5f] = val & 0x33; - break; + case 0x59: /* PAM0 */ + if ((dev->mc_pci_conf[0x59] ^ val) & 0x0f) + i450kx_map(dev, 0, 0x80000, 0x20000, val & 0x0f); + if ((dev->mc_pci_conf[0x59] ^ val) & 0xf0) { + i450kx_map(dev, 0, 0xf0000, 0x10000, val >> 4); + shadowbios = (val & 0x10); + } + dev->mc_pci_conf[0x59] = val & 0x33; + break; + case 0x5a: /* PAM1 */ + if ((dev->mc_pci_conf[0x5a] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xc0000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5a] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xc4000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5a] = val & 0x33; + break; + case 0x5b: /*PAM2 */ + if ((dev->mc_pci_conf[0x5b] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xc8000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5b] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xcc000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5b] = val & 0x33; + break; + case 0x5c: /*PAM3 */ + if ((dev->mc_pci_conf[0x5c] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xd0000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5c] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xd4000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5c] = val & 0x33; + break; + case 0x5d: /* PAM4 */ + if ((dev->mc_pci_conf[0x5d] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xd8000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5d] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xdc000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5d] = val & 0x33; + break; + case 0x5e: /* PAM5 */ + if ((dev->mc_pci_conf[0x5e] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xe0000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5e] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xe4000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5e] = val & 0x33; + break; + case 0x5f: /* PAM6 */ + if ((dev->mc_pci_conf[0x5f] ^ val) & 0x0f) + i450kx_map(dev, 0, 0xe8000, 0x04000, val & 0xf); + if ((dev->mc_pci_conf[0x5f] ^ val) & 0xf0) + i450kx_map(dev, 0, 0xec000, 0x04000, val >> 4); + dev->mc_pci_conf[0x5f] = val & 0x33; + break; - case 0x60 ... 0x6f: - dev->mc_pci_conf[addr] = ((addr & 0x0f) & 0x01) ? 0x00 : (val & 0x7f); - mc_fill_drbs(dev); - break; + case 0x60 ... 0x6f: + dev->mc_pci_conf[addr] = ((addr & 0x0f) & 0x01) ? 0x00 : (val & 0x7f); + mc_fill_drbs(dev); + break; - case 0x74 ... 0x77: - dev->mc_pci_conf[addr] = val; - break; + case 0x74 ... 0x77: + dev->mc_pci_conf[addr] = val; + break; - case 0x78: - dev->mc_pci_conf[addr] = val & 0xf0; - break; - case 0x79: - dev->mc_pci_conf[addr] = val & 0xfe; - break; - case 0x7a: - dev->mc_pci_conf[addr] = val; - break; - case 0x7b: - dev->mc_pci_conf[addr] = val & 0x0f; - break; + case 0x78: + dev->mc_pci_conf[addr] = val & 0xf0; + break; + case 0x79: + dev->mc_pci_conf[addr] = val & 0xfe; + break; + case 0x7a: + dev->mc_pci_conf[addr] = val; + break; + case 0x7b: + dev->mc_pci_conf[addr] = val & 0x0f; + break; - case 0x7c: - dev->mc_pci_conf[addr] = val & 0x1f; - break; - case 0x7d: - dev->mc_pci_conf[addr] = val & 0x0c; - break; - case 0x7e: - dev->mc_pci_conf[addr] = val & 0xf0; - break; - case 0x7f: - dev->mc_pci_conf[addr] = val; - break; + case 0x7c: + dev->mc_pci_conf[addr] = val & 0x1f; + break; + case 0x7d: + dev->mc_pci_conf[addr] = val & 0x0c; + break; + case 0x7e: + dev->mc_pci_conf[addr] = val & 0xf0; + break; + case 0x7f: + dev->mc_pci_conf[addr] = val; + break; - case 0x88: case 0x89: - dev->mc_pci_conf[addr] = val; - break; - case 0x8b: - dev->mc_pci_conf[addr] = val & 0x80; - break; + case 0x88: + case 0x89: + dev->mc_pci_conf[addr] = val; + break; + case 0x8b: + dev->mc_pci_conf[addr] = val & 0x80; + break; - case 0x8c: case 0x8d: - dev->mc_pci_conf[addr] = val; - break; + case 0x8c: + case 0x8d: + dev->mc_pci_conf[addr] = val; + break; - case 0xa4: - dev->mc_pci_conf[addr] = val & 0x01; - break; - case 0xa5: - dev->pb_pci_conf[addr] = val & 0xf0; - break; - case 0xa6: - dev->mc_pci_conf[addr] = val; - break; - case 0xa7: - dev->mc_pci_conf[addr] = val & 0x0f; - break; + case 0xa4: + dev->mc_pci_conf[addr] = val & 0x01; + break; + case 0xa5: + dev->pb_pci_conf[addr] = val & 0xf0; + break; + case 0xa6: + dev->mc_pci_conf[addr] = val; + break; + case 0xa7: + dev->mc_pci_conf[addr] = val & 0x0f; + break; - case 0xa8: - dev->mc_pci_conf[addr] = val & 0xfe; - break; - case 0xa9 ... 0xab: - dev->mc_pci_conf[addr] = val; - break; + case 0xa8: + dev->mc_pci_conf[addr] = val & 0xfe; + break; + case 0xa9 ... 0xab: + dev->mc_pci_conf[addr] = val; + break; - case 0xac ... 0xae: - dev->mc_pci_conf[addr] = val; - break; - case 0xaf: - dev->mc_pci_conf[addr] = val & 0x7f; - break; + case 0xac ... 0xae: + dev->mc_pci_conf[addr] = val; + break; + case 0xaf: + dev->mc_pci_conf[addr] = val & 0x7f; + break; - case 0xb8: case 0xb9: - dev->mc_pci_conf[addr] = val; - i450kx_smram_recalc(dev, 0); - break; - case 0xbb: - dev->mc_pci_conf[addr] = val & 0xf0; - i450kx_smram_recalc(dev, 0); - break; + case 0xb8: + case 0xb9: + dev->mc_pci_conf[addr] = val; + i450kx_smram_recalc(dev, 0); + break; + case 0xbb: + dev->mc_pci_conf[addr] = val & 0xf0; + i450kx_smram_recalc(dev, 0); + break; - case 0xbc: - dev->mc_pci_conf[addr] = val & 0x01; - break; + case 0xbc: + dev->mc_pci_conf[addr] = val & 0x01; + break; - case 0xc0: - dev->mc_pci_conf[addr] = val & 0x07; - break; + case 0xc0: + dev->mc_pci_conf[addr] = val & 0x07; + break; - case 0xc2: - dev->mc_pci_conf[addr] &= ~(val & 0x03); - break; + case 0xc2: + dev->mc_pci_conf[addr] &= ~(val & 0x03); + break; - case 0xc4: - dev->mc_pci_conf[addr] = val & 0xbf; - break; - case 0xc5: - dev->mc_pci_conf[addr] = val & 0x03; - break; + case 0xc4: + dev->mc_pci_conf[addr] = val & 0xbf; + break; + case 0xc5: + dev->mc_pci_conf[addr] = val & 0x03; + break; - case 0xc6: - dev->mc_pci_conf[addr] &= ~(val & 0x19); - break; + case 0xc6: + dev->mc_pci_conf[addr] &= ~(val & 0x19); + break; - case 0xc8: - dev->mc_pci_conf[addr] = val & 0x1f; - break; - case 0xca: case 0xcb: - dev->mc_pci_conf[addr] = val; - break; - } + case 0xc8: + dev->mc_pci_conf[addr] = val & 0x1f; + break; + case 0xca: + case 0xcb: + dev->mc_pci_conf[addr] = val; + break; + } } - static uint8_t mc_read(int func, int addr, void *priv) { - i450kx_t *dev = (i450kx_t *)priv; - uint8_t ret = 0xff; + i450kx_t *dev = (i450kx_t *) priv; + uint8_t ret = 0xff; if (func == 0) - ret = dev->mc_pci_conf[addr]; + ret = dev->mc_pci_conf[addr]; // pclog("i450KX-MC: [R] dev->mc_pci_conf[%02X] = %02X POST: %02X\n", addr, ret, inb(0x80)); return ret; } - static void i450kx_reset(void *priv) { - i450kx_t *dev = (i450kx_t *)priv; - uint32_t i; + i450kx_t *dev = (i450kx_t *) priv; + uint32_t i; // pclog("i450KX: i450kx_reset()\n"); @@ -697,7 +697,7 @@ i450kx_reset(void *priv) i450kx_vid_buf_recalc(dev, 1); pb_write(0, 0x59, 0x30, dev); for (i = 0x5a; i <= 0x5f; i++) - pb_write(0, i, 0x33, dev); + pb_write(0, i, 0x33, dev); /* Defaults MC */ dev->mc_pci_conf[0x00] = 0x86; @@ -769,30 +769,28 @@ i450kx_reset(void *priv) i450kx_vid_buf_recalc(dev, 0); mc_write(0, 0x59, 0x03, dev); for (i = 0x5a; i <= 0x5f; i++) - mc_write(0, i, 0x00, dev); + mc_write(0, i, 0x00, dev); for (i = 0x60; i <= 0x6f; i++) - dev->mc_pci_conf[i] = 0x01; + dev->mc_pci_conf[i] = 0x01; } - static void i450kx_close(void *priv) { - i450kx_t *dev = (i450kx_t *)priv; + i450kx_t *dev = (i450kx_t *) priv; smram_del(dev->smram[1]); smram_del(dev->smram[0]); free(dev); } - static void * i450kx_init(const device_t *info) { - i450kx_t *dev = (i450kx_t *)malloc(sizeof(i450kx_t)); + i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t)); memset(dev, 0, sizeof(i450kx_t)); - pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev); /* Device 19h: Intel 450KX PCI Bridge PB */ - pci_add_card(PCI_ADD_AGPBRIDGE, mc_read, mc_write, dev); /* Device 14h: Intel 450KX Memory Controller MC */ + pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev); /* Device 19h: Intel 450KX PCI Bridge PB */ + pci_add_card(PCI_ADD_AGPBRIDGE, mc_read, mc_write, dev); /* Device 14h: Intel 450KX Memory Controller MC */ dev->smram[0] = smram_add(); dev->smram[1] = smram_add(); @@ -807,15 +805,15 @@ i450kx_init(const device_t *info) } const device_t i450kx_device = { - .name = "Intel 450KX (Mars)", + .name = "Intel 450KX (Mars)", .internal_name = "i450kx", - .flags = DEVICE_PCI, - .local = 0, - .init = i450kx_init, - .close = i450kx_close, - .reset = i450kx_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = i450kx_init, + .close = i450kx_close, + .reset = i450kx_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index f8302e854..8670de9e0 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -50,93 +50,89 @@ #include <86box/smbus.h> #include <86box/chipset.h> - typedef struct { struct _piix_ *dev; - void *trap; - uint8_t dev_id; - uint32_t *sts_reg, *en_reg, sts_mask, en_mask; + void *trap; + uint8_t dev_id; + uint32_t *sts_reg, *en_reg, sts_mask, en_mask; } piix_io_trap_t; typedef struct _piix_ { - uint8_t cur_readout_reg, rev, - type, func_shift, - max_func, pci_slot, - no_mirq0, pad, - regs[4][256], - readout_regs[256], board_config[2]; - uint16_t func0_id, nvr_io_base, - acpi_io_base; - double fast_off_period; - sff8038i_t *bm[2]; - smbus_piix4_t * smbus; - apm_t * apm; - nvr_t * nvr; - ddma_t * ddma; - usb_t * usb; - acpi_t * acpi; - piix_io_trap_t io_traps[26]; - port_92_t * port_92; - pc_timer_t fast_off_timer; + uint8_t cur_readout_reg, rev, + type, func_shift, + max_func, pci_slot, + no_mirq0, pad, + regs[4][256], + readout_regs[256], board_config[2]; + uint16_t func0_id, nvr_io_base, + acpi_io_base; + double fast_off_period; + sff8038i_t *bm[2]; + smbus_piix4_t *smbus; + apm_t *apm; + nvr_t *nvr; + ddma_t *ddma; + usb_t *usb; + acpi_t *acpi; + piix_io_trap_t io_traps[26]; + port_92_t *port_92; + pc_timer_t fast_off_timer; } piix_t; - #ifdef ENABLE_PIIX_LOG int piix_do_log = ENABLE_PIIX_LOG; - static void piix_log(const char *fmt, ...) { va_list ap; if (piix_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define piix_log(fmt, ...) +# define piix_log(fmt, ...) #endif - static void smsc_ide_irqs(piix_t *dev) { int irq_line = 3, irq_mode[2] = { 0, 0 }; if (dev->regs[1][0x09] & 0x01) - irq_mode[0] = (dev->regs[0][0xe1] & 0x01) ? 3 : 1; + irq_mode[0] = (dev->regs[0][0xe1] & 0x01) ? 3 : 1; if (dev->regs[1][0x09] & 0x04) - irq_mode[1] = (dev->regs[0][0xe1] & 0x01) ? 3 : 1; + irq_mode[1] = (dev->regs[0][0xe1] & 0x01) ? 3 : 1; switch ((dev->regs[0][0xe1] >> 1) & 0x07) { - case 0x00: - irq_line = 3; - break; - case 0x01: - irq_line = 5; - break; - case 0x02: - irq_line = 7; - break; - case 0x03: - irq_line = 8; - break; - case 0x04: - irq_line = 11; - break; - case 0x05: - irq_line = 12; - break; - case 0x06: - irq_line = 14; - break; - case 0x07: - irq_line = 15; - break; + case 0x00: + irq_line = 3; + break; + case 0x01: + irq_line = 5; + break; + case 0x02: + irq_line = 7; + break; + case 0x03: + irq_line = 8; + break; + case 0x04: + irq_line = 11; + break; + case 0x05: + irq_line = 12; + break; + case 0x06: + irq_line = 14; + break; + case 0x07: + irq_line = 15; + break; } sff_set_irq_line(dev->bm[0], irq_line); @@ -148,54 +144,52 @@ smsc_ide_irqs(piix_t *dev) sff_set_irq_mode(dev->bm[1], 1, irq_mode[1]); } - static void piix_ide_handlers(piix_t *dev, int bus) { uint16_t main, side; if (bus & 0x01) { - ide_pri_disable(); + ide_pri_disable(); - if (dev->type == 5) { - if (dev->regs[1][0x09] & 0x01) { - main = (dev->regs[1][0x11] << 8) | (dev->regs[1][0x10] & 0xf8); - side = ((dev->regs[1][0x15] << 8) | (dev->regs[1][0x14] & 0xfc)) + 2; - } else { - main = 0x1f0; - side = 0x3f6; - } + if (dev->type == 5) { + if (dev->regs[1][0x09] & 0x01) { + main = (dev->regs[1][0x11] << 8) | (dev->regs[1][0x10] & 0xf8); + side = ((dev->regs[1][0x15] << 8) | (dev->regs[1][0x14] & 0xfc)) + 2; + } else { + main = 0x1f0; + side = 0x3f6; + } - ide_set_base(0, main); - ide_set_side(0, side); - } + ide_set_base(0, main); + ide_set_side(0, side); + } - if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x41] & 0x80)) - ide_pri_enable(); + if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x41] & 0x80)) + ide_pri_enable(); } if (bus & 0x02) { - ide_sec_disable(); + ide_sec_disable(); - if (dev->type == 5) { - if (dev->regs[1][0x09] & 0x04) { - main = (dev->regs[1][0x19] << 8) | (dev->regs[1][0x18] & 0xf8); - side = ((dev->regs[1][0x1d] << 8) | (dev->regs[1][0x1c] & 0xfc)) + 2; - } else { - main = 0x170; - side = 0x376; - } + if (dev->type == 5) { + if (dev->regs[1][0x09] & 0x04) { + main = (dev->regs[1][0x19] << 8) | (dev->regs[1][0x18] & 0xf8); + side = ((dev->regs[1][0x1d] << 8) | (dev->regs[1][0x1c] & 0xfc)) + 2; + } else { + main = 0x170; + side = 0x376; + } - ide_set_base(1, main); - ide_set_side(1, side); - } + ide_set_base(1, main); + ide_set_side(1, side); + } - if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x43] & 0x80)) - ide_sec_enable(); + if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x43] & 0x80)) + ide_sec_enable(); } } - static void piix_ide_bm_handlers(piix_t *dev) { @@ -205,7 +199,6 @@ piix_ide_bm_handlers(piix_t *dev) sff_bus_master_handler(dev->bm[1], (dev->regs[1][0x04] & 1), base + 8); } - static uint8_t kbc_alias_reg_read(uint16_t addr, void *p) { @@ -214,14 +207,12 @@ kbc_alias_reg_read(uint16_t addr, void *p) return ret; } - static void kbc_alias_reg_write(uint16_t addr, uint8_t val, void *p) { outb(0x61, val); } - static void kbc_alias_update_io_mapping(piix_t *dev) { @@ -230,63 +221,59 @@ kbc_alias_update_io_mapping(piix_t *dev) io_removehandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); if (dev->regs[0][0x4e] & 0x08) { - io_sethandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); - io_sethandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); - io_sethandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); + io_sethandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); + io_sethandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); + io_sethandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev); } } - static void smbus_update_io_mapping(piix_t *dev) { smbus_piix4_remap(dev->smbus, ((uint16_t) (dev->regs[3][0x91] << 8)) | (dev->regs[3][0x90] & 0xf0), (dev->regs[3][PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->regs[3][0xd2] & 0x01)); } - static void nvr_update_io_mapping(piix_t *dev) { if (dev->nvr_io_base != 0x0000) { - piix_log("Removing NVR at %04X...\n", dev->nvr_io_base); - nvr_at_handler(0, dev->nvr_io_base, dev->nvr); - nvr_at_handler(0, dev->nvr_io_base + 0x0002, dev->nvr); - nvr_at_handler(0, dev->nvr_io_base + 0x0004, dev->nvr); + piix_log("Removing NVR at %04X...\n", dev->nvr_io_base); + nvr_at_handler(0, dev->nvr_io_base, dev->nvr); + nvr_at_handler(0, dev->nvr_io_base + 0x0002, dev->nvr); + nvr_at_handler(0, dev->nvr_io_base + 0x0004, dev->nvr); } if (dev->type == 5) - dev->nvr_io_base = (dev->regs[0][0xd5] << 8) | (dev->regs[0][0xd4] & 0xf0); + dev->nvr_io_base = (dev->regs[0][0xd5] << 8) | (dev->regs[0][0xd4] & 0xf0); else - dev->nvr_io_base = 0x70; + dev->nvr_io_base = 0x70; piix_log("New NVR I/O base: %04X\n", dev->nvr_io_base); if (dev->regs[0][0xcb] & 0x01) { - piix_log("Adding low NVR at %04X...\n", dev->nvr_io_base); - if (dev->nvr_io_base != 0x0000) { - nvr_at_handler(1, dev->nvr_io_base, dev->nvr); - nvr_at_handler(1, dev->nvr_io_base + 0x0004, dev->nvr); - } + piix_log("Adding low NVR at %04X...\n", dev->nvr_io_base); + if (dev->nvr_io_base != 0x0000) { + nvr_at_handler(1, dev->nvr_io_base, dev->nvr); + nvr_at_handler(1, dev->nvr_io_base + 0x0004, dev->nvr); + } } if (dev->regs[0][0xcb] & 0x04) { - piix_log("Adding high NVR at %04X...\n", dev->nvr_io_base + 0x0002); - if (dev->nvr_io_base != 0x0000) - nvr_at_handler(1, dev->nvr_io_base + 0x0002, dev->nvr); + piix_log("Adding high NVR at %04X...\n", dev->nvr_io_base + 0x0002); + if (dev->nvr_io_base != 0x0000) + nvr_at_handler(1, dev->nvr_io_base + 0x0002, dev->nvr); } } - static void piix_trap_io(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv) { piix_io_trap_t *trap = (piix_io_trap_t *) priv; if (*(trap->en_reg) & trap->en_mask) { - *(trap->sts_reg) |= trap->sts_mask; - acpi_raise_smi(trap->dev->acpi, 1); + *(trap->sts_reg) |= trap->sts_mask; + acpi_raise_smi(trap->dev->acpi, 1); } } - static void piix_trap_io_ide(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv) { @@ -294,44 +281,42 @@ piix_trap_io_ide(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv /* IDE traps are per drive, not per channel. */ if (ide_drives[trap->dev_id]->selected) - piix_trap_io(size, addr, write, val, priv); + piix_trap_io(size, addr, write, val, priv); } - static void piix_trap_update_devctl(piix_t *dev, uint8_t trap_id, uint8_t dev_id, - uint32_t devctl_mask, uint8_t enable, - uint16_t addr, uint16_t size) + uint32_t devctl_mask, uint8_t enable, + uint16_t addr, uint16_t size) { piix_io_trap_t *trap = &dev->io_traps[trap_id]; - enable = (dev->acpi->regs.devctl & devctl_mask) && enable; + enable = (dev->acpi->regs.devctl & devctl_mask) && enable; /* Set up Device I/O traps dynamically. */ if (enable && !trap->trap) { - trap->dev = dev; - trap->trap = io_trap_add((dev_id <= 3) ? piix_trap_io_ide : piix_trap_io, trap); - trap->dev_id = dev_id; - trap->sts_reg = &dev->acpi->regs.devsts; - trap->sts_mask = 0x00010000 << dev_id; - trap->en_reg = &dev->acpi->regs.devctl; - trap->en_mask = devctl_mask; + trap->dev = dev; + trap->trap = io_trap_add((dev_id <= 3) ? piix_trap_io_ide : piix_trap_io, trap); + trap->dev_id = dev_id; + trap->sts_reg = &dev->acpi->regs.devsts; + trap->sts_mask = 0x00010000 << dev_id; + trap->en_reg = &dev->acpi->regs.devctl; + trap->en_mask = devctl_mask; } #ifdef ENABLE_PIIX_LOG if ((dev_id == 9) || (dev_id == 10) || (dev_id == 12) || (dev_id == 13)) - piix_log("PIIX: Mapping trap device %d to %04X-%04X (enable %d)\n", dev_id, addr, addr + size - 1, enable); + piix_log("PIIX: Mapping trap device %d to %04X-%04X (enable %d)\n", dev_id, addr, addr + size - 1, enable); #endif /* Remap I/O trap. */ io_trap_remap(trap->trap, enable, addr, size); } - static void piix_trap_update(void *priv) { - piix_t *dev = (piix_t *) priv; - uint8_t trap_id = 0, *fregs = dev->regs[3]; + piix_t *dev = (piix_t *) priv; + uint8_t trap_id = 0, *fregs = dev->regs[3]; uint16_t temp; piix_trap_update_devctl(dev, trap_id++, 0, 0x00000002, 1, 0x1f0, 8); @@ -350,10 +335,18 @@ piix_trap_update(void *priv) piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x10, 0x200, 8); piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x08, 0x388, 4); switch (fregs[0x5d] & 0x03) { - case 0x00: temp = 0x530; break; - case 0x01: temp = 0x604; break; - case 0x02: temp = 0xe80; break; - default: temp = 0xf40; break; + case 0x00: + temp = 0x530; + break; + case 0x01: + temp = 0x604; + break; + case 0x02: + temp = 0xe80; + break; + default: + temp = 0xf40; + break; } piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x80, temp, 8); piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x01, 0x300 + (0x10 * ((fregs[0x5c] >> 1) & 0x03)), 4); @@ -362,49 +355,81 @@ piix_trap_update(void *priv) piix_trap_update_devctl(dev, trap_id++, 5, 0x00000800, fregs[0x51] & 0x10, 0x377 + (0x80 * !(fregs[0x63] & 0x10)), 1); switch (fregs[0x67] & 0x07) { - case 0x00: temp = 0x3f8; break; - case 0x01: temp = 0x2f8; break; - case 0x02: temp = 0x220; break; - case 0x03: temp = 0x228; break; - case 0x04: temp = 0x238; break; - case 0x05: temp = 0x2e8; break; - case 0x06: temp = 0x338; break; - default: temp = 0x3e8; break; + case 0x00: + temp = 0x3f8; + break; + case 0x01: + temp = 0x2f8; + break; + case 0x02: + temp = 0x220; + break; + case 0x03: + temp = 0x228; + break; + case 0x04: + temp = 0x238; + break; + case 0x05: + temp = 0x2e8; + break; + case 0x06: + temp = 0x338; + break; + default: + temp = 0x3e8; + break; } piix_trap_update_devctl(dev, trap_id++, 6, 0x00002000, fregs[0x51] & 0x40, temp, 8); switch (fregs[0x67] & 0x70) { - case 0x00: temp = 0x3f8; break; - case 0x10: temp = 0x2f8; break; - case 0x20: temp = 0x220; break; - case 0x30: temp = 0x228; break; - case 0x40: temp = 0x238; break; - case 0x50: temp = 0x2e8; break; - case 0x60: temp = 0x338; break; - default: temp = 0x3e8; break; + case 0x00: + temp = 0x3f8; + break; + case 0x10: + temp = 0x2f8; + break; + case 0x20: + temp = 0x220; + break; + case 0x30: + temp = 0x228; + break; + case 0x40: + temp = 0x238; + break; + case 0x50: + temp = 0x2e8; + break; + case 0x60: + temp = 0x338; + break; + default: + temp = 0x3e8; + break; } piix_trap_update_devctl(dev, trap_id++, 7, 0x00008000, fregs[0x52] & 0x01, temp, 8); switch (fregs[0x63] & 0x06) { - case 0x00: - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x3bc, 4); - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x7bc, 3); - break; + case 0x00: + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x3bc, 4); + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x7bc, 3); + break; - case 0x02: - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x378, 8); - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x778, 3); - break; + case 0x02: + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x378, 8); + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x778, 3); + break; - case 0x04: - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x278, 8); - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x678, 3); - break; + case 0x04: + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x278, 8); + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x678, 3); + break; - default: - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0); - piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0); - break; + default: + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0); + piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0); + break; } temp = fregs[0x62] & 0x0f; @@ -427,639 +452,700 @@ piix_trap_update(void *priv) /* Programmable memory trap not implemented. */ } - static void piix_write(int func, int addr, uint8_t val, void *priv) { - piix_t *dev = (piix_t *) priv; + piix_t *dev = (piix_t *) priv; uint8_t *fregs; uint16_t base; - int i; + int i; /* Return on unsupported function. */ if (dev->max_func > 0) { - if (func > dev->max_func) - return; + if (func > dev->max_func) + return; } else { - if (func > 1) - return; + if (func > 1) + return; } /* Ignore the new IDE BAR's on the Intel chips. */ if ((dev->type < 5) && (func == 1) && (addr >= 0x10) && (addr <= 0x1f)) - return; + return; piix_log("PIIX function %i write: %02X to %02X\n", func, val, addr); fregs = (uint8_t *) dev->regs[func]; - if (func == 0) switch (addr) { - case 0x04: - fregs[0x04] = (val & 0x08) | 0x07; - break; - case 0x05: - if (dev->type > 1) - fregs[0x05] = (val & 0x01); - break; - case 0x07: - if ((val & 0x40) && (dev->type > 1)) - fregs[0x07] &= 0xbf; - if (val & 0x20) - fregs[0x07] &= 0xdf; - if (val & 0x10) - fregs[0x07] &= 0xef; - if (val & 0x08) - fregs[0x07] &= 0xf7; - if (val & 0x04) - fregs[0x07] &= 0xfb; - break; - case 0x4c: - fregs[0x4c] = val; - if (dev->type > 1) - dma_alias_remove(); - else - dma_alias_remove_piix(); - if (!(val & 0x80)) { - if (dev->type > 1) - dma_alias_set(); - else - dma_alias_set_piix(); - } - break; - case 0x4e: - fregs[0x4e] = val; - keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0); - if (dev->type >= 4) - kbc_alias_update_io_mapping(dev); - break; - case 0x4f: - if (dev->type > 3) - fregs[0x4f] = val & 0x07; - else if (dev->type == 3) - fregs[0x4f] = val & 0x01; - break; - case 0x60: case 0x61: case 0x62: case 0x63: - piix_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); - fregs[addr] = val & 0x8f; - if (val & 0x80) - pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); - else - pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); - break; - case 0x64: - if (dev->type > 3) - fregs[0x64] = val; - break; - case 0x65: - if (dev->type > 4) - fregs[0x65] = val; - break; - case 0x66: - if (dev->type > 4) - fregs[0x66] = val & 0x81; - break; - case 0x69: - if (dev->type > 1) - fregs[0x69] = val & 0xfe; - else - fregs[0x69] = val & 0xfa; - break; - case 0x6a: - switch (dev->type) { - case 1: - default: - fregs[0x6a] = (fregs[0x6a] & 0xfb) | (val & 0x04); - fregs[0x0e] = (val & 0x04) ? 0x80 : 0x00; - piix_log("PIIX: Write %02X\n", val); - dev->max_func = 0 + !!(val & 0x04); - break; - case 3: - fregs[0x6a] = val & 0xd1; - piix_log("PIIX3: Write %02X\n", val); - dev->max_func = 1 + !!(val & 0x10); - break; - case 4: - fregs[0x6a] = val & 0x80; - break; - case 5: - /* This case is needed so it doesn't behave the PIIX way on the SMSC. */ - break; - } - break; - case 0x6b: - if ((dev->type > 1) && (dev->type <= 4) && (val & 0x80)) - fregs[0x6b] &= 0x7f; - return; - case 0x70: case 0x71: - if ((dev->type > 1) && (addr == 0x71)) - break; - if (dev->type < 4) { - piix_log("Set MIRQ routing: MIRQ%i -> %02X\n", addr & 0x01, val); - if (dev->type > 1) - fregs[addr] = val & 0xef; - else - fregs[addr] = val & 0xcf; - if (val & 0x80) - pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED); - else - pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf); - piix_log("MIRQ%i is %s\n", addr & 0x01, (val & 0x20) ? "disabled" : "enabled"); - } - break; - case 0x76: case 0x77: - if (dev->type > 1) - fregs[addr] = val & 0x87; - else if (dev->type <= 4) - fregs[addr] = val & 0x8f; - break; - case 0x78: case 0x79: - if (dev->type < 4) - fregs[addr] = val; - break; - case 0x80: - if (dev->type > 1) - fregs[addr] = val & 0x7f; - break; - case 0x81: - if (dev->type > 1) - fregs[addr] = val & 0x0f; - break; - case 0x82: - if (dev->type > 3) - fregs[addr] = val & 0x0f; - break; - case 0x90: - if (dev->type > 3) - fregs[addr] = val; - break; - case 0x91: - if (dev->type > 3) - fregs[addr] = val & 0xfc; - break; - case 0x92: case 0x93: case 0x94: case 0x95: - if (dev->type > 3) { - if (addr & 0x01) - fregs[addr] = val & 0xff; - else - fregs[addr] = val & 0xc0; + if (func == 0) + switch (addr) { + case 0x04: + fregs[0x04] = (val & 0x08) | 0x07; + break; + case 0x05: + if (dev->type > 1) + fregs[0x05] = (val & 0x01); + break; + case 0x07: + if ((val & 0x40) && (dev->type > 1)) + fregs[0x07] &= 0xbf; + if (val & 0x20) + fregs[0x07] &= 0xdf; + if (val & 0x10) + fregs[0x07] &= 0xef; + if (val & 0x08) + fregs[0x07] &= 0xf7; + if (val & 0x04) + fregs[0x07] &= 0xfb; + break; + case 0x4c: + fregs[0x4c] = val; + if (dev->type > 1) + dma_alias_remove(); + else + dma_alias_remove_piix(); + if (!(val & 0x80)) { + if (dev->type > 1) + dma_alias_set(); + else + dma_alias_set_piix(); + } + break; + case 0x4e: + fregs[0x4e] = val; + keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0); + if (dev->type >= 4) + kbc_alias_update_io_mapping(dev); + break; + case 0x4f: + if (dev->type > 3) + fregs[0x4f] = val & 0x07; + else if (dev->type == 3) + fregs[0x4f] = val & 0x01; + break; + case 0x60: + case 0x61: + case 0x62: + case 0x63: + piix_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); + fregs[addr] = val & 0x8f; + if (val & 0x80) + pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); + else + pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); + break; + case 0x64: + if (dev->type > 3) + fregs[0x64] = val; + break; + case 0x65: + if (dev->type > 4) + fregs[0x65] = val; + break; + case 0x66: + if (dev->type > 4) + fregs[0x66] = val & 0x81; + break; + case 0x69: + if (dev->type > 1) + fregs[0x69] = val & 0xfe; + else + fregs[0x69] = val & 0xfa; + break; + case 0x6a: + switch (dev->type) { + case 1: + default: + fregs[0x6a] = (fregs[0x6a] & 0xfb) | (val & 0x04); + fregs[0x0e] = (val & 0x04) ? 0x80 : 0x00; + piix_log("PIIX: Write %02X\n", val); + dev->max_func = 0 + !!(val & 0x04); + break; + case 3: + fregs[0x6a] = val & 0xd1; + piix_log("PIIX3: Write %02X\n", val); + dev->max_func = 1 + !!(val & 0x10); + break; + case 4: + fregs[0x6a] = val & 0x80; + break; + case 5: + /* This case is needed so it doesn't behave the PIIX way on the SMSC. */ + break; + } + break; + case 0x6b: + if ((dev->type > 1) && (dev->type <= 4) && (val & 0x80)) + fregs[0x6b] &= 0x7f; + return; + case 0x70: + case 0x71: + if ((dev->type > 1) && (addr == 0x71)) + break; + if (dev->type < 4) { + piix_log("Set MIRQ routing: MIRQ%i -> %02X\n", addr & 0x01, val); + if (dev->type > 1) + fregs[addr] = val & 0xef; + else + fregs[addr] = val & 0xcf; + if (val & 0x80) + pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED); + else + pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf); + piix_log("MIRQ%i is %s\n", addr & 0x01, (val & 0x20) ? "disabled" : "enabled"); + } + break; + case 0x76: + case 0x77: + if (dev->type > 1) + fregs[addr] = val & 0x87; + else if (dev->type <= 4) + fregs[addr] = val & 0x8f; + break; + case 0x78: + case 0x79: + if (dev->type < 4) + fregs[addr] = val; + break; + case 0x80: + if (dev->type > 1) + fregs[addr] = val & 0x7f; + break; + case 0x81: + if (dev->type > 1) + fregs[addr] = val & 0x0f; + break; + case 0x82: + if (dev->type > 3) + fregs[addr] = val & 0x0f; + break; + case 0x90: + if (dev->type > 3) + fregs[addr] = val; + break; + case 0x91: + if (dev->type > 3) + fregs[addr] = val & 0xfc; + break; + case 0x92: + case 0x93: + case 0x94: + case 0x95: + if (dev->type > 3) { + if (addr & 0x01) + fregs[addr] = val & 0xff; + else + fregs[addr] = val & 0xc0; - base = fregs[addr | 0x01] << 8; - base |= fregs[addr & 0xfe]; + base = fregs[addr | 0x01] << 8; + base |= fregs[addr & 0xfe]; - for (i = 0; i < 4; i++) - ddma_update_io_mapping(dev->ddma, (addr & 4) + i, fregs[addr & 0xfe] + (i << 4), fregs[addr | 0x01], (base != 0x0000)); - } - break; - case 0xa0: - if (dev->type < 4) { - fregs[addr] = val & 0x1f; - apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(fregs[0xa2] & 0x80)); - switch ((val & 0x18) >> 3) { - case 0x00: - dev->fast_off_period = PCICLK * 32768.0 * 60000.0; - break; - case 0x01: - default: - dev->fast_off_period = 0.0; - break; - case 0x02: - dev->fast_off_period = PCICLK; - break; - case 0x03: - dev->fast_off_period = PCICLK * 32768.0; - break; - } - cpu_fast_off_count = cpu_fast_off_val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - } - break; - case 0xa2: - if (dev->type < 4) { - fregs[addr] = val & 0xff; - apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80)); - } - break; - case 0xac: case 0xae: - if (dev->type < 4) - fregs[addr] = val & 0xff; - break; - case 0xa3: - if (dev->type == 3) - fregs[addr] = val & 0x01; - break; - case 0xa4: - if (dev->type < 4) { - fregs[addr] = val & 0xfb; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | fregs[addr]; - } - break; - case 0xa5: - if (dev->type < 4) { - fregs[addr] = val & 0xff; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (fregs[addr] << 8); - } - break; - case 0xa6: - if (dev->type < 4) { - fregs[addr] = val & 0xff; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xff00ffff) | (fregs[addr] << 16); - } - break; - case 0xa7: - if (dev->type == 3) - fregs[addr] = val & 0xef; - else if (dev->type < 3) - fregs[addr] = val; - if (dev->type < 4) - cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (fregs[addr] << 24); - break; - case 0xa8: - if (dev->type < 3) { - fregs[addr] = val & 0xff; - cpu_fast_off_val = val; - cpu_fast_off_count = val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - } - break; - case 0xaa: - if (dev->type < 4) - fregs[addr] &= val; - break; - case 0xab: - if (dev->type == 3) - fregs[addr] &= (val & 0x01); - else if (dev->type < 3) - fregs[addr] = val; - break; - case 0xb0: - if (dev->type == 4) - fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73); - else if (dev->type == 5) - fregs[addr] = val & 0x7f; + for (i = 0; i < 4; i++) + ddma_update_io_mapping(dev->ddma, (addr & 4) + i, fregs[addr & 0xfe] + (i << 4), fregs[addr | 0x01], (base != 0x0000)); + } + break; + case 0xa0: + if (dev->type < 4) { + fregs[addr] = val & 0x1f; + apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(fregs[0xa2] & 0x80)); + switch ((val & 0x18) >> 3) { + case 0x00: + dev->fast_off_period = PCICLK * 32768.0 * 60000.0; + break; + case 0x01: + default: + dev->fast_off_period = 0.0; + break; + case 0x02: + dev->fast_off_period = PCICLK; + break; + case 0x03: + dev->fast_off_period = PCICLK * 32768.0; + break; + } + cpu_fast_off_count = cpu_fast_off_val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + } + break; + case 0xa2: + if (dev->type < 4) { + fregs[addr] = val & 0xff; + apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80)); + } + break; + case 0xac: + case 0xae: + if (dev->type < 4) + fregs[addr] = val & 0xff; + break; + case 0xa3: + if (dev->type == 3) + fregs[addr] = val & 0x01; + break; + case 0xa4: + if (dev->type < 4) { + fregs[addr] = val & 0xfb; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | fregs[addr]; + } + break; + case 0xa5: + if (dev->type < 4) { + fregs[addr] = val & 0xff; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (fregs[addr] << 8); + } + break; + case 0xa6: + if (dev->type < 4) { + fregs[addr] = val & 0xff; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xff00ffff) | (fregs[addr] << 16); + } + break; + case 0xa7: + if (dev->type == 3) + fregs[addr] = val & 0xef; + else if (dev->type < 3) + fregs[addr] = val; + if (dev->type < 4) + cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (fregs[addr] << 24); + break; + case 0xa8: + if (dev->type < 3) { + fregs[addr] = val & 0xff; + cpu_fast_off_val = val; + cpu_fast_off_count = val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + } + break; + case 0xaa: + if (dev->type < 4) + fregs[addr] &= val; + break; + case 0xab: + if (dev->type == 3) + fregs[addr] &= (val & 0x01); + else if (dev->type < 3) + fregs[addr] = val; + break; + case 0xb0: + if (dev->type == 4) + fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73); + else if (dev->type == 5) + fregs[addr] = val & 0x7f; - if (dev->type >= 4) - alt_access = !!(val & 0x20); - break; - case 0xb1: - if (dev->type > 3) - fregs[addr] = val & 0xdf; - break; - case 0xb2: - if (dev->type > 3) - fregs[addr] = val; - break; - case 0xb3: - if (dev->type > 3) - fregs[addr] = val & 0xfb; - break; - case 0xcb: - if (dev->type > 3) { - fregs[addr] = val & 0x3d; + if (dev->type >= 4) + alt_access = !!(val & 0x20); + break; + case 0xb1: + if (dev->type > 3) + fregs[addr] = val & 0xdf; + break; + case 0xb2: + if (dev->type > 3) + fregs[addr] = val; + break; + case 0xb3: + if (dev->type > 3) + fregs[addr] = val & 0xfb; + break; + case 0xcb: + if (dev->type > 3) { + fregs[addr] = val & 0x3d; - nvr_update_io_mapping(dev); + nvr_update_io_mapping(dev); - nvr_wp_set(!!(val & 0x08), 0, dev->nvr); - nvr_wp_set(!!(val & 0x10), 1, dev->nvr); - } - break; - case 0xd4: - if ((dev->type > 4) && !(fregs[addr] & 0x01)) { - fregs[addr] = val & 0xf1; - nvr_update_io_mapping(dev); - } - break; - case 0xd5: - if ((dev->type > 4) && !(fregs[0xd4] & 0x01)) { - fregs[addr] = val & 0xff; - nvr_update_io_mapping(dev); - } - break; - case 0xe0: - if (dev->type > 4) - fregs[addr] = val & 0xe7; - break; - case 0xe1: case 0xe4: case 0xe5: case 0xe6: case 0xe7: - case 0xe8: case 0xe9: case 0xea: case 0xeb: - if (dev->type > 4) { - fregs[addr] = val; - if ((dev->type == 5) && (addr == 0xe1)) { - smsc_ide_irqs(dev); - port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x40)); - } - } - break; - } else if (func == 1) switch(addr) { /* IDE */ - case 0x04: - fregs[0x04] = (val & 5); - if (dev->type <= 3) - fregs[0x04] |= 0x02; - piix_ide_handlers(dev, 0x03); - piix_ide_bm_handlers(dev); - break; - case 0x07: - fregs[0x07] &= ~(val & 0x38); - break; - case 0x09: - if (dev->type == 5) { - fregs[0x09] = (fregs[0x09] & 0xfa) | (val & 0x05); - piix_ide_handlers(dev, 0x03); - smsc_ide_irqs(dev); - } - break; - case 0x0d: - fregs[0x0d] = val & 0xf0; - break; - case 0x10: - if (dev->type == 5) { - fregs[0x10] = (val & 0xf8) | 1; - piix_ide_handlers(dev, 0x01); - } - break; - case 0x11: - if (dev->type == 5) { - fregs[0x11] = val; - piix_ide_handlers(dev, 0x01); - } - break; - case 0x14: - if (dev->type == 5) { - fregs[0x14] = (val & 0xfc) | 1; - piix_ide_handlers(dev, 0x01); - } - break; - case 0x15: - if (dev->type == 5) { - fregs[0x15] = val; - piix_ide_handlers(dev, 0x01); - } - break; - case 0x18: - if (dev->type == 5) { - fregs[0x18] = (val & 0xf8) | 1; - piix_ide_handlers(dev, 0x02); - } - break; - case 0x19: - if (dev->type == 5) { - fregs[0x19] = val; - piix_ide_handlers(dev, 0x02); - } - break; - case 0x1c: - if (dev->type == 5) { - fregs[0x1c] = (val & 0xfc) | 1; - piix_ide_handlers(dev, 0x02); - } - break; - case 0x1d: - if (dev->type == 5) { - fregs[0x1d] = val; - piix_ide_handlers(dev, 0x02); - } - break; - case 0x20: - fregs[0x20] = (val & 0xf0) | 1; - piix_ide_bm_handlers(dev); - break; - case 0x21: - fregs[0x21] = val; - piix_ide_bm_handlers(dev); - break; - case 0x3c: - if (dev->type == 5) - fregs[0x3c] = val; - break; - case 0x3d: - if (dev->type == 5) - fregs[0x3d] = val; - break; - case 0x40: case 0x42: - fregs[addr] = val; - break; - case 0x41: case 0x43: - fregs[addr] = val & ((dev->type > 1) ? 0xf3 : 0xb3); - piix_ide_handlers(dev, 1 << !!(addr & 0x02)); - break; - case 0x44: - if (dev->type > 1) - fregs[0x44] = val; - break; - case 0x45: - if (dev->type > 4) - fregs[0x45] = val; - break; - case 0x46: - if (dev->type > 4) - fregs[0x46] = val & 0x03; - break; - case 0x48: - if (dev->type > 3) - fregs[0x48] = val & 0x0f; - break; - case 0x4a: case 0x4b: - if (dev->type > 3) - fregs[addr] = val & 0x33; - break; - case 0x5c: case 0x5d: - if (dev->type > 4) - fregs[addr] = val; - break; - default: - break; - } else if (func == 2) switch(addr) { /* USB */ - case 0x04: - if (dev->type > 4) { - fregs[0x04] = (val & 7); - ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM); - } else { - fregs[0x04] = (val & 5); - uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); - } - break; - case 0x07: - if (dev->type > 4) { - if (val & 0x80) - fregs[0x07] &= 0x7f; - if (val & 0x40) - fregs[0x07] &= 0xbf; - } - if (val & 0x20) - fregs[0x07] &= 0xdf; - if (val & 0x10) - fregs[0x07] &= 0xef; - if (val & 0x08) - fregs[0x07] &= 0xf7; - break; - case 0x0c: - if (dev->type > 4) - fregs[0x0c] = val; - break; - case 0x0d: - if (dev->type < 5) - fregs[0x0d] = val & 0xf0; - break; - case 0x11: - if (dev->type > 4) { - fregs[addr] = val & 0xf0; - ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/); - } - break; - case 0x12: case 0x13: - if (dev->type > 4) { - fregs[addr] = val; - ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/); - } - break; - case 0x20: - if (dev->type < 5) { - fregs[0x20] = (val & 0xe0) | 1; - uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); - } - break; - case 0x21: - if (dev->type < 5) { - fregs[0x21] = val; - uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); - } - break; - case 0x3c: - fregs[0x3c] = val; - break; - case 0x3e: case 0x3f: - case 0x40: case 0x41: case 0x43: - if (dev->type > 4) - fregs[addr] = val; - break; - case 0x42: - if (dev->type > 4) - fregs[addr] = val & 0x8f; - break; - case 0x44: case 0x45: - if (dev->type > 4) - fregs[addr] = val & 0x01; - break; - case 0x6a: - if (dev->type <= 4) - fregs[0x6a] = val & 0x01; - break; - case 0xc0: - if (dev->type <= 4) - fregs[0xc0] = (fregs[0xc0] & ~(val & 0xbf)) | (val & 0x20); - break; - case 0xc1: - if (dev->type <= 4) - fregs[0xc1] &= ~val; - break; - case 0xff: - if (dev->type == 4) { - fregs[addr] = val & 0x10; - nvr_read_addr_set(!!(val & 0x10), dev->nvr); - } - break; - } else if (func == 3) switch(addr) { /* Power Management */ - case 0x04: - fregs[0x04] = (val & 0x01); - smbus_update_io_mapping(dev); - apm_set_do_smi(dev->acpi->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01)); - break; - case 0x07: - if (val & 0x08) - fregs[0x07] &= 0xf7; - break; + nvr_wp_set(!!(val & 0x08), 0, dev->nvr); + nvr_wp_set(!!(val & 0x10), 1, dev->nvr); + } + break; + case 0xd4: + if ((dev->type > 4) && !(fregs[addr] & 0x01)) { + fregs[addr] = val & 0xf1; + nvr_update_io_mapping(dev); + } + break; + case 0xd5: + if ((dev->type > 4) && !(fregs[0xd4] & 0x01)) { + fregs[addr] = val & 0xff; + nvr_update_io_mapping(dev); + } + break; + case 0xe0: + if (dev->type > 4) + fregs[addr] = val & 0xe7; + break; + case 0xe1: + case 0xe4: + case 0xe5: + case 0xe6: + case 0xe7: + case 0xe8: + case 0xe9: + case 0xea: + case 0xeb: + if (dev->type > 4) { + fregs[addr] = val; + if ((dev->type == 5) && (addr == 0xe1)) { + smsc_ide_irqs(dev); + port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x40)); + } + } + break; + } + else if (func == 1) + switch (addr) { /* IDE */ + case 0x04: + fregs[0x04] = (val & 5); + if (dev->type <= 3) + fregs[0x04] |= 0x02; + piix_ide_handlers(dev, 0x03); + piix_ide_bm_handlers(dev); + break; + case 0x07: + fregs[0x07] &= ~(val & 0x38); + break; + case 0x09: + if (dev->type == 5) { + fregs[0x09] = (fregs[0x09] & 0xfa) | (val & 0x05); + piix_ide_handlers(dev, 0x03); + smsc_ide_irqs(dev); + } + break; + case 0x0d: + fregs[0x0d] = val & 0xf0; + break; + case 0x10: + if (dev->type == 5) { + fregs[0x10] = (val & 0xf8) | 1; + piix_ide_handlers(dev, 0x01); + } + break; + case 0x11: + if (dev->type == 5) { + fregs[0x11] = val; + piix_ide_handlers(dev, 0x01); + } + break; + case 0x14: + if (dev->type == 5) { + fregs[0x14] = (val & 0xfc) | 1; + piix_ide_handlers(dev, 0x01); + } + break; + case 0x15: + if (dev->type == 5) { + fregs[0x15] = val; + piix_ide_handlers(dev, 0x01); + } + break; + case 0x18: + if (dev->type == 5) { + fregs[0x18] = (val & 0xf8) | 1; + piix_ide_handlers(dev, 0x02); + } + break; + case 0x19: + if (dev->type == 5) { + fregs[0x19] = val; + piix_ide_handlers(dev, 0x02); + } + break; + case 0x1c: + if (dev->type == 5) { + fregs[0x1c] = (val & 0xfc) | 1; + piix_ide_handlers(dev, 0x02); + } + break; + case 0x1d: + if (dev->type == 5) { + fregs[0x1d] = val; + piix_ide_handlers(dev, 0x02); + } + break; + case 0x20: + fregs[0x20] = (val & 0xf0) | 1; + piix_ide_bm_handlers(dev); + break; + case 0x21: + fregs[0x21] = val; + piix_ide_bm_handlers(dev); + break; + case 0x3c: + if (dev->type == 5) + fregs[0x3c] = val; + break; + case 0x3d: + if (dev->type == 5) + fregs[0x3d] = val; + break; + case 0x40: + case 0x42: + fregs[addr] = val; + break; + case 0x41: + case 0x43: + fregs[addr] = val & ((dev->type > 1) ? 0xf3 : 0xb3); + piix_ide_handlers(dev, 1 << !!(addr & 0x02)); + break; + case 0x44: + if (dev->type > 1) + fregs[0x44] = val; + break; + case 0x45: + if (dev->type > 4) + fregs[0x45] = val; + break; + case 0x46: + if (dev->type > 4) + fregs[0x46] = val & 0x03; + break; + case 0x48: + if (dev->type > 3) + fregs[0x48] = val & 0x0f; + break; + case 0x4a: + case 0x4b: + if (dev->type > 3) + fregs[addr] = val & 0x33; + break; + case 0x5c: + case 0x5d: + if (dev->type > 4) + fregs[addr] = val; + break; + default: + break; + } + else if (func == 2) + switch (addr) { /* USB */ + case 0x04: + if (dev->type > 4) { + fregs[0x04] = (val & 7); + ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM); + } else { + fregs[0x04] = (val & 5); + uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); + } + break; + case 0x07: + if (dev->type > 4) { + if (val & 0x80) + fregs[0x07] &= 0x7f; + if (val & 0x40) + fregs[0x07] &= 0xbf; + } + if (val & 0x20) + fregs[0x07] &= 0xdf; + if (val & 0x10) + fregs[0x07] &= 0xef; + if (val & 0x08) + fregs[0x07] &= 0xf7; + break; + case 0x0c: + if (dev->type > 4) + fregs[0x0c] = val; + break; + case 0x0d: + if (dev->type < 5) + fregs[0x0d] = val & 0xf0; + break; + case 0x11: + if (dev->type > 4) { + fregs[addr] = val & 0xf0; + ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/); + } + break; + case 0x12: + case 0x13: + if (dev->type > 4) { + fregs[addr] = val; + ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/); + } + break; + case 0x20: + if (dev->type < 5) { + fregs[0x20] = (val & 0xe0) | 1; + uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); + } + break; + case 0x21: + if (dev->type < 5) { + fregs[0x21] = val; + uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO); + } + break; + case 0x3c: + fregs[0x3c] = val; + break; + case 0x3e: + case 0x3f: + case 0x40: + case 0x41: + case 0x43: + if (dev->type > 4) + fregs[addr] = val; + break; + case 0x42: + if (dev->type > 4) + fregs[addr] = val & 0x8f; + break; + case 0x44: + case 0x45: + if (dev->type > 4) + fregs[addr] = val & 0x01; + break; + case 0x6a: + if (dev->type <= 4) + fregs[0x6a] = val & 0x01; + break; + case 0xc0: + if (dev->type <= 4) + fregs[0xc0] = (fregs[0xc0] & ~(val & 0xbf)) | (val & 0x20); + break; + case 0xc1: + if (dev->type <= 4) + fregs[0xc1] &= ~val; + break; + case 0xff: + if (dev->type == 4) { + fregs[addr] = val & 0x10; + nvr_read_addr_set(!!(val & 0x10), dev->nvr); + } + break; + } + else if (func == 3) + switch (addr) { /* Power Management */ + case 0x04: + fregs[0x04] = (val & 0x01); + smbus_update_io_mapping(dev); + apm_set_do_smi(dev->acpi->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01)); + break; + case 0x07: + if (val & 0x08) + fregs[0x07] &= 0xf7; + break; #if 0 case 0x3c: fregs[0x3c] = val; break; #endif - case 0x40: - fregs[0x40] = (val & 0xc0) | 1; - dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0); - acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); - break; - case 0x41: - fregs[0x41] = val; - dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0); - acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); - break; - case 0x44: case 0x45: case 0x46: case 0x47: - case 0x48: case 0x49: - case 0x4c: case 0x4d: case 0x4e: - case 0x54: case 0x55: case 0x56: case 0x57: - case 0x59: case 0x5a: - case 0x5c: case 0x5d: case 0x5e: case 0x5f: - case 0x60: case 0x61: case 0x62: - case 0x64: case 0x65: - case 0x67: case 0x68: case 0x69: - case 0x6c: case 0x6e: case 0x6f: - case 0x70: case 0x71: - case 0x74: case 0x77: case 0x78: case 0x79: - case 0x7c: case 0x7d: - case 0xd3: case 0xd4: - case 0xd5: - fregs[addr] = val; - if ((addr == 0x5c) || (addr == 0x60) || (addr == 0x61) || (addr == 0x62) || - (addr == 0x64) || (addr == 0x65) || (addr == 0x68) || (addr == 0x69) || - (addr == 0x70) || (addr == 0x71)) - piix_trap_update(dev); - break; - case 0x4a: - fregs[addr] = val & 0x73; - break; - case 0x4b: - fregs[addr] = val & 0x01; - break; - case 0x4f: case 0x80: case 0xd2: - fregs[addr] = val & 0x0f; - if (addr == 0x80) - acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); - else if (addr == 0xd2) - smbus_update_io_mapping(dev); - break; - case 0x50: - fregs[addr] = val & 0x3f; - break; - case 0x51: - fregs[addr] = val & 0x58; - piix_trap_update(dev); - break; - case 0x52: - fregs[addr] = val & 0x7f; - piix_trap_update(dev); - break; - case 0x58: - fregs[addr] = val & 0x77; - break; - case 0x5b: - fregs[addr] = val & 0x03; - apm_set_do_smi(dev->acpi->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01)); - break; - case 0x63: - fregs[addr] = val & 0xf7; - piix_trap_update(dev); - break; - case 0x66: - fregs[addr] = val & 0xef; - piix_trap_update(dev); - break; - case 0x6a: case 0x72: case 0x7a: case 0x7e: - fregs[addr] = val & 0x1f; - if ((addr == 0x6a) || (addr == 0x72)) - piix_trap_update(dev); - break; - case 0x6d: case 0x75: - fregs[addr] = val & 0x80; - break; - case 0x90: - fregs[0x90] = (val & 0xf0) | 1; - smbus_update_io_mapping(dev); - break; - case 0x91: - fregs[0x91] = val; - smbus_update_io_mapping(dev); - break; - } + case 0x40: + fregs[0x40] = (val & 0xc0) | 1; + dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0); + acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); + break; + case 0x41: + fregs[0x41] = val; + dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0); + acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); + break; + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x59: + case 0x5a: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + case 0x60: + case 0x61: + case 0x62: + case 0x64: + case 0x65: + case 0x67: + case 0x68: + case 0x69: + case 0x6c: + case 0x6e: + case 0x6f: + case 0x70: + case 0x71: + case 0x74: + case 0x77: + case 0x78: + case 0x79: + case 0x7c: + case 0x7d: + case 0xd3: + case 0xd4: + case 0xd5: + fregs[addr] = val; + if ((addr == 0x5c) || (addr == 0x60) || (addr == 0x61) || (addr == 0x62) || (addr == 0x64) || (addr == 0x65) || (addr == 0x68) || (addr == 0x69) || (addr == 0x70) || (addr == 0x71)) + piix_trap_update(dev); + break; + case 0x4a: + fregs[addr] = val & 0x73; + break; + case 0x4b: + fregs[addr] = val & 0x01; + break; + case 0x4f: + case 0x80: + case 0xd2: + fregs[addr] = val & 0x0f; + if (addr == 0x80) + acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01)); + else if (addr == 0xd2) + smbus_update_io_mapping(dev); + break; + case 0x50: + fregs[addr] = val & 0x3f; + break; + case 0x51: + fregs[addr] = val & 0x58; + piix_trap_update(dev); + break; + case 0x52: + fregs[addr] = val & 0x7f; + piix_trap_update(dev); + break; + case 0x58: + fregs[addr] = val & 0x77; + break; + case 0x5b: + fregs[addr] = val & 0x03; + apm_set_do_smi(dev->acpi->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01)); + break; + case 0x63: + fregs[addr] = val & 0xf7; + piix_trap_update(dev); + break; + case 0x66: + fregs[addr] = val & 0xef; + piix_trap_update(dev); + break; + case 0x6a: + case 0x72: + case 0x7a: + case 0x7e: + fregs[addr] = val & 0x1f; + if ((addr == 0x6a) || (addr == 0x72)) + piix_trap_update(dev); + break; + case 0x6d: + case 0x75: + fregs[addr] = val & 0x80; + break; + case 0x90: + fregs[0x90] = (val & 0xf0) | 1; + smbus_update_io_mapping(dev); + break; + case 0x91: + fregs[0x91] = val; + smbus_update_io_mapping(dev); + break; + } } - static uint8_t piix_read(int func, int addr, void *priv) { @@ -1067,38 +1153,36 @@ piix_read(int func, int addr, void *priv) uint8_t ret = 0xff, *fregs; if ((dev->type == 3) && (func == 2) && (dev->max_func == 1) && (addr >= 0x40)) - ret = 0x00; + ret = 0x00; /* Return on unsupported function. */ if ((func <= dev->max_func) || ((func == 1) && (dev->max_func == 0))) { - fregs = (uint8_t *) dev->regs[func]; - ret = fregs[addr]; - if ((func == 0) && (addr == 0x4e)) - ret |= keyboard_at_get_mouse_scan(); - else if ((func == 2) && (addr == 0xff)) - ret |= 0xef; + fregs = (uint8_t *) dev->regs[func]; + ret = fregs[addr]; + if ((func == 0) && (addr == 0x4e)) + ret |= keyboard_at_get_mouse_scan(); + else if ((func == 2) && (addr == 0xff)) + ret |= 0xef; - piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr); + piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr); } return ret; } - static void board_write(uint16_t port, uint8_t val, void *priv) { piix_t *dev = (piix_t *) priv; if (port == 0x0078) - dev->board_config[0] = val; + dev->board_config[0] = val; else if (port == 0x00e0) - dev->cur_readout_reg = val; + dev->cur_readout_reg = val; else if (port == 0x00e1) - dev->readout_regs[dev->cur_readout_reg] = val; + dev->readout_regs[dev->cur_readout_reg] = val; } - static uint8_t board_read(uint16_t port, void *priv) { @@ -1106,22 +1190,21 @@ board_read(uint16_t port, void *priv) uint8_t ret = 0x64; if (port == 0x0078) - ret = dev->board_config[0]; + ret = dev->board_config[0]; else if (port == 0x0079) - ret = dev->board_config[1]; + ret = dev->board_config[1]; else if (port == 0x00e0) - ret = dev->cur_readout_reg; + ret = dev->cur_readout_reg; else if (port == 0x00e1) - ret = dev->readout_regs[dev->cur_readout_reg]; + ret = dev->readout_regs[dev->cur_readout_reg]; return ret; } - static void piix_reset_hard(piix_t *dev) { - int i; + int i; uint8_t *fregs; uint16_t old_base = (dev->regs[1][0x20] & 0xf0) | (dev->regs[1][0x21] << 8); @@ -1130,17 +1213,17 @@ piix_reset_hard(piix_t *dev) sff_bus_master_reset(dev->bm[1], old_base + 8); if (dev->type >= 4) { - sff_set_slot(dev->bm[0], dev->pci_slot); - sff_set_irq_pin(dev->bm[0], PCI_INTA); - sff_set_irq_line(dev->bm[0], 14); - sff_set_irq_mode(dev->bm[0], 0, 0); - sff_set_irq_mode(dev->bm[0], 1, 0); + sff_set_slot(dev->bm[0], dev->pci_slot); + sff_set_irq_pin(dev->bm[0], PCI_INTA); + sff_set_irq_line(dev->bm[0], 14); + sff_set_irq_mode(dev->bm[0], 0, 0); + sff_set_irq_mode(dev->bm[0], 1, 0); - sff_set_slot(dev->bm[1], dev->pci_slot); - sff_set_irq_pin(dev->bm[1], PCI_INTA); - sff_set_irq_line(dev->bm[1], 14); - sff_set_irq_mode(dev->bm[1], 0, 0); - sff_set_irq_mode(dev->bm[1], 1, 0); + sff_set_slot(dev->bm[1], dev->pci_slot); + sff_set_irq_pin(dev->bm[1], PCI_INTA); + sff_set_irq_line(dev->bm[1], 14); + sff_set_irq_mode(dev->bm[1], 0, 0); + sff_set_irq_mode(dev->bm[1], 1, 0); } #ifdef ENABLE_PIIX_LOG @@ -1150,70 +1233,74 @@ piix_reset_hard(piix_t *dev) ide_sec_disable(); if (dev->type > 3) { - nvr_at_handler(0, 0x0072, dev->nvr); - nvr_wp_set(0, 0, dev->nvr); - nvr_wp_set(0, 1, dev->nvr); - nvr_at_handler(1, 0x0074, dev->nvr); - dev->nvr_io_base = 0x0070; + nvr_at_handler(0, 0x0072, dev->nvr); + nvr_wp_set(0, 0, dev->nvr); + nvr_wp_set(0, 1, dev->nvr); + nvr_at_handler(1, 0x0074, dev->nvr); + dev->nvr_io_base = 0x0070; } /* Clear all 4 functions' arrays and set their vendor and device ID's. */ for (i = 0; i < 4; i++) { - memset(dev->regs[i], 0, 256); - if (dev->type == 5) { - dev->regs[i][0x00] = 0x55; dev->regs[i][0x01] = 0x10; /* SMSC/EFAR */ - if (i == 1) { /* IDE controller is 9130, breaking convention */ - dev->regs[i][0x02] = 0x30; - dev->regs[i][0x03] = 0x91; - } else { - dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift); - dev->regs[i][0x03] = (dev->func0_id >> 8); - } - } else { - dev->regs[i][0x00] = 0x86; dev->regs[i][0x01] = 0x80; /* Intel */ - dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift); - dev->regs[i][0x03] = (dev->func0_id >> 8); - } + memset(dev->regs[i], 0, 256); + if (dev->type == 5) { + dev->regs[i][0x00] = 0x55; + dev->regs[i][0x01] = 0x10; /* SMSC/EFAR */ + if (i == 1) { /* IDE controller is 9130, breaking convention */ + dev->regs[i][0x02] = 0x30; + dev->regs[i][0x03] = 0x91; + } else { + dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift); + dev->regs[i][0x03] = (dev->func0_id >> 8); + } + } else { + dev->regs[i][0x00] = 0x86; + dev->regs[i][0x01] = 0x80; /* Intel */ + dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift); + dev->regs[i][0x03] = (dev->func0_id >> 8); + } } /* Function 0: PCI to ISA Bridge */ fregs = (uint8_t *) dev->regs[0]; piix_log("PIIX Function 0: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); fregs[0x04] = 0x07; - fregs[0x06] = 0x80; fregs[0x07] = 0x02; + fregs[0x06] = 0x80; + fregs[0x07] = 0x02; if (dev->type == 4) - fregs[0x08] = (dev->rev & 0x08) ? 0x02 : (dev->rev & 0x07); + fregs[0x08] = (dev->rev & 0x08) ? 0x02 : (dev->rev & 0x07); else - fregs[0x08] = dev->rev; + fregs[0x08] = dev->rev; fregs[0x09] = 0x00; - fregs[0x0a] = 0x01; fregs[0x0b] = 0x06; + fregs[0x0a] = 0x01; + fregs[0x0b] = 0x06; fregs[0x0e] = ((dev->type > 1) || (dev->rev != 2)) ? 0x80 : 0x00; fregs[0x4c] = 0x4d; fregs[0x4e] = 0x03; fregs[0x60] = fregs[0x61] = fregs[0x62] = fregs[0x63] = 0x80; - fregs[0x64] = (dev->type > 3) ? 0x10 : 0x00; - fregs[0x69] = 0x02; + fregs[0x64] = (dev->type > 3) ? 0x10 : 0x00; + fregs[0x69] = 0x02; if ((dev->type == 1) && (dev->rev != 2)) - fregs[0x6a] = 0x04; + fregs[0x6a] = 0x04; else if (dev->type == 3) - fregs[0x6a] = 0x10; + fregs[0x6a] = 0x10; fregs[0x70] = (dev->type < 4) ? 0x80 : 0x00; fregs[0x71] = (dev->type < 3) ? 0x80 : 0x00; if (dev->type <= 4) { - fregs[0x76] = fregs[0x77] = (dev->type > 1) ? 0x04 : 0x0c; + fregs[0x76] = fregs[0x77] = (dev->type > 1) ? 0x04 : 0x0c; } fregs[0x78] = (dev->type < 4) ? 0x02 : 0x00; fregs[0xa0] = (dev->type < 4) ? 0x08 : 0x00; fregs[0xa8] = (dev->type < 4) ? 0x0f : 0x00; if (dev->type > 3) - fregs[0xb0] = (is_pentium) ? 0x00 : 0x04; + fregs[0xb0] = (is_pentium) ? 0x00 : 0x04; fregs[0xcb] = (dev->type > 3) ? 0x21 : 0x00; if (dev->type > 4) { - fregs[0xd4] = 0x70; - fregs[0xe1] = 0x40; - fregs[0xe6] = 0x12; - fregs[0xe8] = 0x02; - fregs[0xea] = 0x12; + fregs[0xd4] = 0x70; + fregs[0xe1] = 0x40; + fregs[0xe6] = 0x12; + fregs[0xe8] = 0x02; + fregs[0xea] = 0x12; } dev->max_func = 0; @@ -1221,78 +1308,90 @@ piix_reset_hard(piix_t *dev) fregs = (uint8_t *) dev->regs[1]; piix_log("PIIX Function 1: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); if (dev->type < 4) - fregs[0x04] = 0x02; - fregs[0x06] = 0x80; fregs[0x07] = 0x02; + fregs[0x04] = 0x02; + fregs[0x06] = 0x80; + fregs[0x07] = 0x02; if (dev->type == 4) - fregs[0x08] = dev->rev & 0x07; + fregs[0x08] = dev->rev & 0x07; else - fregs[0x08] = dev->rev; + fregs[0x08] = dev->rev; if (dev->type == 5) - fregs[0x09] = 0x8a; + fregs[0x09] = 0x8a; else - fregs[0x09] = 0x80; - fregs[0x0a] = 0x01; fregs[0x0b] = 0x01; + fregs[0x09] = 0x80; + fregs[0x0a] = 0x01; + fregs[0x0b] = 0x01; if (dev->type == 5) { - fregs[0x10] = 0xf1; fregs[0x11] = 0x01; - fregs[0x14] = 0xf5; fregs[0x15] = 0x03; - fregs[0x18] = 0x71; fregs[0x19] = 0x01; - fregs[0x1c] = 0x75; fregs[0x1d] = 0x03; + fregs[0x10] = 0xf1; + fregs[0x11] = 0x01; + fregs[0x14] = 0xf5; + fregs[0x15] = 0x03; + fregs[0x18] = 0x71; + fregs[0x19] = 0x01; + fregs[0x1c] = 0x75; + fregs[0x1d] = 0x03; } fregs[0x20] = 0x01; if (dev->type == 5) { - fregs[0x3c] = 0x0e; fregs[0x3d] = 0x01; - fregs[0x45] = 0x55; fregs[0x46] = 0x01; + fregs[0x3c] = 0x0e; + fregs[0x3d] = 0x01; + fregs[0x45] = 0x55; + fregs[0x46] = 0x01; } if ((dev->type == 1) && (dev->rev == 2)) - dev->max_func = 0; /* It starts with IDE disabled, then enables it. */ + dev->max_func = 0; /* It starts with IDE disabled, then enables it. */ else - dev->max_func = 1; + dev->max_func = 1; /* Function 2: USB */ if (dev->type > 1) { - fregs = (uint8_t *) dev->regs[2]; - piix_log("PIIX Function 2: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); - fregs[0x06] = 0x80; fregs[0x07] = 0x02; - if (dev->type == 4) - fregs[0x08] = dev->rev & 0x07; - else if (dev->type < 4) - fregs[0x08] = 0x01; - else - fregs[0x08] = 0x02; - if (dev->type > 4) - fregs[0x09] = 0x10; /* SMSC has OHCI rather than UHCI */ - fregs[0x0a] = 0x03; fregs[0x0b] = 0x0c; - if (dev->type < 5) - fregs[0x20] = 0x01; - fregs[0x3d] = 0x04; - if (dev->type > 4) - fregs[0x60] = (dev->type > 3) ? 0x10 : 0x00; - if (dev->type < 5) { - fregs[0x6a] = (dev->type == 3) ? 0x01 : 0x00; - fregs[0xc1] = 0x20; - fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00; - } - dev->max_func = 2; /* It starts with USB disabled, then enables it. */ + fregs = (uint8_t *) dev->regs[2]; + piix_log("PIIX Function 2: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); + fregs[0x06] = 0x80; + fregs[0x07] = 0x02; + if (dev->type == 4) + fregs[0x08] = dev->rev & 0x07; + else if (dev->type < 4) + fregs[0x08] = 0x01; + else + fregs[0x08] = 0x02; + if (dev->type > 4) + fregs[0x09] = 0x10; /* SMSC has OHCI rather than UHCI */ + fregs[0x0a] = 0x03; + fregs[0x0b] = 0x0c; + if (dev->type < 5) + fregs[0x20] = 0x01; + fregs[0x3d] = 0x04; + if (dev->type > 4) + fregs[0x60] = (dev->type > 3) ? 0x10 : 0x00; + if (dev->type < 5) { + fregs[0x6a] = (dev->type == 3) ? 0x01 : 0x00; + fregs[0xc1] = 0x20; + fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00; + } + dev->max_func = 2; /* It starts with USB disabled, then enables it. */ } /* Function 3: Power Management */ if (dev->type > 3) { - fregs = (uint8_t *) dev->regs[3]; - piix_log("PIIX Function 3: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); - fregs[0x06] = 0x80; fregs[0x07] = 0x02; - if (dev->type > 4) - fregs[0x08] = 0x02; - else - fregs[0x08] = (dev->rev & 0x08) ? 0x02 : 0x01 /*(dev->rev & 0x07)*/; - fregs[0x0a] = 0x80; fregs[0x0b] = 0x06; - /* NOTE: The Specification Update says this should default to 0x00 and be read-only. */ + fregs = (uint8_t *) dev->regs[3]; + piix_log("PIIX Function 3: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); + fregs[0x06] = 0x80; + fregs[0x07] = 0x02; + if (dev->type > 4) + fregs[0x08] = 0x02; + else + fregs[0x08] = (dev->rev & 0x08) ? 0x02 : 0x01 /*(dev->rev & 0x07)*/; + fregs[0x0a] = 0x80; + fregs[0x0b] = 0x06; + /* NOTE: The Specification Update says this should default to 0x00 and be read-only. */ #ifdef WRONG_SPEC - if (dev->type == 4) - fregs[0x3d] = 0x01; + if (dev->type == 4) + fregs[0x3d] = 0x01; #endif - fregs[0x40] = 0x01; - fregs[0x90] = 0x01; - dev->max_func = 3; + fregs[0x40] = 0x01; + fregs[0x90] = 0x01; + dev->max_func = 3; } pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); @@ -1301,27 +1400,25 @@ piix_reset_hard(piix_t *dev) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); if (dev->type < 4) - pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); if (dev->type < 3) - pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); if (dev->type >= 4) - acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f); + acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f); } - static void piix_apm_out(uint16_t port, uint8_t val, void *p) { piix_t *dev = (piix_t *) p; if (dev->apm->do_smi) { - if (dev->type < 4) - dev->regs[0][0xaa] |= 0x80; + if (dev->type < 4) + dev->regs[0][0xaa] |= 0x80; } } - static void piix_fast_off_count(void *priv) { @@ -1331,40 +1428,39 @@ piix_fast_off_count(void *priv) dev->regs[0][0xaa] |= 0x20; } - static void piix_reset(void *p) { - piix_t *dev = (piix_t *)p; + piix_t *dev = (piix_t *) p; if (dev->type > 3) { - piix_write(3, 0x04, 0x00, p); - piix_write(3, 0x5b, 0x00, p); + piix_write(3, 0x04, 0x00, p); + piix_write(3, 0x5b, 0x00, p); } else { - piix_write(0, 0xa0, 0x08, p); - piix_write(0, 0xa2, 0x00, p); - piix_write(0, 0xa4, 0x00, p); - piix_write(0, 0xa5, 0x00, p); - piix_write(0, 0xa6, 0x00, p); - piix_write(0, 0xa7, 0x00, p); - piix_write(0, 0xa8, 0x0f, p); + piix_write(0, 0xa0, 0x08, p); + piix_write(0, 0xa2, 0x00, p); + piix_write(0, 0xa4, 0x00, p); + piix_write(0, 0xa5, 0x00, p); + piix_write(0, 0xa6, 0x00, p); + piix_write(0, 0xa7, 0x00, p); + piix_write(0, 0xa8, 0x0f, p); } if (dev->type == 5) - piix_write(0, 0xe1, 0x40, p); + piix_write(0, 0xe1, 0x40, p); piix_write(1, 0x04, 0x00, p); if (dev->type == 5) { - piix_write(1, 0x09, 0x8a, p); - piix_write(1, 0x10, 0xf1, p); - piix_write(1, 0x11, 0x01, p); - piix_write(1, 0x14, 0xf5, p); - piix_write(1, 0x15, 0x03, p); - piix_write(1, 0x18, 0x71, p); - piix_write(1, 0x19, 0x01, p); - piix_write(1, 0x1c, 0x75, p); - piix_write(1, 0x1d, 0x03, p); + piix_write(1, 0x09, 0x8a, p); + piix_write(1, 0x10, 0xf1, p); + piix_write(1, 0x11, 0x01, p); + piix_write(1, 0x14, 0xf5, p); + piix_write(1, 0x15, 0x03, p); + piix_write(1, 0x18, 0x71, p); + piix_write(1, 0x19, 0x01, p); + piix_write(1, 0x1c, 0x75, p); + piix_write(1, 0x1d, 0x03, p); } else - piix_write(1, 0x09, 0x80, p); + piix_write(1, 0x09, 0x80, p); piix_write(1, 0x20, 0x01, p); piix_write(1, 0x21, 0x00, p); piix_write(1, 0x41, 0x00, p); @@ -1374,83 +1470,81 @@ piix_reset(void *p) ide_sec_disable(); if (dev->type >= 3) { - piix_write(2, 0x04, 0x00, p); - if (dev->type == 5) { - piix_write(2, 0x10, 0x00, p); - piix_write(2, 0x11, 0x00, p); - piix_write(2, 0x12, 0x00, p); - piix_write(2, 0x13, 0x00, p); - } else { - piix_write(2, 0x20, 0x01, p); - piix_write(2, 0x21, 0x00, p); - piix_write(2, 0x22, 0x00, p); - piix_write(2, 0x23, 0x00, p); - } + piix_write(2, 0x04, 0x00, p); + if (dev->type == 5) { + piix_write(2, 0x10, 0x00, p); + piix_write(2, 0x11, 0x00, p); + piix_write(2, 0x12, 0x00, p); + piix_write(2, 0x13, 0x00, p); + } else { + piix_write(2, 0x20, 0x01, p); + piix_write(2, 0x21, 0x00, p); + piix_write(2, 0x22, 0x00, p); + piix_write(2, 0x23, 0x00, p); + } } if (dev->type >= 4) { - piix_write(0, 0xb0, (is_pentium) ? 0x00 : 0x04, p); - piix_write(3, 0x40, 0x01, p); - piix_write(3, 0x41, 0x00, p); - piix_write(3, 0x5b, 0x00, p); - piix_write(3, 0x80, 0x00, p); - piix_write(3, 0x90, 0x01, p); - piix_write(3, 0x91, 0x00, p); - piix_write(3, 0xd2, 0x00, p); + piix_write(0, 0xb0, (is_pentium) ? 0x00 : 0x04, p); + piix_write(3, 0x40, 0x01, p); + piix_write(3, 0x41, 0x00, p); + piix_write(3, 0x5b, 0x00, p); + piix_write(3, 0x80, 0x00, p); + piix_write(3, 0x90, 0x01, p); + piix_write(3, 0x91, 0x00, p); + piix_write(3, 0xd2, 0x00, p); } sff_set_irq_mode(dev->bm[0], 0, 0); sff_set_irq_mode(dev->bm[1], 0, 0); if (dev->no_mirq0 || (dev->type >= 4)) { - sff_set_irq_mode(dev->bm[0], 1, 0); - sff_set_irq_mode(dev->bm[1], 1, 0); + sff_set_irq_mode(dev->bm[0], 1, 0); + sff_set_irq_mode(dev->bm[1], 1, 0); } else { - sff_set_irq_mode(dev->bm[0], 1, 2); - sff_set_irq_mode(dev->bm[1], 1, 2); + sff_set_irq_mode(dev->bm[0], 1, 2); + sff_set_irq_mode(dev->bm[1], 1, 2); } } - static void piix_close(void *priv) { piix_t *dev = (piix_t *) priv; for (int i = 0; i < (sizeof(dev->io_traps) / sizeof(dev->io_traps[0])); i++) - io_trap_remove(dev->io_traps[i].trap); + io_trap_remove(dev->io_traps[i].trap); free(dev); } - static void piix_speed_changed(void *priv) { piix_t *dev = (piix_t *) priv; if (!dev) - return; + return; int te = timer_is_enabled(&dev->fast_off_timer); timer_stop(&dev->fast_off_timer); if (te) - timer_on_auto(&dev->fast_off_timer, ((double) cpu_fast_off_val + 1) * dev->fast_off_period); + timer_on_auto(&dev->fast_off_timer, ((double) cpu_fast_off_val + 1) * dev->fast_off_period); } - static void -*piix_init(const device_t *info) + * + piix_init(const device_t *info) { piix_t *dev = (piix_t *) malloc(sizeof(piix_t)); memset(dev, 0, sizeof(piix_t)); dev->type = info->local & 0x0f; /* If (dev->type == 4) and (dev->rev & 0x08), then this is PIIX4E. */ - dev->rev = (info->local >> 4) & 0x0f; + dev->rev = (info->local >> 4) & 0x0f; dev->func_shift = (info->local >> 8) & 0x0f; - dev->no_mirq0 = (info->local >> 12) & 0x0f; - dev->func0_id = info->local >> 16; + dev->no_mirq0 = (info->local >> 12) & 0x0f; + dev->func0_id = info->local >> 16; dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev); piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot); @@ -1459,55 +1553,55 @@ static void dev->bm[0] = device_add_inst(&sff8038i_device, 1); dev->bm[1] = device_add_inst(&sff8038i_device, 2); if ((dev->type == 1) && (dev->rev == 2)) { - /* PIIX rev. 02 has faulty bus mastering on real hardware, - so set our devices IDE devices to force ATA-3 (no DMA). */ - ide_board_set_force_ata3(0, 1); - ide_board_set_force_ata3(1, 1); + /* PIIX rev. 02 has faulty bus mastering on real hardware, + so set our devices IDE devices to force ATA-3 (no DMA). */ + ide_board_set_force_ata3(0, 1); + ide_board_set_force_ata3(1, 1); } sff_set_irq_mode(dev->bm[0], 0, 0); sff_set_irq_mode(dev->bm[1], 0, 0); if (dev->no_mirq0 || (dev->type >= 4)) { - sff_set_irq_mode(dev->bm[0], 1, 0); - sff_set_irq_mode(dev->bm[1], 1, 0); + sff_set_irq_mode(dev->bm[0], 1, 0); + sff_set_irq_mode(dev->bm[1], 1, 0); } else { - sff_set_irq_mode(dev->bm[0], 1, 2); - sff_set_irq_mode(dev->bm[1], 1, 2); + sff_set_irq_mode(dev->bm[0], 1, 2); + sff_set_irq_mode(dev->bm[1], 1, 2); } if (dev->type >= 3) - dev->usb = device_add(&usb_device); + dev->usb = device_add(&usb_device); if (dev->type > 3) { - dev->nvr = device_add(&piix4_nvr_device); - dev->smbus = device_add(&piix4_smbus_device); + dev->nvr = device_add(&piix4_nvr_device); + dev->smbus = device_add(&piix4_smbus_device); - dev->acpi = device_add(&acpi_intel_device); - acpi_set_slot(dev->acpi, dev->pci_slot); - acpi_set_nvr(dev->acpi, dev->nvr); - acpi_set_gpireg2_default(dev->acpi, (dev->type > 4) ? 0xf1 : 0xdd); - acpi_set_trap_update(dev->acpi, piix_trap_update, dev); + dev->acpi = device_add(&acpi_intel_device); + acpi_set_slot(dev->acpi, dev->pci_slot); + acpi_set_nvr(dev->acpi, dev->nvr); + acpi_set_gpireg2_default(dev->acpi, (dev->type > 4) ? 0xf1 : 0xdd); + acpi_set_trap_update(dev->acpi, piix_trap_update, dev); - dev->ddma = device_add(&ddma_device); + dev->ddma = device_add(&ddma_device); } else - timer_add(&dev->fast_off_timer, piix_fast_off_count, dev, 0); + timer_add(&dev->fast_off_timer, piix_fast_off_count, dev, 0); piix_reset_hard(dev); piix_log("Maximum function: %i\n", dev->max_func); cpu_fast_off_flags = 0x00000000; if (dev->type < 4) { - cpu_fast_off_val = dev->regs[0][0xa8]; - cpu_fast_off_count = cpu_fast_off_val + 1; - cpu_register_fast_off_handler(&dev->fast_off_timer); + cpu_fast_off_val = dev->regs[0][0xa8]; + cpu_fast_off_count = cpu_fast_off_val + 1; + cpu_register_fast_off_handler(&dev->fast_off_timer); } else - cpu_fast_off_val = cpu_fast_off_count = 0; + cpu_fast_off_val = cpu_fast_off_count = 0; /* On PIIX4, PIIX4E, and SMSC, APM is added by the ACPI device. */ if (dev->type < 4) { - dev->apm = device_add(&apm_pci_device); - /* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */ - io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev); + dev->apm = device_add(&apm_pci_device); + /* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */ + io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev); } dev->port_92 = device_add(&port_92_pci_device); @@ -1517,9 +1611,9 @@ static void dma_alias_set(); if (dev->type < 4) - pci_enable_mirq(0); + pci_enable_mirq(0); if (dev->type < 3) - pci_enable_mirq(1); + pci_enable_mirq(1); dev->readout_regs[0] = 0xff; dev->readout_regs[1] = 0x40; @@ -1527,31 +1621,31 @@ static void /* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined): - Bit 6: 1 = can boot, 0 = no; - Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5); - Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????): - Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz; - 0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz; - 1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz; - 1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */ + Bit 6: 1 = can boot, 0 = no; + Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5); + Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????): + Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz; + 0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz; + 1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz; + 1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */ if (cpu_busspeed <= 40000000) - dev->readout_regs[1] |= 0x30; + dev->readout_regs[1] |= 0x30; else if ((cpu_busspeed > 40000000) && (cpu_busspeed <= 50000000)) - dev->readout_regs[1] |= 0x00; + dev->readout_regs[1] |= 0x00; else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - dev->readout_regs[1] |= 0x20; + dev->readout_regs[1] |= 0x20; else if (cpu_busspeed > 60000000) - dev->readout_regs[1] |= 0x10; + dev->readout_regs[1] |= 0x10; if (cpu_dmulti <= 1.5) - dev->readout_regs[1] |= 0x82; + dev->readout_regs[1] |= 0x82; else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0)) - dev->readout_regs[1] |= 0x02; + dev->readout_regs[1] |= 0x02; else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5)) - dev->readout_regs[1] |= 0x00; + dev->readout_regs[1] |= 0x00; else if (cpu_dmulti > 2.5) - dev->readout_regs[1] |= 0x80; + dev->readout_regs[1] |= 0x80; io_sethandler(0x0078, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev); io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev); @@ -1573,16 +1667,16 @@ static void dev->board_config[1] = 0xe0; if (cpu_busspeed <= 50000000) - dev->board_config[1] |= 0x10; + dev->board_config[1] |= 0x10; else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - dev->board_config[1] |= 0x18; + dev->board_config[1] |= 0x18; else if (cpu_busspeed > 60000000) - dev->board_config[1] |= 0x00; + dev->board_config[1] |= 0x00; if (cpu_dmulti <= 1.5) - dev->board_config[1] |= 0x01; + dev->board_config[1] |= 0x01; else - dev->board_config[1] |= 0x00; + dev->board_config[1] |= 0x00; // device_add(&i8254_sec_device); @@ -1590,99 +1684,99 @@ static void } const device_t piix_device = { - .name = "Intel 82371FB (PIIX)", + .name = "Intel 82371FB (PIIX)", .internal_name = "piix", - .flags = DEVICE_PCI, - .local = 0x122e0101, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x122e0101, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t piix_rev02_device = { - .name = "Intel 82371FB (PIIX) (Faulty BusMastering!!)", + .name = "Intel 82371FB (PIIX) (Faulty BusMastering!!)", .internal_name = "piix_rev02", - .flags = DEVICE_PCI, - .local = 0x122e0121, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x122e0121, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t piix3_device = { - .name = "Intel 82371SB (PIIX3)", + .name = "Intel 82371SB (PIIX3)", .internal_name = "piix3", - .flags = DEVICE_PCI, - .local = 0x70000403, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x70000403, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t piix3_ioapic_device = { - .name = "Intel 82371SB (PIIX3) (Boards with I/O APIC)", + .name = "Intel 82371SB (PIIX3) (Boards with I/O APIC)", .internal_name = "piix3_ioapic", - .flags = DEVICE_PCI, - .local = 0x70001403, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x70001403, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t piix4_device = { - .name = "Intel 82371AB/EB (PIIX4/PIIX4E)", + .name = "Intel 82371AB/EB (PIIX4/PIIX4E)", .internal_name = "piix4", - .flags = DEVICE_PCI, - .local = 0x71100004, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x71100004, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t piix4e_device = { - .name = "Intel 82371EB (PIIX4E)", + .name = "Intel 82371EB (PIIX4E)", .internal_name = "piix4e", - .flags = DEVICE_PCI, - .local = 0x71100094, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x71100094, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t slc90e66_device = { - .name = "SMSC SLC90E66 (Victory66)", + .name = "SMSC SLC90E66 (Victory66)", .internal_name = "slc90e66", - .flags = DEVICE_PCI, - .local = 0x94600005, - .init = piix_init, - .close = piix_close, - .reset = piix_reset, + .flags = DEVICE_PCI, + .local = 0x94600005, + .init = piix_init, + .close = piix_close, + .reset = piix_reset, { .available = NULL }, .speed_changed = piix_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/intel_sio.c b/src/chipset/intel_sio.c index bbc85662d..5e9a001df 100644 --- a/src/chipset/intel_sio.c +++ b/src/chipset/intel_sio.c @@ -31,290 +31,292 @@ #include <86box/machine.h> #include <86box/chipset.h> - typedef struct { - uint8_t id, - regs[256]; + uint8_t id, + regs[256]; - uint16_t timer_base, - timer_latch; + uint16_t timer_base, + timer_latch; - double fast_off_period; + double fast_off_period; - pc_timer_t timer, fast_off_timer; + pc_timer_t timer, fast_off_timer; - apm_t * apm; - port_92_t * port_92; + apm_t *apm; + port_92_t *port_92; } sio_t; - #ifdef ENABLE_SIO_LOG int sio_do_log = ENABLE_SIO_LOG; - static void sio_log(const char *fmt, ...) { va_list ap; if (sio_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define sio_log(fmt, ...) +# define sio_log(fmt, ...) #endif - static void sio_timer_write(uint16_t addr, uint8_t val, void *priv) { sio_t *dev = (sio_t *) priv; if (!(addr & 0x0002)) { - if (addr & 0x0001) - dev->timer_latch = (dev->timer_latch & 0xff) | (val << 8); - else - dev->timer_latch = (dev->timer_latch & 0xff00) | val; + if (addr & 0x0001) + dev->timer_latch = (dev->timer_latch & 0xff) | (val << 8); + else + dev->timer_latch = (dev->timer_latch & 0xff00) | val; - timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); + timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); } } - static void sio_timer_writew(uint16_t addr, uint16_t val, void *priv) { sio_t *dev = (sio_t *) priv; if (!(addr & 0x0002)) { - dev->timer_latch = val; + dev->timer_latch = val; - timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); + timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); } } - static uint8_t sio_timer_read(uint16_t addr, void *priv) { - sio_t *dev = (sio_t *) priv; + sio_t *dev = (sio_t *) priv; uint16_t sio_timer_latch; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (!(addr & 0x0002)) { - cycles -= ((int) (PITCONST >> 32)); + cycles -= ((int) (PITCONST >> 32)); - sio_timer_latch = timer_get_remaining_us(&dev->timer); + sio_timer_latch = timer_get_remaining_us(&dev->timer); - if (addr & 0x0001) - ret = sio_timer_latch >> 8; - else - ret = sio_timer_latch & 0xff; + if (addr & 0x0001) + ret = sio_timer_latch >> 8; + else + ret = sio_timer_latch & 0xff; } return ret; } - static uint16_t sio_timer_readw(uint16_t addr, void *priv) { - sio_t *dev = (sio_t *) priv; + sio_t *dev = (sio_t *) priv; uint16_t ret = 0xffff; if (!(addr & 0x0002)) { - cycles -= ((int) (PITCONST >> 32)); + cycles -= ((int) (PITCONST >> 32)); - ret = timer_get_remaining_us(&dev->timer); + ret = timer_get_remaining_us(&dev->timer); } return ret; } - static void sio_write(int func, int addr, uint8_t val, void *priv) { - sio_t *dev = (sio_t *) priv; + sio_t *dev = (sio_t *) priv; uint8_t old; if (func > 0) - return; + return; if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40)) - return; + return; /* The IB (original) variant of the SIO has no PCI IRQ steering. */ if ((addr >= 0x60) && (addr <= 0x63) && (dev->id < 0x03)) - return; + return; old = dev->regs[addr]; switch (addr) { - case 0x04: /*Command register*/ - if (dev->id == 0x03) - dev->regs[addr] = (dev->regs[addr] & 0xf7) | (val & 0x08); - break; + case 0x04: /*Command register*/ + if (dev->id == 0x03) + dev->regs[addr] = (dev->regs[addr] & 0xf7) | (val & 0x08); + break; - case 0x07: - dev->regs[addr] &= ~(val & 0x38); - break; + case 0x07: + dev->regs[addr] &= ~(val & 0x38); + break; - case 0x40: - if (dev->id == 0x03) { - dev->regs[addr] = (val & 0x7f); + case 0x40: + if (dev->id == 0x03) { + dev->regs[addr] = (val & 0x7f); - if (!((val ^ old) & 0x40)) - return; + if (!((val ^ old) & 0x40)) + return; - dma_alias_remove(); - if (!(val & 0x40)) - dma_alias_set(); - } else - dev->regs[addr] = (val & 0x3f); - break; - case 0x41: case 0x44: - dev->regs[addr] = (val & 0x1f); - break; - case 0x42: - if (dev->id == 0x03) - dev->regs[addr] = val; - else - dev->regs[addr] = (val & 0x77); - break; - case 0x43: - if (dev->id == 0x03) - dev->regs[addr] = (val & 0x01); - break; - case 0x45: case 0x46: - case 0x47: case 0x48: - case 0x49: case 0x4a: - case 0x4b: case 0x4e: - case 0x54: case 0x55: - case 0x56: - dev->regs[addr] = val; - break; - case 0x4c: case 0x4d: - dev->regs[addr] = (val & 0x7f); - break; - case 0x4f: - dev->regs[addr] = val; + dma_alias_remove(); + if (!(val & 0x40)) + dma_alias_set(); + } else + dev->regs[addr] = (val & 0x3f); + break; + case 0x41: + case 0x44: + dev->regs[addr] = (val & 0x1f); + break; + case 0x42: + if (dev->id == 0x03) + dev->regs[addr] = val; + else + dev->regs[addr] = (val & 0x77); + break; + case 0x43: + if (dev->id == 0x03) + dev->regs[addr] = (val & 0x01); + break; + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4e: + case 0x54: + case 0x55: + case 0x56: + dev->regs[addr] = val; + break; + case 0x4c: + case 0x4d: + dev->regs[addr] = (val & 0x7f); + break; + case 0x4f: + dev->regs[addr] = val; - if (!((val ^ old) & 0x40)) - return; + if (!((val ^ old) & 0x40)) + return; - port_92_remove(dev->port_92); - if (val & 0x40) - port_92_add(dev->port_92); - break; - case 0x57: - dev->regs[addr] = val; + port_92_remove(dev->port_92); + if (val & 0x40) + port_92_add(dev->port_92); + break; + case 0x57: + dev->regs[addr] = val; - dma_remove_sg(); - dma_set_sg_base(val); - break; - case 0x60: case 0x61: case 0x62: case 0x63: - if (dev->id == 0x03) { - sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); - dev->regs[addr] = val & 0x8f; - if (val & 0x80) - pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); - else - pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); - } - break; - case 0x80: - case 0x81: - if (addr == 0x80) - dev->regs[addr] = val & 0xfd; - else - dev->regs[addr] = val; + dma_remove_sg(); + dma_set_sg_base(val); + break; + case 0x60: + case 0x61: + case 0x62: + case 0x63: + if (dev->id == 0x03) { + sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); + dev->regs[addr] = val & 0x8f; + if (val & 0x80) + pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); + else + pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); + } + break; + case 0x80: + case 0x81: + if (addr == 0x80) + dev->regs[addr] = val & 0xfd; + else + dev->regs[addr] = val; - if (dev->timer_base & 0x01) { - io_removehandler(dev->timer_base & 0xfffc, 0x0004, - sio_timer_read, sio_timer_readw, NULL, - sio_timer_write, sio_timer_writew, NULL, dev); - } - dev->timer_base = (dev->regs[0x81] << 8) | (dev->regs[0x80] & 0xfd); - if (dev->timer_base & 0x01) { - io_sethandler(dev->timer_base & 0xfffc, 0x0004, - sio_timer_read, sio_timer_readw, NULL, - sio_timer_write, sio_timer_writew, NULL, dev); - } - break; - case 0xa0: - if (dev->id == 0x03) { - dev->regs[addr] = val & 0x1f; - apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80)); - switch ((val & 0x18) >> 3) { - case 0x00: - dev->fast_off_period = PCICLK * 32768.0 * 60000.0; - break; - case 0x01: - default: - dev->fast_off_period = 0.0; - break; - case 0x02: - dev->fast_off_period = PCICLK; - break; - case 0x03: - dev->fast_off_period = PCICLK * 32768.0; - break; - } - cpu_fast_off_count = cpu_fast_off_val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - } - break; - case 0xa2: - if (dev->id == 0x03) { - dev->regs[addr] = val & 0xff; - apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); - } - break; - case 0xaa: - if (dev->id == 0x03) - dev->regs[addr] &= (val & 0xff); - break; - case 0xac: case 0xae: - if (dev->id == 0x03) - dev->regs[addr] = val & 0xff; - break; - case 0xa4: - if (dev->id == 0x03) { - dev->regs[addr] = val & 0xfb; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr]; - } - break; - case 0xa5: - if (dev->id == 0x03) { - dev->regs[addr] = val & 0xff; - cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8); - } - break; - case 0xa7: - if (dev->id == 0x03) { - dev->regs[addr] = val & 0xa0; - cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24); - } - break; - case 0xa8: - dev->regs[addr] = val & 0xff; - cpu_fast_off_val = val; - cpu_fast_off_count = val + 1; - cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); - break; + if (dev->timer_base & 0x01) { + io_removehandler(dev->timer_base & 0xfffc, 0x0004, + sio_timer_read, sio_timer_readw, NULL, + sio_timer_write, sio_timer_writew, NULL, dev); + } + dev->timer_base = (dev->regs[0x81] << 8) | (dev->regs[0x80] & 0xfd); + if (dev->timer_base & 0x01) { + io_sethandler(dev->timer_base & 0xfffc, 0x0004, + sio_timer_read, sio_timer_readw, NULL, + sio_timer_write, sio_timer_writew, NULL, dev); + } + break; + case 0xa0: + if (dev->id == 0x03) { + dev->regs[addr] = val & 0x1f; + apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80)); + switch ((val & 0x18) >> 3) { + case 0x00: + dev->fast_off_period = PCICLK * 32768.0 * 60000.0; + break; + case 0x01: + default: + dev->fast_off_period = 0.0; + break; + case 0x02: + dev->fast_off_period = PCICLK; + break; + case 0x03: + dev->fast_off_period = PCICLK * 32768.0; + break; + } + cpu_fast_off_count = cpu_fast_off_val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + } + break; + case 0xa2: + if (dev->id == 0x03) { + dev->regs[addr] = val & 0xff; + apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80)); + } + break; + case 0xaa: + if (dev->id == 0x03) + dev->regs[addr] &= (val & 0xff); + break; + case 0xac: + case 0xae: + if (dev->id == 0x03) + dev->regs[addr] = val & 0xff; + break; + case 0xa4: + if (dev->id == 0x03) { + dev->regs[addr] = val & 0xfb; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr]; + } + break; + case 0xa5: + if (dev->id == 0x03) { + dev->regs[addr] = val & 0xff; + cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8); + } + break; + case 0xa7: + if (dev->id == 0x03) { + dev->regs[addr] = val & 0xa0; + cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24); + } + break; + case 0xa8: + dev->regs[addr] = val & 0xff; + cpu_fast_off_val = val; + cpu_fast_off_count = val + 1; + cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period); + break; } } - static uint8_t sio_read(int func, int addr, void *priv) { - sio_t *dev = (sio_t *) priv; + sio_t *dev = (sio_t *) priv; uint8_t ret; ret = 0xff; @@ -325,47 +327,44 @@ sio_read(int func, int addr, void *priv) return ret; } - static void sio_config_write(uint16_t addr, uint8_t val, void *priv) { } - static uint8_t sio_config_read(uint16_t port, void *priv) { uint8_t ret = 0x00; switch (port & 0x000f) { - case 3: - ret = 0xff; - break; - case 5: - ret = 0xd3; + case 3: + ret = 0xff; + break; + case 5: + ret = 0xd3; - switch (cpu_pci_speed) { - case 20000000: - ret |= 0x0c; - break; - case 25000000: - default: - ret |= 0x00; - break; - case 30000000: - ret |= 0x08; - break; - case 33333333: - ret |= 0x04; - break; - } - break; + switch (cpu_pci_speed) { + case 20000000: + ret |= 0x0c; + break; + case 25000000: + default: + ret |= 0x00; + break; + case 30000000: + ret |= 0x08; + break; + case 33333333: + ret |= 0x04; + break; + } + break; } return ret; } - static void sio_reset_hard(void *priv) { @@ -373,27 +372,37 @@ sio_reset_hard(void *priv) memset(dev->regs, 0, 256); - dev->regs[0x00] = 0x86; dev->regs[0x01] = 0x80; /*Intel*/ - dev->regs[0x02] = 0x84; dev->regs[0x03] = 0x04; /*82378IB (SIO)*/ + dev->regs[0x00] = 0x86; + dev->regs[0x01] = 0x80; /*Intel*/ + dev->regs[0x02] = 0x84; + dev->regs[0x03] = 0x04; /*82378IB (SIO)*/ dev->regs[0x04] = 0x07; dev->regs[0x07] = 0x02; dev->regs[0x08] = dev->id; - dev->regs[0x40] = 0x20; dev->regs[0x41] = 0x00; + dev->regs[0x40] = 0x20; + dev->regs[0x41] = 0x00; dev->regs[0x42] = 0x04; - dev->regs[0x45] = 0x10; dev->regs[0x46] = 0x0f; + dev->regs[0x45] = 0x10; + dev->regs[0x46] = 0x0f; dev->regs[0x48] = 0x01; - dev->regs[0x4a] = 0x10; dev->regs[0x4b] = 0x0f; - dev->regs[0x4c] = 0x56; dev->regs[0x4d] = 0x40; - dev->regs[0x4e] = 0x07; dev->regs[0x4f] = 0x4f; + dev->regs[0x4a] = 0x10; + dev->regs[0x4b] = 0x0f; + dev->regs[0x4c] = 0x56; + dev->regs[0x4d] = 0x40; + dev->regs[0x4e] = 0x07; + dev->regs[0x4f] = 0x4f; dev->regs[0x57] = 0x04; if (dev->id == 0x03) { - dev->regs[0x60] = 0x80; dev->regs[0x61] = 0x80; dev->regs[0x62] = 0x80; dev->regs[0x63] = 0x80; + dev->regs[0x60] = 0x80; + dev->regs[0x61] = 0x80; + dev->regs[0x62] = 0x80; + dev->regs[0x63] = 0x80; } dev->regs[0x80] = 0x78; if (dev->id == 0x03) { - dev->regs[0xa0] = 0x08; - dev->regs[0xa8] = 0x0f; + dev->regs[0xa0] = 0x08; + dev->regs[0xa8] = 0x0f; } pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); @@ -402,25 +411,23 @@ sio_reset_hard(void *priv) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); if (dev->timer_base & 0x0001) { - io_removehandler(dev->timer_base & 0xfffc, 0x0004, - sio_timer_read, sio_timer_readw, NULL, - sio_timer_write, sio_timer_writew, NULL, dev); + io_removehandler(dev->timer_base & 0xfffc, 0x0004, + sio_timer_read, sio_timer_readw, NULL, + sio_timer_write, sio_timer_writew, NULL, dev); } dev->timer_base = 0x0078; } - static void sio_apm_out(uint16_t port, uint8_t val, void *p) { sio_t *dev = (sio_t *) p; if (dev->apm->do_smi) - dev->regs[0xaa] |= 0x80; + dev->regs[0xaa] |= 0x80; } - static void sio_fast_off_count(void *priv) { @@ -430,7 +437,6 @@ sio_fast_off_count(void *priv) dev->regs[0xaa] |= 0x20; } - static void sio_reset(void *p) { @@ -441,48 +447,45 @@ sio_reset(void *p) dma_set_params(1, 0xffffffff); if (dev->id == 0x03) { - sio_write(0, 0xa0, 0x08, p); - sio_write(0, 0xa2, 0x00, p); - sio_write(0, 0xa4, 0x00, p); - sio_write(0, 0xa5, 0x00, p); - sio_write(0, 0xa6, 0x00, p); - sio_write(0, 0xa7, 0x00, p); - sio_write(0, 0xa8, 0x0f, p); + sio_write(0, 0xa0, 0x08, p); + sio_write(0, 0xa2, 0x00, p); + sio_write(0, 0xa4, 0x00, p); + sio_write(0, 0xa5, 0x00, p); + sio_write(0, 0xa6, 0x00, p); + sio_write(0, 0xa7, 0x00, p); + sio_write(0, 0xa8, 0x0f, p); } } - static void sio_close(void *p) { - sio_t *dev = (sio_t *)p; + sio_t *dev = (sio_t *) p; free(dev); } - static void sio_speed_changed(void *priv) { sio_t *dev = (sio_t *) priv; - int te; + int te; te = timer_is_enabled(&dev->timer); timer_disable(&dev->timer); if (te) - timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); + timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC); if (dev->id == 0x03) { - te = timer_is_enabled(&dev->fast_off_timer); + te = timer_is_enabled(&dev->fast_off_timer); - timer_stop(&dev->fast_off_timer); - if (te) - timer_on_auto(&dev->fast_off_timer, dev->fast_off_period); + timer_stop(&dev->fast_off_timer); + if (te) + timer_on_auto(&dev->fast_off_timer, dev->fast_off_period); } } - static void * sio_init(const device_t *info) { @@ -494,24 +497,24 @@ sio_init(const device_t *info) dev->id = info->local; if (dev->id == 0x03) - timer_add(&dev->fast_off_timer, sio_fast_off_count, dev, 0); + timer_add(&dev->fast_off_timer, sio_fast_off_count, dev, 0); sio_reset_hard(dev); cpu_fast_off_flags = 0x00000000; if (dev->id == 0x03) { - cpu_fast_off_val = dev->regs[0xa8]; - cpu_fast_off_count = cpu_fast_off_val + 1; + cpu_fast_off_val = dev->regs[0xa8]; + cpu_fast_off_count = cpu_fast_off_val + 1; - cpu_register_fast_off_handler(&dev->fast_off_timer); + cpu_register_fast_off_handler(&dev->fast_off_timer); } else - cpu_fast_off_val = cpu_fast_off_count = 0; + cpu_fast_off_val = cpu_fast_off_count = 0; if (dev->id == 0x03) { - dev->apm = device_add(&apm_pci_device); - /* APM intercept handler to update 82378ZB SMI status on APM SMI. */ - io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, sio_apm_out, NULL, NULL, dev); + dev->apm = device_add(&apm_pci_device); + /* APM intercept handler to update 82378ZB SMI status on APM SMI. */ + io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, sio_apm_out, NULL, NULL, dev); } dev->port_92 = device_add(&port_92_pci_device); @@ -522,12 +525,12 @@ sio_init(const device_t *info) dma_high_page_init(); if (dev->id == 0x03) - dma_alias_set(); + dma_alias_set(); io_sethandler(0x0073, 0x0001, - sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev); + sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev); io_sethandler(0x0075, 0x0001, - sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev); + sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev); timer_add(&dev->timer, NULL, NULL, 0); @@ -536,32 +539,30 @@ sio_init(const device_t *info) return dev; } - const device_t sio_device = { - .name = "Intel 82378IB (SIO)", + .name = "Intel 82378IB (SIO)", .internal_name = "sio", - .flags = DEVICE_PCI, - .local = 0x00, - .init = sio_init, - .close = sio_close, - .reset = sio_reset, + .flags = DEVICE_PCI, + .local = 0x00, + .init = sio_init, + .close = sio_close, + .reset = sio_reset, { .available = NULL }, .speed_changed = sio_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; - const device_t sio_zb_device = { - .name = "Intel 82378ZB (SIO)", + .name = "Intel 82378ZB (SIO)", .internal_name = "sio_zb", - .flags = DEVICE_PCI, - .local = 0x03, - .init = sio_init, - .close = sio_close, - .reset = sio_reset, + .flags = DEVICE_PCI, + .local = 0x03, + .init = sio_init, + .close = sio_close, + .reset = sio_reset, { .available = NULL }, .speed_changed = sio_speed_changed, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/neat.c b/src/chipset/neat.c index 8e7bc1937..6b4f476fe 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -30,266 +30,260 @@ #include <86box/mem.h> #include <86box/chipset.h> -#define NEAT_DEBUG 0 - - -#define EMS_MAXPAGE 4 -#define EMS_PGSIZE 16384 +#define NEAT_DEBUG 0 +#define EMS_MAXPAGE 4 +#define EMS_PGSIZE 16384 /* CS8221 82C211 controller registers. */ -#define REG_RA0 0x60 /* PROCCLK selector */ -# define RA0_MASK 0x34 /* RR11 X1XR */ -# define RA0_READY 0x01 /* local bus READY timeout */ -# define RA0_RDYNMIEN 0x04 /* local bus READY tmo NMI enable */ -# define RA0_PROCCLK 0x10 /* PROCCLK=BCLK (1) or CLK2IN (0) */ -# define RA0_ALTRST 0x20 /* alternate CPU reset (1) */ -# define RA0_REV 0xc0 /* chip revision ID */ -# define RA0_REV_SH 6 -# define RA0_REV_ID 2 /* faked revision# for 82C211 */ +#define REG_RA0 0x60 /* PROCCLK selector */ +#define RA0_MASK 0x34 /* RR11 X1XR */ +#define RA0_READY 0x01 /* local bus READY timeout */ +#define RA0_RDYNMIEN 0x04 /* local bus READY tmo NMI enable */ +#define RA0_PROCCLK 0x10 /* PROCCLK=BCLK (1) or CLK2IN (0) */ +#define RA0_ALTRST 0x20 /* alternate CPU reset (1) */ +#define RA0_REV 0xc0 /* chip revision ID */ +#define RA0_REV_SH 6 +#define RA0_REV_ID 2 /* faked revision# for 82C211 */ -#define REG_RA1 0x61 /* Command Delay */ -# define RA1_MASK 0xff /* 1111 1111 */ -# define RA1_BUSDLY 0x03 /* AT BUS command delay */ -# define RA1_BUSDLY_SH 0 -# define RA1_BUS8DLY 0x0c /* AT BUS 8bit command delay */ -# define RA1_BUS8DLY_SH 2 -# define RA1_MEMDLY 0x30 /* AT BUS 16bit memory delay */ -# define RA1_MEMDLY_SH 4 -# define RA1_QUICKEN 0x40 /* Quick Mode enable */ -# define RA1_HOLDDLY 0x80 /* Hold Time Delay */ +#define REG_RA1 0x61 /* Command Delay */ +#define RA1_MASK 0xff /* 1111 1111 */ +#define RA1_BUSDLY 0x03 /* AT BUS command delay */ +#define RA1_BUSDLY_SH 0 +#define RA1_BUS8DLY 0x0c /* AT BUS 8bit command delay */ +#define RA1_BUS8DLY_SH 2 +#define RA1_MEMDLY 0x30 /* AT BUS 16bit memory delay */ +#define RA1_MEMDLY_SH 4 +#define RA1_QUICKEN 0x40 /* Quick Mode enable */ +#define RA1_HOLDDLY 0x80 /* Hold Time Delay */ -#define REG_RA2 0x62 /* Wait State / BCLK selector */ -# define RA2_MASK 0x3f /* XX11 1111 */ -# define RA2_BCLK 0x03 /* BCLK select */ -# define RA2_BCLK_SH 0 -# define BCLK_IN2 0 /* BCLK = CLK2IN/2 */ -# define BCLK_IN 1 /* BCLK = CLK2IN */ -# define BCLK_AT 2 /* BCLK = ATCLK */ -# define RA2_AT8WS 0x0c /* AT 8-bit wait states */ -# define RA2_AT8WS_SH 2 -# define AT8WS_2 0 /* 2 wait states */ -# define AT8WS_3 1 /* 3 wait states */ -# define AT8WS_4 2 /* 4 wait states */ -# define AT8WS_5 4 /* 5 wait states */ -# define RA2_ATWS 0x30 /* AT 16-bit wait states */ -# define RA2_ATWS_SH 4 -# define ATWS_2 0 /* 2 wait states */ -# define ATWS_3 1 /* 3 wait states */ -# define ATWS_4 2 /* 4 wait states */ -# define ATWS_5 4 /* 5 wait states */ +#define REG_RA2 0x62 /* Wait State / BCLK selector */ +#define RA2_MASK 0x3f /* XX11 1111 */ +#define RA2_BCLK 0x03 /* BCLK select */ +#define RA2_BCLK_SH 0 +#define BCLK_IN2 0 /* BCLK = CLK2IN/2 */ +#define BCLK_IN 1 /* BCLK = CLK2IN */ +#define BCLK_AT 2 /* BCLK = ATCLK */ +#define RA2_AT8WS 0x0c /* AT 8-bit wait states */ +#define RA2_AT8WS_SH 2 +#define AT8WS_2 0 /* 2 wait states */ +#define AT8WS_3 1 /* 3 wait states */ +#define AT8WS_4 2 /* 4 wait states */ +#define AT8WS_5 4 /* 5 wait states */ +#define RA2_ATWS 0x30 /* AT 16-bit wait states */ +#define RA2_ATWS_SH 4 +#define ATWS_2 0 /* 2 wait states */ +#define ATWS_3 1 /* 3 wait states */ +#define ATWS_4 2 /* 4 wait states */ +#define ATWS_5 4 /* 5 wait states */ /* CS8221 82C212 controller registers. */ -#define REG_RB0 0x64 /* Version ID */ -# define RB0_MASK 0x60 /* R11X XXXX */ -# define RB0_REV 0x60 /* Chip revsion number */ -# define RB0_REV_SH 5 -# define RB0_REV_ID 2 /* faked revision# for 82C212 */ -# define RB0_VERSION 0x80 /* Chip version (0=82C212) */ +#define REG_RB0 0x64 /* Version ID */ +#define RB0_MASK 0x60 /* R11X XXXX */ +#define RB0_REV 0x60 /* Chip revsion number */ +#define RB0_REV_SH 5 +#define RB0_REV_ID 2 /* faked revision# for 82C212 */ +#define RB0_VERSION 0x80 /* Chip version (0=82C212) */ -#define REG_RB1 0x65 /* ROM configuration */ -# define RB1_MASK 0xff /* 1111 1111 */ -# define RB1_ROMF0 0x01 /* ROM F0000 enabled (0) */ -# define RB1_ROME0 0x02 /* ROM E0000 disabled (1) */ -# define RB1_ROMD0 0x04 /* ROM D0000 disabled (1) */ -# define RB1_ROMC0 0x08 /* ROM C0000 disabled (1) */ -# define RB1_SHADOWF0 0x10 /* Shadow F0000 R/W (0) */ -# define RB1_SHADOWE0 0x20 /* Shadow E0000 R/W (0) */ -# define RB1_SHADOWD0 0x40 /* Shadow D0000 R/W (0) */ -# define RB1_SHADOWC0 0x80 /* Shadow C0000 R/W (0) */ +#define REG_RB1 0x65 /* ROM configuration */ +#define RB1_MASK 0xff /* 1111 1111 */ +#define RB1_ROMF0 0x01 /* ROM F0000 enabled (0) */ +#define RB1_ROME0 0x02 /* ROM E0000 disabled (1) */ +#define RB1_ROMD0 0x04 /* ROM D0000 disabled (1) */ +#define RB1_ROMC0 0x08 /* ROM C0000 disabled (1) */ +#define RB1_SHADOWF0 0x10 /* Shadow F0000 R/W (0) */ +#define RB1_SHADOWE0 0x20 /* Shadow E0000 R/W (0) */ +#define RB1_SHADOWD0 0x40 /* Shadow D0000 R/W (0) */ +#define RB1_SHADOWC0 0x80 /* Shadow C0000 R/W (0) */ -#define REG_RB2 0x66 /* Memory Enable 1 */ -# define RB2_MASK 0x80 /* 1XXX XXXX */ -# define RB2_TOP128 0x80 /* top 128K is on sysboard (1) */ +#define REG_RB2 0x66 /* Memory Enable 1 */ +#define RB2_MASK 0x80 /* 1XXX XXXX */ +#define RB2_TOP128 0x80 /* top 128K is on sysboard (1) */ -#define REG_RB3 0x67 /* Memory Enable 2 */ -# define RB3_MASK 0xff /* 1111 1111 */ -# define RB3_SHENB0 0x01 /* enable B0000-B3FFF shadow (1) */ -# define RB3_SHENB4 0x02 /* enable B4000-B7FFF shadow (1) */ -# define RB3_SHENB8 0x04 /* enable B8000-BBFFF shadow (1) */ -# define RB3_SHENBC 0x08 /* enable BC000-BFFFF shadow (1) */ -# define RB3_SHENA0 0x10 /* enable A0000-A3FFF shadow (1) */ -# define RB3_SHENA4 0x20 /* enable A4000-A7FFF shadow (1) */ -# define RB3_SHENA8 0x40 /* enable A8000-ABFFF shadow (1) */ -# define RB3_SHENAC 0x80 /* enable AC000-AFFFF shadow (1) */ +#define REG_RB3 0x67 /* Memory Enable 2 */ +#define RB3_MASK 0xff /* 1111 1111 */ +#define RB3_SHENB0 0x01 /* enable B0000-B3FFF shadow (1) */ +#define RB3_SHENB4 0x02 /* enable B4000-B7FFF shadow (1) */ +#define RB3_SHENB8 0x04 /* enable B8000-BBFFF shadow (1) */ +#define RB3_SHENBC 0x08 /* enable BC000-BFFFF shadow (1) */ +#define RB3_SHENA0 0x10 /* enable A0000-A3FFF shadow (1) */ +#define RB3_SHENA4 0x20 /* enable A4000-A7FFF shadow (1) */ +#define RB3_SHENA8 0x40 /* enable A8000-ABFFF shadow (1) */ +#define RB3_SHENAC 0x80 /* enable AC000-AFFFF shadow (1) */ -#define REG_RB4 0x68 /* Memory Enable 3 */ -# define RB4_MASK 0xff /* 1111 1111 */ -# define RB4_SHENC0 0x01 /* enable C0000-C3FFF shadow (1) */ -# define RB4_SHENC4 0x02 /* enable C4000-C7FFF shadow (1) */ -# define RB4_SHENC8 0x04 /* enable C8000-CBFFF shadow (1) */ -# define RB4_SHENCC 0x08 /* enable CC000-CFFFF shadow (1) */ -# define RB4_SHEND0 0x10 /* enable D0000-D3FFF shadow (1) */ -# define RB4_SHEND4 0x20 /* enable D4000-D7FFF shadow (1) */ -# define RB4_SHEND8 0x40 /* enable D8000-DBFFF shadow (1) */ -# define RB4_SHENDC 0x80 /* enable DC000-DFFFF shadow (1) */ +#define REG_RB4 0x68 /* Memory Enable 3 */ +#define RB4_MASK 0xff /* 1111 1111 */ +#define RB4_SHENC0 0x01 /* enable C0000-C3FFF shadow (1) */ +#define RB4_SHENC4 0x02 /* enable C4000-C7FFF shadow (1) */ +#define RB4_SHENC8 0x04 /* enable C8000-CBFFF shadow (1) */ +#define RB4_SHENCC 0x08 /* enable CC000-CFFFF shadow (1) */ +#define RB4_SHEND0 0x10 /* enable D0000-D3FFF shadow (1) */ +#define RB4_SHEND4 0x20 /* enable D4000-D7FFF shadow (1) */ +#define RB4_SHEND8 0x40 /* enable D8000-DBFFF shadow (1) */ +#define RB4_SHENDC 0x80 /* enable DC000-DFFFF shadow (1) */ -#define REG_RB5 0x69 /* Memory Enable 4 */ -# define RB5_MASK 0xff /* 1111 1111 */ -# define RB5_SHENE0 0x01 /* enable E0000-E3FFF shadow (1) */ -# define RB5_SHENE4 0x02 /* enable E4000-E7FFF shadow (1) */ -# define RB5_SHENE8 0x04 /* enable E8000-EBFFF shadow (1) */ -# define RB5_SHENEC 0x08 /* enable EC000-EFFFF shadow (1) */ -# define RB5_SHENF0 0x10 /* enable F0000-F3FFF shadow (1) */ -# define RB5_SHENF4 0x20 /* enable F4000-F7FFF shadow (1) */ -# define RB5_SHENF8 0x40 /* enable F8000-FBFFF shadow (1) */ -# define RB5_SHENFC 0x80 /* enable FC000-FFFFF shadow (1) */ +#define REG_RB5 0x69 /* Memory Enable 4 */ +#define RB5_MASK 0xff /* 1111 1111 */ +#define RB5_SHENE0 0x01 /* enable E0000-E3FFF shadow (1) */ +#define RB5_SHENE4 0x02 /* enable E4000-E7FFF shadow (1) */ +#define RB5_SHENE8 0x04 /* enable E8000-EBFFF shadow (1) */ +#define RB5_SHENEC 0x08 /* enable EC000-EFFFF shadow (1) */ +#define RB5_SHENF0 0x10 /* enable F0000-F3FFF shadow (1) */ +#define RB5_SHENF4 0x20 /* enable F4000-F7FFF shadow (1) */ +#define RB5_SHENF8 0x40 /* enable F8000-FBFFF shadow (1) */ +#define RB5_SHENFC 0x80 /* enable FC000-FFFFF shadow (1) */ -#define REG_RB6 0x6a /* Bank 0/1 Enable */ -# define RB6_MASK 0xe0 /* 111R RRRR */ -# define RB6_BANKS 0x20 /* #banks used (1=two) */ -# define RB6_RTYPE 0xc0 /* DRAM chip size used */ -# define RTYPE_SH 6 -# define RTYPE_NONE 0 /* Disabled */ -# define RTYPE_MIXED 1 /* 64K/256K mixed (for 640K) */ -# define RTYPE_256K 2 /* 256K (default) */ -# define RTYPE_1M 3 /* 1M */ +#define REG_RB6 0x6a /* Bank 0/1 Enable */ +#define RB6_MASK 0xe0 /* 111R RRRR */ +#define RB6_BANKS 0x20 /* #banks used (1=two) */ +#define RB6_RTYPE 0xc0 /* DRAM chip size used */ +#define RTYPE_SH 6 +#define RTYPE_NONE 0 /* Disabled */ +#define RTYPE_MIXED 1 /* 64K/256K mixed (for 640K) */ +#define RTYPE_256K 2 /* 256K (default) */ +#define RTYPE_1M 3 /* 1M */ -#define REG_RB7 0x6b /* DRAM configuration */ -# define RB7_MASK 0xff /* 1111 1111 */ -# define RB7_ROMWS 0x03 /* ROM access wait states */ -# define RB7_ROMWS_SH 0 -# define ROMWS_0 0 /* 0 wait states */ -# define ROMWS_1 1 /* 1 wait states */ -# define ROMWS_2 2 /* 2 wait states */ -# define ROMWS_3 3 /* 3 wait states (default) */ -# define RB7_EMSWS 0x0c /* EMS access wait states */ -# define RB7_EMSWS_SH 2 -# define EMSWS_0 0 /* 0 wait states */ -# define EMSWS_1 1 /* 1 wait states */ -# define EMSWS_2 2 /* 2 wait states */ -# define EMSWS_3 3 /* 3 wait states (default) */ -# define RB7_EMSEN 0x10 /* enable EMS (1=on) */ -# define RB7_RAMWS 0x20 /* RAM access wait state (1=1ws) */ -# define RB7_UMAREL 0x40 /* relocate 640-1024K to 1M */ -# define RB7_PAGEEN 0x80 /* enable Page/Interleaved mode */ +#define REG_RB7 0x6b /* DRAM configuration */ +#define RB7_MASK 0xff /* 1111 1111 */ +#define RB7_ROMWS 0x03 /* ROM access wait states */ +#define RB7_ROMWS_SH 0 +#define ROMWS_0 0 /* 0 wait states */ +#define ROMWS_1 1 /* 1 wait states */ +#define ROMWS_2 2 /* 2 wait states */ +#define ROMWS_3 3 /* 3 wait states (default) */ +#define RB7_EMSWS 0x0c /* EMS access wait states */ +#define RB7_EMSWS_SH 2 +#define EMSWS_0 0 /* 0 wait states */ +#define EMSWS_1 1 /* 1 wait states */ +#define EMSWS_2 2 /* 2 wait states */ +#define EMSWS_3 3 /* 3 wait states (default) */ +#define RB7_EMSEN 0x10 /* enable EMS (1=on) */ +#define RB7_RAMWS 0x20 /* RAM access wait state (1=1ws) */ +#define RB7_UMAREL 0x40 /* relocate 640-1024K to 1M */ +#define RB7_PAGEEN 0x80 /* enable Page/Interleaved mode */ -#define REG_RB8 0x6c /* Bank 2/3 Enable */ -# define RB8_MASK 0xf0 /* 1111 RRRR */ -# define RB8_4WAY 0x10 /* enable 4-way interleave mode */ -# define RB8_BANKS 0x20 /* enable 2 banks (1) */ -# define RB8_RTYPE 0xc0 /* DRAM chip size used */ -# define RB8_RTYPE_SH 6 +#define REG_RB8 0x6c /* Bank 2/3 Enable */ +#define RB8_MASK 0xf0 /* 1111 RRRR */ +#define RB8_4WAY 0x10 /* enable 4-way interleave mode */ +#define RB8_BANKS 0x20 /* enable 2 banks (1) */ +#define RB8_RTYPE 0xc0 /* DRAM chip size used */ +#define RB8_RTYPE_SH 6 -#define REG_RB9 0x6d /* EMS base address */ -# define RB9_MASK 0xff /* 1111 1111 */ -# define RB9_BASE 0x0f /* I/O base address selection */ -# define RB9_BASE_SH 0 -# define RB9_FRAME 0xf0 /* frame address selection */ -# define RB9_FRAME_SH 4 +#define REG_RB9 0x6d /* EMS base address */ +#define RB9_MASK 0xff /* 1111 1111 */ +#define RB9_BASE 0x0f /* I/O base address selection */ +#define RB9_BASE_SH 0 +#define RB9_FRAME 0xf0 /* frame address selection */ +#define RB9_FRAME_SH 4 -#define REG_RB10 0x6e /* EMS address extension */ -# define RB10_MASK 0xff /* 1111 1111 */ -# define RB10_P3EXT 0x03 /* page 3 extension */ -# define RB10_P3EXT_SH 0 -# define PEXT_0M 0 /* page is at 0-2M */ -# define PEXT_2M 1 /* page is at 2-4M */ -# define PEXT_4M 2 /* page is at 4-6M */ -# define PEXT_6M 3 /* page is at 6-8M */ -# define RB10_P2EXT 0x0c /* page 2 extension */ -# define RB10_P2EXT_SH 2 -# define RB10_P1EXT 0x30 /* page 1 extension */ -# define RB10_P1EXT_SH 4 -# define RB10_P0EXT 0xc0 /* page 0 extension */ -# define RB10_P0EXT_SH 6 +#define REG_RB10 0x6e /* EMS address extension */ +#define RB10_MASK 0xff /* 1111 1111 */ +#define RB10_P3EXT 0x03 /* page 3 extension */ +#define RB10_P3EXT_SH 0 +#define PEXT_0M 0 /* page is at 0-2M */ +#define PEXT_2M 1 /* page is at 2-4M */ +#define PEXT_4M 2 /* page is at 4-6M */ +#define PEXT_6M 3 /* page is at 6-8M */ +#define RB10_P2EXT 0x0c /* page 2 extension */ +#define RB10_P2EXT_SH 2 +#define RB10_P1EXT 0x30 /* page 1 extension */ +#define RB10_P1EXT_SH 4 +#define RB10_P0EXT 0xc0 /* page 0 extension */ +#define RB10_P0EXT_SH 6 -#define REG_RB11 0x6f /* Miscellaneous */ -# define RB11_MASK 0xe6 /* 111R R11R */ -# define RB11_GA20 0x02 /* gate for A20 */ -# define RB11_RASTMO 0x04 /* enable RAS timeout counter */ -# define RB11_EMSLEN 0xe0 /* EMS memory chunk size */ -# define RB11_EMSLEN_SH 5 +#define REG_RB11 0x6f /* Miscellaneous */ +#define RB11_MASK 0xe6 /* 111R R11R */ +#define RB11_GA20 0x02 /* gate for A20 */ +#define RB11_RASTMO 0x04 /* enable RAS timeout counter */ +#define RB11_EMSLEN 0xe0 /* EMS memory chunk size */ +#define RB11_EMSLEN_SH 5 typedef struct { - int8_t enabled; /* 1=ENABLED */ - char pad; - uint16_t page; /* selected page in EMS block */ - uint32_t start; /* start of EMS in RAM */ - uint8_t *addr; /* start addr in EMS RAM */ - mem_mapping_t mapping; /* mapping entry for page */ + int8_t enabled; /* 1=ENABLED */ + char pad; + uint16_t page; /* selected page in EMS block */ + uint32_t start; /* start of EMS in RAM */ + uint8_t *addr; /* start addr in EMS RAM */ + mem_mapping_t mapping; /* mapping entry for page */ } emspage_t; typedef struct { - uint8_t regs[128]; /* all the CS8221 registers */ - uint8_t indx; /* programmed index into registers */ + uint8_t regs[128]; /* all the CS8221 registers */ + uint8_t indx; /* programmed index into registers */ - char pad; + char pad; - uint16_t ems_base, /* configured base address */ - ems_oldbase; - uint32_t ems_frame, /* configured frame address */ - ems_oldframe; - uint16_t ems_size, /* EMS size in KB */ - ems_pages; /* EMS size in pages */ - emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */ + uint16_t ems_base, /* configured base address */ + ems_oldbase; + uint32_t ems_frame, /* configured frame address */ + ems_oldframe; + uint16_t ems_size, /* EMS size in KB */ + ems_pages; /* EMS size in pages */ + emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */ } neat_t; - #ifdef ENABLE_NEAT_LOG int neat_do_log = ENABLE_NEAT_LOG; - static void neat_log(const char *fmt, ...) { - va_list ap; + va_list ap; - if (neat_do_log) - { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); - } + if (neat_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } } #else -#define neat_log(fmt, ...) +# define neat_log(fmt, ...) #endif - /* Read one byte from paged RAM. */ static uint8_t ems_readb(uint32_t addr, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; uint8_t ret = 0xff; /* Grab the data. */ - ret = *(uint8_t *)(dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)); + ret = *(uint8_t *) (dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)); - return(ret); + return (ret); } /* Read one word from paged RAM. */ static uint16_t ems_readw(uint32_t addr, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; uint16_t ret = 0xffff; /* Grab the data. */ - ret = *(uint16_t *)(dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)); + ret = *(uint16_t *) (dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)); - return(ret); + return (ret); } /* Write one byte to paged RAM. */ static void ems_writeb(uint32_t addr, uint8_t val, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; /* Write the data. */ - *(uint8_t *)(dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)) = val; + *(uint8_t *) (dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)) = val; } /* Write one word to paged RAM. */ static void ems_writew(uint32_t addr, uint16_t val, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; /* Write the data. */ - *(uint16_t *)(dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)) = val; + *(uint16_t *) (dev->ems[((addr & 0xffff) >> 14)].addr + (addr & 0x3fff)) = val; } /* Re-calculate the active-page physical address. */ @@ -297,36 +291,36 @@ static void ems_recalc(neat_t *dev, emspage_t *ems) { if (ems->page >= dev->ems_pages) { - /* That page does not exist. */ - ems->enabled = 0; + /* That page does not exist. */ + ems->enabled = 0; } /* Pre-calculate the page address in EMS RAM. */ ems->addr = ram + ems->start + (ems->page * EMS_PGSIZE); if (ems->enabled) { - /* Update the EMS RAM address for this page. */ - mem_mapping_set_exec(&ems->mapping, ems->addr); + /* Update the EMS RAM address for this page. */ + mem_mapping_set_exec(&ems->mapping, ems->addr); - /* Enable this page. */ - mem_mapping_enable(&ems->mapping); + /* Enable this page. */ + mem_mapping_enable(&ems->mapping); #if NEAT_DEBUG > 1 - neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n", - ems->page, ems->addr-ram, ems->enabled?"en":"dis"); + neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n", + ems->page, ems->addr - ram, ems->enabled ? "en" : "dis"); #endif } else { - /* Disable this page. */ - mem_mapping_disable(&ems->mapping); + /* Disable this page. */ + mem_mapping_disable(&ems->mapping); } } static void ems_write(uint16_t port, uint8_t val, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; emspage_t *ems; - int vpage; + int vpage; #if NEAT_DEBUG > 1 neat_log("NEAT: ems_write(%04x, %02x)\n", port, val); @@ -334,42 +328,42 @@ ems_write(uint16_t port, uint8_t val, void *priv) /* Get the viewport page number. */ vpage = (port / EMS_PGSIZE); - ems = &dev->ems[vpage]; + ems = &dev->ems[vpage]; - switch(port & 0x000f) { - case 0x0008: - case 0x0009: - ems->enabled = !!(val & 0x80); - ems->page &= 0x0180; /* clear lower bits */ - ems->page |= (val & 0x7f); /* add new bits */ - ems_recalc(dev, ems); - break; + switch (port & 0x000f) { + case 0x0008: + case 0x0009: + ems->enabled = !!(val & 0x80); + ems->page &= 0x0180; /* clear lower bits */ + ems->page |= (val & 0x7f); /* add new bits */ + ems_recalc(dev, ems); + break; } } static uint8_t ems_read(uint16_t port, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; uint8_t ret = 0xff; - int vpage; + int vpage; /* Get the viewport page number. */ vpage = (port / EMS_PGSIZE); - switch(port & 0x000f) { - case 0x0008: /* page number register */ - ret = dev->ems[vpage].page & 0x7f; - if (dev->ems[vpage].enabled) - ret |= 0x80; - break; + switch (port & 0x000f) { + case 0x0008: /* page number register */ + ret = dev->ems[vpage].page & 0x7f; + if (dev->ems[vpage].enabled) + ret |= 0x80; + break; } #if NEAT_DEBUG > 1 neat_log("NEAT: ems_read(%04x) = %02x\n", port, ret); #endif - return(ret); + return (ret); } /* Initialize the EMS module. */ @@ -379,29 +373,30 @@ ems_init(neat_t *dev, int en) int i; /* Remove if needed. */ - if (! en) { - if (dev->ems_base > 0) for (i = 0; i < EMS_MAXPAGE; i++) { - /* Disable for now. */ - mem_mapping_disable(&dev->ems[i].mapping); + if (!en) { + if (dev->ems_base > 0) + for (i = 0; i < EMS_MAXPAGE; i++) { + /* Disable for now. */ + mem_mapping_disable(&dev->ems[i].mapping); - /* Remove I/O handler. */ - io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2, - ems_read,NULL,NULL, ems_write,NULL,NULL, dev); - } + /* Remove I/O handler. */ + io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2, + ems_read, NULL, NULL, ems_write, NULL, NULL, dev); + } #ifdef ENABLE_NEAT_LOG - neat_log("NEAT: EMS disabled\n"); + neat_log("NEAT: EMS disabled\n"); #endif - return; + return; } /* Get configured I/O address. */ - i = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; + i = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH; dev->ems_base = 0x0208 + (0x10 * i); /* Get configured frame address. */ - i = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; + i = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH; dev->ems_frame = 0xC0000 + (EMS_PGSIZE * i); /* @@ -410,253 +405,249 @@ ems_init(neat_t *dev, int en) * up the I/O control handler. */ for (i = 0; i < EMS_MAXPAGE; i++) { - /* Create and initialize a page mapping. */ - mem_mapping_add(&dev->ems[i].mapping, - dev->ems_frame + (EMS_PGSIZE*i), EMS_PGSIZE, - ems_readb, ems_readw, NULL, - ems_writeb, ems_writew, NULL, - ram, MEM_MAPPING_EXTERNAL, - dev); + /* Create and initialize a page mapping. */ + mem_mapping_add(&dev->ems[i].mapping, + dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE, + ems_readb, ems_readw, NULL, + ems_writeb, ems_writew, NULL, + ram, MEM_MAPPING_EXTERNAL, + dev); - /* Disable for now. */ - mem_mapping_disable(&dev->ems[i].mapping); + /* Disable for now. */ + mem_mapping_disable(&dev->ems[i].mapping); - /* Set up an I/O port handler. */ - io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2, - ems_read,NULL,NULL, ems_write,NULL,NULL, dev); + /* Set up an I/O port handler. */ + io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2, + ems_read, NULL, NULL, ems_write, NULL, NULL, dev); - /* - * TODO: update the 'high_mem' mapping to reflect that we now - * have NN MB less extended memory available.. - */ + /* + * TODO: update the 'high_mem' mapping to reflect that we now + * have NN MB less extended memory available.. + */ } neat_log("NEAT: EMS enabled, I/O=%04xH, Frame=%05XH\n", - dev->ems_base, dev->ems_frame); + dev->ems_base, dev->ems_frame); } static void neat_write(uint16_t port, uint8_t val, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; uint8_t xval, *reg; - int i; + int i; #if NEAT_DEBUG > 2 neat_log("NEAT: write(%04x, %02x)\n", port, val); #endif switch (port) { - case 0x22: - dev->indx = val; - break; + case 0x22: + dev->indx = val; + break; - case 0x23: - reg = &dev->regs[dev->indx]; - xval = *reg ^ val; - switch (dev->indx) { - case REG_RA0: - val &= RA0_MASK; - *reg = (*reg & ~RA0_MASK) | val | \ - (RA0_REV_ID << RA0_REV_SH); + case 0x23: + reg = &dev->regs[dev->indx]; + xval = *reg ^ val; + switch (dev->indx) { + case REG_RA0: + val &= RA0_MASK; + *reg = (*reg & ~RA0_MASK) | val | (RA0_REV_ID << RA0_REV_SH); #if NEAT_DEBUG > 1 - neat_log("NEAT: RA0=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RA0=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RA1: - val &= RA1_MASK; - *reg = (*reg & ~RA1_MASK) | val; + case REG_RA1: + val &= RA1_MASK; + *reg = (*reg & ~RA1_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RA1=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RA1=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RA2: - val &= RA2_MASK; - *reg = (*reg & ~RA2_MASK) | val; + case REG_RA2: + val &= RA2_MASK; + *reg = (*reg & ~RA2_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RA2=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RA2=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB0: - val &= RB0_MASK; - *reg = (*reg & ~RB0_MASK) | val | \ - (RB0_REV_ID << RB0_REV_SH); + case REG_RB0: + val &= RB0_MASK; + *reg = (*reg & ~RB0_MASK) | val | (RB0_REV_ID << RB0_REV_SH); #if NEAT_DEBUG > 1 - neat_log("NEAT: RB0=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB0=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB1: - val &= RB1_MASK; - *reg = (*reg & ~RB1_MASK) | val; + case REG_RB1: + val &= RB1_MASK; + *reg = (*reg & ~RB1_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB1=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB1=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB2: - val &= RB2_MASK; - *reg = (*reg & ~RB2_MASK) | val; + case REG_RB2: + val &= RB2_MASK; + *reg = (*reg & ~RB2_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB3: - val &= RB3_MASK; - *reg = (*reg & ~RB3_MASK) | val; + case REG_RB3: + val &= RB3_MASK; + *reg = (*reg & ~RB3_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB3=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB3=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB4: - val &= RB4_MASK; - *reg = (*reg & ~RB4_MASK) | val; + case REG_RB4: + val &= RB4_MASK; + *reg = (*reg & ~RB4_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB4=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB4=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB5: - val &= RB5_MASK; - *reg = (*reg & ~RB5_MASK) | val; + case REG_RB5: + val &= RB5_MASK; + *reg = (*reg & ~RB5_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB5=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB5=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB6: - val &= RB6_MASK; - *reg = (*reg & ~RB6_MASK) | val; + case REG_RB6: + val &= RB6_MASK; + *reg = (*reg & ~RB6_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB6=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB6=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB7: - val &= RB7_MASK; - *reg = val; + case REG_RB7: + val &= RB7_MASK; + *reg = val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg); #endif - if (val & RB7_EMSEN) - ems_init(dev, 1); - else if (xval & RB7_EMSEN) - ems_init(dev, 0); + if (val & RB7_EMSEN) + ems_init(dev, 1); + else if (xval & RB7_EMSEN) + ems_init(dev, 0); - if (xval & RB7_UMAREL) { - if (val & RB7_UMAREL) - mem_remap_top(384); - else - mem_remap_top(0); - } - break; + if (xval & RB7_UMAREL) { + if (val & RB7_UMAREL) + mem_remap_top(384); + else + mem_remap_top(0); + } + break; - case REG_RB8: - val &= RB8_MASK; - *reg = (*reg & ~RB8_MASK) | val; + case REG_RB8: + val &= RB8_MASK; + *reg = (*reg & ~RB8_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB8=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB8=%02x(%02x)\n", val, *reg); #endif - break; + break; - case REG_RB9: - val &= RB9_MASK; - *reg = (*reg & ~RB9_MASK) | val; + case REG_RB9: + val &= RB9_MASK; + *reg = (*reg & ~RB9_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg); #endif - if (dev->regs[REG_RB7] & RB7_EMSEN) { - ems_init(dev, 0); - ems_init(dev, 1); - } - break; + if (dev->regs[REG_RB7] & RB7_EMSEN) { + ems_init(dev, 0); + ems_init(dev, 1); + } + break; - case REG_RB10: - val &= RB10_MASK; - *reg = (*reg & ~RB10_MASK) | val; + case REG_RB10: + val &= RB10_MASK; + *reg = (*reg & ~RB10_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg); #endif - dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21; - dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21; - dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21; - dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21; - for (i = 0; i < EMS_MAXPAGE; i++) - ems_recalc(dev, &dev->ems[i]); - break; + dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21; + dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21; + dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21; + dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21; + for (i = 0; i < EMS_MAXPAGE; i++) + ems_recalc(dev, &dev->ems[i]); + break; - case REG_RB11: - val &= RB11_MASK; - *reg = (*reg & ~RB11_MASK) | val; + case REG_RB11: + val &= RB11_MASK; + *reg = (*reg & ~RB11_MASK) | val; #if NEAT_DEBUG > 1 - neat_log("NEAT: RB11=%02x(%02x)\n", val, *reg); + neat_log("NEAT: RB11=%02x(%02x)\n", val, *reg); #endif - i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH; - switch(i) { - case 0: /* "less than 2MB" */ - dev->ems_size = 512; - break; + i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH; + switch (i) { + case 0: /* "less than 2MB" */ + dev->ems_size = 512; + break; - case 1: /* 1 MB */ - case 2: /* 2 MB */ - case 3: /* 3 MB */ - case 4: /* 4 MB */ - case 5: /* 5 MB */ - case 6: /* 6 MB */ - case 7: /* 7 MB */ - dev->ems_size = i << 10; - break; - } - dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE; - if (dev->regs[REG_RB7] & RB7_EMSEN) { - neat_log("NEAT: EMS %iKB (%i pages)\n", - dev->ems_size, dev->ems_pages); - } - break; + case 1: /* 1 MB */ + case 2: /* 2 MB */ + case 3: /* 3 MB */ + case 4: /* 4 MB */ + case 5: /* 5 MB */ + case 6: /* 6 MB */ + case 7: /* 7 MB */ + dev->ems_size = i << 10; + break; + } + dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE; + if (dev->regs[REG_RB7] & RB7_EMSEN) { + neat_log("NEAT: EMS %iKB (%i pages)\n", + dev->ems_size, dev->ems_pages); + } + break; - default: - neat_log("NEAT: inv write to reg %02x (%02x)\n", - dev->indx, val); - break; - } - break; + default: + neat_log("NEAT: inv write to reg %02x (%02x)\n", + dev->indx, val); + break; + } + break; } } - static uint8_t neat_read(uint16_t port, void *priv) { - neat_t *dev = (neat_t *)priv; + neat_t *dev = (neat_t *) priv; uint8_t ret = 0xff; switch (port) { - case 0x22: - ret = dev->indx; - break; + case 0x22: + ret = dev->indx; + break; - case 0x23: - ret = dev->regs[dev->indx]; - break; + case 0x23: + ret = dev->regs[dev->indx]; + break; - default: - break; + default: + break; } #if NEAT_DEBUG > 2 neat_log("NEAT: read(%04x) = %02x\n", port, ret); #endif - return(ret); + return (ret); } - static void neat_close(void *priv) { @@ -665,21 +656,20 @@ neat_close(void *priv) free(dev); } - static void * neat_init(const device_t *info) { neat_t *dev; - int i; + int i; /* Create an instance. */ - dev = (neat_t *)malloc(sizeof(neat_t)); + dev = (neat_t *) malloc(sizeof(neat_t)); memset(dev, 0x00, sizeof(neat_t)); /* Initialize some of the registers to specific defaults. */ for (i = REG_RA0; i <= REG_RB11; i++) { - dev->indx = i; - neat_write(0x0023, 0x00, dev); + dev->indx = i; + neat_write(0x0023, 0x00, dev); } /* @@ -690,150 +680,150 @@ neat_init(const device_t *info) * bits, based on our cpu speed. */ i = 0; - switch(mem_size) { - case 512: /* 512KB */ - /* 256K, 0, 0, 0 */ - dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_NONE<regs[REG_RB6] &= ~RB6_BANKS; /* one bank */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */ + i = 2; + break; - case 640: /* 640KB */ - /* 256K, 64K, 0, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_MIXED<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_NONE<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */ + i = 4; + break; - case 1024: /* 1MB */ - /* 256K, 256K, 0, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_NONE<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */ + i = 5; + break; - case 1536: /* 1.5MB */ - /* 256K, 256K, 256K, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_256K<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + i = 7; + break; - case 1664: /* 1.64MB */ - /* 256K, 64K, 256K, 256K */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_MIXED<regs[REG_RB8] |= RB8_BANKS; /* two banks */ - dev->regs[REG_RB8] |= (RTYPE_256K<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */ + dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */ + dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + i = 10; + break; - case 2048: /* 2MB */ + case 2048: /* 2MB */ #if 1 - /* 256K, 256K, 256K, 256K */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] |= RB8_BANKS; /* two banks */ - dev->regs[REG_RB8] |= (RTYPE_256K<regs[REG_RB8] |= RB8_4WAY; /* 4way intl */ - i = 11; + /* 256K, 256K, 256K, 256K */ + dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */ + dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */ + i = 11; #else - /* 1M, 0, 0, 0 */ - dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */ - dev->regs[REG_RB6] |= (RTYPE_1M<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_NONE<regs[REG_RB6] &= ~RB6_BANKS; /* one bank */ + dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */ + i = 3; #endif - break; + break; - case 3072: /* 3MB */ - /* 256K, 256K, 1M, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_1M<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + i = 8; + break; - case 4096: /* 4MB */ - /* 1M, 1M, 0, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_1M<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_NONE<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */ + i = 6; + break; - case 4224: /* 4.64MB */ - /* 256K, 64K, 1M, 1M */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_MIXED<regs[REG_RB8] |= RB8_BANKS; /* two banks */ - dev->regs[REG_RB8] |= (RTYPE_1M<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */ + dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */ + dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + i = 12; + break; - case 5120: /* 5MB */ - /* 256K, 256K, 1M, 1M */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_256K<regs[REG_RB8] |= RB8_BANKS; /* two banks */ - dev->regs[REG_RB8] |= (RTYPE_1M<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */ + dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */ + dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + i = 13; + break; - case 6144: /* 6MB */ - /* 1M, 1M, 1M, 0 */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_1M<regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ - dev->regs[REG_RB8] |= (RTYPE_1M<regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */ + dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + i = 9; + break; - case 8192: /* 8MB */ - /* 1M, 1M, 1M, 1M */ - dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ - dev->regs[REG_RB6] |= (RTYPE_1M<regs[REG_RB8] |= RB8_BANKS; /* two banks */ - dev->regs[REG_RB8] |= (RTYPE_1M<regs[REG_RB8] |= RB8_4WAY; /* 4way intl */ - i = 14; - break; + case 8192: /* 8MB */ + /* 1M, 1M, 1M, 1M */ + dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */ + dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */ + dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */ + dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */ + i = 14; + break; - default: - neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size); + default: + neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size); } if (i > 0) { - neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size); + neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size); } /* Set up an I/O handler for the chipset. */ io_sethandler(0x0022, 2, - neat_read,NULL,NULL, neat_write,NULL,NULL, dev); + neat_read, NULL, NULL, neat_write, NULL, NULL, dev); return dev; } const device_t neat_device = { - .name = "C&T CS8121 (NEAT)", + .name = "C&T CS8121 (NEAT)", .internal_name = "neat", - .flags = 0, - .local = 0, - .init = neat_init, - .close = neat_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = neat_init, + .close = neat_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/olivetti_eva.c b/src/chipset/olivetti_eva.c index 0728d44e5..b06030508 100644 --- a/src/chipset/olivetti_eva.c +++ b/src/chipset/olivetti_eva.c @@ -16,7 +16,6 @@ * Copyright 2020-2021 EngiNerd */ - #include #include #include @@ -35,8 +34,8 @@ typedef struct { - uint8_t reg_065; - uint8_t reg_067; + uint8_t reg_065; + uint8_t reg_067; uint8_t reg_069; } olivetti_eva_t; @@ -50,11 +49,11 @@ olivetti_eva_log(const char *fmt, ...) if (olivetti_eva_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); - va_end(ap); + va_end(ap); } } #else -#define olivetti_eva_log(fmt, ...) +# define olivetti_eva_log(fmt, ...) #endif static void @@ -98,7 +97,7 @@ static uint8_t olivetti_eva_read(uint16_t addr, void *priv) { olivetti_eva_t *dev = (olivetti_eva_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; switch (addr) { case 0x065: ret = dev->reg_065; @@ -115,7 +114,6 @@ olivetti_eva_read(uint16_t addr, void *priv) return ret; } - static void olivetti_eva_close(void *priv) { @@ -157,15 +155,15 @@ olivetti_eva_init(const device_t *info) } const device_t olivetti_eva_device = { - .name = "Olivetti EVA Gate Array", + .name = "Olivetti EVA Gate Array", .internal_name = "olivetta_eva", - .flags = 0, - .local = 0, - .init = olivetti_eva_init, - .close = olivetti_eva_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = olivetti_eva_init, + .close = olivetti_eva_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti283.c b/src/chipset/opti283.c index 8e9403c29..7053e2f2f 100644 --- a/src/chipset/opti283.c +++ b/src/chipset/opti283.c @@ -30,7 +30,6 @@ #include <86box/mem.h> #include <86box/chipset.h> - #ifdef ENABLE_OPTI283_LOG int opti283_do_log = ENABLE_OPTI283_LOG; @@ -39,33 +38,29 @@ opti283_log(const char *fmt, ...) { va_list ap; - if (opti283_do_log) - { + if (opti283_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define opti283_log(fmt, ...) +# define opti283_log(fmt, ...) #endif - typedef struct { - uint32_t phys, virt; + uint32_t phys, virt; } mem_remapping_t; - typedef struct { - uint8_t index, shadow_high, - regs[256]; - mem_remapping_t mem_remappings[2]; - mem_mapping_t mem_mappings[2]; + uint8_t index, shadow_high, + regs[256]; + mem_remapping_t mem_remappings[2]; + mem_mapping_t mem_mappings[2]; } opti283_t; - static uint8_t opti283_read_remapped_ram(uint32_t addr, void *priv) { @@ -74,7 +69,6 @@ opti283_read_remapped_ram(uint32_t addr, void *priv) return mem_read_ram((addr - dev->virt) + dev->phys, priv); } - static uint16_t opti283_read_remapped_ramw(uint32_t addr, void *priv) { @@ -83,7 +77,6 @@ opti283_read_remapped_ramw(uint32_t addr, void *priv) return mem_read_ramw((addr - dev->virt) + dev->phys, priv); } - static uint32_t opti283_read_remapped_raml(uint32_t addr, void *priv) { @@ -92,7 +85,6 @@ opti283_read_remapped_raml(uint32_t addr, void *priv) return mem_read_raml((addr - dev->virt) + dev->phys, priv); } - static void opti283_write_remapped_ram(uint32_t addr, uint8_t val, void *priv) { @@ -101,7 +93,6 @@ opti283_write_remapped_ram(uint32_t addr, uint8_t val, void *priv) mem_write_ram((addr - dev->virt) + dev->phys, val, priv); } - static void opti283_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv) { @@ -110,7 +101,6 @@ opti283_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv) mem_write_ramw((addr - dev->virt) + dev->phys, val, priv); } - static void opti283_write_remapped_raml(uint32_t addr, uint32_t val, void *priv) { @@ -119,161 +109,157 @@ opti283_write_remapped_raml(uint32_t addr, uint32_t val, void *priv) mem_write_raml((addr - dev->virt) + dev->phys, val, priv); } - static void opti283_shadow_recalc(opti283_t *dev) { uint32_t i, base; uint32_t rbase; - uint8_t sh_enable, sh_mode; - uint8_t rom, sh_copy; + uint8_t sh_enable, sh_mode; + uint8_t rom, sh_copy; shadowbios = shadowbios_write = 0; - dev->shadow_high = 0; + dev->shadow_high = 0; opti283_log("OPTI 283: %02X %02X %02X %02X\n", dev->regs[0x11], dev->regs[0x12], dev->regs[0x13], dev->regs[0x14]); if (dev->regs[0x11] & 0x80) { - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - opti283_log("OPTI 283: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n"); - shadowbios_write = 1; + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n"); + shadowbios_write = 1; } else { - shadowbios = 1; - if (dev->regs[0x14] & 0x80) { - mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_INTERNAL\n"); - shadowbios_write = 1; - } else { - mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_DISABLED\n"); - } + shadowbios = 1; + if (dev->regs[0x14] & 0x80) { + mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_INTERNAL\n"); + shadowbios_write = 1; + } else { + mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_DISABLED\n"); + } - mem_set_mem_state_both(0xf1000, 0x0f000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - opti283_log("OPTI 283: F1000-FFFFF READ_INTERNAL, WRITE_DISABLED\n"); + mem_set_mem_state_both(0xf1000, 0x0f000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + opti283_log("OPTI 283: F1000-FFFFF READ_INTERNAL, WRITE_DISABLED\n"); } sh_copy = dev->regs[0x11] & 0x08; for (i = 0; i < 12; i++) { - base = 0xc0000 + (i << 14); - if (i >= 4) - sh_enable = dev->regs[0x12] & (1 << (i - 4)); - else - sh_enable = dev->regs[0x13] & (1 << (i + 4)); - sh_mode = dev->regs[0x11] & (1 << (i >> 2)); - rom = dev->regs[0x11] & (1 << ((i >> 2) + 4)); - opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4))); + base = 0xc0000 + (i << 14); + if (i >= 4) + sh_enable = dev->regs[0x12] & (1 << (i - 4)); + else + sh_enable = dev->regs[0x13] & (1 << (i + 4)); + sh_mode = dev->regs[0x11] & (1 << (i >> 2)); + rom = dev->regs[0x11] & (1 << ((i >> 2) + 4)); + opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4))); - if (sh_enable && rom) { - if (base >= 0x000e0000) - shadowbios |= 1; - if (base >= 0x000d0000) - dev->shadow_high |= 1; + if (sh_enable && rom) { + if (base >= 0x000e0000) + shadowbios |= 1; + if (base >= 0x000d0000) + dev->shadow_high |= 1; - if (sh_mode) { - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); - } else { - if (base >= 0x000e0000) - shadowbios_write |= 1; + if (sh_mode) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); + } else { + if (base >= 0x000e0000) + shadowbios_write |= 1; - if (sh_copy) { - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); - } else { - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); - opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff); - } - } - } else { - if (base >= 0xe0000) { - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED); - opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff); - } else { - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED); - opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); - } - } + if (sh_copy) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); + } else { + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); + opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff); + } + } + } else { + if (base >= 0xe0000) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED); + opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff); + } else { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED); + opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); + } + } } rbase = ((uint32_t) (dev->regs[0x13] & 0x0f)) << 20; if (rbase > 0) { - dev->mem_remappings[0].virt = rbase; - mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000); + dev->mem_remappings[0].virt = rbase; + mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000); - if (!dev->shadow_high) { - rbase += 0x00020000; - dev->mem_remappings[1].virt = rbase; - mem_mapping_set_addr(&dev->mem_mappings[1], rbase , 0x00020000); - } else - mem_mapping_disable(&dev->mem_mappings[1]); + if (!dev->shadow_high) { + rbase += 0x00020000; + dev->mem_remappings[1].virt = rbase; + mem_mapping_set_addr(&dev->mem_mappings[1], rbase, 0x00020000); + } else + mem_mapping_disable(&dev->mem_mappings[1]); } else { - mem_mapping_disable(&dev->mem_mappings[0]); - mem_mapping_disable(&dev->mem_mappings[1]); + mem_mapping_disable(&dev->mem_mappings[0]); + mem_mapping_disable(&dev->mem_mappings[1]); } flushmmucache_nopc(); } - static void opti283_write(uint16_t addr, uint8_t val, void *priv) { - opti283_t *dev = (opti283_t *)priv; + opti283_t *dev = (opti283_t *) priv; switch (addr) { - case 0x22: - dev->index = val; - break; + case 0x22: + dev->index = val; + break; - case 0x24: - opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); + case 0x24: + opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); - switch (dev->index) { - case 0x10: - dev->regs[dev->index] = val; - break; + switch (dev->index) { + case 0x10: + dev->regs[dev->index] = val; + break; - case 0x14: - reset_on_hlt = !!(val & 0x40); - /* FALLTHROUGH */ - case 0x11: case 0x12: - case 0x13: - dev->regs[dev->index] = val; - opti283_shadow_recalc(dev); - break; - } - break; + case 0x14: + reset_on_hlt = !!(val & 0x40); + /* FALLTHROUGH */ + case 0x11: + case 0x12: + case 0x13: + dev->regs[dev->index] = val; + opti283_shadow_recalc(dev); + break; + } + break; } } - static uint8_t opti283_read(uint16_t addr, void *priv) { - opti283_t *dev = (opti283_t *)priv; - uint8_t ret = 0xff; + opti283_t *dev = (opti283_t *) priv; + uint8_t ret = 0xff; if (addr == 0x24) - ret = dev->regs[dev->index]; + ret = dev->regs[dev->index]; return ret; } - static void opti283_close(void *priv) { - opti283_t *dev = (opti283_t *)priv; + opti283_t *dev = (opti283_t *) priv; free(dev); } - static void * opti283_init(const device_t *info) { - opti283_t *dev = (opti283_t *)malloc(sizeof(opti283_t)); + opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t)); memset(dev, 0x00, sizeof(opti283_t)); io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev); @@ -286,14 +272,14 @@ opti283_init(const device_t *info) dev->mem_remappings[1].phys = 0x000d0000; mem_mapping_add(&dev->mem_mappings[0], 0, 0x00020000, - opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml, - opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml, + opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml, + opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml, &ram[dev->mem_remappings[0].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[0]); mem_mapping_disable(&dev->mem_mappings[0]); mem_mapping_add(&dev->mem_mappings[1], 0, 0x00020000, - opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml, - opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml, + opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml, + opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml, &ram[dev->mem_remappings[1].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[1]); mem_mapping_disable(&dev->mem_mappings[1]); @@ -303,15 +289,15 @@ opti283_init(const device_t *info) } const device_t opti283_device = { - .name = "OPTi 82C283", + .name = "OPTi 82C283", .internal_name = "opti283", - .flags = 0, - .local = 0, - .init = opti283_init, - .close = opti283_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti283_init, + .close = opti283_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti291.c b/src/chipset/opti291.c index 6bf8851e7..52a2803aa 100644 --- a/src/chipset/opti291.c +++ b/src/chipset/opti291.c @@ -34,128 +34,125 @@ int opti291_do_log = ENABLE_OPTI291_LOG; static void opti291_log(const char *fmt, ...) { - va_list ap; + va_list ap; - if (opti291_do_log) - { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); - } + if (opti291_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } } #else -#define opti291_log(fmt, ...) +# define opti291_log(fmt, ...) #endif typedef struct { - uint8_t index, regs[256]; - port_92_t *port_92; + uint8_t index, regs[256]; + port_92_t *port_92; } opti291_t; -static void opti291_recalc(opti291_t *dev) +static void +opti291_recalc(opti291_t *dev) { - mem_set_mem_state_both(0xf0000, 0x10000, (!(dev->regs[0x23] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); + mem_set_mem_state_both(0xf0000, 0x10000, (!(dev->regs[0x23] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); - for (uint32_t i = 0; i < 4; i++) - { - mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x26] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : ((dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); - mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, ((dev->regs[0x25] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : ((dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); - mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, ((dev->regs[0x24] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : ((dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); - } - flushmmucache(); + for (uint32_t i = 0; i < 4; i++) { + mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x26] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : ((dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); + mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, ((dev->regs[0x25] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : ((dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); + mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, ((dev->regs[0x24] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : ((dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))); + } + flushmmucache(); } static void opti291_write(uint16_t addr, uint8_t val, void *priv) { - opti291_t *dev = (opti291_t *)priv; + opti291_t *dev = (opti291_t *) priv; - switch (addr) - { - case 0x22: - dev->index = val; - break; - case 0x24: - opti291_log("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val); - switch (dev->index) - { - case 0x20: - dev->regs[dev->index] = val & 0x3f; - break; - case 0x21: - dev->regs[dev->index] = val & 0xf3; - break; - case 0x22: - dev->regs[dev->index] = val; - break; - case 0x23: - case 0x24: - case 0x25: - case 0x26: - dev->regs[dev->index] = val; - opti291_recalc(dev); - break; - case 0x27: - case 0x28: - dev->regs[dev->index] = val; - break; - case 0x29: - dev->regs[dev->index] = val & 0x0f; - break; - case 0x2a: - case 0x2b: - case 0x2c: - dev->regs[dev->index] = val; - break; - } - break; - } + switch (addr) { + case 0x22: + dev->index = val; + break; + case 0x24: + opti291_log("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val); + switch (dev->index) { + case 0x20: + dev->regs[dev->index] = val & 0x3f; + break; + case 0x21: + dev->regs[dev->index] = val & 0xf3; + break; + case 0x22: + dev->regs[dev->index] = val; + break; + case 0x23: + case 0x24: + case 0x25: + case 0x26: + dev->regs[dev->index] = val; + opti291_recalc(dev); + break; + case 0x27: + case 0x28: + dev->regs[dev->index] = val; + break; + case 0x29: + dev->regs[dev->index] = val & 0x0f; + break; + case 0x2a: + case 0x2b: + case 0x2c: + dev->regs[dev->index] = val; + break; + } + break; + } } static uint8_t opti291_read(uint16_t addr, void *priv) { - opti291_t *dev = (opti291_t *)priv; + opti291_t *dev = (opti291_t *) priv; - return (addr == 0x24) ? dev->regs[dev->index] : 0xff; + return (addr == 0x24) ? dev->regs[dev->index] : 0xff; } static void opti291_close(void *priv) { - opti291_t *dev = (opti291_t *)priv; + opti291_t *dev = (opti291_t *) priv; - free(dev); + free(dev); } static void * opti291_init(const device_t *info) { - opti291_t *dev = (opti291_t *)malloc(sizeof(opti291_t)); - memset(dev, 0, sizeof(opti291_t)); + opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t)); + memset(dev, 0, sizeof(opti291_t)); - io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); - io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); - dev->regs[0x22] = 0xf0; - dev->regs[0x23] = 0x40; - dev->regs[0x28] = 0x08; - dev->regs[0x29] = 0xa0; - device_add(&port_92_device); - opti291_recalc(dev); + io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); + io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); + dev->regs[0x22] = 0xf0; + dev->regs[0x23] = 0x40; + dev->regs[0x28] = 0x08; + dev->regs[0x29] = 0xa0; + device_add(&port_92_device); + opti291_recalc(dev); - return dev; + return dev; } const device_t opti291_device = { - .name = "OPTi 82C291", + .name = "OPTi 82C291", .internal_name = "opti291", - .flags = 0, - .local = 0, - .init = opti291_init, - .close = opti291_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti291_init, + .close = opti291_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti391.c b/src/chipset/opti391.c index 51c8d9daa..b787fae8f 100644 --- a/src/chipset/opti391.c +++ b/src/chipset/opti391.c @@ -28,7 +28,6 @@ #include <86box/mem.h> #include <86box/chipset.h> - #ifdef ENABLE_OPTI391_LOG int opti391_do_log = ENABLE_OPTI391_LOG; @@ -37,160 +36,159 @@ opti391_log(const char *fmt, ...) { va_list ap; - if (opti391_do_log) - { + if (opti391_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define opti391_log(fmt, ...) +# define opti391_log(fmt, ...) #endif - typedef struct { - uint32_t phys, virt; + uint32_t phys, virt; } mem_remapping_t; - typedef struct { - uint8_t index, regs[256]; + uint8_t index, regs[256]; } opti391_t; - static void opti391_shadow_recalc(opti391_t *dev) { uint32_t i, base; - uint8_t sh_enable, sh_master; - uint8_t sh_wp, sh_write_internal; + uint8_t sh_enable, sh_master; + uint8_t sh_wp, sh_write_internal; shadowbios = shadowbios_write = 0; /* F0000-FFFFF */ sh_enable = !(dev->regs[0x22] & 0x80); if (sh_enable) - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); else - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); sh_write_internal = (dev->regs[0x26] & 0x40); /* D0000-EFFFF */ for (i = 0; i < 8; i++) { - base = 0xd0000 + (i << 14); - if (base >= 0xe0000) { - sh_master = (dev->regs[0x22] & 0x40); - sh_wp = (dev->regs[0x22] & 0x10); - } else { - sh_master = (dev->regs[0x22] & 0x20); - sh_wp = (dev->regs[0x22] & 0x08); - } - sh_enable = dev->regs[0x23] & (1 << i); + base = 0xd0000 + (i << 14); + if (base >= 0xe0000) { + sh_master = (dev->regs[0x22] & 0x40); + sh_wp = (dev->regs[0x22] & 0x10); + } else { + sh_master = (dev->regs[0x22] & 0x20); + sh_wp = (dev->regs[0x22] & 0x08); + } + sh_enable = dev->regs[0x23] & (1 << i); - if (sh_master) { - if (sh_enable) { - if (sh_wp) - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } else if (sh_write_internal) - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } else if (sh_write_internal) - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + if (sh_master) { + if (sh_enable) { + if (sh_wp) + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } else if (sh_write_internal) + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } else if (sh_write_internal) + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); } /* C0000-CFFFF */ sh_master = !(dev->regs[0x26] & 0x10); - sh_wp = (dev->regs[0x26] & 0x20); + sh_wp = (dev->regs[0x26] & 0x20); for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); - sh_enable = dev->regs[0x26] & (1 << i); + base = 0xc0000 + (i << 14); + sh_enable = dev->regs[0x26] & (1 << i); - if (sh_master) { - if (sh_enable) { - if (sh_wp) - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } else if (sh_write_internal) - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } else if (sh_write_internal) - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - else - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + if (sh_master) { + if (sh_enable) { + if (sh_wp) + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } else if (sh_write_internal) + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } else if (sh_write_internal) + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + else + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); } } - static void opti391_write(uint16_t addr, uint8_t val, void *priv) { - opti391_t *dev = (opti391_t *)priv; + opti391_t *dev = (opti391_t *) priv; switch (addr) { - case 0x22: - dev->index = val; - break; + case 0x22: + dev->index = val; + break; - case 0x24: - opti391_log("OPTi 391: dev->regs[%02x] = %02x\n", dev->index, val); + case 0x24: + opti391_log("OPTi 391: dev->regs[%02x] = %02x\n", dev->index, val); - switch (dev->index) { - case 0x20: - dev->regs[dev->index] = (dev->regs[dev->index] & 0xc0) | (val & 0x3f); - break; + switch (dev->index) { + case 0x20: + dev->regs[dev->index] = (dev->regs[dev->index] & 0xc0) | (val & 0x3f); + break; - case 0x21: case 0x24: case 0x25: case 0x27: - case 0x28: case 0x29: case 0x2a: case 0x2b: - dev->regs[dev->index] = val; - break; + case 0x21: + case 0x24: + case 0x25: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + dev->regs[dev->index] = val; + break; - case 0x22: case 0x23: - case 0x26: - dev->regs[dev->index] = val; - opti391_shadow_recalc(dev); - break; - } - break; + case 0x22: + case 0x23: + case 0x26: + dev->regs[dev->index] = val; + opti391_shadow_recalc(dev); + break; + } + break; } } - static uint8_t opti391_read(uint16_t addr, void *priv) { - opti391_t *dev = (opti391_t *)priv; - uint8_t ret = 0xff; + opti391_t *dev = (opti391_t *) priv; + uint8_t ret = 0xff; if (addr == 0x24) - ret = dev->regs[dev->index]; + ret = dev->regs[dev->index]; return ret; } - static void opti391_close(void *priv) { - opti391_t *dev = (opti391_t *)priv; + opti391_t *dev = (opti391_t *) priv; free(dev); } - static void * opti391_init(const device_t *info) { - opti391_t *dev = (opti391_t *)malloc(sizeof(opti391_t)); + opti391_t *dev = (opti391_t *) malloc(sizeof(opti391_t)); memset(dev, 0x00, sizeof(opti391_t)); io_sethandler(0x0022, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev); @@ -212,15 +210,15 @@ opti391_init(const device_t *info) } const device_t opti391_device = { - .name = "OPTi 82C391", + .name = "OPTi 82C391", .internal_name = "opti391", - .flags = 0, - .local = 0, - .init = opti391_init, - .close = opti391_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti391_init, + .close = opti391_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti495.c b/src/chipset/opti495.c index c02f9cc1f..627952d09 100644 --- a/src/chipset/opti495.c +++ b/src/chipset/opti495.c @@ -31,159 +31,151 @@ #include <86box/port_92.h> #include <86box/chipset.h> - typedef struct { - uint8_t idx, - regs[256], - scratch[2]; + uint8_t idx, + regs[256], + scratch[2]; } opti495_t; - #ifdef ENABLE_OPTI495_LOG int opti495_do_log = ENABLE_OPTI495_LOG; - static void opti495_log(const char *fmt, ...) { va_list ap; if (opti495_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define opti495_log(fmt, ...) +# define opti495_log(fmt, ...) #endif - static void opti495_recalc(opti495_t *dev) { uint32_t base; uint32_t i, shflags = 0; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; if (dev->regs[0x22] & 0x80) { - shadowbios = 1; - shadowbios_write = 0; - shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; + shadowbios = 1; + shadowbios_write = 0; + shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; } else { - shadowbios = 0; - shadowbios_write = 1; - shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; + shadowbios = 0; + shadowbios_write = 1; + shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; } mem_set_mem_state_both(0xf0000, 0x10000, shflags); for (i = 0; i < 8; i++) { - base = 0xd0000 + (i << 14); + base = 0xd0000 + (i << 14); - if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && - (dev->regs[0x23] & (1 << i))) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - if (dev->regs[0x26] & 0x40) { - shflags = MEM_READ_EXTANY; - shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else - shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; - } + if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + if (dev->regs[0x26] & 0x40) { + shflags = MEM_READ_EXTANY; + shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else + shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); + base = 0xc0000 + (i << 14); - if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - if (dev->regs[0x26] & 0x40) { - shflags = MEM_READ_EXTANY; - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else - shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; - } + if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + if (dev->regs[0x26] & 0x40) { + shflags = MEM_READ_EXTANY; + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else + shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } flushmmucache(); } - static void opti495_write(uint16_t addr, uint8_t val, void *priv) { opti495_t *dev = (opti495_t *) priv; switch (addr) { - case 0x22: - opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); - dev->idx = val; - break; - case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - dev->regs[dev->idx] = val; - opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); + case 0x22: + opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); + dev->idx = val; + break; + case 0x24: + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { + dev->regs[dev->idx] = val; + opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); - switch(dev->idx) { - case 0x21: - cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); - cpu_update_waitstates(); - break; + switch (dev->idx) { + case 0x21: + cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); + cpu_update_waitstates(); + break; - case 0x22: - case 0x23: - case 0x26: - opti495_recalc(dev); - break; - } - } - break; + case 0x22: + case 0x23: + case 0x26: + opti495_recalc(dev); + break; + } + } + break; - case 0xe1: - case 0xe2: - dev->scratch[~addr & 0x01] = val; - break; + case 0xe1: + case 0xe2: + dev->scratch[~addr & 0x01] = val; + break; } } - static uint8_t opti495_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; opti495_t *dev = (opti495_t *) priv; switch (addr) { - case 0x22: - opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); - break; - case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - ret = dev->regs[dev->idx]; - opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); - } - break; - case 0xe1: - case 0xe2: - ret = dev->scratch[~addr & 0x01]; - break; + case 0x22: + opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); + break; + case 0x24: + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { + ret = dev->regs[dev->idx]; + opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); + } + break; + case 0xe1: + case 0xe2: + ret = dev->scratch[~addr & 0x01]; + break; } return ret; } - static void opti495_close(void *priv) { @@ -192,7 +184,6 @@ opti495_close(void *priv) free(dev); } - static void * opti495_init(const device_t *info) { @@ -207,26 +198,26 @@ opti495_init(const device_t *info) dev->scratch[0] = dev->scratch[1] = 0xff; if (info->local == 1) { - /* 85C495 */ - dev->regs[0x20] = 0x02; - dev->regs[0x21] = 0x20; - dev->regs[0x22] = 0xe4; - dev->regs[0x25] = 0xf0; - dev->regs[0x26] = 0x80; - dev->regs[0x27] = 0xb1; - dev->regs[0x28] = 0x80; - dev->regs[0x29] = 0x10; + /* 85C495 */ + dev->regs[0x20] = 0x02; + dev->regs[0x21] = 0x20; + dev->regs[0x22] = 0xe4; + dev->regs[0x25] = 0xf0; + dev->regs[0x26] = 0x80; + dev->regs[0x27] = 0xb1; + dev->regs[0x28] = 0x80; + dev->regs[0x29] = 0x10; } else { - /* 85C493 */ - dev->regs[0x20] = 0x40; - dev->regs[0x22] = 0x84; - dev->regs[0x24] = 0x87; - dev->regs[0x25] = 0xf1; /* Note: 0xf0 is also valid default. */ - dev->regs[0x27] = 0x91; - dev->regs[0x28] = 0x80; - dev->regs[0x29] = 0x10; - dev->regs[0x2a] = 0x80; - dev->regs[0x2b] = 0x10; + /* 85C493 */ + dev->regs[0x20] = 0x40; + dev->regs[0x22] = 0x84; + dev->regs[0x24] = 0x87; + dev->regs[0x25] = 0xf1; /* Note: 0xf0 is also valid default. */ + dev->regs[0x27] = 0x91; + dev->regs[0x28] = 0x80; + dev->regs[0x29] = 0x10; + dev->regs[0x2a] = 0x80; + dev->regs[0x2b] = 0x10; } opti495_recalc(dev); @@ -237,29 +228,29 @@ opti495_init(const device_t *info) } const device_t opti493_device = { - .name = "OPTi 82C493", + .name = "OPTi 82C493", .internal_name = "opti493", - .flags = 0, - .local = 0, - .init = opti495_init, - .close = opti495_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti495_init, + .close = opti495_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t opti495_device = { - .name = "OPTi 82C495", + .name = "OPTi 82C495", .internal_name = "opti495", - .flags = 0, - .local = 1, - .init = opti495_init, - .close = opti495_close, - .reset = NULL, + .flags = 0, + .local = 1, + .init = opti495_init, + .close = opti495_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti499.c b/src/chipset/opti499.c index 08c06d58c..519b394a4 100644 --- a/src/chipset/opti499.c +++ b/src/chipset/opti499.c @@ -31,172 +31,167 @@ #include <86box/port_92.h> #include <86box/chipset.h> - typedef struct { - uint8_t idx, - regs[256], scratch[2]; + uint8_t idx, + regs[256], scratch[2]; } opti499_t; - #ifdef ENABLE_OPTI499_LOG int opti499_do_log = ENABLE_OPTI499_LOG; - static void opti499_log(const char *fmt, ...) { va_list ap; if (opti499_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define opti499_log(fmt, ...) +# define opti499_log(fmt, ...) #endif - static void opti499_recalc(opti499_t *dev) { uint32_t base; uint32_t i, shflags = 0; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; if (dev->regs[0x22] & 0x80) { - shadowbios = 1; - shadowbios_write = 0; - shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; + shadowbios = 1; + shadowbios_write = 0; + shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; } else { - shadowbios = 0; - shadowbios_write = 1; - shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; + shadowbios = 0; + shadowbios_write = 1; + shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; } mem_set_mem_state_both(0xf0000, 0x10000, shflags); for (i = 0; i < 8; i++) { - base = 0xd0000 + (i << 14); + base = 0xd0000 + (i << 14); - if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && - (dev->regs[0x23] & (1 << i))) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - if (dev->regs[0x2d] && (1 << ((i >> 1) + 2))) - shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; - else - shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL; - } + if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + if (dev->regs[0x2d] && (1 << ((i >> 1) + 2))) + shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; + else + shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL; + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); + base = 0xc0000 + (i << 14); - if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - if (dev->regs[0x26] & 0x40) { - if (dev->regs[0x2d] && (1 << (i >> 1))) - shflags = MEM_READ_EXTANY; - else - shflags = MEM_READ_EXTERNAL; - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - if (dev->regs[0x2d] && (1 << (i >> 1))) - shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; - else - shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL; - } - } + if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + if (dev->regs[0x26] & 0x40) { + if (dev->regs[0x2d] && (1 << (i >> 1))) + shflags = MEM_READ_EXTANY; + else + shflags = MEM_READ_EXTERNAL; + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + if (dev->regs[0x2d] && (1 << (i >> 1))) + shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY; + else + shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL; + } + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } flushmmucache_nopc(); } - static void opti499_write(uint16_t addr, uint8_t val, void *priv) { opti499_t *dev = (opti499_t *) priv; switch (addr) { - case 0x22: - opti499_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); - dev->idx = val; - break; - case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - if (dev->idx == 0x20) - dev->regs[dev->idx] = (dev->regs[dev->idx] & 0xc0) | (val & 0x3f); - else - dev->regs[dev->idx] = val; - opti499_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); + case 0x22: + opti499_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); + dev->idx = val; + break; + case 0x24: + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { + if (dev->idx == 0x20) + dev->regs[dev->idx] = (dev->regs[dev->idx] & 0xc0) | (val & 0x3f); + else + dev->regs[dev->idx] = val; + opti499_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); - switch(dev->idx) { - case 0x20: - reset_on_hlt = !(val & 0x02); - break; + switch (dev->idx) { + case 0x20: + reset_on_hlt = !(val & 0x02); + break; - case 0x21: - cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); - cpu_update_waitstates(); - break; + case 0x21: + cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); + cpu_update_waitstates(); + break; - case 0x22: case 0x23: - case 0x26: case 0x2d: - opti499_recalc(dev); - break; - } - } - break; + case 0x22: + case 0x23: + case 0x26: + case 0x2d: + opti499_recalc(dev); + break; + } + } + break; - case 0xe1: case 0xe2: - dev->scratch[~addr & 0x01] = val; - break; + case 0xe1: + case 0xe2: + dev->scratch[~addr & 0x01] = val; + break; } } - static uint8_t opti499_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; opti499_t *dev = (opti499_t *) priv; switch (addr) { - case 0x22: - opti499_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); - break; - case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { - if (dev->idx == 0x2d) - ret = dev->regs[dev->idx] & 0xbf; - else - ret = dev->regs[dev->idx]; - opti499_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); - } - break; - case 0xe1: - case 0xe2: - ret = dev->scratch[~addr & 0x01]; - break; + case 0x22: + opti499_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); + break; + case 0x24: + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { + if (dev->idx == 0x2d) + ret = dev->regs[dev->idx] & 0xbf; + else + ret = dev->regs[dev->idx]; + opti499_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); + } + break; + case 0xe1: + case 0xe2: + ret = dev->scratch[~addr & 0x01]; + break; } return ret; } - static void opti499_reset(void *priv) { @@ -213,7 +208,7 @@ opti499_reset(void *priv) dev->regs[0x27] = 0xd1; dev->regs[0x28] = dev->regs[0x2a] = 0x80; dev->regs[0x29] = dev->regs[0x2b] = 0x10; - dev->regs[0x2d] = 0x40; + dev->regs[0x2d] = 0x40; reset_on_hlt = 1; @@ -225,7 +220,6 @@ opti499_reset(void *priv) free(dev); } - static void opti499_close(void *priv) { @@ -234,7 +228,6 @@ opti499_close(void *priv) free(dev); } - static void * opti499_init(const device_t *info) { @@ -254,15 +247,15 @@ opti499_init(const device_t *info) } const device_t opti499_device = { - .name = "OPTi 82C499", + .name = "OPTi 82C499", .internal_name = "opti499", - .flags = 0, - .local = 1, - .init = opti499_init, - .close = opti499_close, - .reset = opti499_reset, + .flags = 0, + .local = 1, + .init = opti499_init, + .close = opti499_close, + .reset = opti499_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti5x7.c b/src/chipset/opti5x7.c index f0459a97f..d85ed4f54 100644 --- a/src/chipset/opti5x7.c +++ b/src/chipset/opti5x7.c @@ -45,43 +45,39 @@ opti5x7_log(const char *fmt, ...) { va_list ap; - if (opti5x7_do_log) - { + if (opti5x7_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define opti5x7_log(fmt, ...) +# define opti5x7_log(fmt, ...) #endif static void opti5x7_shadow_map(int cur_reg, opti5x7_t *dev) { -/* -Register 4h: Cxxxx Segment -Register 5h: Dxxxx Segment + /* + Register 4h: Cxxxx Segment + Register 5h: Dxxxx Segment -Bits 7-6: xC000-xFFFF -Bits 5-4: x8000-xBFFF -Bits 3-2: x4000-x7FFF -Bits 0-1: x0000-x3FFF + Bits 7-6: xC000-xFFFF + Bits 5-4: x8000-xBFFF + Bits 3-2: x4000-x7FFF + Bits 0-1: x0000-x3FFF - x-y - 0 0 Read/Write AT bus - 1 0 Read from AT - Write to DRAM - 1 1 Read from DRAM - Write to DRAM - 0 1 Read from DRAM (write protected) -*/ - if (cur_reg == 0x06) - { + x-y + 0 0 Read/Write AT bus + 1 0 Read from AT - Write to DRAM + 1 1 Read from DRAM - Write to DRAM + 0 1 Read from DRAM (write protected) + */ + if (cur_reg == 0x06) { mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); - } - else - { + } else { for (int i = 0; i < 4; i++) mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); } @@ -92,63 +88,61 @@ Bits 0-1: x0000-x3FFF static void opti5x7_write(uint16_t addr, uint8_t val, void *priv) { - opti5x7_t *dev = (opti5x7_t *)priv; + opti5x7_t *dev = (opti5x7_t *) priv; - switch (addr) - { - case 0x22: - dev->idx = val; - break; - case 0x24: - switch (dev->idx) - { - case 0x00: /* DRAM Configuration Register #1 */ - dev->regs[dev->idx] = val & 0x7f; + switch (addr) { + case 0x22: + dev->idx = val; break; - case 0x01: /* DRAM Control Register #1 */ - dev->regs[dev->idx] = val; + case 0x24: + switch (dev->idx) { + case 0x00: /* DRAM Configuration Register #1 */ + dev->regs[dev->idx] = val & 0x7f; + break; + case 0x01: /* DRAM Control Register #1 */ + dev->regs[dev->idx] = val; + break; + case 0x02: /* Cache Control Register #1 */ + dev->regs[dev->idx] = val; + cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c); + cpu_update_waitstates(); + break; + case 0x03: /* Cache Control Register #2 */ + dev->regs[dev->idx] = val; + break; + case 0x04: /* Shadow RAM Control Register #1 */ + case 0x05: /* Shadow RAM Control Register #2 */ + case 0x06: /* Shadow RAM Control Register #3 */ + dev->regs[dev->idx] = val; + opti5x7_shadow_map(dev->idx, dev); + break; + case 0x07: /* Tag Test Register */ + case 0x08: /* CPU Cache Control Register #1 */ + case 0x09: /* System Memory Function Register #1 */ + case 0x0a: /* System Memory Address Decode Register #1 */ + case 0x0b: /* System Memory Address Decode Register #2 */ + dev->regs[dev->idx] = val; + break; + case 0x0c: /* Extended DMA Register */ + dev->regs[dev->idx] = val & 0xcf; + break; + case 0x0d: /* ROMCS# Register */ + case 0x0e: /* Local Master Preemption Register */ + case 0x0f: /* Deturbo Control Register #1 */ + case 0x10: /* Cache Write-Hit Control Register */ + case 0x11: /* Master Cycle Control Register */ + dev->regs[dev->idx] = val; + break; + } + opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]); break; - case 0x02: /* Cache Control Register #1 */ - dev->regs[dev->idx] = val; - cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c); - cpu_update_waitstates(); - break; - case 0x03: /* Cache Control Register #2 */ - dev->regs[dev->idx] = val; - break; - case 0x04: /* Shadow RAM Control Register #1 */ - case 0x05: /* Shadow RAM Control Register #2 */ - case 0x06: /* Shadow RAM Control Register #3 */ - dev->regs[dev->idx] = val; - opti5x7_shadow_map(dev->idx, dev); - break; - case 0x07: /* Tag Test Register */ - case 0x08: /* CPU Cache Control Register #1 */ - case 0x09: /* System Memory Function Register #1 */ - case 0x0a: /* System Memory Address Decode Register #1 */ - case 0x0b: /* System Memory Address Decode Register #2 */ - dev->regs[dev->idx] = val; - break; - case 0x0c: /* Extended DMA Register */ - dev->regs[dev->idx] = val & 0xcf; - break; - case 0x0d: /* ROMCS# Register */ - case 0x0e: /* Local Master Preemption Register */ - case 0x0f: /* Deturbo Control Register #1 */ - case 0x10: /* Cache Write-Hit Control Register */ - case 0x11: /* Master Cycle Control Register */ - dev->regs[dev->idx] = val; - break; - } - opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]); - break; } } static uint8_t opti5x7_read(uint16_t addr, void *priv) { - opti5x7_t *dev = (opti5x7_t *)priv; + opti5x7_t *dev = (opti5x7_t *) priv; return (addr == 0x24) ? dev->regs[dev->idx] : 0xff; } @@ -156,7 +150,7 @@ opti5x7_read(uint16_t addr, void *priv) static void opti5x7_close(void *priv) { - opti5x7_t *dev = (opti5x7_t *)priv; + opti5x7_t *dev = (opti5x7_t *) priv; free(dev); } @@ -164,7 +158,7 @@ opti5x7_close(void *priv) static void * opti5x7_init(const device_t *info) { - opti5x7_t *dev = (opti5x7_t *)malloc(sizeof(opti5x7_t)); + opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t)); memset(dev, 0, sizeof(opti5x7_t)); io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); @@ -176,15 +170,15 @@ opti5x7_init(const device_t *info) } const device_t opti5x7_device = { - .name = "OPTi 82C5x6/82C5x7", + .name = "OPTi 82C5x6/82C5x7", .internal_name = "opti5x7", - .flags = 0, - .local = 0, - .init = opti5x7_init, - .close = opti5x7_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti5x7_init, + .close = opti5x7_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti822.c b/src/chipset/opti822.c index 0235e3ee9..cdcd2d2f8 100644 --- a/src/chipset/opti822.c +++ b/src/chipset/opti822.c @@ -33,9 +33,9 @@ #include <86box/chipset.h> /* Shadow RAM */ -#define SYSTEM_READ ((dev->pci_conf[0x44] & 2) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) +#define SYSTEM_READ ((dev->pci_conf[0x44] & 2) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) #define SYSTEM_WRITE ((dev->pci_conf[0x44] & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) -#define SHADOW_READ ((dev->pci_conf[cur_reg] & (1 << (4 + i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) +#define SHADOW_READ ((dev->pci_conf[cur_reg] & (1 << (4 + i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) #define SHADOW_WRITE ((dev->pci_conf[cur_reg] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) #ifdef ENABLE_OPTI822_LOG @@ -45,25 +45,24 @@ opti822_log(const char *fmt, ...) { va_list ap; - if (opti822_do_log) - { + if (opti822_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define opti822_log(fmt, ...) +# define opti822_log(fmt, ...) #endif -typedef struct opti822_t -{ +typedef struct opti822_t { uint8_t pci_conf[256]; } opti822_t; -int opti822_irq_routing[7] = {5, 9, 0x0a, 0x0b, 0x0c, 0x0e, 0x0f}; +int opti822_irq_routing[7] = { 5, 9, 0x0a, 0x0b, 0x0c, 0x0e, 0x0f }; -void opti822_shadow(int cur_reg, opti822_t *dev) +void +opti822_shadow(int cur_reg, opti822_t *dev) { if (cur_reg == 0x44) mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE); @@ -78,183 +77,179 @@ static void opti822_write(int func, int addr, uint8_t val, void *priv) { - opti822_t *dev = (opti822_t *)priv; + opti822_t *dev = (opti822_t *) priv; - switch (func) - { - case 0x04: /* Command Register */ - dev->pci_conf[addr] = val & 0x40; - break; + switch (func) { + case 0x04: /* Command Register */ + dev->pci_conf[addr] = val & 0x40; + break; - case 0x05: /* Command Register */ - dev->pci_conf[addr] = val & 1; - break; + case 0x05: /* Command Register */ + dev->pci_conf[addr] = val & 1; + break; - case 0x06: /* Status Register */ - dev->pci_conf[addr] |= val & 0xc0; - break; + case 0x06: /* Status Register */ + dev->pci_conf[addr] |= val & 0xc0; + break; - case 0x07: /* Status Register */ - dev->pci_conf[addr] = val & 0xa9; - break; + case 0x07: /* Status Register */ + dev->pci_conf[addr] = val & 0xa9; + break; - case 0x40: - dev->pci_conf[addr] = val & 0xc0; - break; + case 0x40: + dev->pci_conf[addr] = val & 0xc0; + break; - case 0x41: - dev->pci_conf[addr] = val & 0xcf; - break; + case 0x41: + dev->pci_conf[addr] = val & 0xcf; + break; - case 0x42: - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x42: + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x43: - dev->pci_conf[addr] = val; - break; + case 0x43: + dev->pci_conf[addr] = val; + break; - case 0x44: /* Shadow RAM */ - case 0x45: - case 0x46: - case 0x47: - dev->pci_conf[addr] = (addr == 0x44) ? (val & 0xcb) : val; - opti822_shadow(addr, dev); - break; + case 0x44: /* Shadow RAM */ + case 0x45: + case 0x46: + case 0x47: + dev->pci_conf[addr] = (addr == 0x44) ? (val & 0xcb) : val; + opti822_shadow(addr, dev); + break; - case 0x48: - case 0x49: - case 0x4a: - case 0x4b: - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - case 0x50: - case 0x51: - case 0x52: - case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - dev->pci_conf[addr] = val; - break; + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + dev->pci_conf[addr] = val; + break; - case 0x58: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x58: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x59: - case 0x5a: - case 0x5b: - case 0x5c: - case 0x5d: - case 0x5e: - case 0x5f: - dev->pci_conf[addr] = val; - break; + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + dev->pci_conf[addr] = val; + break; - case 0x60: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x60: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x61: - case 0x62: - case 0x63: - case 0x64: - case 0x65: - case 0x66: - case 0x67: - dev->pci_conf[addr] = val; - break; + case 0x61: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + case 0x66: + case 0x67: + dev->pci_conf[addr] = val; + break; - case 0x68: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x68: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x69: - case 0x6a: - case 0x6b: - case 0x6c: - case 0x6d: - case 0x6e: - case 0x6f: - dev->pci_conf[addr] = val; - break; + case 0x69: + case 0x6a: + case 0x6b: + case 0x6c: + case 0x6d: + case 0x6e: + case 0x6f: + dev->pci_conf[addr] = val; + break; - case 0x70: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x70: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x71: - case 0x72: - case 0x73: - dev->pci_conf[addr] = val; - break; + case 0x71: + case 0x72: + case 0x73: + dev->pci_conf[addr] = val; + break; - case 0x74: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x74: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x75: - case 0x76: - dev->pci_conf[addr] = val; - break; + case 0x75: + case 0x76: + dev->pci_conf[addr] = val; + break; - case 0x77: - dev->pci_conf[addr] = val & 0xe7; - break; + case 0x77: + dev->pci_conf[addr] = val & 0xe7; + break; - case 0x78: - dev->pci_conf[addr] = val; - break; + case 0x78: + dev->pci_conf[addr] = val; + break; - case 0x79: - dev->pci_conf[addr] = val & 0xfc; - break; + case 0x79: + dev->pci_conf[addr] = val & 0xfc; + break; - case 0x7a: - case 0x7b: - case 0x7c: - case 0x7d: - case 0x7e: - dev->pci_conf[addr] = val; - break; + case 0x7a: + case 0x7b: + case 0x7c: + case 0x7d: + case 0x7e: + dev->pci_conf[addr] = val; + break; - case 0x7f: - dev->pci_conf[addr] = val & 3; - break; + case 0x7f: + dev->pci_conf[addr] = val & 3; + break; - case 0x80: - case 0x81: - case 0x82: - case 0x84: - case 0x85: - case 0x86: - dev->pci_conf[addr] = val; - break; + case 0x80: + case 0x81: + case 0x82: + case 0x84: + case 0x85: + case 0x86: + dev->pci_conf[addr] = val; + break; - case 0x88: /* PCI IRQ Routing */ - case 0x89: /* Very hacky implementation. Needs surely a rewrite after */ - case 0x8a: /* a PCI rework happens. */ - case 0x8b: - case 0x8c: - case 0x8d: - case 0x8e: - case 0x8f: - dev->pci_conf[addr] = val; - if (addr % 2) - { - pci_set_irq_routing(PCI_INTB, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTA, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); - } - else - { - pci_set_irq_routing(PCI_INTD, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTC, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); - } - break; + case 0x88: /* PCI IRQ Routing */ + case 0x89: /* Very hacky implementation. Needs surely a rewrite after */ + case 0x8a: /* a PCI rework happens. */ + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0x8f: + dev->pci_conf[addr] = val; + if (addr % 2) { + pci_set_irq_routing(PCI_INTB, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTA, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); + } else { + pci_set_irq_routing(PCI_INTD, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTC, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); + } + break; } opti822_log("OPTI822: dev->pci_conf[%02x] = %02x\n", addr, dev->pci_conf[addr]); @@ -263,14 +258,14 @@ opti822_write(int func, int addr, uint8_t val, void *priv) static uint8_t opti822_read(int func, int addr, void *priv) { - opti822_t *dev = (opti822_t *)priv; + opti822_t *dev = (opti822_t *) priv; return dev->pci_conf[addr]; } static void opti822_reset(void *priv) { - opti822_t *dev = (opti822_t *)priv; + opti822_t *dev = (opti822_t *) priv; dev->pci_conf[0x00] = 0x45; dev->pci_conf[0x01] = 0x10; @@ -291,7 +286,7 @@ opti822_reset(void *priv) static void opti822_close(void *priv) { - opti822_t *dev = (opti822_t *)priv; + opti822_t *dev = (opti822_t *) priv; free(dev); } @@ -299,7 +294,7 @@ opti822_close(void *priv) static void * opti822_init(const device_t *info) { - opti822_t *dev = (opti822_t *)malloc(sizeof(opti822_t)); + opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t)); memset(dev, 0, sizeof(opti822_t)); pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_read, opti822_write, dev); @@ -310,15 +305,15 @@ opti822_init(const device_t *info) } const device_t opti822_device = { - .name = "OPTi 82C822 PCIB", + .name = "OPTi 82C822 PCIB", .internal_name = "opti822", - .flags = DEVICE_PCI, - .local = 0, - .init = opti822_init, - .close = opti822_close, - .reset = opti822_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = opti822_init, + .close = opti822_close, + .reset = opti822_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/opti895.c b/src/chipset/opti895.c index 9eb360e02..b2e9ae0e0 100644 --- a/src/chipset/opti895.c +++ b/src/chipset/opti895.c @@ -32,195 +32,186 @@ #include <86box/port_92.h> #include <86box/chipset.h> - typedef struct { - uint8_t idx, forced_green, - regs[256], - scratch[2]; + uint8_t idx, forced_green, + regs[256], + scratch[2]; - smram_t *smram; + smram_t *smram; } opti895_t; - #ifdef ENABLE_OPTI895_LOG int opti895_do_log = ENABLE_OPTI895_LOG; - static void opti895_log(const char *fmt, ...) { va_list ap; if (opti895_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define opti895_log(fmt, ...) +# define opti895_log(fmt, ...) #endif - static void opti895_recalc(opti895_t *dev) { uint32_t base; uint32_t i, shflags = 0; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; if (dev->regs[0x22] & 0x80) { - shadowbios = 1; - shadowbios_write = 0; - shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; + shadowbios = 1; + shadowbios_write = 0; + shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; } else { - shadowbios = 0; - shadowbios_write = 1; - shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; + shadowbios = 0; + shadowbios_write = 1; + shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; } mem_set_mem_state_both(0xf0000, 0x10000, shflags); for (i = 0; i < 8; i++) { - base = 0xd0000 + (i << 14); + base = 0xd0000 + (i << 14); - if (dev->regs[0x23] & (1 << i)) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - shflags = (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; - if (dev->regs[0x26] & 0x40) - shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - else { - if (dev->regs[0x26] & 0x80) - shflags |= (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; - else - shflags |= MEM_WRITE_EXTERNAL; - } - } + if (dev->regs[0x23] & (1 << i)) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + shflags = (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; + if (dev->regs[0x26] & 0x40) + shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + else { + if (dev->regs[0x26] & 0x80) + shflags |= (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; + else + shflags |= MEM_WRITE_EXTERNAL; + } + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { - base = 0xc0000 + (i << 14); + base = 0xc0000 + (i << 14); - if (dev->regs[0x26] & (1 << i)) { - shflags = MEM_READ_INTERNAL; - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - } else { - shflags = (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; - if (dev->regs[0x26] & 0x40) - shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; - else { - if (dev->regs[0x26] & 0x80) - shflags |= (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; - else - shflags |= MEM_WRITE_EXTERNAL; - } - } + if (dev->regs[0x26] & (1 << i)) { + shflags = MEM_READ_INTERNAL; + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + } else { + shflags = (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; + if (dev->regs[0x26] & 0x40) + shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + else { + if (dev->regs[0x26] & 0x80) + shflags |= (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; + else + shflags |= MEM_WRITE_EXTERNAL; + } + } - mem_set_mem_state_both(base, 0x4000, shflags); + mem_set_mem_state_both(base, 0x4000, shflags); } flushmmucache_nopc(); } - static void opti895_write(uint16_t addr, uint8_t val, void *priv) { opti895_t *dev = (opti895_t *) priv; switch (addr) { - case 0x22: - dev->idx = val; - break; - case 0x23: - if (dev->idx == 0x01) { - dev->regs[dev->idx] = val; - opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val); - } - break; - case 0x24: - if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || - ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { - dev->regs[dev->idx] = val; - opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val); + case 0x22: + dev->idx = val; + break; + case 0x23: + if (dev->idx == 0x01) { + dev->regs[dev->idx] = val; + opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val); + } + break; + case 0x24: + if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { + dev->regs[dev->idx] = val; + opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val); - switch(dev->idx) { - case 0x21: - cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); - cpu_update_waitstates(); - break; + switch (dev->idx) { + case 0x21: + cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); + cpu_update_waitstates(); + break; - case 0x22: - case 0x23: - case 0x26: - case 0x2d: - opti895_recalc(dev); - break; + case 0x22: + case 0x23: + case 0x26: + case 0x2d: + opti895_recalc(dev); + break; - case 0x24: - smram_state_change(dev->smram, 0, !!(val & 0x80)); - break; + case 0x24: + smram_state_change(dev->smram, 0, !!(val & 0x80)); + break; - case 0xe0: - if (!(val & 0x01)) - dev->forced_green = 0; - break; + case 0xe0: + if (!(val & 0x01)) + dev->forced_green = 0; + break; - case 0xe1: - if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) { - smi_raise(); - dev->forced_green = 1; - break; - } - break; - } - } - break; + case 0xe1: + if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) { + smi_raise(); + dev->forced_green = 1; + break; + } + break; + } + } + break; - case 0xe1: - case 0xe2: - dev->scratch[addr - 0xe1] = val; - break; + case 0xe1: + case 0xe2: + dev->scratch[addr - 0xe1] = val; + break; } } - static uint8_t opti895_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; opti895_t *dev = (opti895_t *) priv; switch (addr) { - case 0x23: - if (dev->idx == 0x01) - ret = dev->regs[dev->idx]; - break; - case 0x24: - if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || - ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { - ret = dev->regs[dev->idx]; - if (dev->idx == 0xe0) - ret = (ret & 0xf6) | (in_smm ? 0x00 : 0x08) | !!dev->forced_green; - } - break; - case 0xe1: - case 0xe2: - ret = dev->scratch[addr - 0xe1]; - break; + case 0x23: + if (dev->idx == 0x01) + ret = dev->regs[dev->idx]; + break; + case 0x24: + if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) || ((dev->idx >= 0xe0) && (dev->idx <= 0xef))) { + ret = dev->regs[dev->idx]; + if (dev->idx == 0xe0) + ret = (ret & 0xf6) | (in_smm ? 0x00 : 0x08) | !!dev->forced_green; + } + break; + case 0xe1: + case 0xe2: + ret = dev->scratch[addr - 0xe1]; + break; } return ret; } - static void opti895_close(void *priv) { @@ -231,7 +222,6 @@ opti895_close(void *priv) free(dev); } - static void * opti895_init(const device_t *info) { @@ -273,29 +263,29 @@ opti895_init(const device_t *info) } const device_t opti802g_device = { - .name = "OPTi 82C802G", + .name = "OPTi 82C802G", .internal_name = "opti802g", - .flags = 0, - .local = 0, - .init = opti895_init, - .close = opti895_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti895_init, + .close = opti895_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t opti895_device = { - .name = "OPTi 82C895", + .name = "OPTi 82C895", .internal_name = "opti895", - .flags = 0, - .local = 0, - .init = opti895_init, - .close = opti895_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = opti895_init, + .close = opti895_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/scamp.c b/src/chipset/scamp.c index 621f7d9c5..5a30c3730 100644 --- a/src/chipset/scamp.c +++ b/src/chipset/scamp.c @@ -34,32 +34,29 @@ #include <86box/port_92.h> #include <86box/chipset.h> +#define CFG_ID 0x00 +#define CFG_SLTPTR 0x02 +#define CFG_RAMMAP 0x03 +#define CFG_EMSEN1 0x0b +#define CFG_EMSEN2 0x0c +#define CFG_ABAXS 0x0e +#define CFG_CAXS 0x0f +#define CFG_DAXS 0x10 +#define CFG_FEAXS 0x11 -#define CFG_ID 0x00 -#define CFG_SLTPTR 0x02 -#define CFG_RAMMAP 0x03 -#define CFG_EMSEN1 0x0b -#define CFG_EMSEN2 0x0c -#define CFG_ABAXS 0x0e -#define CFG_CAXS 0x0f -#define CFG_DAXS 0x10 -#define CFG_FEAXS 0x11 - -#define ID_VL82C311 0xd6 +#define ID_VL82C311 0xd6 #define RAMMAP_REMP386 (1 << 4) #define EMSEN1_EMSMAP (1 << 4) #define EMSEN1_EMSENAB (1 << 7) -#define NR_ELEMS(x) (sizeof(x) / sizeof(x[0])) - +#define NR_ELEMS(x) (sizeof(x) / sizeof(x[0])) /*Commodore SL386SX requires proper memory slot decoding to detect memory size. Therefore we emulate the SCAMP memory address decoding, and therefore are limited to the DRAM combinations supported by the actual chip*/ -enum -{ +enum { BANK_NONE, BANK_256K, BANK_256K_INTERLEAVED, @@ -69,589 +66,572 @@ enum BANK_4M_INTERLEAVED }; - typedef struct { - void * parent; - int bank; + void *parent; + int bank; } ram_struct_t; typedef struct { - void * parent; - int segment; + void *parent; + int segment; } ems_struct_t; typedef struct { - int cfg_index; - uint8_t cfg_regs[256]; - int cfg_enable, ram_config; + int cfg_index; + uint8_t cfg_regs[256]; + int cfg_enable, ram_config; - int ems_index; - int ems_autoinc; - uint16_t ems[0x24]; - mem_mapping_t ems_mappings[20]; /*a0000-effff*/ - uint32_t mappings[20]; + int ems_index; + int ems_autoinc; + uint16_t ems[0x24]; + mem_mapping_t ems_mappings[20]; /*a0000-effff*/ + uint32_t mappings[20]; mem_mapping_t ram_mapping[2]; - ram_struct_t ram_struct[2]; - ems_struct_t ems_struct[20]; + ram_struct_t ram_struct[2]; + ems_struct_t ems_struct[20]; - uint32_t ram_virt_base[2], ram_phys_base[2]; - uint32_t ram_mask[2]; - int row_virt_shift[2], row_phys_shift[2]; - int ram_interleaved[2], ibank_shift[2]; + uint32_t ram_virt_base[2], ram_phys_base[2]; + uint32_t ram_mask[2]; + int row_virt_shift[2], row_phys_shift[2]; + int ram_interleaved[2], ibank_shift[2]; - port_92_t * port_92; + port_92_t *port_92; } scamp_t; static const struct { - int size_kb; - int rammap; - int bank[2]; -} ram_configs[] = -{ - {512, 0x0, {BANK_256K, BANK_NONE}}, - {1024, 0x1, {BANK_256K_INTERLEAVED, BANK_NONE}}, - {1536, 0x2, {BANK_256K_INTERLEAVED, BANK_256K}}, - {2048, 0x3, {BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED}}, - {3072, 0xc, {BANK_256K_INTERLEAVED, BANK_1M}}, - {4096, 0x5, {BANK_1M_INTERLEAVED, BANK_NONE}}, - {5120, 0xd, {BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED}}, - {6144, 0x6, {BANK_1M_INTERLEAVED, BANK_1M}}, - {8192, 0x7, {BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED}}, - {12288, 0xe, {BANK_1M_INTERLEAVED, BANK_4M}}, - {16384, 0x9, {BANK_4M_INTERLEAVED, BANK_NONE}}, + int size_kb; + int rammap; + int bank[2]; +} ram_configs[] = { + {512, 0x0, { BANK_256K, BANK_NONE } }, + { 1024, 0x1, { BANK_256K_INTERLEAVED, BANK_NONE } }, + { 1536, 0x2, { BANK_256K_INTERLEAVED, BANK_256K } }, + { 2048, 0x3, { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }}, + { 3072, 0xc, { BANK_256K_INTERLEAVED, BANK_1M } }, + { 4096, 0x5, { BANK_1M_INTERLEAVED, BANK_NONE } }, + { 5120, 0xd, { BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED } }, + { 6144, 0x6, { BANK_1M_INTERLEAVED, BANK_1M } }, + { 8192, 0x7, { BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED } }, + { 12288, 0xe, { BANK_1M_INTERLEAVED, BANK_4M } }, + { 16384, 0x9, { BANK_4M_INTERLEAVED, BANK_NONE } }, }; static const struct { - int bank[2]; - int remapped; -} rammap[16] = -{ - {{BANK_256K, BANK_NONE}, 0}, - {{BANK_256K_INTERLEAVED, BANK_NONE}, 0}, - {{BANK_256K_INTERLEAVED, BANK_256K}, 0}, - {{BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED}, 0}, + int bank[2]; + int remapped; +} rammap[16] = { + {{ BANK_256K, BANK_NONE }, 0}, + { { BANK_256K_INTERLEAVED, BANK_NONE }, 0}, + { { BANK_256K_INTERLEAVED, BANK_256K }, 0}, + { { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }, 0}, - {{BANK_1M, BANK_NONE}, 0}, - {{BANK_1M_INTERLEAVED, BANK_NONE}, 0}, - {{BANK_1M_INTERLEAVED, BANK_1M}, 0}, - {{BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED}, 0}, + { { BANK_1M, BANK_NONE }, 0}, + { { BANK_1M_INTERLEAVED, BANK_NONE }, 0}, + { { BANK_1M_INTERLEAVED, BANK_1M }, 0}, + { { BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED }, 0}, - {{BANK_4M, BANK_NONE}, 0}, - {{BANK_4M_INTERLEAVED, BANK_NONE}, 0}, - {{BANK_NONE, BANK_4M}, 1}, /*Bank 2 remapped to 0*/ - {{BANK_NONE, BANK_4M_INTERLEAVED}, 1}, /*Banks 2/3 remapped to 0/1*/ + { { BANK_4M, BANK_NONE }, 0}, + { { BANK_4M_INTERLEAVED, BANK_NONE }, 0}, + { { BANK_NONE, BANK_4M }, 1}, /*Bank 2 remapped to 0*/ + { { BANK_NONE, BANK_4M_INTERLEAVED }, 1}, /*Banks 2/3 remapped to 0/1*/ - {{BANK_256K_INTERLEAVED, BANK_1M}, 0}, - {{BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED}, 0}, - {{BANK_1M_INTERLEAVED, BANK_4M}, 0}, - {{BANK_1M_INTERLEAVED, BANK_4M_INTERLEAVED}, 0}, /*Undocumented - probably wrong!*/ + { { BANK_256K_INTERLEAVED, BANK_1M }, 0}, + { { BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED }, 0}, + { { BANK_1M_INTERLEAVED, BANK_4M }, 0}, + { { BANK_1M_INTERLEAVED, BANK_4M_INTERLEAVED }, 0}, /*Undocumented - probably wrong!*/ }; - /* The column bits masked when using 256kbit DRAMs in 4Mbit mode aren't contiguous, so we use separate routines for that special case */ static uint8_t ram_mirrored_256k_in_4mi_read(uint32_t addr, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; byte = addr & 1; if (!dev->ram_interleaved[bank]) { - if (addr & 0x400) - return 0xff; + if (addr & 0x400) + return 0xff; - addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); - column = (addr >> 1) & dev->ram_mask[bank]; - row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9); + addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); + column = (addr >> 1) & dev->ram_mask[bank]; + row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9); - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); } else { - column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); - row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9); + column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); + row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9); - addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank]+1)); + addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1)); } return ram[addr + dev->ram_phys_base[bank]]; } - static void ram_mirrored_256k_in_4mi_write(uint32_t addr, uint8_t val, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; byte = addr & 1; if (!dev->ram_interleaved[bank]) { - if (addr & 0x400) - return; + if (addr & 0x400) + return; - addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); - column = (addr >> 1) & dev->ram_mask[bank]; - row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9); + addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); + column = (addr >> 1) & dev->ram_mask[bank]; + row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9); - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); } else { - column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); - row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9); + column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); + row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9); - addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank]+1)); + addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1)); } ram[addr + dev->ram_phys_base[bank]] = val; } - /*Read/write handlers for interleaved memory banks. We must keep CPU and ram array mapping linear, otherwise we won't be able to execute code from interleaved banks*/ static uint8_t ram_mirrored_interleaved_read(uint32_t addr, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; byte = addr & 1; if (!dev->ram_interleaved[bank]) { - if (addr & 0x400) - return 0xff; + if (addr & 0x400) + return 0xff; - addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); - column = (addr >> 1) & dev->ram_mask[bank]; - row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; + addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); + column = (addr >> 1) & dev->ram_mask[bank]; + row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); } else { - column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); - row = (addr >> (dev->row_virt_shift[bank]+1)) & dev->ram_mask[bank]; + column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); + row = (addr >> (dev->row_virt_shift[bank] + 1)) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank]+1)); + addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1)); } return ram[addr + dev->ram_phys_base[bank]]; } - static void ram_mirrored_interleaved_write(uint32_t addr, uint8_t val, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; byte = addr & 1; if (!dev->ram_interleaved[bank]) { - if (addr & 0x400) - return; + if (addr & 0x400) + return; - addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); - column = (addr >> 1) & dev->ram_mask[bank]; - row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; + addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1); + column = (addr >> 1) & dev->ram_mask[bank]; + row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); } else { - column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); - row = (addr >> (dev->row_virt_shift[bank]+1)) & dev->ram_mask[bank]; + column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1); + row = (addr >> (dev->row_virt_shift[bank] + 1)) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank]+1)); + addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1)); } ram[addr + dev->ram_phys_base[bank]] = val; } - static uint8_t ram_mirrored_read(uint32_t addr, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; - byte = addr & 1; + byte = addr & 1; column = (addr >> 1) & dev->ram_mask[bank]; - row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); return ram[addr + dev->ram_phys_base[bank]]; } - static void ram_mirrored_write(uint32_t addr, uint8_t val, void *priv) { - ram_struct_t *rs = (ram_struct_t *) priv; - scamp_t *dev = rs->parent; - int bank = rs->bank, byte; - int row, column; + ram_struct_t *rs = (ram_struct_t *) priv; + scamp_t *dev = rs->parent; + int bank = rs->bank, byte; + int row, column; addr -= dev->ram_virt_base[bank]; - byte = addr & 1; + byte = addr & 1; column = (addr >> 1) & dev->ram_mask[bank]; - row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; - addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); + row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank]; + addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]); ram[addr + dev->ram_phys_base[bank]] = val; } - static void recalc_mappings(void *priv) { scamp_t *dev = (scamp_t *) priv; - int c; - uint32_t virt_base = 0, old_virt_base; - uint8_t cur_rammap = dev->cfg_regs[CFG_RAMMAP] & 0xf; - int bank_nr = 0, phys_bank; + int c; + uint32_t virt_base = 0, old_virt_base; + uint8_t cur_rammap = dev->cfg_regs[CFG_RAMMAP] & 0xf; + int bank_nr = 0, phys_bank; mem_set_mem_state_both((1 << 20), (16256 - 1024) * 1024, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); for (c = 0; c < 2; c++) - mem_mapping_disable(&dev->ram_mapping[c]); + mem_mapping_disable(&dev->ram_mapping[c]); /* Once the BIOS programs the correct DRAM configuration, switch to regular linear memory mapping */ if (cur_rammap == ram_configs[dev->ram_config].rammap) { - mem_mapping_set_handler(&ram_low_mapping, - mem_read_ram, mem_read_ramw, mem_read_raml, - mem_write_ram, mem_write_ramw, mem_write_raml); - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - if (mem_size > 1024) - mem_set_mem_state_both((1 << 20), (mem_size - 1024) << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_mapping_enable(&ram_high_mapping); - return; + mem_mapping_set_handler(&ram_low_mapping, + mem_read_ram, mem_read_ramw, mem_read_raml, + mem_write_ram, mem_write_ramw, mem_write_raml); + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + if (mem_size > 1024) + mem_set_mem_state_both((1 << 20), (mem_size - 1024) << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_mapping_enable(&ram_high_mapping); + return; } else { - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL); - mem_mapping_disable(&ram_low_mapping); + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL); + mem_mapping_disable(&ram_low_mapping); } if (rammap[cur_rammap].bank[0] == BANK_NONE) - bank_nr = 1; + bank_nr = 1; for (; bank_nr < 2; bank_nr++) { - old_virt_base = virt_base; - phys_bank = ram_configs[dev->ram_config].bank[bank_nr]; + old_virt_base = virt_base; + phys_bank = ram_configs[dev->ram_config].bank[bank_nr]; - dev->ram_virt_base[bank_nr] = virt_base; + dev->ram_virt_base[bank_nr] = virt_base; - if (virt_base == 0) { - switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_NONE: - fatal(" Bank %i is empty!\n }\n}\n", bank_nr); - break; + if (virt_base == 0) { + switch (rammap[cur_rammap].bank[bank_nr]) { + case BANK_NONE: + fatal(" Bank %i is empty!\n }\n}\n", bank_nr); + break; - case BANK_256K: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - } - virt_base += (1 << 19); - dev->row_virt_shift[bank_nr] = 10; - break; + case BANK_256K: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + } + virt_base += (1 << 19); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_256K_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - } - virt_base += (1 << 20); - dev->row_virt_shift[bank_nr] = 10; - break; + case BANK_256K_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + } + virt_base += (1 << 20); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_1M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x100000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 21); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_1M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x100000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 21); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_1M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x300000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (3 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 22); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_1M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x300000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (3 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 22); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_4M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x700000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (7 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 23); - dev->row_virt_shift[bank_nr] = 12; - break; + case BANK_4M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x700000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (7 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 23); + dev->row_virt_shift[bank_nr] = 12; + break; - case BANK_4M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); - mem_mapping_set_p(&ram_low_mapping, (void *)&dev->ram_struct[bank_nr]); - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0xf00000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); - mem_set_mem_state_both((1 << 20), (15 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 24); - dev->row_virt_shift[bank_nr] = 12; - break; - } - } else { - switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_NONE: - break; + case BANK_4M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000); + mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]); + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0xf00000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]); + mem_set_mem_state_both((1 << 20), (15 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 24); + dev->row_virt_shift[bank_nr] = 12; + break; + } + } else { + switch (rammap[cur_rammap].bank[bank_nr]) { + case BANK_NONE: + break; - case BANK_256K: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x80000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 19), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 19); - dev->row_virt_shift[bank_nr] = 10; - break; + case BANK_256K: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x80000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 19), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 19); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_256K_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x100000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 20); - dev->row_virt_shift[bank_nr] = 10; - break; + case BANK_256K_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x100000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 20); + dev->row_virt_shift[bank_nr] = 10; + break; - case BANK_1M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x200000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 21), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 21); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_1M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x200000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 21), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 21); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_1M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x400000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 22), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 22); - dev->row_virt_shift[bank_nr] = 11; - break; + case BANK_1M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x400000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 22), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 22); + dev->row_virt_shift[bank_nr] = 11; + break; - case BANK_4M: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x800000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 23), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 23); - dev->row_virt_shift[bank_nr] = 12; - break; + case BANK_4M: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x800000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 23), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 23); + dev->row_virt_shift[bank_nr] = 12; + break; - case BANK_4M_INTERLEAVED: - if (phys_bank != BANK_NONE) { - mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x1000000); - mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); - mem_set_mem_state_both(virt_base, (1 << 24), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - } - virt_base += (1 << 24); - dev->row_virt_shift[bank_nr] = 12; - break; - } - } - switch (rammap[cur_rammap].bank[bank_nr]) { - case BANK_256K: case BANK_1M: case BANK_4M: - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL); - break; + case BANK_4M_INTERLEAVED: + if (phys_bank != BANK_NONE) { + mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x1000000); + mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]); + mem_set_mem_state_both(virt_base, (1 << 24), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + } + virt_base += (1 << 24); + dev->row_virt_shift[bank_nr] = 12; + break; + } + } + switch (rammap[cur_rammap].bank[bank_nr]) { + case BANK_256K: + case BANK_1M: + case BANK_4M: + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL); + break; - case BANK_256K_INTERLEAVED: case BANK_1M_INTERLEAVED: - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - break; + case BANK_256K_INTERLEAVED: + case BANK_1M_INTERLEAVED: + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + break; - case BANK_4M_INTERLEAVED: - if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) { - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_256k_in_4mi_read, NULL, NULL, - ram_mirrored_256k_in_4mi_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_256k_in_4mi_read, NULL, NULL, - ram_mirrored_256k_in_4mi_write, NULL, NULL); - } else { - mem_mapping_set_handler(&dev->ram_mapping[bank_nr], - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - if (!old_virt_base) - mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_interleaved_read, NULL, NULL, - ram_mirrored_interleaved_write, NULL, NULL); - } - break; - } + case BANK_4M_INTERLEAVED: + if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) { + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_256k_in_4mi_read, NULL, NULL, + ram_mirrored_256k_in_4mi_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_256k_in_4mi_read, NULL, NULL, + ram_mirrored_256k_in_4mi_write, NULL, NULL); + } else { + mem_mapping_set_handler(&dev->ram_mapping[bank_nr], + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + if (!old_virt_base) + mem_mapping_set_handler(&ram_low_mapping, + ram_mirrored_interleaved_read, NULL, NULL, + ram_mirrored_interleaved_write, NULL, NULL); + } + break; + } } } - static void recalc_sltptr(scamp_t *dev) { - uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16; + uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16; - if (sltptr >= 0xa0000 && sltptr < 0x100000) - sltptr = 0x100000; - if (sltptr > 0xfe0000) - sltptr = 0xfe0000; + if (sltptr >= 0xa0000 && sltptr < 0x100000) + sltptr = 0x100000; + if (sltptr > 0xfe0000) + sltptr = 0xfe0000; - if (sltptr >= 0xa0000) - { - mem_set_mem_state(0, 0xa0000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } - else - { - mem_set_mem_state(0, sltptr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - mem_set_mem_state(sltptr, 0xa0000-sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - } + if (sltptr >= 0xa0000) { + mem_set_mem_state(0, 0xa0000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } else { + mem_set_mem_state(0, sltptr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + } } static uint8_t scamp_ems_read(uint32_t addr, void *priv) { - ems_struct_t *ems = (ems_struct_t *) priv; - scamp_t *dev = ems->parent; - int segment = ems->segment; + ems_struct_t *ems = (ems_struct_t *) priv; + scamp_t *dev = ems->parent; + int segment = ems->segment; - addr = (addr & 0x3fff) | dev->mappings[segment]; - return ram[addr]; + addr = (addr & 0x3fff) | dev->mappings[segment]; + return ram[addr]; } static void scamp_ems_write(uint32_t addr, uint8_t val, void *priv) { - ems_struct_t *ems = (ems_struct_t *) priv; - scamp_t *dev = ems->parent; - int segment = ems->segment; + ems_struct_t *ems = (ems_struct_t *) priv; + scamp_t *dev = ems->parent; + int segment = ems->segment; - addr = (addr & 0x3fff) | dev->mappings[segment]; - ram[addr] = val; + addr = (addr & 0x3fff) | dev->mappings[segment]; + ram[addr] = val; } static void recalc_ems(scamp_t *dev) { - int segment; - const uint32_t ems_base[12] = - { - 0xc0000, 0xc4000, 0xc8000, 0xcc000, - 0xd0000, 0xd4000, 0xd8000, 0xdc000, - 0xe0000, 0xe4000, 0xe8000, 0xec000 - }; - uint32_t new_mappings[20]; - uint16_t ems_enable; + int segment; + const uint32_t ems_base[12] = { + 0xc0000, 0xc4000, 0xc8000, 0xcc000, + 0xd0000, 0xd4000, 0xd8000, 0xdc000, + 0xe0000, 0xe4000, 0xe8000, 0xec000 + }; + uint32_t new_mappings[20]; + uint16_t ems_enable; - for (segment = 0; segment < 20; segment++) - new_mappings[segment] = 0xa0000 + segment*0x4000; + for (segment = 0; segment < 20; segment++) + new_mappings[segment] = 0xa0000 + segment * 0x4000; - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) - ems_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8); - else - ems_enable = 0; + if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) + ems_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8); + else + ems_enable = 0; - for (segment = 0; segment < 12; segment++) - { - if (ems_enable & (1 << segment)) - { - uint32_t phys_addr = dev->ems[segment] << 14; + for (segment = 0; segment < 12; segment++) { + if (ems_enable & (1 << segment)) { + uint32_t phys_addr = dev->ems[segment] << 14; - /*If physical address is in remapped memory then adjust down to a0000-fffff range*/ - if ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) && phys_addr >= (mem_size * 1024) - && phys_addr < ((mem_size + 384) * 1024)) - phys_addr = (phys_addr - mem_size * 1024) + 0xa0000; - new_mappings[(ems_base[segment] - 0xa0000) >> 14] = phys_addr; - } + /*If physical address is in remapped memory then adjust down to a0000-fffff range*/ + if ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) && phys_addr >= (mem_size * 1024) + && phys_addr < ((mem_size + 384) * 1024)) + phys_addr = (phys_addr - mem_size * 1024) + 0xa0000; + new_mappings[(ems_base[segment] - 0xa0000) >> 14] = phys_addr; } + } - for (segment = 0; segment < 20; segment++) - { - if (new_mappings[segment] != dev->mappings[segment]) - { - dev->mappings[segment] = new_mappings[segment]; - if (new_mappings[segment] < (mem_size * 1024)) - { - mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]); - mem_mapping_enable(&dev->ems_mappings[segment]); - } - else - mem_mapping_disable(&dev->ems_mappings[segment]); - } + for (segment = 0; segment < 20; segment++) { + if (new_mappings[segment] != dev->mappings[segment]) { + dev->mappings[segment] = new_mappings[segment]; + if (new_mappings[segment] < (mem_size * 1024)) { + mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]); + mem_mapping_enable(&dev->ems_mappings[segment]); + } else + mem_mapping_disable(&dev->ems_mappings[segment]); } + } } static void shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable) { - if (ems_enable) - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - else switch (state) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } + if (ems_enable) + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + else + switch (state) { + case 0: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + } flushmmucache_nopc(); } @@ -659,51 +639,51 @@ shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable) static void shadow_recalc(scamp_t *dev) { - uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_ABAXS]; - uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS]; - uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS]; - uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS]; - uint32_t ems_enable; + uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_ABAXS]; + uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS]; + uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS]; + uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS]; + uint32_t ems_enable; - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) { - if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP) /*Axxx/Bxxx/Dxxx*/ - ems_enable = (dev->cfg_regs[CFG_EMSEN2] & 0xf) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 4) | ((dev->cfg_regs[CFG_EMSEN2] & 0xf0) << 8); - else /*Cxxx/Dxxx/Exxx*/ - ems_enable = (dev->cfg_regs[CFG_EMSEN2] << 8) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 16); - } else - ems_enable = 0; + if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) { + if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP) /*Axxx/Bxxx/Dxxx*/ + ems_enable = (dev->cfg_regs[CFG_EMSEN2] & 0xf) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 4) | ((dev->cfg_regs[CFG_EMSEN2] & 0xf0) << 8); + else /*Cxxx/Dxxx/Exxx*/ + ems_enable = (dev->cfg_regs[CFG_EMSEN2] << 8) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 16); + } else + ems_enable = 0; - /*Enabling remapping will disable all shadowing*/ - if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) - mem_remap_top(384); + /*Enabling remapping will disable all shadowing*/ + if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) + mem_remap_top(384); - shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00001); - shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00002); - shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00004); - shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00008); + shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00001); + shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00002); + shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00004); + shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00008); - shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00010); - shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00020); - shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00040); - shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00080); + shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00010); + shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00020); + shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00040); + shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00080); - shadow_control(0xc0000, 0x4000, caxs & 3, ems_enable & 0x00100); - shadow_control(0xc4000, 0x4000, (caxs >> 2) & 3, ems_enable & 0x00200); - shadow_control(0xc8000, 0x4000, (caxs >> 4) & 3, ems_enable & 0x00400); - shadow_control(0xcc000, 0x4000, (caxs >> 6) & 3, ems_enable & 0x00800); + shadow_control(0xc0000, 0x4000, caxs & 3, ems_enable & 0x00100); + shadow_control(0xc4000, 0x4000, (caxs >> 2) & 3, ems_enable & 0x00200); + shadow_control(0xc8000, 0x4000, (caxs >> 4) & 3, ems_enable & 0x00400); + shadow_control(0xcc000, 0x4000, (caxs >> 6) & 3, ems_enable & 0x00800); - shadow_control(0xd0000, 0x4000, daxs & 3, ems_enable & 0x01000); - shadow_control(0xd4000, 0x4000, (daxs >> 2) & 3, ems_enable & 0x02000); - shadow_control(0xd8000, 0x4000, (daxs >> 4) & 3, ems_enable & 0x04000); - shadow_control(0xdc000, 0x4000, (daxs >> 6) & 3, ems_enable & 0x08000); + shadow_control(0xd0000, 0x4000, daxs & 3, ems_enable & 0x01000); + shadow_control(0xd4000, 0x4000, (daxs >> 2) & 3, ems_enable & 0x02000); + shadow_control(0xd8000, 0x4000, (daxs >> 4) & 3, ems_enable & 0x04000); + shadow_control(0xdc000, 0x4000, (daxs >> 6) & 3, ems_enable & 0x08000); - shadow_control(0xe0000, 0x4000, feaxs & 3, ems_enable & 0x10000); - shadow_control(0xe4000, 0x4000, feaxs & 3, ems_enable & 0x20000); - shadow_control(0xe8000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x40000); - shadow_control(0xec000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x80000); + shadow_control(0xe0000, 0x4000, feaxs & 3, ems_enable & 0x10000); + shadow_control(0xe4000, 0x4000, feaxs & 3, ems_enable & 0x20000); + shadow_control(0xe8000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x40000); + shadow_control(0xec000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x80000); - shadow_control(0xf0000, 0x8000, (feaxs >> 4) & 3, 0); - shadow_control(0xf8000, 0x8000, (feaxs >> 6) & 3, 0); + shadow_control(0xf0000, 0x8000, (feaxs >> 4) & 3, 0); + shadow_control(0xf8000, 0x8000, (feaxs >> 6) & 3, 0); } static void @@ -712,117 +692,115 @@ scamp_write(uint16_t addr, uint8_t val, void *priv) scamp_t *dev = (scamp_t *) priv; switch (addr) { - case 0xe8: - dev->ems_index = val & 0x1f; - dev->ems_autoinc = val & 0x40; - break; + case 0xe8: + dev->ems_index = val & 0x1f; + dev->ems_autoinc = val & 0x40; + break; - case 0xea: - if (dev->ems_index < 0x24) { - dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x300) | val; - recalc_ems(dev); - } - break; - case 0xeb: - if (dev->ems_index < 0x24) { - dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x0ff) | ((val & 3) << 8); - recalc_ems(dev); - } - if (dev->ems_autoinc) - dev->ems_index = (dev->ems_index + 1) & 0x3f; - break; + case 0xea: + if (dev->ems_index < 0x24) { + dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x300) | val; + recalc_ems(dev); + } + break; + case 0xeb: + if (dev->ems_index < 0x24) { + dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x0ff) | ((val & 3) << 8); + recalc_ems(dev); + } + if (dev->ems_autoinc) + dev->ems_index = (dev->ems_index + 1) & 0x3f; + break; - case 0xec: - if (dev->cfg_enable) - dev->cfg_index = val; - break; + case 0xec: + if (dev->cfg_enable) + dev->cfg_index = val; + break; - case 0xed: - if (dev->cfg_enable && (dev->cfg_index >= 0x02) && (dev->cfg_index <= 0x16)) { - dev->cfg_regs[dev->cfg_index] = val; - switch (dev->cfg_index) { - case CFG_SLTPTR: - recalc_sltptr(dev); - break; + case 0xed: + if (dev->cfg_enable && (dev->cfg_index >= 0x02) && (dev->cfg_index <= 0x16)) { + dev->cfg_regs[dev->cfg_index] = val; + switch (dev->cfg_index) { + case CFG_SLTPTR: + recalc_sltptr(dev); + break; - case CFG_RAMMAP: - recalc_mappings(dev); - mem_mapping_disable(&ram_remapped_mapping); - shadow_recalc(dev); - break; + case CFG_RAMMAP: + recalc_mappings(dev); + mem_mapping_disable(&ram_remapped_mapping); + shadow_recalc(dev); + break; - case CFG_EMSEN1: - case CFG_EMSEN2: - shadow_recalc(dev); - recalc_ems(dev); - break; + case CFG_EMSEN1: + case CFG_EMSEN2: + shadow_recalc(dev); + recalc_ems(dev); + break; - case CFG_ABAXS: - case CFG_CAXS: - case CFG_DAXS: - case CFG_FEAXS: - shadow_recalc(dev); - break; - } - } - break; + case CFG_ABAXS: + case CFG_CAXS: + case CFG_DAXS: + case CFG_FEAXS: + shadow_recalc(dev); + break; + } + } + break; - case 0xee: - if (dev->cfg_enable && mem_a20_alt) { - dev->port_92->reg &= 0xfd; - mem_a20_alt = 0; - mem_a20_recalc(); - } - break; + case 0xee: + if (dev->cfg_enable && mem_a20_alt) { + dev->port_92->reg &= 0xfd; + mem_a20_alt = 0; + mem_a20_recalc(); + } + break; } } - static uint8_t scamp_read(uint16_t addr, void *priv) { scamp_t *dev = (scamp_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; switch (addr) { - case 0xe8: - ret = dev->ems_index | dev->ems_autoinc; - break; + case 0xe8: + ret = dev->ems_index | dev->ems_autoinc; + break; - case 0xea: - if (dev->ems_index < 0x24) - ret = dev->ems[dev->ems_index] & 0xff; - break; - case 0xeb: - if (dev->ems_index < 0x24) - ret = (dev->ems[dev->ems_index] >> 8) | 0xfc; - if (dev->ems_autoinc) - dev->ems_index = (dev->ems_index + 1) & 0x3f; - break; + case 0xea: + if (dev->ems_index < 0x24) + ret = dev->ems[dev->ems_index] & 0xff; + break; + case 0xeb: + if (dev->ems_index < 0x24) + ret = (dev->ems[dev->ems_index] >> 8) | 0xfc; + if (dev->ems_autoinc) + dev->ems_index = (dev->ems_index + 1) & 0x3f; + break; - case 0xed: - if (dev->cfg_enable && (dev->cfg_index >= 0x00) && (dev->cfg_index <= 0x16)) - ret = (dev->cfg_regs[dev->cfg_index]); - break; + case 0xed: + if (dev->cfg_enable && (dev->cfg_index >= 0x00) && (dev->cfg_index <= 0x16)) + ret = (dev->cfg_regs[dev->cfg_index]); + break; - case 0xee: - if (!mem_a20_alt) { - dev->port_92->reg |= 0x02; - mem_a20_alt = 1; - mem_a20_recalc(); - } - break; + case 0xee: + if (!mem_a20_alt) { + dev->port_92->reg |= 0x02; + mem_a20_alt = 1; + mem_a20_recalc(); + } + break; - case 0xef: - softresetx86(); - cpu_set_edx(); - break; + case 0xef: + softresetx86(); + cpu_set_edx(); + break; } return ret; } - static void scamp_close(void *priv) { @@ -831,124 +809,123 @@ scamp_close(void *priv) free(dev); } - static void * scamp_init(const device_t *info) { uint32_t addr; - int c; - scamp_t *dev = (scamp_t *)malloc(sizeof(scamp_t)); + int c; + scamp_t *dev = (scamp_t *) malloc(sizeof(scamp_t)); memset(dev, 0x00, sizeof(scamp_t)); dev->cfg_regs[CFG_ID] = ID_VL82C311; - dev->cfg_enable = 1; + dev->cfg_enable = 1; io_sethandler(0x00e8, 0x0001, - scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); + scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); io_sethandler(0x00ea, 0x0006, - scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); + scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); io_sethandler(0x00f4, 0x0002, - scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); + scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); io_sethandler(0x00f9, 0x0001, - scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); + scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); io_sethandler(0x00fb, 0x0001, - scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); + scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev); dev->ram_config = 0; /* Find best fit configuration for the requested memory size */ for (c = 0; c < NR_ELEMS(ram_configs); c++) { - if (mem_size < ram_configs[c].size_kb) - break; + if (mem_size < ram_configs[c].size_kb) + break; - dev->ram_config = c; + dev->ram_config = c; } mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[0]); mem_mapping_set_handler(&ram_low_mapping, - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL); + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL); mem_mapping_disable(&ram_high_mapping); - mem_mapping_set_addr(&ram_mid_mapping, 0xf0000, 0x10000); - mem_mapping_set_exec(&ram_mid_mapping, ram+0xf0000); + mem_mapping_set_addr(&ram_mid_mapping, 0xf0000, 0x10000); + mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000); addr = 0; for (c = 0; c < 2; c++) { - dev->ram_struct[c].parent = dev; - dev->ram_struct[c].bank = c; - mem_mapping_add(&dev->ram_mapping[c], 0, 0, - ram_mirrored_read, NULL, NULL, - ram_mirrored_write, NULL, NULL, - &ram[addr], MEM_MAPPING_INTERNAL, (void *) &dev->ram_struct[c]); - mem_mapping_disable(&dev->ram_mapping[c]); + dev->ram_struct[c].parent = dev; + dev->ram_struct[c].bank = c; + mem_mapping_add(&dev->ram_mapping[c], 0, 0, + ram_mirrored_read, NULL, NULL, + ram_mirrored_write, NULL, NULL, + &ram[addr], MEM_MAPPING_INTERNAL, (void *) &dev->ram_struct[c]); + mem_mapping_disable(&dev->ram_mapping[c]); - dev->ram_phys_base[c] = addr; + dev->ram_phys_base[c] = addr; - switch (ram_configs[dev->ram_config].bank[c]) { - case BANK_NONE: - dev->ram_mask[c] = 0; - dev->ram_interleaved[c] = 0; - break; + switch (ram_configs[dev->ram_config].bank[c]) { + case BANK_NONE: + dev->ram_mask[c] = 0; + dev->ram_interleaved[c] = 0; + break; - case BANK_256K: - addr += (1 << 19); - dev->ram_mask[c] = 0x1ff; - dev->row_phys_shift[c] = 10; - dev->ram_interleaved[c] = 0; - break; + case BANK_256K: + addr += (1 << 19); + dev->ram_mask[c] = 0x1ff; + dev->row_phys_shift[c] = 10; + dev->ram_interleaved[c] = 0; + break; - case BANK_256K_INTERLEAVED: - addr += (1 << 20); - dev->ram_mask[c] = 0x1ff; - dev->row_phys_shift[c] = 10; - dev->ibank_shift[c] = 19; - dev->ram_interleaved[c] = 1; - break; + case BANK_256K_INTERLEAVED: + addr += (1 << 20); + dev->ram_mask[c] = 0x1ff; + dev->row_phys_shift[c] = 10; + dev->ibank_shift[c] = 19; + dev->ram_interleaved[c] = 1; + break; - case BANK_1M: - addr += (1 << 21); - dev->ram_mask[c] = 0x3ff; - dev->row_phys_shift[c] = 11; - dev->ram_interleaved[c] = 0; - break; + case BANK_1M: + addr += (1 << 21); + dev->ram_mask[c] = 0x3ff; + dev->row_phys_shift[c] = 11; + dev->ram_interleaved[c] = 0; + break; - case BANK_1M_INTERLEAVED: - addr += (1 << 22); - dev->ram_mask[c] = 0x3ff; - dev->row_phys_shift[c] = 11; - dev->ibank_shift[c] = 21; - dev->ram_interleaved[c] = 1; - break; + case BANK_1M_INTERLEAVED: + addr += (1 << 22); + dev->ram_mask[c] = 0x3ff; + dev->row_phys_shift[c] = 11; + dev->ibank_shift[c] = 21; + dev->ram_interleaved[c] = 1; + break; - case BANK_4M: - addr += (1 << 23); - dev->ram_mask[c] = 0x7ff; - dev->row_phys_shift[c] = 12; - dev->ram_interleaved[c] = 0; - break; + case BANK_4M: + addr += (1 << 23); + dev->ram_mask[c] = 0x7ff; + dev->row_phys_shift[c] = 12; + dev->ram_interleaved[c] = 0; + break; - case BANK_4M_INTERLEAVED: - addr += (1 << 24); - dev->ram_mask[c] = 0x7ff; - dev->row_phys_shift[c] = 12; - dev->ibank_shift[c] = 23; - dev->ram_interleaved[c] = 1; - break; - } + case BANK_4M_INTERLEAVED: + addr += (1 << 24); + dev->ram_mask[c] = 0x7ff; + dev->row_phys_shift[c] = 12; + dev->ibank_shift[c] = 23; + dev->ram_interleaved[c] = 1; + break; + } } mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - for (c = 0; c < 20; c++) { - dev->ems_struct[c].parent = dev; - dev->ems_struct[c].segment = c; - mem_mapping_add(&dev->ems_mappings[c], - 0xa0000 + c*0x4000, 0x4000, - scamp_ems_read, NULL, NULL, - scamp_ems_write, NULL, NULL, - ram + 0xa0000 + c*0x4000, MEM_MAPPING_INTERNAL, (void *)&dev->ems_struct[c]); - dev->mappings[c] = 0xa0000 + c*0x4000; - } + for (c = 0; c < 20; c++) { + dev->ems_struct[c].parent = dev; + dev->ems_struct[c].segment = c; + mem_mapping_add(&dev->ems_mappings[c], + 0xa0000 + c * 0x4000, 0x4000, + scamp_ems_read, NULL, NULL, + scamp_ems_write, NULL, NULL, + ram + 0xa0000 + c * 0x4000, MEM_MAPPING_INTERNAL, (void *) &dev->ems_struct[c]); + dev->mappings[c] = 0xa0000 + c * 0x4000; + } dev->port_92 = device_add(&port_92_device); @@ -956,15 +933,15 @@ scamp_init(const device_t *info) } const device_t vlsi_scamp_device = { - .name = "VLSI SCAMP", + .name = "VLSI SCAMP", .internal_name = "vlsi_scamp", - .flags = 0, - .local = 0, - .init = scamp_init, - .close = scamp_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = scamp_init, + .close = scamp_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/scat.c b/src/chipset/scat.c index 1e7ba9263..7b5a1d37d 100644 --- a/src/chipset/scat.c +++ b/src/chipset/scat.c @@ -34,21 +34,20 @@ #include <86box/rom.h> #include <86box/chipset.h> - -#define SCAT_DMA_WAIT_STATE_CONTROL 0x01 -#define SCAT_VERSION 0x40 -#define SCAT_CLOCK_CONTROL 0x41 -#define SCAT_PERIPHERAL_CONTROL 0x44 -#define SCAT_MISCELLANEOUS_STATUS 0x45 -#define SCAT_POWER_MANAGEMENT 0x46 -#define SCAT_ROM_ENABLE 0x48 -#define SCAT_RAM_WRITE_PROTECT 0x49 -#define SCAT_SHADOW_RAM_ENABLE_1 0x4A -#define SCAT_SHADOW_RAM_ENABLE_2 0x4B -#define SCAT_SHADOW_RAM_ENABLE_3 0x4C -#define SCAT_DRAM_CONFIGURATION 0x4D -#define SCAT_EXTENDED_BOUNDARY 0x4E -#define SCAT_EMS_CONTROL 0x4F +#define SCAT_DMA_WAIT_STATE_CONTROL 0x01 +#define SCAT_VERSION 0x40 +#define SCAT_CLOCK_CONTROL 0x41 +#define SCAT_PERIPHERAL_CONTROL 0x44 +#define SCAT_MISCELLANEOUS_STATUS 0x45 +#define SCAT_POWER_MANAGEMENT 0x46 +#define SCAT_ROM_ENABLE 0x48 +#define SCAT_RAM_WRITE_PROTECT 0x49 +#define SCAT_SHADOW_RAM_ENABLE_1 0x4A +#define SCAT_SHADOW_RAM_ENABLE_2 0x4B +#define SCAT_SHADOW_RAM_ENABLE_3 0x4C +#define SCAT_DRAM_CONFIGURATION 0x4D +#define SCAT_EXTENDED_BOUNDARY 0x4E +#define SCAT_EMS_CONTROL 0x4F #define SCATSX_LAPTOP_FEATURES 0x60 #define SCATSX_FAST_VIDEO_CONTROL 0x61 @@ -56,36 +55,34 @@ #define SCATSX_HIGH_PERFORMANCE_REFRESH 0x63 #define SCATSX_CAS_TIMING_FOR_DMA 0x64 - typedef struct { - uint8_t valid, pad; + uint8_t valid, pad; - uint8_t regs_2x8; - uint8_t regs_2x9; + uint8_t regs_2x8; + uint8_t regs_2x9; - struct scat_t * scat; + struct scat_t *scat; } ems_page_t; typedef struct scat_t { - int type; + int type; - int indx; - uint8_t regs[256]; - uint8_t reg_2xA; + int indx; + uint8_t regs[256]; + uint8_t reg_2xA; - uint32_t xms_bound; + uint32_t xms_bound; - int external_is_RAS; + int external_is_RAS; - ems_page_t null_page, page[32]; + ems_page_t null_page, page[32]; - mem_mapping_t low_mapping[32]; - mem_mapping_t remap_mapping[6]; - mem_mapping_t efff_mapping[44]; - mem_mapping_t ems_mapping[32]; + mem_mapping_t low_mapping[32]; + mem_mapping_t remap_mapping[6]; + mem_mapping_t efff_mapping[44]; + mem_mapping_t ems_mapping[32]; } scat_t; - static const uint8_t max_map[32] = { 0, 1, 1, 1, 2, 3, 4, 8, 4, 8, 12, 16, 20, 24, 28, 32, @@ -106,10 +103,8 @@ static const uint8_t scatsx_external_is_RAS[33] = { 0 }; - -static uint8_t scat_in(uint16_t port, void *priv); -static void scat_out(uint16_t port, uint8_t val, void *priv); - +static uint8_t scat_in(uint16_t port, void *priv); +static void scat_out(uint16_t port, uint8_t val, void *priv); static void shadow_state_update(scat_t *dev) @@ -121,901 +116,885 @@ shadow_state_update(scat_t *dev) shadowbios = shadowbios_write = 0; for (i = 0; i < 24; i++) { - if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) < 4) - val = 0; - else - val = (dev->regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1; + if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) < 4) + val = 0; + else + val = (dev->regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1; - base = 0xa0000 + (i << 14); - bit = (base - 0xc0000) >> 15; - romcs = 0; + base = 0xa0000 + (i << 14); + bit = (base - 0xc0000) >> 15; + romcs = 0; - if (base >= 0xc0000) - romcs = dev->regs[SCAT_ROM_ENABLE] & (1 << bit); + if (base >= 0xc0000) + romcs = dev->regs[SCAT_ROM_ENABLE] & (1 << bit); - if (base >= 0xe0000) { - shadowbios |= val; - shadowbios_write |= val; - } + if (base >= 0xe0000) { + shadowbios |= val; + shadowbios_write |= val; + } - shflags = val ? MEM_READ_INTERNAL : (romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL); - shflags |= (val ? MEM_WRITE_INTERNAL : (romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL)); + shflags = val ? MEM_READ_INTERNAL : (romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL); + shflags |= (val ? MEM_WRITE_INTERNAL : (romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL)); - mem_set_mem_state(base, 0x4000, shflags); + mem_set_mem_state(base, 0x4000, shflags); } flushmmucache(); } - static void set_xms_bound(scat_t *dev, uint8_t val) { uint32_t xms_max = ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && ((val & 0x10) != 0)) || (dev->regs[SCAT_VERSION] >= 4) ? 0xfe0000 : 0xfc0000; - int i; + int i; switch (val & 0x0f) { - case 1: - dev->xms_bound = 0x100000; - break; + case 1: + dev->xms_bound = 0x100000; + break; - case 2: - dev->xms_bound = 0x140000; - break; + case 2: + dev->xms_bound = 0x140000; + break; - case 3: - dev->xms_bound = 0x180000; - break; + case 3: + dev->xms_bound = 0x180000; + break; - case 4: - dev->xms_bound = 0x200000; - break; + case 4: + dev->xms_bound = 0x200000; + break; - case 5: - dev->xms_bound = 0x300000; - break; + case 5: + dev->xms_bound = 0x300000; + break; - case 6: - dev->xms_bound = 0x400000; - break; + case 6: + dev->xms_bound = 0x400000; + break; - case 7: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x600000 : 0x500000; - break; + case 7: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x600000 : 0x500000; + break; - case 8: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x800000 : 0x700000; - break; + case 8: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x800000 : 0x700000; + break; - case 9: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xa00000 : 0x800000; - break; + case 9: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xa00000 : 0x800000; + break; - case 10: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xc00000 : 0x900000; - break; + case 10: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xc00000 : 0x900000; + break; - case 11: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xe00000 : 0xa00000; - break; + case 11: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xe00000 : 0xa00000; + break; - case 12: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xb00000; - break; + case 12: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xb00000; + break; - case 13: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xc00000; - break; + case 13: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xc00000; + break; - case 14: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xd00000; - break; + case 14: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xd00000; + break; - case 15: - dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xf00000; - break; + case 15: + dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xf00000; + break; - default: - dev->xms_bound = xms_max; - break; + default: + dev->xms_bound = xms_max; + break; } - if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (val & 0x40) == 0 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || - (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) { - if ((val & 0x0f) == 0 || dev->xms_bound > 0x160000) - dev->xms_bound = 0x160000; + if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (val & 0x40) == 0 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) { + if ((val & 0x0f) == 0 || dev->xms_bound > 0x160000) + dev->xms_bound = 0x160000; - if (dev->xms_bound > 0x100000) - mem_set_mem_state(0x100000, dev->xms_bound - 0x100000, - MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + if (dev->xms_bound > 0x100000) + mem_set_mem_state(0x100000, dev->xms_bound - 0x100000, + MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - if (dev->xms_bound < 0x160000) - mem_set_mem_state(dev->xms_bound, 0x160000 - dev->xms_bound, - MEM_READ_EXTANY | MEM_WRITE_EXTANY); + if (dev->xms_bound < 0x160000) + mem_set_mem_state(dev->xms_bound, 0x160000 - dev->xms_bound, + MEM_READ_EXTANY | MEM_WRITE_EXTANY); } else { - if (dev->xms_bound > xms_max) - dev->xms_bound = xms_max; + if (dev->xms_bound > xms_max) + dev->xms_bound = xms_max; - if (dev->xms_bound > 0x100000) - mem_set_mem_state(0x100000, dev->xms_bound - 0x100000, - MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + if (dev->xms_bound > 0x100000) + mem_set_mem_state(0x100000, dev->xms_bound - 0x100000, + MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - if (dev->xms_bound < ((uint32_t)mem_size << 10)) - mem_set_mem_state(dev->xms_bound, (mem_size << 10) - dev->xms_bound, - MEM_READ_EXTANY | MEM_WRITE_EXTANY); + if (dev->xms_bound < ((uint32_t) mem_size << 10)) + mem_set_mem_state(dev->xms_bound, (mem_size << 10) - dev->xms_bound, + MEM_READ_EXTANY | MEM_WRITE_EXTANY); } mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000, - ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && ((val & 0x10) != 0)) || - (dev->regs[SCAT_VERSION] >= 4) ? 0x60000 : 0x40000); + ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && ((val & 0x10) != 0)) || (dev->regs[SCAT_VERSION] >= 4) ? 0x60000 : 0x40000); if (dev->regs[SCAT_VERSION] & 0xf0) { - for (i = 0; i < 8; i++) { - if (val & 0x10) - mem_mapping_disable(&bios_high_mapping); - else - mem_mapping_enable(&bios_high_mapping); - } + for (i = 0; i < 8; i++) { + if (val & 0x10) + mem_mapping_disable(&bios_high_mapping); + else + mem_mapping_enable(&bios_high_mapping); + } } } - static uint32_t get_addr(scat_t *dev, uint32_t addr, ems_page_t *p) { #if 1 - int nbanks_2048k, nbanks_512k; + int nbanks_2048k, nbanks_512k; uint32_t addr2; - int nbank; + int nbank; #else uint32_t nbanks_2048k, nbanks_512k, addr2, nbank; #endif if (p && p->valid && (dev->regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80)) - addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14; + addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14; if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { - switch((dev->regs[SCAT_EXTENDED_BOUNDARY] & ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 0x40 : 0)) | (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f)) { - case 0x41: - nbank = addr >> 19; - if (nbank < 4) - nbank = 1; - else if (nbank == 4) - nbank = 0; - else - nbank -= 3; - break; + switch ((dev->regs[SCAT_EXTENDED_BOUNDARY] & ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 0x40 : 0)) | (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f)) { + case 0x41: + nbank = addr >> 19; + if (nbank < 4) + nbank = 1; + else if (nbank == 4) + nbank = 0; + else + nbank -= 3; + break; - case 0x42: - nbank = addr >> 19; - if (nbank < 8) - nbank = 1 + (nbank >> 2); - else if (nbank == 8) - nbank = 0; - else - nbank -= 6; - break; + case 0x42: + nbank = addr >> 19; + if (nbank < 8) + nbank = 1 + (nbank >> 2); + else if (nbank == 8) + nbank = 0; + else + nbank -= 6; + break; - case 0x43: - nbank = addr >> 19; - if (nbank < 12) - nbank = 1 + (nbank >> 2); - else if (nbank == 12) - nbank = 0; - else - nbank -= 9; - break; + case 0x43: + nbank = addr >> 19; + if (nbank < 12) + nbank = 1 + (nbank >> 2); + else if (nbank == 12) + nbank = 0; + else + nbank -= 9; + break; - case 0x44: - nbank = addr >> 19; - if (nbank < 4) - nbank = 2; - else if (nbank < 6) - nbank -= 4; - else - nbank -= 3; - break; + case 0x44: + nbank = addr >> 19; + if (nbank < 4) + nbank = 2; + else if (nbank < 6) + nbank -= 4; + else + nbank -= 3; + break; - case 0x45: - nbank = addr >> 19; - if (nbank < 8) - nbank = 2 + (nbank >> 2); - else if (nbank < 10) - nbank -= 8; - else - nbank -= 6; - break; + case 0x45: + nbank = addr >> 19; + if (nbank < 8) + nbank = 2 + (nbank >> 2); + else if (nbank < 10) + nbank -= 8; + else + nbank -= 6; + break; - default: - nbank = addr >> (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8 && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) ? 19 : 21); - break; - } + default: + nbank = addr >> (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8 && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) ? 19 : 21); + break; + } - nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3; + nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3; - if ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && - (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3 && - nbank == 2 && (addr & 0x7ffff) < 0x60000 && mem_size > 640) { - nbank = 1; - addr ^= 0x70000; - } + if ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3 && nbank == 2 && (addr & 0x7ffff) < 0x60000 && mem_size > 640) { + nbank = 1; + addr ^= 0x70000; + } - if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) { - if (nbank == 3) - nbank = 7; - else - return 0xffffffff; - } else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) { - switch(nbank) { - case 7: - nbank = 3; - break; + if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) { + if (nbank == 3) + nbank = 7; + else + return 0xffffffff; + } else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) { + switch (nbank) { + case 7: + nbank = 3; + break; - /* Note - In the following cases, the chipset accesses multiple memory banks - at the same time, so it's impossible to predict which memory bank - is actually accessed. */ - case 5: - case 1: - nbank = 1; - break; + /* Note - In the following cases, the chipset accesses multiple memory banks + at the same time, so it's impossible to predict which memory bank + is actually accessed. */ + case 5: + case 1: + nbank = 1; + break; - case 3: - nbank = 2; - break; + case 3: + nbank = 2; + break; - default: - nbank = 0; - break; - } - } + default: + nbank = 0; + break; + } + } - if ((dev->regs[SCAT_VERSION] & 0x0f) > 3 && (mem_size > 2048) && (mem_size & 1536)) { - if ((mem_size & 1536) == 512) { - if (nbank == 0) - addr &= 0x7ffff; - else - addr = 0x80000 + ((addr & 0x1fffff) | ((nbank - 1) << 21)); - } else { - if (nbank < 2) - addr = (addr & 0x7ffff) | (nbank << 19); - else - addr = 0x100000 + ((addr & 0x1fffff) | ((nbank - 2) << 21)); - } - } else { - if (mem_size <= ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 2048 : 4096) && (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8) || dev->external_is_RAS)) { - nbanks_2048k = 0; - nbanks_512k = mem_size >> 9; - } else { - nbanks_2048k = mem_size >> 11; - nbanks_512k = (mem_size & 1536) >> 9; - } + if ((dev->regs[SCAT_VERSION] & 0x0f) > 3 && (mem_size > 2048) && (mem_size & 1536)) { + if ((mem_size & 1536) == 512) { + if (nbank == 0) + addr &= 0x7ffff; + else + addr = 0x80000 + ((addr & 0x1fffff) | ((nbank - 1) << 21)); + } else { + if (nbank < 2) + addr = (addr & 0x7ffff) | (nbank << 19); + else + addr = 0x100000 + ((addr & 0x1fffff) | ((nbank - 2) << 21)); + } + } else { + if (mem_size <= ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 2048 : 4096) && (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8) || dev->external_is_RAS)) { + nbanks_2048k = 0; + nbanks_512k = mem_size >> 9; + } else { + nbanks_2048k = mem_size >> 11; + nbanks_512k = (mem_size & 1536) >> 9; + } - if (nbank < nbanks_2048k || (nbanks_2048k > 0 && nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7))) { - addr &= 0x1fffff; - addr |= (nbank << 21); - } else if (nbank < nbanks_2048k + nbanks_512k || nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7)) { - addr &= 0x7ffff; - addr |= (nbanks_2048k << 21) | ((nbank - nbanks_2048k) << 19); - } else { - addr &= 0x1ffff; - addr |= (nbanks_2048k << 21) | (nbanks_512k << 19) | ((nbank - nbanks_2048k - nbanks_512k) << 17); - } - } + if (nbank < nbanks_2048k || (nbanks_2048k > 0 && nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7))) { + addr &= 0x1fffff; + addr |= (nbank << 21); + } else if (nbank < nbanks_2048k + nbanks_512k || nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7)) { + addr &= 0x7ffff; + addr |= (nbanks_2048k << 21) | ((nbank - nbanks_2048k) << 19); + } else { + addr &= 0x1ffff; + addr |= (nbanks_2048k << 21) | (nbanks_512k << 19) | ((nbank - nbanks_2048k - nbanks_512k) << 17); + } + } } else { - switch(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) { - case 0x02: - case 0x04: - nbank = addr >> 19; - if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else - addr2 = addr >> 10; - break; + switch (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) { + case 0x02: + case 0x04: + nbank = addr >> 19; + if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else + addr2 = addr >> 10; + break; - case 0x03: - nbank = addr >> 19; - if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) == 2 && (addr & 0x7ffff) < 0x60000) { - addr ^= 0x1f0000; - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else - addr2 = addr >> 10; - break; + case 0x03: + nbank = addr >> 19; + if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) == 2 && (addr & 0x7ffff) < 0x60000) { + addr ^= 0x1f0000; + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else + addr2 = addr >> 10; + break; - case 0x05: - nbank = addr >> 19; - if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) { - nbank = (addr >> 10) & 3; - addr2 = addr >> 12; - } else - addr2 = addr >> 10; - break; + case 0x05: + nbank = addr >> 19; + if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) { + nbank = (addr >> 10) & 3; + addr2 = addr >> 12; + } else + addr2 = addr >> 10; + break; - case 0x06: - nbank = addr >> 19; - if (nbank < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else { - nbank = 2 + ((addr - 0x100000) >> 21); - addr2 = (addr - 0x100000) >> 11; - } - break; + case 0x06: + nbank = addr >> 19; + if (nbank < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else { + nbank = 2 + ((addr - 0x100000) >> 21); + addr2 = (addr - 0x100000) >> 11; + } + break; - case 0x07: - case 0x0f: - nbank = addr >> 19; - if (nbank < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else if (nbank < 10) { - nbank = 2 + (((addr - 0x100000) >> 11) & 1); - addr2 = (addr - 0x100000) >> 12; - } else { - nbank = 4 + ((addr - 0x500000) >> 21); - addr2 = (addr - 0x500000) >> 11; - } - break; + case 0x07: + case 0x0f: + nbank = addr >> 19; + if (nbank < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else if (nbank < 10) { + nbank = 2 + (((addr - 0x100000) >> 11) & 1); + addr2 = (addr - 0x100000) >> 12; + } else { + nbank = 4 + ((addr - 0x500000) >> 21); + addr2 = (addr - 0x500000) >> 11; + } + break; - case 0x08: - nbank = addr >> 19; - if (nbank < 4) { - nbank = 1; - addr2 = addr >> 11; - } else if (nbank == 4) { - nbank = 0; - addr2 = addr >> 10; - } else { - nbank -= 3; - addr2 = addr >> 10; - } - break; + case 0x08: + nbank = addr >> 19; + if (nbank < 4) { + nbank = 1; + addr2 = addr >> 11; + } else if (nbank == 4) { + nbank = 0; + addr2 = addr >> 10; + } else { + nbank -= 3; + addr2 = addr >> 10; + } + break; - case 0x09: - nbank = addr >> 19; - if (nbank < 8) { - nbank = 1 + ((addr >> 11) & 1); - addr2 = addr >> 12; - } else if (nbank == 8) { - nbank = 0; - addr2 = addr >> 10; - } else { - nbank -= 6; - addr2 = addr >> 10; - } - break; + case 0x09: + nbank = addr >> 19; + if (nbank < 8) { + nbank = 1 + ((addr >> 11) & 1); + addr2 = addr >> 12; + } else if (nbank == 8) { + nbank = 0; + addr2 = addr >> 10; + } else { + nbank -= 6; + addr2 = addr >> 10; + } + break; - case 0x0a: - nbank = addr >> 19; - if (nbank < 8) { - nbank = 1 + ((addr >> 11) & 1); - addr2 = addr >> 12; - } else if (nbank < 12) { - nbank = 3; - addr2 = addr >> 11; - } else if (nbank == 12) { - nbank = 0; - addr2 = addr >> 10; - } else { - nbank -= 9; - addr2 = addr >> 10; - } - break; + case 0x0a: + nbank = addr >> 19; + if (nbank < 8) { + nbank = 1 + ((addr >> 11) & 1); + addr2 = addr >> 12; + } else if (nbank < 12) { + nbank = 3; + addr2 = addr >> 11; + } else if (nbank == 12) { + nbank = 0; + addr2 = addr >> 10; + } else { + nbank -= 9; + addr2 = addr >> 10; + } + break; - case 0x0b: - nbank = addr >> 21; - addr2 = addr >> 11; - break; + case 0x0b: + nbank = addr >> 21; + addr2 = addr >> 11; + break; - case 0x0c: - case 0x0d: - nbank = addr >> 21; - if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { - nbank = (addr >> 11) & 1; - addr2 = addr >> 12; - } else - addr2 = addr >> 11; - break; + case 0x0c: + case 0x0d: + nbank = addr >> 21; + if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) { + nbank = (addr >> 11) & 1; + addr2 = addr >> 12; + } else + addr2 = addr >> 11; + break; - case 0x0e: - case 0x13: - nbank = addr >> 21; - if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) { - nbank = (addr >> 11) & 3; - addr2 = addr >> 13; - } else - addr2 = addr >> 11; - break; + case 0x0e: + case 0x13: + nbank = addr >> 21; + if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) { + nbank = (addr >> 11) & 3; + addr2 = addr >> 13; + } else + addr2 = addr >> 11; + break; - case 0x10: - case 0x11: - nbank = addr >> 19; - if (nbank < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else if (nbank < 10) { - nbank = 2 + (((addr - 0x100000) >> 11) & 1); - addr2 = (addr - 0x100000) >> 12; - } else if (nbank < 18) { - nbank = 4 + (((addr - 0x500000) >> 11) & 1); - addr2 = (addr - 0x500000) >> 12; - } else { - nbank = 6 + ((addr - 0x900000) >> 21); - addr2 = (addr - 0x900000) >> 11; - } - break; + case 0x10: + case 0x11: + nbank = addr >> 19; + if (nbank < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else if (nbank < 10) { + nbank = 2 + (((addr - 0x100000) >> 11) & 1); + addr2 = (addr - 0x100000) >> 12; + } else if (nbank < 18) { + nbank = 4 + (((addr - 0x500000) >> 11) & 1); + addr2 = (addr - 0x500000) >> 12; + } else { + nbank = 6 + ((addr - 0x900000) >> 21); + addr2 = (addr - 0x900000) >> 11; + } + break; - case 0x12: - nbank = addr >> 19; - if (nbank < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else if (nbank < 10) { - nbank = 2 + (((addr - 0x100000) >> 11) & 1); - addr2 = (addr - 0x100000) >> 12; - } else { - nbank = 4 + (((addr - 0x500000) >> 11) & 3); - addr2 = (addr - 0x500000) >> 13; - } - break; + case 0x12: + nbank = addr >> 19; + if (nbank < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else if (nbank < 10) { + nbank = 2 + (((addr - 0x100000) >> 11) & 1); + addr2 = (addr - 0x100000) >> 12; + } else { + nbank = 4 + (((addr - 0x500000) >> 11) & 3); + addr2 = (addr - 0x500000) >> 13; + } + break; - case 0x14: - case 0x15: - nbank = addr >> 21; - if ((nbank & 7) < 4) { - nbank = (addr >> 11) & 3; - addr2 = addr >> 13; - } else if ((nbank & 7) < 6) { - nbank = 4 + (((addr - 0x800000) >> 11) & 1); - addr2 = (addr - 0x800000) >> 12; - } else { - nbank = 6 + (((addr - 0xc00000) >> 11) & 3); - addr2 = (addr - 0xc00000) >> 13; - } - break; + case 0x14: + case 0x15: + nbank = addr >> 21; + if ((nbank & 7) < 4) { + nbank = (addr >> 11) & 3; + addr2 = addr >> 13; + } else if ((nbank & 7) < 6) { + nbank = 4 + (((addr - 0x800000) >> 11) & 1); + addr2 = (addr - 0x800000) >> 12; + } else { + nbank = 6 + (((addr - 0xc00000) >> 11) & 3); + addr2 = (addr - 0xc00000) >> 13; + } + break; - case 0x16: - nbank = ((addr >> 21) & 4) | ((addr >> 11) & 3); - addr2 = addr >> 13; - break; + case 0x16: + nbank = ((addr >> 21) & 4) | ((addr >> 11) & 3); + addr2 = addr >> 13; + break; - case 0x17: - if (dev->external_is_RAS && (addr & 0x800) == 0) - return 0xffffffff; - nbank = addr >> 19; - if (nbank < 2) { - nbank = (addr >> 10) & 1; - addr2 = addr >> 11; - } else { - nbank = 2 + ((addr - 0x100000) >> 23); - addr2 = (addr - 0x100000) >> 12; - } - break; + case 0x17: + if (dev->external_is_RAS && (addr & 0x800) == 0) + return 0xffffffff; + nbank = addr >> 19; + if (nbank < 2) { + nbank = (addr >> 10) & 1; + addr2 = addr >> 11; + } else { + nbank = 2 + ((addr - 0x100000) >> 23); + addr2 = (addr - 0x100000) >> 12; + } + break; - case 0x18: - if (dev->external_is_RAS && (addr & 0x800) == 0) - return 0xffffffff; - nbank = addr >> 21; - if (nbank < 4) { - nbank = 1; - addr2 = addr >> 12; - } else if (nbank == 4) { - nbank = 0; - addr2 = addr >> 11; - } else { - nbank -= 3; - addr2 = addr >> 11; - } - break; + case 0x18: + if (dev->external_is_RAS && (addr & 0x800) == 0) + return 0xffffffff; + nbank = addr >> 21; + if (nbank < 4) { + nbank = 1; + addr2 = addr >> 12; + } else if (nbank == 4) { + nbank = 0; + addr2 = addr >> 11; + } else { + nbank -= 3; + addr2 = addr >> 11; + } + break; - case 0x19: - if (dev->external_is_RAS && (addr & 0x800) == 0) - return 0xffffffff; - nbank = addr >> 23; - if ((nbank & 3) < 2) { - nbank = (addr >> 12) & 1; - addr2 = addr >> 13; - } else - addr2 = addr >> 12; - break; + case 0x19: + if (dev->external_is_RAS && (addr & 0x800) == 0) + return 0xffffffff; + nbank = addr >> 23; + if ((nbank & 3) < 2) { + nbank = (addr >> 12) & 1; + addr2 = addr >> 13; + } else + addr2 = addr >> 12; + break; - default: - if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6) { - nbank = addr >> 19; - addr2 = (addr >> 10) & 0x1ff; - } else if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) { - nbank = addr >> 21; - addr2 = (addr >> 11) & 0x3ff; - } else { - nbank = addr >> 23; - addr2 = (addr >> 12) & 0x7ff; - } - break; - } + default: + if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6) { + nbank = addr >> 19; + addr2 = (addr >> 10) & 0x1ff; + } else if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) { + nbank = addr >> 21; + addr2 = (addr >> 11) & 0x3ff; + } else { + nbank = addr >> 23; + addr2 = (addr >> 12) & 0x7ff; + } + break; + } - nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3; + nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3; - if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 0x16 && nbank == 3) - return 0xffffffff; + if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 0x16 && nbank == 3) + return 0xffffffff; - if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) { - if (nbank == 3) - nbank = 7; - else - return 0xffffffff; - } else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) { - switch(nbank) { - case 7: - nbank = 3; - break; + if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) { + if (nbank == 3) + nbank = 7; + else + return 0xffffffff; + } else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) { + switch (nbank) { + case 7: + nbank = 3; + break; - /* Note - In the following cases, the chipset accesses multiple memory banks - at the same time, so it's impossible to predict which memory bank - is actually accessed. */ - case 5: - case 1: - nbank = 1; - break; + /* Note - In the following cases, the chipset accesses multiple memory banks + at the same time, so it's impossible to predict which memory bank + is actually accessed. */ + case 5: + case 1: + nbank = 1; + break; - case 3: - nbank = 2; - break; + case 3: + nbank = 2; + break; - default: - nbank = 0; - break; - } - } + default: + nbank = 0; + break; + } + } - switch(mem_size & ~511) { - case 1024: - case 1536: - addr &= 0x3ff; - if (nbank < 2) - addr |= (nbank << 10) | ((addr2 & 0x1ff) << 11); - else - addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19); - break; + switch (mem_size & ~511) { + case 1024: + case 1536: + addr &= 0x3ff; + if (nbank < 2) + addr |= (nbank << 10) | ((addr2 & 0x1ff) << 11); + else + addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19); + break; - case 2048: - if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 5) { - addr &= 0x3ff; - if (nbank < 4) - addr |= (nbank << 10) | ((addr2 & 0x1ff) << 12); - else - addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19); - } else { - addr &= 0x7ff; - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - } - break; + case 2048: + if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 5) { + addr &= 0x3ff; + if (nbank < 4) + addr |= (nbank << 10) | ((addr2 & 0x1ff) << 12); + else + addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19); + } else { + addr &= 0x7ff; + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + } + break; - case 2560: - if (nbank == 0) - addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); - else { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21)); - } - break; + case 2560: + if (nbank == 0) + addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); + else { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21)); + } + break; - case 3072: - if (nbank < 2) - addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); - else - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); - break; + case 3072: + if (nbank < 2) + addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); + else + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); + break; - case 4096: - case 6144: - addr &= 0x7ff; - if (nbank < 2) - addr |= (nbank << 11) | ((addr2 & 0x3ff) << 12); - else - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - break; + case 4096: + case 6144: + addr &= 0x7ff; + if (nbank < 2) + addr |= (nbank << 11) | ((addr2 & 0x3ff) << 12); + else + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + break; - case 4608: - if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) { - if (nbank == 0) - addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); - else if (nbank < 3) - addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12)); - else - addr = 0x480000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 3) << 19)); - } else if (nbank == 0) - addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); - else { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21)); - } - break; + case 4608: + if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) { + if (nbank == 0) + addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); + else if (nbank < 3) + addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12)); + else + addr = 0x480000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 3) << 19)); + } else if (nbank == 0) + addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); + else { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21)); + } + break; - case 5120: - case 7168: - if (nbank < 2) - addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); - else if (nbank < 4) - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); - else - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); - break; + case 5120: + case 7168: + if (nbank < 2) + addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); + else if (nbank < 4) + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); + else + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); + break; - case 6656: - if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) { - if (nbank == 0) - addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); - else if (nbank < 3) - addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12)); - else if (nbank == 3) - addr = 0x480000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11)); - else - addr = 0x680000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 4) << 19)); - } else if (nbank == 0) - addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); - else if (nbank == 1) { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr = addr + 0x80000 + (addr2 << 11); - } else { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr = addr + 0x280000 + ((addr2 << 12) | ((nbank & 1) << 11) | (((nbank - 2) & 6) << 21)); - } - break; + case 6656: + if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) { + if (nbank == 0) + addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); + else if (nbank < 3) + addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12)); + else if (nbank == 3) + addr = 0x480000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11)); + else + addr = 0x680000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 4) << 19)); + } else if (nbank == 0) + addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10); + else if (nbank == 1) { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr = addr + 0x80000 + (addr2 << 11); + } else { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr = addr + 0x280000 + ((addr2 << 12) | ((nbank & 1) << 11) | (((nbank - 2) & 6) << 21)); + } + break; - case 8192: - addr &= 0x7ff; - if (nbank < 4) - addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); - else - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - break; + case 8192: + addr &= 0x7ff; + if (nbank < 4) + addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); + else + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + break; - case 9216: - if (nbank < 2) - addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); - else if (dev->external_is_RAS) { - if (nbank < 6) - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); - else - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); - } else - addr = 0x100000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23)); - break; + case 9216: + if (nbank < 2) + addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); + else if (dev->external_is_RAS) { + if (nbank < 6) + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); + else + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); + } else + addr = 0x100000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23)); + break; - case 10240: - if (dev->external_is_RAS) { - addr &= 0x7ff; - if (nbank < 4) - addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); - else - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - } else if (nbank == 0) - addr = (addr & 0x7ff) | ((addr2 & 0x3ff) << 11); - else { - addr &= 0xfff; - addr2 &= 0x7ff; - addr = addr + 0x200000 + ((addr2 << 12) | ((nbank - 1) << 23)); - } - break; + case 10240: + if (dev->external_is_RAS) { + addr &= 0x7ff; + if (nbank < 4) + addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); + else + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + } else if (nbank == 0) + addr = (addr & 0x7ff) | ((addr2 & 0x3ff) << 11); + else { + addr &= 0xfff; + addr2 &= 0x7ff; + addr = addr + 0x200000 + ((addr2 << 12) | ((nbank - 1) << 23)); + } + break; - case 11264: - if (nbank < 2) - addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); - else if (nbank < 6) - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); - else - addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); - break; + case 11264: + if (nbank < 2) + addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11); + else if (nbank < 6) + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11)); + else + addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21)); + break; - case 12288: - if (dev->external_is_RAS) { - addr &= 0x7ff; - if (nbank < 4) - addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); - else if (nbank < 6) - addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21); - else - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - } else { - if (nbank < 2) - addr = (addr & 0x7ff) | (nbank << 11) | ((addr2 & 0x3ff) << 12); - else - addr = 0x400000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23)); - } - break; + case 12288: + if (dev->external_is_RAS) { + addr &= 0x7ff; + if (nbank < 4) + addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); + else if (nbank < 6) + addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21); + else + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + } else { + if (nbank < 2) + addr = (addr & 0x7ff) | (nbank << 11) | ((addr2 & 0x3ff) << 12); + else + addr = 0x400000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23)); + } + break; - case 13312: - if (nbank < 2) - addr = (addr & 0x3FF) | (nbank << 10) | ((addr2 & 0x1FF) << 11); - else if (nbank < 4) - addr = 0x100000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 12) | ((nbank & 1) << 11)); - else - addr = 0x500000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 13) | ((nbank & 3) << 11)); - break; + case 13312: + if (nbank < 2) + addr = (addr & 0x3FF) | (nbank << 10) | ((addr2 & 0x1FF) << 11); + else if (nbank < 4) + addr = 0x100000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 12) | ((nbank & 1) << 11)); + else + addr = 0x500000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 13) | ((nbank & 3) << 11)); + break; - case 14336: - addr &= 0x7ff; - if (nbank < 4) - addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); - else if (nbank < 6) - addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21); - else - addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); - break; + case 14336: + addr &= 0x7ff; + if (nbank < 4) + addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13); + else if (nbank < 6) + addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21); + else + addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21); + break; - case 16384: - if (dev->external_is_RAS) { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr |= ((nbank & 3) << 11) | (addr2 << 13) | ((nbank & 4) << 21); - } else { - addr &= 0xfff; - addr2 &= 0x7ff; - if (nbank < 2) - addr |= (addr2 << 13) | (nbank << 12); - else - addr |= (addr2 << 12) | (nbank << 23); - } - break; + case 16384: + if (dev->external_is_RAS) { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr |= ((nbank & 3) << 11) | (addr2 << 13) | ((nbank & 4) << 21); + } else { + addr &= 0xfff; + addr2 &= 0x7ff; + if (nbank < 2) + addr |= (addr2 << 13) | (nbank << 12); + else + addr |= (addr2 << 12) | (nbank << 23); + } + break; - default: - if (mem_size < 2048 || ((mem_size & 1536) == 512) || (mem_size == 2048 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6)) { - addr &= 0x3ff; - addr2 &= 0x1ff; - addr |= (addr2 << 10) | (nbank << 19); - } else if (mem_size < 8192 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) { - addr &= 0x7ff; - addr2 &= 0x3ff; - addr |= (addr2 << 11) | (nbank << 21); - } else { - addr &= 0xfff; - addr2 &= 0x7ff; - addr |= (addr2 << 12) | (nbank << 23); - } - break; - } + default: + if (mem_size < 2048 || ((mem_size & 1536) == 512) || (mem_size == 2048 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6)) { + addr &= 0x3ff; + addr2 &= 0x1ff; + addr |= (addr2 << 10) | (nbank << 19); + } else if (mem_size < 8192 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) { + addr &= 0x7ff; + addr2 &= 0x3ff; + addr |= (addr2 << 11) | (nbank << 21); + } else { + addr &= 0xfff; + addr2 &= 0x7ff; + addr |= (addr2 << 12) | (nbank << 23); + } + break; + } } return addr; } - static void set_global_EMS_state(scat_t *dev, int state) { uint32_t base_addr, virt_addr; - int i, conf; + int i, conf; for (i = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 24; i < 32; i++) { - base_addr = (i + 16) << 14; + base_addr = (i + 16) << 14; - if (i >= 24) - base_addr += 0x30000; - if (state && (dev->page[i].regs_2x9 & 0x80)) { - virt_addr = get_addr(dev, base_addr, &dev->page[i]); - if (i < 24) - mem_mapping_disable(&dev->efff_mapping[i]); - else - mem_mapping_disable(&dev->efff_mapping[i + 12]); - mem_mapping_enable(&dev->ems_mapping[i]); + if (i >= 24) + base_addr += 0x30000; + if (state && (dev->page[i].regs_2x9 & 0x80)) { + virt_addr = get_addr(dev, base_addr, &dev->page[i]); + if (i < 24) + mem_mapping_disable(&dev->efff_mapping[i]); + else + mem_mapping_disable(&dev->efff_mapping[i + 12]); + mem_mapping_enable(&dev->ems_mapping[i]); - if (virt_addr < ((uint32_t)mem_size << 10)) - mem_mapping_set_exec(&dev->ems_mapping[i], ram + virt_addr); - else - mem_mapping_set_exec(&dev->ems_mapping[i], NULL); - } else { - mem_mapping_set_exec(&dev->ems_mapping[i], ram + base_addr); - mem_mapping_disable(&dev->ems_mapping[i]); + if (virt_addr < ((uint32_t) mem_size << 10)) + mem_mapping_set_exec(&dev->ems_mapping[i], ram + virt_addr); + else + mem_mapping_set_exec(&dev->ems_mapping[i], NULL); + } else { + mem_mapping_set_exec(&dev->ems_mapping[i], ram + base_addr); + mem_mapping_disable(&dev->ems_mapping[i]); - conf = (dev->regs[SCAT_VERSION] & 0xf0) ? (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) - : (dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) | - ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2); - if (i < 24) { - if (conf > 1 || (conf == 1 && i < 16)) - mem_mapping_enable(&dev->efff_mapping[i]); - else - mem_mapping_disable(&dev->efff_mapping[i]); - } else if (conf > 3 || ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && conf == 2)) - mem_mapping_enable(&dev->efff_mapping[i + 12]); - else - mem_mapping_disable(&dev->efff_mapping[i + 12]); - } + conf = (dev->regs[SCAT_VERSION] & 0xf0) ? (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) + : (dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2); + if (i < 24) { + if (conf > 1 || (conf == 1 && i < 16)) + mem_mapping_enable(&dev->efff_mapping[i]); + else + mem_mapping_disable(&dev->efff_mapping[i]); + } else if (conf > 3 || ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && conf == 2)) + mem_mapping_enable(&dev->efff_mapping[i + 12]); + else + mem_mapping_disable(&dev->efff_mapping[i + 12]); + } } flushmmucache(); } - static void memmap_state_update(scat_t *dev) { uint32_t addr; - int i; + int i; for (i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) { - addr = get_addr(dev, 0x40000 + (i << 14), &dev->null_page); - mem_mapping_set_exec(&dev->efff_mapping[i], - addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); + addr = get_addr(dev, 0x40000 + (i << 14), &dev->null_page); + mem_mapping_set_exec(&dev->efff_mapping[i], + addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); } addr = get_addr(dev, 0, &dev->null_page); mem_mapping_set_exec(&dev->low_mapping[0], - addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); + addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); addr = get_addr(dev, 0xf0000, &dev->null_page); mem_mapping_set_exec(&dev->low_mapping[1], - addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); + addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); for (i = 2; i < 32; i++) { - addr = get_addr(dev, i << 19, &dev->null_page); - mem_mapping_set_exec(&dev->low_mapping[i], - addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); + addr = get_addr(dev, i << 19, &dev->null_page); + mem_mapping_set_exec(&dev->low_mapping[i], + addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); } if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { - for (i = 0; i < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | - ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; i++) - mem_mapping_enable(&dev->low_mapping[i]); + for (i = 0; i < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; i++) + mem_mapping_enable(&dev->low_mapping[i]); - for (; i < 32; i++) - mem_mapping_disable(&dev->low_mapping[i]); + for (; i < 32; i++) + mem_mapping_disable(&dev->low_mapping[i]); - for (i = 24; i < 36; i++) { - if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40)) < 4) - mem_mapping_disable(&dev->efff_mapping[i]); - else - mem_mapping_enable(&dev->efff_mapping[i]); - } + for (i = 24; i < 36; i++) { + if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40)) < 4) + mem_mapping_disable(&dev->efff_mapping[i]); + else + mem_mapping_enable(&dev->efff_mapping[i]); + } } else { - for (i = 0; i < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; i++) - mem_mapping_enable(&dev->low_mapping[i]); + for (i = 0; i < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; i++) + mem_mapping_enable(&dev->low_mapping[i]); - for (; i < 32; i++) - mem_mapping_disable(&dev->low_mapping[i]); + for (; i < 32; i++) + mem_mapping_disable(&dev->low_mapping[i]); - for(i = 24; i < 36; i++) { - if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 2 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3) - mem_mapping_disable(&dev->efff_mapping[i]); - else - mem_mapping_enable(&dev->efff_mapping[i]); - } + for (i = 24; i < 36; i++) { + if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 2 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3) + mem_mapping_disable(&dev->efff_mapping[i]); + else + mem_mapping_enable(&dev->efff_mapping[i]); + } } - if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && - (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) || ((dev->regs[SCAT_VERSION] & 0xf0) != 0)) { - if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && - (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || - (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) { - mem_mapping_disable(&dev->low_mapping[2]); + if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) || ((dev->regs[SCAT_VERSION] & 0xf0) != 0)) { + if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) { + mem_mapping_disable(&dev->low_mapping[2]); - for (i = 0; i < 6; i++) { - addr = get_addr(dev, 0x100000 + (i << 16), &dev->null_page); - mem_mapping_set_exec(&dev->remap_mapping[i], - addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL); - mem_mapping_enable(&dev->remap_mapping[i]); - } - } else { - for (i = 0; i < 6; i++) - mem_mapping_disable(&dev->remap_mapping[i]); + for (i = 0; i < 6; i++) { + addr = get_addr(dev, 0x100000 + (i << 16), &dev->null_page); + mem_mapping_set_exec(&dev->remap_mapping[i], + addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL); + mem_mapping_enable(&dev->remap_mapping[i]); + } + } else { + for (i = 0; i < 6; i++) + mem_mapping_disable(&dev->remap_mapping[i]); - if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && - (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) > 4) || - (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && - (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 3)) - mem_mapping_enable(&dev->low_mapping[2]); - } + if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) > 4) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 3)) + mem_mapping_enable(&dev->low_mapping[2]); + } } else { - for (i = 0; i < 6; i++) - mem_mapping_disable(&dev->remap_mapping[i]); + for (i = 0; i < 6; i++) + mem_mapping_disable(&dev->remap_mapping[i]); - mem_mapping_enable(&dev->low_mapping[2]); + mem_mapping_enable(&dev->low_mapping[2]); } set_global_EMS_state(dev, dev->regs[SCAT_EMS_CONTROL] & 0x80); @@ -1023,511 +1002,500 @@ memmap_state_update(scat_t *dev) flushmmucache_cr3(); } - static void scat_out(uint16_t port, uint8_t val, void *priv) { - scat_t *dev = (scat_t *)priv; - uint8_t reg_valid = 0, - shadow_update = 0, - map_update = 0, - indx; + scat_t *dev = (scat_t *) priv; + uint8_t reg_valid = 0, + shadow_update = 0, + map_update = 0, + indx; uint32_t base_addr, virt_addr; switch (port) { - case 0x22: - dev->indx = val; - break; + case 0x22: + dev->indx = val; + break; - case 0x23: - switch (dev->indx) { - case SCAT_DMA_WAIT_STATE_CONTROL: - case SCAT_CLOCK_CONTROL: - case SCAT_PERIPHERAL_CONTROL: - reg_valid = 1; - break; + case 0x23: + switch (dev->indx) { + case SCAT_DMA_WAIT_STATE_CONTROL: + case SCAT_CLOCK_CONTROL: + case SCAT_PERIPHERAL_CONTROL: + reg_valid = 1; + break; - case SCAT_EMS_CONTROL: - io_removehandler(0x0208, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); - io_removehandler(0x0218, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); + case SCAT_EMS_CONTROL: + io_removehandler(0x0208, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); + io_removehandler(0x0218, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); - if (val & 0x40) { - if (val & 1) - io_sethandler(0x0218, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); - else - io_sethandler(0x0208, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); - } - set_global_EMS_state(dev, val & 0x80); - reg_valid = 1; - break; + if (val & 0x40) { + if (val & 1) + io_sethandler(0x0218, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); + else + io_sethandler(0x0208, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev); + } + set_global_EMS_state(dev, val & 0x80); + reg_valid = 1; + break; - case SCAT_POWER_MANAGEMENT: - /* TODO - Only use AUX parity disable bit for this version. - Other bits should be implemented later. */ - val &= (dev->regs[SCAT_VERSION] & 0xf0) == 0 ? 0x40 : 0x60; - reg_valid = 1; - break; + case SCAT_POWER_MANAGEMENT: + /* TODO - Only use AUX parity disable bit for this version. + Other bits should be implemented later. */ + val &= (dev->regs[SCAT_VERSION] & 0xf0) == 0 ? 0x40 : 0x60; + reg_valid = 1; + break; - case SCAT_DRAM_CONFIGURATION: - map_update = 1; + case SCAT_DRAM_CONFIGURATION: + map_update = 1; - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { - cpu_waitstates = (val & 0x70) == 0 ? 1 : 2; - cpu_update_waitstates(); - } + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { + cpu_waitstates = (val & 0x70) == 0 ? 1 : 2; + cpu_update_waitstates(); + } - reg_valid = 1; - break; + reg_valid = 1; + break; - case SCAT_EXTENDED_BOUNDARY: - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { - if (dev->regs[SCAT_VERSION] < 4) { - val &= 0xbf; - set_xms_bound(dev, val & 0x0f); - } else { - val = (val & 0x7f) | 0x80; - set_xms_bound(dev, val & 0x4f); - } - } else - set_xms_bound(dev, val & 0x1f); + case SCAT_EXTENDED_BOUNDARY: + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { + if (dev->regs[SCAT_VERSION] < 4) { + val &= 0xbf; + set_xms_bound(dev, val & 0x0f); + } else { + val = (val & 0x7f) | 0x80; + set_xms_bound(dev, val & 0x4f); + } + } else + set_xms_bound(dev, val & 0x1f); - mem_set_mem_state(0x40000, 0x60000, (val & 0x20) ? MEM_READ_EXTANY | MEM_WRITE_EXTANY : - MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - if ((val ^ dev->regs[SCAT_EXTENDED_BOUNDARY]) & 0xc0) - map_update = 1; - reg_valid = 1; - break; + mem_set_mem_state(0x40000, 0x60000, (val & 0x20) ? MEM_READ_EXTANY | MEM_WRITE_EXTANY : MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + if ((val ^ dev->regs[SCAT_EXTENDED_BOUNDARY]) & 0xc0) + map_update = 1; + reg_valid = 1; + break; - case SCAT_ROM_ENABLE: - case SCAT_RAM_WRITE_PROTECT: - case SCAT_SHADOW_RAM_ENABLE_1: - case SCAT_SHADOW_RAM_ENABLE_2: - case SCAT_SHADOW_RAM_ENABLE_3: - reg_valid = 1; - shadow_update = 1; - break; + case SCAT_ROM_ENABLE: + case SCAT_RAM_WRITE_PROTECT: + case SCAT_SHADOW_RAM_ENABLE_1: + case SCAT_SHADOW_RAM_ENABLE_2: + case SCAT_SHADOW_RAM_ENABLE_3: + reg_valid = 1; + shadow_update = 1; + break; - case SCATSX_LAPTOP_FEATURES: - if ((dev->regs[SCAT_VERSION] & 0xf0) != 0) { - val = (val & ~8) | (dev->regs[SCATSX_LAPTOP_FEATURES] & 8); - reg_valid = 1; - } - break; + case SCATSX_LAPTOP_FEATURES: + if ((dev->regs[SCAT_VERSION] & 0xf0) != 0) { + val = (val & ~8) | (dev->regs[SCATSX_LAPTOP_FEATURES] & 8); + reg_valid = 1; + } + break; - case SCATSX_FAST_VIDEO_CONTROL: - case SCATSX_FAST_VIDEORAM_ENABLE: - case SCATSX_HIGH_PERFORMANCE_REFRESH: - case SCATSX_CAS_TIMING_FOR_DMA: - if ((dev->regs[SCAT_VERSION] & 0xf0) != 0) - reg_valid = 1; - break; + case SCATSX_FAST_VIDEO_CONTROL: + case SCATSX_FAST_VIDEORAM_ENABLE: + case SCATSX_HIGH_PERFORMANCE_REFRESH: + case SCATSX_CAS_TIMING_FOR_DMA: + if ((dev->regs[SCAT_VERSION] & 0xf0) != 0) + reg_valid = 1; + break; - default: - break; - } + default: + break; + } - if (reg_valid) - dev->regs[dev->indx] = val; + if (reg_valid) + dev->regs[dev->indx] = val; - if (shadow_update) - shadow_state_update(dev); + if (shadow_update) + shadow_state_update(dev); - if (map_update) - memmap_state_update(dev); - break; + if (map_update) + memmap_state_update(dev); + break; - case 0x208: - case 0x218: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) - indx = dev->reg_2xA & 0x1f; - else - indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; - dev->page[indx].regs_2x8 = val; - base_addr = (indx + 16) << 14; - if (indx >= 24) - base_addr += 0x30000; + case 0x208: + case 0x218: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) + indx = dev->reg_2xA & 0x1f; + else + indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; + dev->page[indx].regs_2x8 = val; + base_addr = (indx + 16) << 14; + if (indx >= 24) + base_addr += 0x30000; - if ((dev->regs[SCAT_EMS_CONTROL] & 0x80) && (dev->page[indx].regs_2x9 & 0x80)) { - virt_addr = get_addr(dev, base_addr, &dev->page[indx]); - if (virt_addr < ((uint32_t)mem_size << 10)) - mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr); - else - mem_mapping_set_exec(&dev->ems_mapping[indx], NULL); - flushmmucache(); - } - } - break; + if ((dev->regs[SCAT_EMS_CONTROL] & 0x80) && (dev->page[indx].regs_2x9 & 0x80)) { + virt_addr = get_addr(dev, base_addr, &dev->page[indx]); + if (virt_addr < ((uint32_t) mem_size << 10)) + mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr); + else + mem_mapping_set_exec(&dev->ems_mapping[indx], NULL); + flushmmucache(); + } + } + break; - case 0x209: - case 0x219: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) - indx = dev->reg_2xA & 0x1f; - else - indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; - dev->page[indx].regs_2x9 = val; - base_addr = (indx + 16) << 14; - if (indx >= 24) - base_addr += 0x30000; + case 0x209: + case 0x219: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) + indx = dev->reg_2xA & 0x1f; + else + indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; + dev->page[indx].regs_2x9 = val; + base_addr = (indx + 16) << 14; + if (indx >= 24) + base_addr += 0x30000; - if (dev->regs[SCAT_EMS_CONTROL] & 0x80) { - if (val & 0x80) { - virt_addr = get_addr(dev, base_addr, &dev->page[indx]); - if (indx < 24) - mem_mapping_disable(&dev->efff_mapping[indx]); - else - mem_mapping_disable(&dev->efff_mapping[indx + 12]); - if (virt_addr < ((uint32_t)mem_size << 10)) - mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr); - else - mem_mapping_set_exec(&dev->ems_mapping[indx], NULL); - mem_mapping_enable(&dev->ems_mapping[indx]); - } else { - mem_mapping_set_exec(&dev->ems_mapping[indx], ram + base_addr); - mem_mapping_disable(&dev->ems_mapping[indx]); - if (indx < 24) - mem_mapping_enable(&dev->efff_mapping[indx]); - else - mem_mapping_enable(&dev->efff_mapping[indx + 12]); - } + if (dev->regs[SCAT_EMS_CONTROL] & 0x80) { + if (val & 0x80) { + virt_addr = get_addr(dev, base_addr, &dev->page[indx]); + if (indx < 24) + mem_mapping_disable(&dev->efff_mapping[indx]); + else + mem_mapping_disable(&dev->efff_mapping[indx + 12]); + if (virt_addr < ((uint32_t) mem_size << 10)) + mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr); + else + mem_mapping_set_exec(&dev->ems_mapping[indx], NULL); + mem_mapping_enable(&dev->ems_mapping[indx]); + } else { + mem_mapping_set_exec(&dev->ems_mapping[indx], ram + base_addr); + mem_mapping_disable(&dev->ems_mapping[indx]); + if (indx < 24) + mem_mapping_enable(&dev->efff_mapping[indx]); + else + mem_mapping_enable(&dev->efff_mapping[indx + 12]); + } - flushmmucache(); - } + flushmmucache(); + } - if (dev->reg_2xA & 0x80) - dev->reg_2xA = (dev->reg_2xA & 0xe0) | ((dev->reg_2xA + 1) & (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x1f : 3)); - } - break; + if (dev->reg_2xA & 0x80) + dev->reg_2xA = (dev->reg_2xA & 0xe0) | ((dev->reg_2xA + 1) & (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x1f : 3)); + } + break; - case 0x20a: - case 0x21a: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) - dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3; - break; + case 0x20a: + case 0x21a: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) + dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3; + break; } } - static uint8_t scat_in(uint16_t port, void *priv) { - scat_t *dev = (scat_t *)priv; + scat_t *dev = (scat_t *) priv; uint8_t ret = 0xff, indx; switch (port) { - case 0x23: - switch (dev->indx) { - case SCAT_MISCELLANEOUS_STATUS: - ret = (dev->regs[dev->indx] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5); - break; + case 0x23: + switch (dev->indx) { + case SCAT_MISCELLANEOUS_STATUS: + ret = (dev->regs[dev->indx] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5); + break; - case SCAT_DRAM_CONFIGURATION: - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) - ret = (dev->regs[dev->indx] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10); - else - ret = dev->regs[dev->indx]; - break; + case SCAT_DRAM_CONFIGURATION: + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) + ret = (dev->regs[dev->indx] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10); + else + ret = dev->regs[dev->indx]; + break; - case SCAT_EXTENDED_BOUNDARY: - ret = dev->regs[dev->indx]; - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { - if ((dev->regs[SCAT_VERSION] & 0x0f) >= 4) - ret |= 0x80; - else - ret &= 0xaf; - } - break; + case SCAT_EXTENDED_BOUNDARY: + ret = dev->regs[dev->indx]; + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) { + if ((dev->regs[SCAT_VERSION] & 0x0f) >= 4) + ret |= 0x80; + else + ret &= 0xaf; + } + break; - default: - ret = dev->regs[dev->indx]; - break; - } - break; + default: + ret = dev->regs[dev->indx]; + break; + } + break; - case 0x208: - case 0x218: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) - indx = dev->reg_2xA & 0x1f; - else - indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; - ret = dev->page[indx].regs_2x8; - } - break; + case 0x208: + case 0x218: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) + indx = dev->reg_2xA & 0x1f; + else + indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; + ret = dev->page[indx].regs_2x8; + } + break; - case 0x209: - case 0x219: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { - if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) - indx = dev->reg_2xA & 0x1f; - else - indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; - ret = dev->page[indx].regs_2x9; - } - break; + case 0x209: + case 0x219: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) { + if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) + indx = dev->reg_2xA & 0x1f; + else + indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24; + ret = dev->page[indx].regs_2x9; + } + break; - case 0x20a: - case 0x21a: - if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) - ret = dev->reg_2xA; - break; + case 0x20a: + case 0x21a: + if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) + ret = dev->reg_2xA; + break; } return ret; } - static uint8_t mem_read_scatb(uint32_t addr, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint8_t val = 0xff; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint8_t val = 0xff; addr = get_addr(dev, addr, page); - if (addr < ((uint32_t)mem_size << 10)) - val = ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + val = ram[addr]; return val; } - static uint16_t mem_read_scatw(uint32_t addr, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint16_t val = 0xffff; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint16_t val = 0xffff; addr = get_addr(dev, addr, page); - if (addr < ((uint32_t)mem_size << 10)) - val = *(uint16_t *)&ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + val = *(uint16_t *) &ram[addr]; return val; } - static uint32_t mem_read_scatl(uint32_t addr, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint32_t val = 0xffffffff; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint32_t val = 0xffffffff; addr = get_addr(dev, addr, page); - if (addr < ((uint32_t)mem_size << 10)) - val = *(uint32_t *)&ram[addr]; + if (addr < ((uint32_t) mem_size << 10)) + val = *(uint32_t *) &ram[addr]; return val; } - static void mem_write_scatb(uint32_t addr, uint8_t val, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint32_t oldaddr = addr, chkaddr; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint32_t oldaddr = addr, chkaddr; - addr = get_addr(dev, addr, page); + addr = get_addr(dev, addr, page); chkaddr = page->valid ? addr : oldaddr; if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) { - if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) - return; + if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) + return; } - if (addr < ((uint32_t)mem_size << 10)) - ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + ram[addr] = val; } - static void mem_write_scatw(uint32_t addr, uint16_t val, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint32_t oldaddr = addr, chkaddr; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint32_t oldaddr = addr, chkaddr; - addr = get_addr(dev, addr, page); + addr = get_addr(dev, addr, page); chkaddr = page->valid ? addr : oldaddr; if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) { - if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) - return; + if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) + return; } - if (addr < ((uint32_t)mem_size << 10)) - *(uint16_t *)&ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + *(uint16_t *) &ram[addr] = val; } - static void mem_write_scatl(uint32_t addr, uint32_t val, void *priv) { - ems_page_t *page = (ems_page_t *)priv; - scat_t *dev = (scat_t *)page->scat; - uint32_t oldaddr = addr, chkaddr; + ems_page_t *page = (ems_page_t *) priv; + scat_t *dev = (scat_t *) page->scat; + uint32_t oldaddr = addr, chkaddr; - addr = get_addr(dev, addr, page); + addr = get_addr(dev, addr, page); chkaddr = page->valid ? addr : oldaddr; if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) { - if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) - return; + if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15))) + return; } - if (addr < ((uint32_t)mem_size << 10)) - *(uint32_t *)&ram[addr] = val; + if (addr < ((uint32_t) mem_size << 10)) + *(uint32_t *) &ram[addr] = val; } - static void scat_close(void *priv) { - scat_t *dev = (scat_t *)priv; + scat_t *dev = (scat_t *) priv; free(dev); } - static void * scat_init(const device_t *info) { - scat_t *dev; + scat_t *dev; uint32_t i, k; - int sx; + int sx; - dev = (scat_t *)malloc(sizeof(scat_t)); + dev = (scat_t *) malloc(sizeof(scat_t)); memset(dev, 0x00, sizeof(scat_t)); dev->type = info->local; sx = (dev->type == 32) ? 1 : 0; for (i = 0; i < sizeof(dev->regs); i++) - dev->regs[i] = 0xff; + dev->regs[i] = 0xff; if (sx) { - dev->regs[SCAT_VERSION] = 0x13; - dev->regs[SCAT_CLOCK_CONTROL] = 6; - dev->regs[SCAT_PERIPHERAL_CONTROL] = 0; - dev->regs[SCAT_DRAM_CONFIGURATION] = 1; - dev->regs[SCATSX_LAPTOP_FEATURES] = 0; - dev->regs[SCATSX_FAST_VIDEO_CONTROL] = 0; - dev->regs[SCATSX_FAST_VIDEORAM_ENABLE] = 0; - dev->regs[SCATSX_HIGH_PERFORMANCE_REFRESH] = 8; - dev->regs[SCATSX_CAS_TIMING_FOR_DMA] = 3; + dev->regs[SCAT_VERSION] = 0x13; + dev->regs[SCAT_CLOCK_CONTROL] = 6; + dev->regs[SCAT_PERIPHERAL_CONTROL] = 0; + dev->regs[SCAT_DRAM_CONFIGURATION] = 1; + dev->regs[SCATSX_LAPTOP_FEATURES] = 0; + dev->regs[SCATSX_FAST_VIDEO_CONTROL] = 0; + dev->regs[SCATSX_FAST_VIDEORAM_ENABLE] = 0; + dev->regs[SCATSX_HIGH_PERFORMANCE_REFRESH] = 8; + dev->regs[SCATSX_CAS_TIMING_FOR_DMA] = 3; } else { - switch(dev->type) { - case 4: - dev->regs[SCAT_VERSION] = 4; - break; + switch (dev->type) { + case 4: + dev->regs[SCAT_VERSION] = 4; + break; - default: - dev->regs[SCAT_VERSION] = 1; - break; - } - dev->regs[SCAT_CLOCK_CONTROL] = 2; - dev->regs[SCAT_PERIPHERAL_CONTROL] = 0x80; - dev->regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12; + default: + dev->regs[SCAT_VERSION] = 1; + break; + } + dev->regs[SCAT_CLOCK_CONTROL] = 2; + dev->regs[SCAT_PERIPHERAL_CONTROL] = 0x80; + dev->regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12; } dev->regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0; - dev->regs[SCAT_MISCELLANEOUS_STATUS] = 0x37; - dev->regs[SCAT_ROM_ENABLE] = 0xc0; - dev->regs[SCAT_RAM_WRITE_PROTECT] = 0; - dev->regs[SCAT_POWER_MANAGEMENT] = 0; - dev->regs[SCAT_SHADOW_RAM_ENABLE_1] = 0; - dev->regs[SCAT_SHADOW_RAM_ENABLE_2] = 0; - dev->regs[SCAT_SHADOW_RAM_ENABLE_3] = 0; - dev->regs[SCAT_EXTENDED_BOUNDARY] = 0; - dev->regs[SCAT_EMS_CONTROL] = 0; + dev->regs[SCAT_MISCELLANEOUS_STATUS] = 0x37; + dev->regs[SCAT_ROM_ENABLE] = 0xc0; + dev->regs[SCAT_RAM_WRITE_PROTECT] = 0; + dev->regs[SCAT_POWER_MANAGEMENT] = 0; + dev->regs[SCAT_SHADOW_RAM_ENABLE_1] = 0; + dev->regs[SCAT_SHADOW_RAM_ENABLE_2] = 0; + dev->regs[SCAT_SHADOW_RAM_ENABLE_3] = 0; + dev->regs[SCAT_EXTENDED_BOUNDARY] = 0; + dev->regs[SCAT_EMS_CONTROL] = 0; /* Disable all system mappings, we will override them. */ mem_mapping_disable(&ram_low_mapping); - if (! sx) - mem_mapping_disable(&ram_mid_mapping); + if (!sx) + mem_mapping_disable(&ram_mid_mapping); mem_mapping_disable(&ram_high_mapping); k = (sx) ? 0x80000 : 0x40000; - dev->null_page.valid = 0; + dev->null_page.valid = 0; dev->null_page.regs_2x8 = 0xff; dev->null_page.regs_2x9 = 0xff; - dev->null_page.scat = dev; + dev->null_page.scat = dev; mem_mapping_add(&dev->low_mapping[0], 0, k, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - ram, MEM_MAPPING_INTERNAL, &dev->null_page); + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + ram, MEM_MAPPING_INTERNAL, &dev->null_page); mem_mapping_add(&dev->low_mapping[1], 0xf0000, 0x10000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - ram + 0xf0000, MEM_MAPPING_INTERNAL, &dev->null_page); + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + ram + 0xf0000, MEM_MAPPING_INTERNAL, &dev->null_page); for (i = 2; i < 32; i++) { - mem_mapping_add(&dev->low_mapping[i], (i << 19), 0x80000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - ram + (i<<19), MEM_MAPPING_INTERNAL, &dev->null_page); + mem_mapping_add(&dev->low_mapping[i], (i << 19), 0x80000, + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + ram + (i << 19), MEM_MAPPING_INTERNAL, &dev->null_page); } if (sx) { - i = 16; - k = 0x40000; + i = 16; + k = 0x40000; } else { - i = 0; - k = (dev->regs[SCAT_VERSION] < 4) ? 0x40000 : 0x60000; + i = 0; + k = (dev->regs[SCAT_VERSION] < 4) ? 0x40000 : 0x60000; } mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000, k); for (; i < 44; i++) { - mem_mapping_add(&dev->efff_mapping[i], 0x40000 + (i << 14), 0x4000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - mem_size > (256 + (i << 4)) ? ram + 0x40000 + (i << 14) : NULL, - MEM_MAPPING_INTERNAL, &dev->null_page); + mem_mapping_add(&dev->efff_mapping[i], 0x40000 + (i << 14), 0x4000, + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + mem_size > (256 + (i << 4)) ? ram + 0x40000 + (i << 14) : NULL, + MEM_MAPPING_INTERNAL, &dev->null_page); - if (sx) - mem_mapping_enable(&dev->efff_mapping[i]); + if (sx) + mem_mapping_enable(&dev->efff_mapping[i]); } if (sx) { - for (i = 24; i < 32; i++) { - dev->page[i].valid = 1; - dev->page[i].regs_2x8 = 0xff; - dev->page[i].regs_2x9 = 0x03; - dev->page[i].scat = dev; - mem_mapping_add(&dev->ems_mapping[i], (i + 28) << 14, 0x04000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - ram + ((i + 28) << 14), 0, &dev->page[i]); - mem_mapping_disable(&dev->ems_mapping[i]); - } + for (i = 24; i < 32; i++) { + dev->page[i].valid = 1; + dev->page[i].regs_2x8 = 0xff; + dev->page[i].regs_2x9 = 0x03; + dev->page[i].scat = dev; + mem_mapping_add(&dev->ems_mapping[i], (i + 28) << 14, 0x04000, + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + ram + ((i + 28) << 14), 0, &dev->page[i]); + mem_mapping_disable(&dev->ems_mapping[i]); + } } else { - for (i = 0; i < 32; i++) { - dev->page[i].valid = 1; - dev->page[i].regs_2x8 = 0xff; - dev->page[i].regs_2x9 = 0x03; - dev->page[i].scat = dev; - mem_mapping_add(&dev->ems_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - ram + ((i + (i >= 24 ? 28 : 16)) << 14), - 0, &dev->page[i]); - } + for (i = 0; i < 32; i++) { + dev->page[i].valid = 1; + dev->page[i].regs_2x8 = 0xff; + dev->page[i].regs_2x9 = 0x03; + dev->page[i].scat = dev; + mem_mapping_add(&dev->ems_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + ram + ((i + (i >= 24 ? 28 : 16)) << 14), + 0, &dev->page[i]); + } } for (i = 0; i < 6; i++) { - mem_mapping_add(&dev->remap_mapping[i], 0x100000 + (i << 16), 0x10000, - mem_read_scatb, mem_read_scatw, mem_read_scatl, - mem_write_scatb, mem_write_scatw, mem_write_scatl, - mem_size >= 1024 ? ram + get_addr(dev, 0x100000 + (i << 16), &dev->null_page) : NULL, - MEM_MAPPING_INTERNAL, &dev->null_page); + mem_mapping_add(&dev->remap_mapping[i], 0x100000 + (i << 16), 0x10000, + mem_read_scatb, mem_read_scatw, mem_read_scatl, + mem_write_scatb, mem_write_scatw, mem_write_scatl, + mem_size >= 1024 ? ram + get_addr(dev, 0x100000 + (i << 16), &dev->null_page) : NULL, + MEM_MAPPING_INTERNAL, &dev->null_page); } if (sx) { - dev->external_is_RAS = scatsx_external_is_RAS[mem_size >> 9]; + dev->external_is_RAS = scatsx_external_is_RAS[mem_size >> 9]; } else { - dev->external_is_RAS = (dev->regs[SCAT_VERSION] > 3) || (((mem_size & ~2047) >> 11) + ((mem_size & 1536) >> 9) + ((mem_size & 511) >> 7)) > 4; + dev->external_is_RAS = (dev->regs[SCAT_VERSION] > 3) || (((mem_size & ~2047) >> 11) + ((mem_size & 1536) >> 9) + ((mem_size & 511) >> 7)) > 4; } set_xms_bound(dev, 0); @@ -1535,51 +1503,51 @@ scat_init(const device_t *info) shadow_state_update(dev); io_sethandler(0x0022, 2, - scat_in, NULL, NULL, scat_out, NULL, NULL, dev); + scat_in, NULL, NULL, scat_out, NULL, NULL, dev); device_add(&port_92_device); - return(dev); + return (dev); } const device_t scat_device = { - .name = "C&T SCAT (v1)", + .name = "C&T SCAT (v1)", .internal_name = "scat", - .flags = 0, - .local = 0, - .init = scat_init, - .close = scat_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = scat_init, + .close = scat_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t scat_4_device = { - .name = "C&T SCAT (v4)", + .name = "C&T SCAT (v4)", .internal_name = "scat_4", - .flags = 0, - .local = 4, - .init = scat_init, - .close = scat_close, - .reset = NULL, + .flags = 0, + .local = 4, + .init = scat_init, + .close = scat_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t scat_sx_device = { - .name = "C&T SCATsx", + .name = "C&T SCATsx", .internal_name = "scat_sx", - .flags = 0, - .local = 32, - .init = scat_init, - .close = scat_close, - .reset = NULL, + .flags = 0, + .local = 32, + .init = scat_init, + .close = scat_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_5511.c b/src/chipset/sis_5511.c index d0900629d..a4f3f42b1 100644 --- a/src/chipset/sis_5511.c +++ b/src/chipset/sis_5511.c @@ -39,70 +39,68 @@ #include <86box/chipset.h> /* IDE Flags (1 Native / 0 Compatibility)*/ -#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1) +#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1) #define SECONDARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 4) -#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8) -#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2) -#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8) -#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2) -#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8)) +#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8) +#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2) +#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8) +#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2) +#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8)) #ifdef ENABLE_SIS_5511_LOG int sis_5511_do_log = ENABLE_SIS_5511_LOG; static void sis_5511_log(const char *fmt, ...) { - va_list ap; + va_list ap; - if (sis_5511_do_log) - { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); - } + if (sis_5511_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } } #else -#define sis_5511_log(fmt, ...) +# define sis_5511_log(fmt, ...) #endif -typedef struct sis_5511_t -{ - uint8_t pci_conf[256], pci_conf_sb[2][256], - index, regs[16]; +typedef struct sis_5511_t { + uint8_t pci_conf[256], pci_conf_sb[2][256], + index, regs[16]; - int nb_pci_slot, sb_pci_slot; + int nb_pci_slot, sb_pci_slot; - sff8038i_t *ide_drive[2]; - smram_t *smram; - port_92_t *port_92; + sff8038i_t *ide_drive[2]; + smram_t *smram; + port_92_t *port_92; } sis_5511_t; static void sis_5511_shadow_recalc(sis_5511_t *dev) { - int i, state; + int i, state; uint32_t base; for (i = 0x80; i <= 0x86; i++) { - if (i == 0x86) { - state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state_both(0xf0000, 0x10000, state); - pclog("000F0000-000FFFFF\n"); - } else { - base = ((i & 0x07) << 15) + 0xc0000; + if (i == 0x86) { + state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + mem_set_mem_state_both(0xf0000, 0x10000, state); + pclog("000F0000-000FFFFF\n"); + } else { + base = ((i & 0x07) << 15) + 0xc0000; - state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state_both(base, 0x4000, state); - pclog("%08X-%08X\n", base, base + 0x3fff); + state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + mem_set_mem_state_both(base, 0x4000, state); + pclog("%08X-%08X\n", base, base + 0x3fff); - state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state_both(base + 0x4000, 0x4000, state); - pclog("%08X-%08X\n", base + 0x4000, base + 0x7fff); - } + state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + mem_set_mem_state_both(base + 0x4000, 0x4000, state); + pclog("%08X-%08X\n", base + 0x4000, base + 0x7fff); + } } flushmmucache_nopc(); @@ -114,512 +112,503 @@ sis_5511_smram_recalc(sis_5511_t *dev) smram_disable_all(); switch (dev->pci_conf[0x65] >> 6) { - case 0: - smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); - break; - case 1: - smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); - break; - case 2: - smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); - break; - } + case 0: + smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); + break; + case 1: + smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); + break; + case 2: + smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1); + break; + } - flushmmucache(); + flushmmucache(); } - -void sis_5513_ide_handler(sis_5511_t *dev) +void +sis_5513_ide_handler(sis_5511_t *dev) { - ide_pri_disable(); - ide_sec_disable(); - if (dev->pci_conf_sb[1][4] & 1) - { - if (dev->pci_conf_sb[1][0x4a] & 4) - { - ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0); - ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6); - ide_pri_enable(); - } - if (dev->pci_conf_sb[1][0x4a] & 2) - { - ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170); - ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376); - ide_sec_enable(); - } - } + ide_pri_disable(); + ide_sec_disable(); + if (dev->pci_conf_sb[1][4] & 1) { + if (dev->pci_conf_sb[1][0x4a] & 4) { + ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0); + ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6); + ide_pri_enable(); + } + if (dev->pci_conf_sb[1][0x4a] & 2) { + ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170); + ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376); + ide_sec_enable(); + } + } } -void sis_5513_bm_handler(sis_5511_t *dev) +void +sis_5513_bm_handler(sis_5511_t *dev) { - sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE); - sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8); + sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE); + sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8); } - static void sis_5511_write(int func, int addr, uint8_t val, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; switch (addr) { - case 0x07: /* Status - High Byte */ - dev->pci_conf[addr] &= 0xb0; - break; + case 0x07: /* Status - High Byte */ + dev->pci_conf[addr] &= 0xb0; + break; - case 0x50: - dev->pci_conf[addr] = val; - cpu_cache_ext_enabled = !!(val & 0x40); - cpu_update_waitstates(); - break; + case 0x50: + dev->pci_conf[addr] = val; + cpu_cache_ext_enabled = !!(val & 0x40); + cpu_update_waitstates(); + break; - case 0x51: - dev->pci_conf[addr] = val & 0xfe; - break; + case 0x51: + dev->pci_conf[addr] = val & 0xfe; + break; - case 0x52: - dev->pci_conf[addr] = val & 0x3f; - break; + case 0x52: + dev->pci_conf[addr] = val & 0x3f; + break; - case 0x53: case 0x54: - dev->pci_conf[addr] = val; - break; + case 0x53: + case 0x54: + dev->pci_conf[addr] = val; + break; - case 0x55: - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x55: + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x56 ... 0x59: - dev->pci_conf[addr] = val; - break; + case 0x56 ... 0x59: + dev->pci_conf[addr] = val; + break; - case 0x5a: - /* TODO: Fast Gate A20 Emulation and Fast Reset Emulation on the KBC. - The former (bit 7) means the chipset intercepts D1h to 64h and 00h to 60h. - The latter (bit 6) means the chipset intercepts all odd FXh to 64h. - Bit 5 sets fast reset latency. This should be fixed on the other SiS - chipsets as well. */ - dev->pci_conf[addr] = val; - break; + case 0x5a: + /* TODO: Fast Gate A20 Emulation and Fast Reset Emulation on the KBC. + The former (bit 7) means the chipset intercepts D1h to 64h and 00h to 60h. + The latter (bit 6) means the chipset intercepts all odd FXh to 64h. + Bit 5 sets fast reset latency. This should be fixed on the other SiS + chipsets as well. */ + dev->pci_conf[addr] = val; + break; - case 0x5b: - dev->pci_conf[addr] = val & 0xf7; - break; + case 0x5b: + dev->pci_conf[addr] = val & 0xf7; + break; - case 0x5c: - dev->pci_conf[addr] = val & 0xcf; - break; + case 0x5c: + dev->pci_conf[addr] = val & 0xcf; + break; - case 0x5d: - dev->pci_conf[addr] = val; - break; + case 0x5d: + dev->pci_conf[addr] = val; + break; - case 0x5e: - dev->pci_conf[addr] = val & 0xfe; - break; + case 0x5e: + dev->pci_conf[addr] = val & 0xfe; + break; - case 0x5f: - dev->pci_conf[addr] = val & 0xfe; - break; + case 0x5f: + dev->pci_conf[addr] = val & 0xfe; + break; - case 0x60: - dev->pci_conf[addr] = val & 0x3e; - if ((dev->pci_conf[0x68] & 1) && (val & 2)) { - smi_raise(); - dev->pci_conf[0x69] |= 1; - } - break; + case 0x60: + dev->pci_conf[addr] = val & 0x3e; + if ((dev->pci_conf[0x68] & 1) && (val & 2)) { + smi_raise(); + dev->pci_conf[0x69] |= 1; + } + break; - case 0x61 ... 0x64: - dev->pci_conf[addr] = val; - break; + case 0x61 ... 0x64: + dev->pci_conf[addr] = val; + break; - case 0x65: - dev->pci_conf[addr] = val & 0xd0; - sis_5511_smram_recalc(dev); - break; + case 0x65: + dev->pci_conf[addr] = val & 0xd0; + sis_5511_smram_recalc(dev); + break; - case 0x66: - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x66: + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x67: case 0x68: - dev->pci_conf[addr] = val; - break; + case 0x67: + case 0x68: + dev->pci_conf[addr] = val; + break; - case 0x69: - dev->pci_conf[addr] &= val; - break; + case 0x69: + dev->pci_conf[addr] &= val; + break; - case 0x6a ... 0x6e: - dev->pci_conf[addr] = val; - break; + case 0x6a ... 0x6e: + dev->pci_conf[addr] = val; + break; - case 0x6f: - dev->pci_conf[addr] = val & 0x3f; - break; + case 0x6f: + dev->pci_conf[addr] = val & 0x3f; + break; - case 0x70: /* DRAM Bank Register 0-0 */ - case 0x71: /* DRAM Bank Register 0-0 */ - case 0x72: /* DRAM Bank Register 0-1 */ - dev->pci_conf[addr] = val; - break; + case 0x70: /* DRAM Bank Register 0-0 */ + case 0x71: /* DRAM Bank Register 0-0 */ + case 0x72: /* DRAM Bank Register 0-1 */ + dev->pci_conf[addr] = val; + break; - case 0x73: /* DRAM Bank Register 0-1 */ - dev->pci_conf[addr] = val & 0x83; - break; + case 0x73: /* DRAM Bank Register 0-1 */ + dev->pci_conf[addr] = val & 0x83; + break; - case 0x74: /* DRAM Bank Register 1-0 */ - dev->pci_conf[addr] = val; - break; + case 0x74: /* DRAM Bank Register 1-0 */ + dev->pci_conf[addr] = val; + break; - case 0x75: /* DRAM Bank Register 1-0 */ - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x75: /* DRAM Bank Register 1-0 */ + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x76: /* DRAM Bank Register 1-1 */ - dev->pci_conf[addr] = val; - break; + case 0x76: /* DRAM Bank Register 1-1 */ + dev->pci_conf[addr] = val; + break; - case 0x77: /* DRAM Bank Register 1-1 */ - dev->pci_conf[addr] = val & 0x83; - break; + case 0x77: /* DRAM Bank Register 1-1 */ + dev->pci_conf[addr] = val & 0x83; + break; - case 0x78: /* DRAM Bank Register 2-0 */ - dev->pci_conf[addr] = val; - break; + case 0x78: /* DRAM Bank Register 2-0 */ + dev->pci_conf[addr] = val; + break; - case 0x79: /* DRAM Bank Register 2-0 */ - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x79: /* DRAM Bank Register 2-0 */ + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x7a: /* DRAM Bank Register 2-1 */ - dev->pci_conf[addr] = val; - break; + case 0x7a: /* DRAM Bank Register 2-1 */ + dev->pci_conf[addr] = val; + break; - case 0x7b: /* DRAM Bank Register 2-1 */ - dev->pci_conf[addr] = val & 0x83; - break; + case 0x7b: /* DRAM Bank Register 2-1 */ + dev->pci_conf[addr] = val & 0x83; + break; - case 0x7c: /* DRAM Bank Register 3-0 */ - dev->pci_conf[addr] = val; - break; + case 0x7c: /* DRAM Bank Register 3-0 */ + dev->pci_conf[addr] = val; + break; - case 0x7d: /* DRAM Bank Register 3-0 */ - dev->pci_conf[addr] = val & 0x7f; - break; + case 0x7d: /* DRAM Bank Register 3-0 */ + dev->pci_conf[addr] = val & 0x7f; + break; - case 0x7e: /* DRAM Bank Register 3-1 */ - dev->pci_conf[addr] = val; - break; + case 0x7e: /* DRAM Bank Register 3-1 */ + dev->pci_conf[addr] = val; + break; - case 0x7f: /* DRAM Bank Register 3-1 */ - dev->pci_conf[addr] = val & 0x83; - break; + case 0x7f: /* DRAM Bank Register 3-1 */ + dev->pci_conf[addr] = val & 0x83; + break; - case 0x80: - case 0x81: - case 0x82: - case 0x83: - case 0x84: - case 0x85: - case 0x86: - dev->pci_conf[addr] = val & ((addr == 0x86) ? 0xe8 : 0xee); - sis_5511_shadow_recalc(dev); - break; + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + dev->pci_conf[addr] = val & ((addr == 0x86) ? 0xe8 : 0xee); + sis_5511_shadow_recalc(dev); + break; - case 0x90: /* 5512 General Purpose Register Index */ - case 0x91: /* 5512 General Purpose Register Index */ - case 0x92: /* 5512 General Purpose Register Index */ - case 0x93: /* 5512 General Purpose Register Index */ - dev->pci_conf[addr] = val; - break; - } - sis_5511_log("SiS 5511: dev->pci_conf[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80)); + case 0x90: /* 5512 General Purpose Register Index */ + case 0x91: /* 5512 General Purpose Register Index */ + case 0x92: /* 5512 General Purpose Register Index */ + case 0x93: /* 5512 General Purpose Register Index */ + dev->pci_conf[addr] = val; + break; + } + sis_5511_log("SiS 5511: dev->pci_conf[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80)); } static uint8_t sis_5511_read(int func, int addr, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; - sis_5511_log("SiS 5511: dev->pci_conf[%02x] (%02x) POST %02x\n", addr, dev->pci_conf[addr], inb(0x80)); - return dev->pci_conf[addr]; + sis_5511_t *dev = (sis_5511_t *) priv; + sis_5511_log("SiS 5511: dev->pci_conf[%02x] (%02x) POST %02x\n", addr, dev->pci_conf[addr], inb(0x80)); + return dev->pci_conf[addr]; } -void sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev) +void +sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev) { - switch (addr) - { - case 0x04: /* Command */ - dev->pci_conf_sb[0][addr] = val & 7; - break; + switch (addr) { + case 0x04: /* Command */ + dev->pci_conf_sb[0][addr] = val & 7; + break; - case 0x07: /* Status */ - dev->pci_conf_sb[0][addr] &= val & 0x36; - break; + case 0x07: /* Status */ + dev->pci_conf_sb[0][addr] &= val & 0x36; + break; - case 0x40: /* BIOS Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x3f; - break; + case 0x40: /* BIOS Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x3f; + break; - case 0x41: /* INTA# Remapping Control Register */ - case 0x42: /* INTB# Remapping Control Register */ - case 0x43: /* INTC# Remapping Control Register */ - case 0x44: /* INTD# Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x8f; - pci_set_irq_routing(addr & 7, (val & 0x80) ? (val & 0x80) : PCI_IRQ_DISABLED); - break; + case 0x41: /* INTA# Remapping Control Register */ + case 0x42: /* INTB# Remapping Control Register */ + case 0x43: /* INTC# Remapping Control Register */ + case 0x44: /* INTD# Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x8f; + pci_set_irq_routing(addr & 7, (val & 0x80) ? (val & 0x80) : PCI_IRQ_DISABLED); + break; - case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ - case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ - case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ - case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - case 0x50: - case 0x51: - case 0x52: - case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - case 0x58: - case 0x59: - case 0x5a: - case 0x5b: - case 0x5c: - case 0x5d: - case 0x5e: - case 0x5f: - dev->pci_conf_sb[0][addr] = val; - break; + case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ + case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ + case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ + case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + dev->pci_conf_sb[0][addr] = val; + break; - case 0x60: /* MIRQ0 Remapping Control Register */ - case 0x61: /* MIRQ1 Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0xcf; - pci_set_mirq_routing(addr & 1, (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); - break; + case 0x60: /* MIRQ0 Remapping Control Register */ + case 0x61: /* MIRQ1 Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0xcf; + pci_set_mirq_routing(addr & 1, (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); + break; - case 0x62: /* On-board Device DMA Control Register */ - dev->pci_conf_sb[0][addr] = val; - break; + case 0x62: /* On-board Device DMA Control Register */ + dev->pci_conf_sb[0][addr] = val; + break; - case 0x63: /* IDEIRQ Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x8f; - if (val & 0x80) - { - sff_set_irq_line(dev->ide_drive[0], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); - sff_set_irq_line(dev->ide_drive[1], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); - } - break; + case 0x63: /* IDEIRQ Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x8f; + if (val & 0x80) { + sff_set_irq_line(dev->ide_drive[0], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); + sff_set_irq_line(dev->ide_drive[1], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); + } + break; - case 0x64: /* GPIO0 Control Register */ - dev->pci_conf_sb[0][addr] = val & 0xef; - break; + case 0x64: /* GPIO0 Control Register */ + dev->pci_conf_sb[0][addr] = val & 0xef; + break; - case 0x65: - dev->pci_conf_sb[0][addr] = val & 0x80; - break; + case 0x65: + dev->pci_conf_sb[0][addr] = val & 0x80; + break; - case 0x66: /* GPIO0 Output Mode Control Register */ - case 0x67: /* GPIO0 Output Mode Control Register */ - dev->pci_conf_sb[0][addr] = val; - break; + case 0x66: /* GPIO0 Output Mode Control Register */ + case 0x67: /* GPIO0 Output Mode Control Register */ + dev->pci_conf_sb[0][addr] = val; + break; - case 0x6a: /* GPIO Status Register */ - dev->pci_conf_sb[0][addr] &= val & 0x15; - break; - } + case 0x6a: /* GPIO Status Register */ + dev->pci_conf_sb[0][addr] &= val & 0x15; + break; + } } -void sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev) +void +sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev) { - switch (addr) - { - case 0x04: /* Command low byte */ - dev->pci_conf_sb[1][addr] = val & 5; - sis_5513_ide_handler(dev); - sis_5513_bm_handler(dev); - break; - case 0x07: /* Status high byte */ - dev->pci_conf_sb[1][addr] &= val & 0x3f; - break; - case 0x09: /* Programming Interface Byte */ - dev->pci_conf_sb[1][addr] = val; - sis_5513_ide_handler(dev); - break; - case 0x0d: /* Latency Timer */ - dev->pci_conf_sb[1][addr] = val; - break; + switch (addr) { + case 0x04: /* Command low byte */ + dev->pci_conf_sb[1][addr] = val & 5; + sis_5513_ide_handler(dev); + sis_5513_bm_handler(dev); + break; + case 0x07: /* Status high byte */ + dev->pci_conf_sb[1][addr] &= val & 0x3f; + break; + case 0x09: /* Programming Interface Byte */ + dev->pci_conf_sb[1][addr] = val; + sis_5513_ide_handler(dev); + break; + case 0x0d: /* Latency Timer */ + dev->pci_conf_sb[1][addr] = val; + break; - case 0x10: /* Primary Channel Base Address Register */ - case 0x11: /* Primary Channel Base Address Register */ - case 0x12: /* Primary Channel Base Address Register */ - case 0x13: /* Primary Channel Base Address Register */ - case 0x14: /* Primary Channel Base Address Register */ - case 0x15: /* Primary Channel Base Address Register */ - case 0x16: /* Primary Channel Base Address Register */ - case 0x17: /* Primary Channel Base Address Register */ - case 0x18: /* Secondary Channel Base Address Register */ - case 0x19: /* Secondary Channel Base Address Register */ - case 0x1a: /* Secondary Channel Base Address Register */ - case 0x1b: /* Secondary Channel Base Address Register */ - case 0x1c: /* Secondary Channel Base Address Register */ - case 0x1d: /* Secondary Channel Base Address Register */ - case 0x1e: /* Secondary Channel Base Address Register */ - case 0x1f: /* Secondary Channel Base Address Register */ - dev->pci_conf_sb[1][addr] = val; - sis_5513_ide_handler(dev); - break; + case 0x10: /* Primary Channel Base Address Register */ + case 0x11: /* Primary Channel Base Address Register */ + case 0x12: /* Primary Channel Base Address Register */ + case 0x13: /* Primary Channel Base Address Register */ + case 0x14: /* Primary Channel Base Address Register */ + case 0x15: /* Primary Channel Base Address Register */ + case 0x16: /* Primary Channel Base Address Register */ + case 0x17: /* Primary Channel Base Address Register */ + case 0x18: /* Secondary Channel Base Address Register */ + case 0x19: /* Secondary Channel Base Address Register */ + case 0x1a: /* Secondary Channel Base Address Register */ + case 0x1b: /* Secondary Channel Base Address Register */ + case 0x1c: /* Secondary Channel Base Address Register */ + case 0x1d: /* Secondary Channel Base Address Register */ + case 0x1e: /* Secondary Channel Base Address Register */ + case 0x1f: /* Secondary Channel Base Address Register */ + dev->pci_conf_sb[1][addr] = val; + sis_5513_ide_handler(dev); + break; - case 0x20: /* Bus Master IDE Control Register Base Address */ - case 0x21: /* Bus Master IDE Control Register Base Address */ - case 0x22: /* Bus Master IDE Control Register Base Address */ - case 0x23: /* Bus Master IDE Control Register Base Address */ - dev->pci_conf_sb[1][addr] = val; - sis_5513_bm_handler(dev); - break; + case 0x20: /* Bus Master IDE Control Register Base Address */ + case 0x21: /* Bus Master IDE Control Register Base Address */ + case 0x22: /* Bus Master IDE Control Register Base Address */ + case 0x23: /* Bus Master IDE Control Register Base Address */ + dev->pci_conf_sb[1][addr] = val; + sis_5513_bm_handler(dev); + break; - case 0x30: /* Expansion ROM Base Address */ - case 0x31: /* Expansion ROM Base Address */ - case 0x32: /* Expansion ROM Base Address */ - case 0x33: /* Expansion ROM Base Address */ - dev->pci_conf_sb[1][addr] = val; - break; + case 0x30: /* Expansion ROM Base Address */ + case 0x31: /* Expansion ROM Base Address */ + case 0x32: /* Expansion ROM Base Address */ + case 0x33: /* Expansion ROM Base Address */ + dev->pci_conf_sb[1][addr] = val; + break; - case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */ - case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */ - case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */ - case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */ - case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */ - case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */ - case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */ - case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */ - case 0x48: /* IDE Command Recovery Time Control */ - case 0x49: /* IDE Command Active Time Control */ - dev->pci_conf_sb[1][addr] = val; - break; + case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */ + case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */ + case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */ + case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */ + case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */ + case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */ + case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */ + case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */ + case 0x48: /* IDE Command Recovery Time Control */ + case 0x49: /* IDE Command Active Time Control */ + dev->pci_conf_sb[1][addr] = val; + break; - case 0x4a: /* IDE General Control Register 0 */ - dev->pci_conf_sb[1][addr] = val & 0x9f; - sis_5513_ide_handler(dev); - break; + case 0x4a: /* IDE General Control Register 0 */ + dev->pci_conf_sb[1][addr] = val & 0x9f; + sis_5513_ide_handler(dev); + break; - case 0x4b: /* IDE General Control Register 1 */ - dev->pci_conf_sb[1][addr] = val & 0xef; - break; + case 0x4b: /* IDE General Control Register 1 */ + dev->pci_conf_sb[1][addr] = val & 0xef; + break; - case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */ - case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */ - case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */ - case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */ - dev->pci_conf_sb[1][addr] = val; - break; - } + case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */ + case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */ + case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */ + case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */ + dev->pci_conf_sb[1][addr] = val; + break; + } } static void sis_5513_write(int func, int addr, uint8_t val, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; - switch (func) - { - case 0: - sis_5513_pci_to_isa_write(addr, val, dev); - break; - case 1: - sis_5513_ide_write(addr, val, dev); - break; - } - sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST: %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80)); + sis_5511_t *dev = (sis_5511_t *) priv; + switch (func) { + case 0: + sis_5513_pci_to_isa_write(addr, val, dev); + break; + case 1: + sis_5513_ide_write(addr, val, dev); + break; + } + sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST: %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80)); } static uint8_t sis_5513_read(int func, int addr, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; - sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80)); - if ((func >= 0) && (func <= 1)) - return dev->pci_conf_sb[func][addr]; - else - return 0xff; + sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80)); + if ((func >= 0) && (func <= 1)) + return dev->pci_conf_sb[func][addr]; + else + return 0xff; } static void sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; - switch (addr) - { - case 0x22: - dev->index = val - 0x50; - break; - case 0x23: - switch (dev->index) - { - case 0x00: - dev->regs[dev->index] = val & 0xed; - switch (val >> 6) - { - case 0: - cpu_set_isa_speed(7159091); - break; - case 1: - cpu_set_isa_pci_div(4); - break; - case 2: - cpu_set_isa_pci_div(3); - break; - } - break; - case 0x01: - dev->regs[dev->index] = val & 0xf4; - break; - case 0x03: - dev->regs[dev->index] = val & 3; - break; - case 0x04: /* BIOS Register */ - dev->regs[dev->index] = val; - break; - case 0x05: - dev->regs[dev->index] = inb(0x70); - break; - case 0x08: - case 0x09: - case 0x0a: - case 0x0b: - dev->regs[dev->index] = val; - break; - } - sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80)); - break; - } + switch (addr) { + case 0x22: + dev->index = val - 0x50; + break; + case 0x23: + switch (dev->index) { + case 0x00: + dev->regs[dev->index] = val & 0xed; + switch (val >> 6) { + case 0: + cpu_set_isa_speed(7159091); + break; + case 1: + cpu_set_isa_pci_div(4); + break; + case 2: + cpu_set_isa_pci_div(3); + break; + } + break; + case 0x01: + dev->regs[dev->index] = val & 0xf4; + break; + case 0x03: + dev->regs[dev->index] = val & 3; + break; + case 0x04: /* BIOS Register */ + dev->regs[dev->index] = val; + break; + case 0x05: + dev->regs[dev->index] = inb(0x70); + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + dev->regs[dev->index] = val; + break; + } + sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80)); + break; + } } static uint8_t sis_5513_isa_read(uint16_t addr, void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; - if (addr == 0x23) - { - sis_5511_log("SiS 5513-ISA: dev->regs[%02x] (%02x) POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80)); - return dev->regs[dev->index]; - } - else - return 0xff; + if (addr == 0x23) { + sis_5511_log("SiS 5513-ISA: dev->regs[%02x] (%02x) POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80)); + return dev->regs[dev->index]; + } else + return 0xff; } - static void sis_5511_reset(void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; /* SiS 5511 */ dev->pci_conf[0x00] = 0x39; @@ -628,12 +617,12 @@ sis_5511_reset(void *priv) dev->pci_conf[0x03] = 0x55; dev->pci_conf[0x04] = 0x07; dev->pci_conf[0x05] = dev->pci_conf[0x06] = 0x00; - dev->pci_conf[0x07] = 0x02; - dev->pci_conf[0x08] = 0x00; + dev->pci_conf[0x07] = 0x02; + dev->pci_conf[0x08] = 0x00; dev->pci_conf[0x09] = dev->pci_conf[0x0a] = 0x00; - dev->pci_conf[0x0b] = 0x06; + dev->pci_conf[0x0b] = 0x06; dev->pci_conf[0x50] = dev->pci_conf[0x51] = 0x00; - dev->pci_conf[0x52] = 0x20; + dev->pci_conf[0x52] = 0x20; dev->pci_conf[0x53] = dev->pci_conf[0x54] = 0x00; dev->pci_conf[0x55] = dev->pci_conf[0x56] = 0x00; dev->pci_conf[0x57] = dev->pci_conf[0x58] = 0x00; @@ -642,10 +631,10 @@ sis_5511_reset(void *priv) dev->pci_conf[0x5d] = dev->pci_conf[0x5e] = 0x00; dev->pci_conf[0x5f] = dev->pci_conf[0x60] = 0x00; dev->pci_conf[0x61] = dev->pci_conf[0x62] = 0xff; - dev->pci_conf[0x63] = 0xff; + dev->pci_conf[0x63] = 0xff; dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00; - dev->pci_conf[0x66] = 0x00; - dev->pci_conf[0x67] = 0xff; + dev->pci_conf[0x66] = 0x00; + dev->pci_conf[0x67] = 0xff; dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00; dev->pci_conf[0x6a] = dev->pci_conf[0x6b] = 0x00; dev->pci_conf[0x6c] = dev->pci_conf[0x6d] = 0x00; @@ -654,49 +643,49 @@ sis_5511_reset(void *priv) cpu_cache_ext_enabled = 0; cpu_update_waitstates(); - dev->pci_conf[0x6b] = 0xff; - dev->pci_conf[0x6c] = 0xff; - dev->pci_conf[0x70] = 4; - dev->pci_conf[0x72] = 4; - dev->pci_conf[0x73] = 0x80; - dev->pci_conf[0x74] = 4; - dev->pci_conf[0x76] = 4; - dev->pci_conf[0x77] = 0x80; - dev->pci_conf[0x78] = 4; - dev->pci_conf[0x7a] = 4; - dev->pci_conf[0x7b] = 0x80; - dev->pci_conf[0x7c] = 4; - dev->pci_conf[0x7e] = 4; - dev->pci_conf[0x7f] = 0x80; - dev->pci_conf[0x80] = 0x00; - dev->pci_conf[0x81] = 0x00; - dev->pci_conf[0x82] = 0x00; - dev->pci_conf[0x83] = 0x00; - dev->pci_conf[0x84] = 0x00; - dev->pci_conf[0x85] = 0x00; - dev->pci_conf[0x86] = 0x00; - sis_5511_smram_recalc(dev); - sis_5511_shadow_recalc(dev); + dev->pci_conf[0x6b] = 0xff; + dev->pci_conf[0x6c] = 0xff; + dev->pci_conf[0x70] = 4; + dev->pci_conf[0x72] = 4; + dev->pci_conf[0x73] = 0x80; + dev->pci_conf[0x74] = 4; + dev->pci_conf[0x76] = 4; + dev->pci_conf[0x77] = 0x80; + dev->pci_conf[0x78] = 4; + dev->pci_conf[0x7a] = 4; + dev->pci_conf[0x7b] = 0x80; + dev->pci_conf[0x7c] = 4; + dev->pci_conf[0x7e] = 4; + dev->pci_conf[0x7f] = 0x80; + dev->pci_conf[0x80] = 0x00; + dev->pci_conf[0x81] = 0x00; + dev->pci_conf[0x82] = 0x00; + dev->pci_conf[0x83] = 0x00; + dev->pci_conf[0x84] = 0x00; + dev->pci_conf[0x85] = 0x00; + dev->pci_conf[0x86] = 0x00; + sis_5511_smram_recalc(dev); + sis_5511_shadow_recalc(dev); - /* SiS 5513 */ - dev->pci_conf_sb[0][0x00] = 0x39; - dev->pci_conf_sb[0][0x01] = 0x10; - dev->pci_conf_sb[0][0x02] = 8; - dev->pci_conf_sb[0][0x04] = 7; - dev->pci_conf_sb[0][0x0a] = 1; - dev->pci_conf_sb[0][0x0b] = 6; - dev->pci_conf_sb[0][0x0e] = 0x80; + /* SiS 5513 */ + dev->pci_conf_sb[0][0x00] = 0x39; + dev->pci_conf_sb[0][0x01] = 0x10; + dev->pci_conf_sb[0][0x02] = 8; + dev->pci_conf_sb[0][0x04] = 7; + dev->pci_conf_sb[0][0x0a] = 1; + dev->pci_conf_sb[0][0x0b] = 6; + dev->pci_conf_sb[0][0x0e] = 0x80; - /* SiS 5513 IDE Controller */ - dev->pci_conf_sb[1][0x00] = 0x39; - dev->pci_conf_sb[1][0x01] = 0x10; - dev->pci_conf_sb[1][0x02] = 0x13; - dev->pci_conf_sb[1][0x03] = 0x55; - dev->pci_conf_sb[1][0x0a] = 1; - dev->pci_conf_sb[1][0x0b] = 1; - dev->pci_conf_sb[1][0x0e] = 0x80; - sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot); - sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot); + /* SiS 5513 IDE Controller */ + dev->pci_conf_sb[1][0x00] = 0x39; + dev->pci_conf_sb[1][0x01] = 0x10; + dev->pci_conf_sb[1][0x02] = 0x13; + dev->pci_conf_sb[1][0x03] = 0x55; + dev->pci_conf_sb[1][0x0a] = 1; + dev->pci_conf_sb[1][0x0b] = 1; + dev->pci_conf_sb[1][0x0e] = 0x80; + sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot); + sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot); sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE); sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8); } @@ -704,51 +693,51 @@ sis_5511_reset(void *priv) static void sis_5511_close(void *priv) { - sis_5511_t *dev = (sis_5511_t *)priv; + sis_5511_t *dev = (sis_5511_t *) priv; - smram_del(dev->smram); - free(dev); + smram_del(dev->smram); + free(dev); } static void * sis_5511_init(const device_t *info) { - sis_5511_t *dev = (sis_5511_t *)malloc(sizeof(sis_5511_t)); - memset(dev, 0, sizeof(sis_5511_t)); + sis_5511_t *dev = (sis_5511_t *) malloc(sizeof(sis_5511_t)); + memset(dev, 0, sizeof(sis_5511_t)); - dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev); /* Device 0: SiS 5511 */ - dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev); /* Device 1: SiS 5513 */ - io_sethandler(0x0022, 0x0002, sis_5513_isa_read, NULL, NULL, sis_5513_isa_write, NULL, NULL, dev); /* Ports 22h-23h: SiS 5513 ISA */ + dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev); /* Device 0: SiS 5511 */ + dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev); /* Device 1: SiS 5513 */ + io_sethandler(0x0022, 0x0002, sis_5513_isa_read, NULL, NULL, sis_5513_isa_write, NULL, NULL, dev); /* Ports 22h-23h: SiS 5513 ISA */ - /* MIRQ */ - pci_enable_mirq(0); - pci_enable_mirq(1); + /* MIRQ */ + pci_enable_mirq(0); + pci_enable_mirq(1); - /* Port 92h */ - dev->port_92 = device_add(&port_92_device); + /* Port 92h */ + dev->port_92 = device_add(&port_92_device); - /* SFF IDE */ - dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1); - dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2); + /* SFF IDE */ + dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1); + dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2); - /* SMRAM */ - dev->smram = smram_add(); + /* SMRAM */ + dev->smram = smram_add(); - sis_5511_reset(dev); + sis_5511_reset(dev); - return dev; + return dev; } const device_t sis_5511_device = { - .name = "SiS 5511", + .name = "SiS 5511", .internal_name = "sis_5511", - .flags = DEVICE_PCI, - .local = 0, - .init = sis_5511_init, - .close = sis_5511_close, - .reset = sis_5511_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = sis_5511_init, + .close = sis_5511_close, + .reset = sis_5511_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_5571.c b/src/chipset/sis_5571.c index 2d9d92c8d..c761e4f85 100644 --- a/src/chipset/sis_5571.c +++ b/src/chipset/sis_5571.c @@ -37,720 +37,705 @@ #include <86box/chipset.h> /* Shadow RAM */ -#define LSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) -#define LSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) -#define MSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) -#define MSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) -#define SYSTEM_READ ((dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) +#define LSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) +#define LSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) +#define MSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) +#define MSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) +#define SYSTEM_READ ((dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) #define SYSTEM_WRITE ((dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) /* IDE Flags (1 Native / 0 Compatibility)*/ -#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1) +#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1) #define SECONDARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 4) -#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8) -#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2) -#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8) -#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2) -#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8)) +#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8) +#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2) +#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8) +#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2) +#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8)) #ifdef ENABLE_SIS_5571_LOG int sis_5571_do_log = ENABLE_SIS_5571_LOG; static void sis_5571_log(const char *fmt, ...) { - va_list ap; + va_list ap; - if (sis_5571_do_log) - { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); - } + if (sis_5571_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } } #else -#define sis_5571_log(fmt, ...) +# define sis_5571_log(fmt, ...) #endif -typedef struct sis_5571_t -{ - uint8_t pci_conf[256], pci_conf_sb[3][256]; +typedef struct sis_5571_t { + uint8_t pci_conf[256], pci_conf_sb[3][256]; - int nb_pci_slot, sb_pci_slot; + int nb_pci_slot, sb_pci_slot; - port_92_t *port_92; - sff8038i_t *ide_drive[2]; - smram_t *smram; - usb_t *usb; + port_92_t *port_92; + sff8038i_t *ide_drive[2]; + smram_t *smram; + usb_t *usb; } sis_5571_t; static void sis_5571_shadow_recalc(int cur_reg, sis_5571_t *dev) { - if (cur_reg != 0x76) - { - mem_set_mem_state_both(0xc0000 + (0x8000 * (cur_reg & 0x07)), 0x4000, LSB_READ | LSB_WRITE); - mem_set_mem_state_both(0xc4000 + (0x8000 * (cur_reg & 0x07)), 0x4000, MSB_READ | MSB_WRITE); - } - else - mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE); + if (cur_reg != 0x76) { + mem_set_mem_state_both(0xc0000 + (0x8000 * (cur_reg & 0x07)), 0x4000, LSB_READ | LSB_WRITE); + mem_set_mem_state_both(0xc4000 + (0x8000 * (cur_reg & 0x07)), 0x4000, MSB_READ | MSB_WRITE); + } else + mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE); - flushmmucache_nopc(); + flushmmucache_nopc(); } static void sis_5571_smm_recalc(sis_5571_t *dev) { - smram_disable_all(); + smram_disable_all(); - switch ((dev->pci_conf[0xa3] & 0xc0) >> 6) - { - case 0x00: - smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); - break; - case 0x01: - smram_enable(dev->smram, 0xe0000, 0xa0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); - break; - case 0x02: - smram_enable(dev->smram, 0xe0000, 0xb0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); - break; - case 0x03: - smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1); - break; - } + switch ((dev->pci_conf[0xa3] & 0xc0) >> 6) { + case 0x00: + smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); + break; + case 0x01: + smram_enable(dev->smram, 0xe0000, 0xa0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); + break; + case 0x02: + smram_enable(dev->smram, 0xe0000, 0xb0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1); + break; + case 0x03: + smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1); + break; + } - flushmmucache(); + flushmmucache(); } -void sis_5571_ide_handler(sis_5571_t *dev) +void +sis_5571_ide_handler(sis_5571_t *dev) { - ide_pri_disable(); - ide_sec_disable(); - if (dev->pci_conf_sb[1][4] & 1) - { - if (dev->pci_conf_sb[1][0x4a] & 4) - { - ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0); - ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6); - ide_pri_enable(); - } - if (dev->pci_conf_sb[1][0x4a] & 2) - { - ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170); - ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376); - ide_sec_enable(); - } - } + ide_pri_disable(); + ide_sec_disable(); + if (dev->pci_conf_sb[1][4] & 1) { + if (dev->pci_conf_sb[1][0x4a] & 4) { + ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0); + ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6); + ide_pri_enable(); + } + if (dev->pci_conf_sb[1][0x4a] & 2) { + ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170); + ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376); + ide_sec_enable(); + } + } } -void sis_5571_bm_handler(sis_5571_t *dev) +void +sis_5571_bm_handler(sis_5571_t *dev) { - sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE); - sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8); + sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE); + sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8); } static void memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; + sis_5571_t *dev = (sis_5571_t *) priv; - switch (addr) - { - case 0x04: /* Command - low byte */ - case 0x05: /* Command - high byte */ - dev->pci_conf[addr] |= val; - break; + switch (addr) { + case 0x04: /* Command - low byte */ + case 0x05: /* Command - high byte */ + dev->pci_conf[addr] |= val; + break; - case 0x06: /* Status - Low Byte */ - dev->pci_conf[addr] &= val; - break; + case 0x06: /* Status - Low Byte */ + dev->pci_conf[addr] &= val; + break; - case 0x07: /* Status - High Byte */ - dev->pci_conf[addr] &= val & 0xbe; - break; + case 0x07: /* Status - High Byte */ + dev->pci_conf[addr] &= val & 0xbe; + break; - case 0x0d: /* Master latency timer */ - dev->pci_conf[addr] = val; - break; + case 0x0d: /* Master latency timer */ + dev->pci_conf[addr] = val; + break; - case 0x50: /* Host Interface and DRAM arbiter */ - dev->pci_conf[addr] = val & 0xec; - break; + case 0x50: /* Host Interface and DRAM arbiter */ + dev->pci_conf[addr] = val & 0xec; + break; - case 0x51: /* CACHE */ - dev->pci_conf[addr] = val; - cpu_cache_ext_enabled = !!(val & 0x40); - cpu_update_waitstates(); - break; + case 0x51: /* CACHE */ + dev->pci_conf[addr] = val; + cpu_cache_ext_enabled = !!(val & 0x40); + cpu_update_waitstates(); + break; - case 0x52: - dev->pci_conf[addr] = val & 0xd0; - break; + case 0x52: + dev->pci_conf[addr] = val & 0xd0; + break; - case 0x53: /* DRAM */ - dev->pci_conf[addr] = val & 0xfe; - break; + case 0x53: /* DRAM */ + dev->pci_conf[addr] = val & 0xfe; + break; - case 0x54: /* FP/EDO */ - dev->pci_conf[addr] = val; - break; + case 0x54: /* FP/EDO */ + dev->pci_conf[addr] = val; + break; - case 0x55: - dev->pci_conf[addr] = val & 0xe0; - break; + case 0x55: + dev->pci_conf[addr] = val & 0xe0; + break; - case 0x56: /* MDLE delay */ - case 0x57: /* SDRAM */ - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x56: /* MDLE delay */ + case 0x57: /* SDRAM */ + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x59: /* Buffer strength and current rating */ - dev->pci_conf[addr] = val; - break; + case 0x59: /* Buffer strength and current rating */ + dev->pci_conf[addr] = val; + break; - case 0x5a: - dev->pci_conf[addr] = val & 0x03; - break; + case 0x5a: + dev->pci_conf[addr] = val & 0x03; + break; - case 0x60: /* Undocumented */ - case 0x61: /* Undocumented */ - case 0x62: /* Undocumented */ - case 0x63: /* Undocumented */ - case 0x64: /* Undocumented */ - case 0x65: /* Undocumented */ - case 0x66: /* Undocumented */ - case 0x67: /* Undocumented */ - case 0x68: /* Undocumented */ - case 0x69: /* Undocumented */ - case 0x6a: /* Undocumented */ - case 0x6b: /* Undocumented */ - dev->pci_conf[addr] = val; - break; + case 0x60: /* Undocumented */ + case 0x61: /* Undocumented */ + case 0x62: /* Undocumented */ + case 0x63: /* Undocumented */ + case 0x64: /* Undocumented */ + case 0x65: /* Undocumented */ + case 0x66: /* Undocumented */ + case 0x67: /* Undocumented */ + case 0x68: /* Undocumented */ + case 0x69: /* Undocumented */ + case 0x6a: /* Undocumented */ + case 0x6b: /* Undocumented */ + dev->pci_conf[addr] = val; + break; - case 0x70: - case 0x71: - case 0x72: - case 0x73: - case 0x74: - case 0x75: - case 0x76: /* Attribute of shadow RAM for BIOS area */ - dev->pci_conf[addr] = val & ((addr != 0x76) ? 0xee : 0xe8); - sis_5571_shadow_recalc(addr, dev); - sis_5571_smm_recalc(dev); - break; + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x76: /* Attribute of shadow RAM for BIOS area */ + dev->pci_conf[addr] = val & ((addr != 0x76) ? 0xee : 0xe8); + sis_5571_shadow_recalc(addr, dev); + sis_5571_smm_recalc(dev); + break; - case 0x77: /* Characteristics of non-cacheable area */ - dev->pci_conf[addr] = val & 0x0f; - break; + case 0x77: /* Characteristics of non-cacheable area */ + dev->pci_conf[addr] = val & 0x0f; + break; - case 0x78: /* Allocation of Non-Cacheable area #1 */ - case 0x79: /* NCA1REG2 */ - case 0x7a: /* Allocation of Non-Cacheable area #2 */ - case 0x7b: /* NCA2REG2 */ - dev->pci_conf[addr] = val; - break; + case 0x78: /* Allocation of Non-Cacheable area #1 */ + case 0x79: /* NCA1REG2 */ + case 0x7a: /* Allocation of Non-Cacheable area #2 */ + case 0x7b: /* NCA2REG2 */ + dev->pci_conf[addr] = val; + break; - case 0x80: /* PCI master characteristics */ - dev->pci_conf[addr] = val & 0xfe; - break; + case 0x80: /* PCI master characteristics */ + dev->pci_conf[addr] = val & 0xfe; + break; - case 0x81: - dev->pci_conf[addr] = val & 0xcc; - break; + case 0x81: + dev->pci_conf[addr] = val & 0xcc; + break; - case 0x82: - dev->pci_conf[addr] = val; - break; + case 0x82: + dev->pci_conf[addr] = val; + break; - case 0x83: /* CPU to PCI characteristics */ - dev->pci_conf[addr] = val; - port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80)); - break; + case 0x83: /* CPU to PCI characteristics */ + dev->pci_conf[addr] = val; + port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80)); + break; - case 0x84: - case 0x85: - case 0x86: - dev->pci_conf[addr] = val; - break; + case 0x84: + case 0x85: + case 0x86: + dev->pci_conf[addr] = val; + break; - case 0x87: /* Miscellanea */ - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x87: /* Miscellanea */ + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x90: /* PMU control register */ - case 0x91: /* Address trap for green function */ - case 0x92: - dev->pci_conf[addr] = val; - break; + case 0x90: /* PMU control register */ + case 0x91: /* Address trap for green function */ + case 0x92: + dev->pci_conf[addr] = val; + break; - case 0x93: /* STPCLK# and APM SMI control */ - dev->pci_conf[addr] = val; + case 0x93: /* STPCLK# and APM SMI control */ + dev->pci_conf[addr] = val; - if ((dev->pci_conf[0x9b] & 1) && !!(val & 2)) - { - smi_raise(); - dev->pci_conf[0x9d] |= 1; - } - break; + if ((dev->pci_conf[0x9b] & 1) && !!(val & 2)) { + smi_raise(); + dev->pci_conf[0x9d] |= 1; + } + break; - case 0x94: /* 6x86 and Green function control */ - dev->pci_conf[addr] = val & 0xf8; - break; + case 0x94: /* 6x86 and Green function control */ + dev->pci_conf[addr] = val & 0xf8; + break; - case 0x95: /* Test mode control */ - case 0x96: /* Time slot and Programmable 10-bit I/O port definition */ - dev->pci_conf[addr] = val & 0xfb; - break; + case 0x95: /* Test mode control */ + case 0x96: /* Time slot and Programmable 10-bit I/O port definition */ + dev->pci_conf[addr] = val & 0xfb; + break; - case 0x97: /* programmable 10-bit I/O port address */ - case 0x98: /* Programmable 16-bit I/O port */ - case 0x99: - case 0x9a: - case 0x9b: - case 0x9c: - dev->pci_conf[addr] = val; - break; + case 0x97: /* programmable 10-bit I/O port address */ + case 0x98: /* Programmable 16-bit I/O port */ + case 0x99: + case 0x9a: + case 0x9b: + case 0x9c: + dev->pci_conf[addr] = val; + break; - case 0x9d: - dev->pci_conf[addr] &= val; - break; + case 0x9d: + dev->pci_conf[addr] &= val; + break; - case 0x9e: /* STPCLK# Assertion Timer */ - case 0x9f: /* STPCLK# De-assertion Timer */ - case 0xa0: - case 0xa1: - case 0xa2: - dev->pci_conf[addr] = val; - break; + case 0x9e: /* STPCLK# Assertion Timer */ + case 0x9f: /* STPCLK# De-assertion Timer */ + case 0xa0: + case 0xa1: + case 0xa2: + dev->pci_conf[addr] = val; + break; - case 0xa3: /* SMRAM access control and Power supply control */ - dev->pci_conf[addr] = val & 0xd0; - sis_5571_smm_recalc(dev); - break; - } - sis_5571_log("SiS5571: dev->pci_conf[%02x] = %02x\n", addr, val); + case 0xa3: /* SMRAM access control and Power supply control */ + dev->pci_conf[addr] = val & 0xd0; + sis_5571_smm_recalc(dev); + break; + } + sis_5571_log("SiS5571: dev->pci_conf[%02x] = %02x\n", addr, val); } static uint8_t memory_pci_bridge_read(int func, int addr, void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; - sis_5571_log("SiS5571: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]); - return dev->pci_conf[addr]; + sis_5571_t *dev = (sis_5571_t *) priv; + sis_5571_log("SiS5571: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]); + return dev->pci_conf[addr]; } static void pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; - switch (func) - { - case 0: /* Bridge */ - switch (addr) - { - case 0x04: /* Command */ - dev->pci_conf_sb[0][addr] |= val & 0x0f; - break; + sis_5571_t *dev = (sis_5571_t *) priv; + switch (func) { + case 0: /* Bridge */ + switch (addr) { + case 0x04: /* Command */ + dev->pci_conf_sb[0][addr] |= val & 0x0f; + break; - case 0x06: /* Status */ - dev->pci_conf_sb[0][addr] &= val; - break; + case 0x06: /* Status */ + dev->pci_conf_sb[0][addr] &= val; + break; - case 0x40: /* BIOS Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x3f; - break; + case 0x40: /* BIOS Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x3f; + break; - case 0x41: /* INTA# Remapping Control Register */ - case 0x42: /* INTB# Remapping Control Register */ - case 0x43: /* INTC# Remapping Control Register */ - case 0x44: /* INTD# Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x8f; - pci_set_irq_routing((addr & 0x07), !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); - break; + case 0x41: /* INTA# Remapping Control Register */ + case 0x42: /* INTB# Remapping Control Register */ + case 0x43: /* INTC# Remapping Control Register */ + case 0x44: /* INTD# Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x8f; + pci_set_irq_routing((addr & 0x07), !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); + break; - case 0x45: - dev->pci_conf_sb[0][addr] = val & 0xec; - switch ((val & 0xc0) >> 6) - { - case 0: - cpu_set_isa_speed(7159091); - break; - case 1: - cpu_set_isa_pci_div(4); - break; - case 2: - cpu_set_isa_pci_div(3); - break; - } - break; + case 0x45: + dev->pci_conf_sb[0][addr] = val & 0xec; + switch ((val & 0xc0) >> 6) { + case 0: + cpu_set_isa_speed(7159091); + break; + case 1: + cpu_set_isa_pci_div(4); + break; + case 2: + cpu_set_isa_pci_div(3); + break; + } + break; - case 0x46: - dev->pci_conf_sb[0][addr] = val & 0xec; - break; + case 0x46: + dev->pci_conf_sb[0][addr] = val & 0xec; + break; - case 0x47: /* DMA Clock and Wait State Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x3e; - break; + case 0x47: /* DMA Clock and Wait State Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x3e; + break; - case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ - case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ - case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ - case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ - dev->pci_conf_sb[0][addr] = val; - break; + case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ + case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ + case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ + case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ + dev->pci_conf_sb[0][addr] = val; + break; - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - case 0x50: - case 0x51: - case 0x52: - case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - case 0x58: - case 0x59: - case 0x5a: - case 0x5b: - case 0x5c: - case 0x5d: - case 0x5e: - dev->pci_conf_sb[0][addr] = val; - break; + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + dev->pci_conf_sb[0][addr] = val; + break; - case 0x5f: - dev->pci_conf_sb[0][addr] = val & 0x3f; - break; + case 0x5f: + dev->pci_conf_sb[0][addr] = val & 0x3f; + break; - case 0x60: - dev->pci_conf_sb[0][addr] = val; - break; + case 0x60: + dev->pci_conf_sb[0][addr] = val; + break; - case 0x61: /* MIRQ Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val; - pci_set_mirq_routing(PCI_MIRQ0, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); - break; + case 0x61: /* MIRQ Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val; + pci_set_mirq_routing(PCI_MIRQ0, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED); + break; - case 0x62: /* On-board Device DMA Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x0f; - dma_set_drq((val & 0x07), 1); - break; + case 0x62: /* On-board Device DMA Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x0f; + dma_set_drq((val & 0x07), 1); + break; - case 0x63: /* IDEIRQ Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x8f; - if (val & 0x80) - { - sff_set_irq_line(dev->ide_drive[0], val & 0x0f); - sff_set_irq_line(dev->ide_drive[1], val & 0x0f); - } - break; + case 0x63: /* IDEIRQ Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x8f; + if (val & 0x80) { + sff_set_irq_line(dev->ide_drive[0], val & 0x0f); + sff_set_irq_line(dev->ide_drive[1], val & 0x0f); + } + break; - case 0x64: /* GPIO Control Register */ - dev->pci_conf_sb[0][addr] = val & 0xef; - break; + case 0x64: /* GPIO Control Register */ + dev->pci_conf_sb[0][addr] = val & 0xef; + break; - case 0x65: - dev->pci_conf_sb[0][addr] = val & 0x1b; - break; + case 0x65: + dev->pci_conf_sb[0][addr] = val & 0x1b; + break; - case 0x66: /* GPIO Output Mode Control Register */ - case 0x67: /* GPIO Output Mode Control Register */ - dev->pci_conf_sb[0][addr] = val; - break; + case 0x66: /* GPIO Output Mode Control Register */ + case 0x67: /* GPIO Output Mode Control Register */ + dev->pci_conf_sb[0][addr] = val; + break; - case 0x68: /* USBIRQ Remapping Control Register */ - dev->pci_conf_sb[0][addr] = val & 0x1b; - break; + case 0x68: /* USBIRQ Remapping Control Register */ + dev->pci_conf_sb[0][addr] = val & 0x1b; + break; - case 0x69: - dev->pci_conf_sb[0][addr] = val; - break; + case 0x69: + dev->pci_conf_sb[0][addr] = val; + break; - case 0x6a: - dev->pci_conf_sb[0][addr] = val & 0xfc; - break; + case 0x6a: + dev->pci_conf_sb[0][addr] = val & 0xfc; + break; - case 0x6b: - dev->pci_conf_sb[0][addr] = val; - break; + case 0x6b: + dev->pci_conf_sb[0][addr] = val; + break; - case 0x6c: - dev->pci_conf_sb[0][addr] = val & 0x03; - break; + case 0x6c: + dev->pci_conf_sb[0][addr] = val & 0x03; + break; - case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */ - case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */ - dev->pci_conf_sb[0][addr] = val; - break; + case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */ + case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */ + dev->pci_conf_sb[0][addr] = val; + break; - case 0x70: - dev->pci_conf_sb[0][addr] = val & 0xde; - break; + case 0x70: + dev->pci_conf_sb[0][addr] = val & 0xde; + break; - case 0x71: /* Type-F DMA Control Register */ - dev->pci_conf_sb[0][addr] = val & 0xfe; - break; + case 0x71: /* Type-F DMA Control Register */ + dev->pci_conf_sb[0][addr] = val & 0xfe; + break; - case 0x72: /* SMI Triggered By IRQ/GPIO Control */ - case 0x73: /* SMI Triggered By IRQ/GPIO Control */ - dev->pci_conf_sb[0][addr] = (addr == 0x72) ? val & 0xfe : val; - break; + case 0x72: /* SMI Triggered By IRQ/GPIO Control */ + case 0x73: /* SMI Triggered By IRQ/GPIO Control */ + dev->pci_conf_sb[0][addr] = (addr == 0x72) ? val & 0xfe : val; + break; - case 0x74: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */ - case 0x75: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */ - case 0x76: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */ - case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */ - dev->pci_conf_sb[0][addr] = val; - break; - } - sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] = %02x\n", addr, val); - break; + case 0x74: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */ + case 0x75: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */ + case 0x76: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */ + case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */ + dev->pci_conf_sb[0][addr] = val; + break; + } + sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] = %02x\n", addr, val); + break; - case 1: /* IDE Controller */ - switch (addr) - { - case 0x04: /* Command low byte */ - dev->pci_conf_sb[1][addr] = val & 0x05; - sis_5571_ide_handler(dev); - sis_5571_bm_handler(dev); - break; + case 1: /* IDE Controller */ + switch (addr) { + case 0x04: /* Command low byte */ + dev->pci_conf_sb[1][addr] = val & 0x05; + sis_5571_ide_handler(dev); + sis_5571_bm_handler(dev); + break; - case 0x07: /* Status high byte */ - dev->pci_conf_sb[1][addr] &= val; - break; + case 0x07: /* Status high byte */ + dev->pci_conf_sb[1][addr] &= val; + break; - case 0x09: /* Programming Interface Byte */ - dev->pci_conf_sb[1][addr] = val & 0xcf; - sis_5571_ide_handler(dev); - break; + case 0x09: /* Programming Interface Byte */ + dev->pci_conf_sb[1][addr] = val & 0xcf; + sis_5571_ide_handler(dev); + break; - case 0x0d: /* Latency Time */ - case 0x10: /* Primary Channel Base Address Register */ - case 0x11: /* Primary Channel Base Address Register */ - case 0x12: /* Primary Channel Base Address Register */ - case 0x13: /* Primary Channel Base Address Register */ - case 0x14: /* Primary Channel Base Address Register */ - case 0x15: /* Primary Channel Base Address Register */ - case 0x16: /* Primary Channel Base Address Register */ - case 0x17: /* Primary Channel Base Address Register */ - case 0x18: /* Secondary Channel Base Address Register */ - case 0x19: /* Secondary Channel Base Address Register */ - case 0x1a: /* Secondary Channel Base Address Register */ - case 0x1b: /* Secondary Channel Base Address Register */ - case 0x1c: /* Secondary Channel Base Address Register */ - case 0x1d: /* Secondary Channel Base Address Register */ - case 0x1e: /* Secondary Channel Base Address Register */ - case 0x1f: /* Secondary Channel Base Address Register */ - dev->pci_conf_sb[1][addr] = val; - sis_5571_ide_handler(dev); - break; + case 0x0d: /* Latency Time */ + case 0x10: /* Primary Channel Base Address Register */ + case 0x11: /* Primary Channel Base Address Register */ + case 0x12: /* Primary Channel Base Address Register */ + case 0x13: /* Primary Channel Base Address Register */ + case 0x14: /* Primary Channel Base Address Register */ + case 0x15: /* Primary Channel Base Address Register */ + case 0x16: /* Primary Channel Base Address Register */ + case 0x17: /* Primary Channel Base Address Register */ + case 0x18: /* Secondary Channel Base Address Register */ + case 0x19: /* Secondary Channel Base Address Register */ + case 0x1a: /* Secondary Channel Base Address Register */ + case 0x1b: /* Secondary Channel Base Address Register */ + case 0x1c: /* Secondary Channel Base Address Register */ + case 0x1d: /* Secondary Channel Base Address Register */ + case 0x1e: /* Secondary Channel Base Address Register */ + case 0x1f: /* Secondary Channel Base Address Register */ + dev->pci_conf_sb[1][addr] = val; + sis_5571_ide_handler(dev); + break; - case 0x20: /* Bus Master IDE Control Register Base Address */ - case 0x21: /* Bus Master IDE Control Register Base Address */ - case 0x22: /* Bus Master IDE Control Register Base Address */ - case 0x23: /* Bus Master IDE Control Register Base Address */ - dev->pci_conf_sb[1][addr] = val; - sis_5571_bm_handler(dev); - break; + case 0x20: /* Bus Master IDE Control Register Base Address */ + case 0x21: /* Bus Master IDE Control Register Base Address */ + case 0x22: /* Bus Master IDE Control Register Base Address */ + case 0x23: /* Bus Master IDE Control Register Base Address */ + dev->pci_conf_sb[1][addr] = val; + sis_5571_bm_handler(dev); + break; - case 0x30: /* Expansion ROM Base Address */ - case 0x31: /* Expansion ROM Base Address */ - case 0x32: /* Expansion ROM Base Address */ - case 0x33: /* Expansion ROM Base Address */ - case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */ - case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */ - case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */ - case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */ - case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */ - case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */ - case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */ - case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */ - case 0x48: /* IDE Command Recovery Time Control */ - case 0x49: /* IDE Command Active Time Control */ - dev->pci_conf_sb[1][addr] = val; - break; + case 0x30: /* Expansion ROM Base Address */ + case 0x31: /* Expansion ROM Base Address */ + case 0x32: /* Expansion ROM Base Address */ + case 0x33: /* Expansion ROM Base Address */ + case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */ + case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */ + case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */ + case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */ + case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */ + case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */ + case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */ + case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */ + case 0x48: /* IDE Command Recovery Time Control */ + case 0x49: /* IDE Command Active Time Control */ + dev->pci_conf_sb[1][addr] = val; + break; - case 0x4a: /* IDE General Control Register 0 */ - dev->pci_conf_sb[1][addr] = val & 0xaf; - sis_5571_ide_handler(dev); - break; + case 0x4a: /* IDE General Control Register 0 */ + dev->pci_conf_sb[1][addr] = val & 0xaf; + sis_5571_ide_handler(dev); + break; - case 0x4b: /* IDE General Control register 1 */ - case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */ - case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */ - case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */ - case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */ - dev->pci_conf_sb[1][addr] = val; - break; - } - sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val); - break; + case 0x4b: /* IDE General Control register 1 */ + case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */ + case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */ + case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */ + case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */ + dev->pci_conf_sb[1][addr] = val; + break; + } + sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val); + break; - case 2: /* USB Controller */ - switch (addr) - { - case 0x04: /* Command - Low Byte */ - dev->pci_conf_sb[2][addr] = val; - ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1); - break; + case 2: /* USB Controller */ + switch (addr) { + case 0x04: /* Command - Low Byte */ + dev->pci_conf_sb[2][addr] = val; + ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1); + break; - case 0x05: /* Command - High Byte */ - dev->pci_conf_sb[2][addr] = val & 0x03; - break; + case 0x05: /* Command - High Byte */ + dev->pci_conf_sb[2][addr] = val & 0x03; + break; - case 0x06: /* Status - Low Byte */ - dev->pci_conf_sb[2][addr] &= val & 0xc0; - break; + case 0x06: /* Status - Low Byte */ + dev->pci_conf_sb[2][addr] &= val & 0xc0; + break; - case 0x07: /* Status - High Byte */ - dev->pci_conf_sb[2][addr] &= val; - break; + case 0x07: /* Status - High Byte */ + dev->pci_conf_sb[2][addr] &= val; + break; - case 0x10: /* Memory Space Base Address Register */ - case 0x11: /* Memory Space Base Address Register */ - case 0x12: /* Memory Space Base Address Register */ - case 0x13: /* Memory Space Base Address Register */ - dev->pci_conf_sb[2][addr] = val & ((addr == 0x11) ? 0x0f : 0xff); - ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1); - break; + case 0x10: /* Memory Space Base Address Register */ + case 0x11: /* Memory Space Base Address Register */ + case 0x12: /* Memory Space Base Address Register */ + case 0x13: /* Memory Space Base Address Register */ + dev->pci_conf_sb[2][addr] = val & ((addr == 0x11) ? 0x0f : 0xff); + ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1); + break; - case 0x14: /* IO Space Base Address Register */ - case 0x15: /* IO Space Base Address Register */ - case 0x16: /* IO Space Base Address Register */ - case 0x17: /* IO Space Base Address Register */ - case 0x3c: /* Interrupt Line */ - dev->pci_conf_sb[2][addr] = val; - break; - } - sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val); - } + case 0x14: /* IO Space Base Address Register */ + case 0x15: /* IO Space Base Address Register */ + case 0x16: /* IO Space Base Address Register */ + case 0x17: /* IO Space Base Address Register */ + case 0x3c: /* Interrupt Line */ + dev->pci_conf_sb[2][addr] = val; + break; + } + sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val); + } } static uint8_t pci_isa_bridge_read(int func, int addr, void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; + sis_5571_t *dev = (sis_5571_t *) priv; - switch (func) - { - case 0: - sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[0][addr]); - return dev->pci_conf_sb[0][addr]; - case 1: - sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[1][addr]); - return dev->pci_conf_sb[1][addr]; - case 2: - sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[2][addr]); - return dev->pci_conf_sb[2][addr]; - default: - return 0xff; - } + switch (func) { + case 0: + sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[0][addr]); + return dev->pci_conf_sb[0][addr]; + case 1: + sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[1][addr]); + return dev->pci_conf_sb[1][addr]; + case 2: + sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[2][addr]); + return dev->pci_conf_sb[2][addr]; + default: + return 0xff; + } } static void sis_5571_reset(void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; + sis_5571_t *dev = (sis_5571_t *) priv; - /* Memory/PCI Bridge */ - dev->pci_conf[0x00] = 0x39; - dev->pci_conf[0x01] = 0x10; - dev->pci_conf[0x02] = 0x71; - dev->pci_conf[0x03] = 0x55; - dev->pci_conf[0x04] = 0xfd; - dev->pci_conf[0x0b] = 0x06; - dev->pci_conf[0x9e] = 0xff; - dev->pci_conf[0x9f] = 0xff; - dev->pci_conf[0xa2] = 0xff; + /* Memory/PCI Bridge */ + dev->pci_conf[0x00] = 0x39; + dev->pci_conf[0x01] = 0x10; + dev->pci_conf[0x02] = 0x71; + dev->pci_conf[0x03] = 0x55; + dev->pci_conf[0x04] = 0xfd; + dev->pci_conf[0x0b] = 0x06; + dev->pci_conf[0x9e] = 0xff; + dev->pci_conf[0x9f] = 0xff; + dev->pci_conf[0xa2] = 0xff; - /* PCI to ISA bridge */ - dev->pci_conf_sb[0][0x00] = 0x39; - dev->pci_conf_sb[0][0x01] = 0x10; - dev->pci_conf_sb[0][0x02] = 0x08; - dev->pci_conf_sb[0][0x04] = 0xfd; - dev->pci_conf_sb[0][0x08] = 0x01; - dev->pci_conf_sb[0][0x0a] = 0x01; - dev->pci_conf_sb[0][0x0b] = 0x06; + /* PCI to ISA bridge */ + dev->pci_conf_sb[0][0x00] = 0x39; + dev->pci_conf_sb[0][0x01] = 0x10; + dev->pci_conf_sb[0][0x02] = 0x08; + dev->pci_conf_sb[0][0x04] = 0xfd; + dev->pci_conf_sb[0][0x08] = 0x01; + dev->pci_conf_sb[0][0x0a] = 0x01; + dev->pci_conf_sb[0][0x0b] = 0x06; - /* IDE Controller */ - dev->pci_conf_sb[1][0x00] = 0x39; - dev->pci_conf_sb[1][0x01] = 0x10; - dev->pci_conf_sb[1][0x02] = 0x13; - dev->pci_conf_sb[1][0x03] = 0x55; - dev->pci_conf_sb[1][0x08] = 0xc0; - dev->pci_conf_sb[1][0x0a] = 0x01; - dev->pci_conf_sb[1][0x0b] = 0x01; - dev->pci_conf_sb[1][0x0e] = 0x80; - dev->pci_conf_sb[1][0x4a] = 0x06; - sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot); - sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot); - sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE); - sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8); + /* IDE Controller */ + dev->pci_conf_sb[1][0x00] = 0x39; + dev->pci_conf_sb[1][0x01] = 0x10; + dev->pci_conf_sb[1][0x02] = 0x13; + dev->pci_conf_sb[1][0x03] = 0x55; + dev->pci_conf_sb[1][0x08] = 0xc0; + dev->pci_conf_sb[1][0x0a] = 0x01; + dev->pci_conf_sb[1][0x0b] = 0x01; + dev->pci_conf_sb[1][0x0e] = 0x80; + dev->pci_conf_sb[1][0x4a] = 0x06; + sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot); + sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot); + sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE); + sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8); - /* USB Controller */ - dev->pci_conf_sb[2][0x00] = 0x39; - dev->pci_conf_sb[2][0x01] = 0x10; - dev->pci_conf_sb[2][0x02] = 0x01; - dev->pci_conf_sb[2][0x03] = 0x70; - dev->pci_conf_sb[2][0x08] = 0xb0; - dev->pci_conf_sb[2][0x09] = 0x10; - dev->pci_conf_sb[2][0x0a] = 0x03; - dev->pci_conf_sb[2][0x0b] = 0xc0; - dev->pci_conf_sb[2][0x0e] = 0x80; - dev->pci_conf_sb[2][0x14] = 0x01; - dev->pci_conf_sb[2][0x3d] = 0x01; + /* USB Controller */ + dev->pci_conf_sb[2][0x00] = 0x39; + dev->pci_conf_sb[2][0x01] = 0x10; + dev->pci_conf_sb[2][0x02] = 0x01; + dev->pci_conf_sb[2][0x03] = 0x70; + dev->pci_conf_sb[2][0x08] = 0xb0; + dev->pci_conf_sb[2][0x09] = 0x10; + dev->pci_conf_sb[2][0x0a] = 0x03; + dev->pci_conf_sb[2][0x0b] = 0xc0; + dev->pci_conf_sb[2][0x0e] = 0x80; + dev->pci_conf_sb[2][0x14] = 0x01; + dev->pci_conf_sb[2][0x3d] = 0x01; } static void sis_5571_close(void *priv) { - sis_5571_t *dev = (sis_5571_t *)priv; + sis_5571_t *dev = (sis_5571_t *) priv; - smram_del(dev->smram); - free(dev); + smram_del(dev->smram); + free(dev); } static void * sis_5571_init(const device_t *info) { - sis_5571_t *dev = (sis_5571_t *)malloc(sizeof(sis_5571_t)); - memset(dev, 0x00, sizeof(sis_5571_t)); + sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t)); + memset(dev, 0x00, sizeof(sis_5571_t)); - dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev); - dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev); + dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev); + dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev); - /* MIRQ */ - pci_enable_mirq(0); + /* MIRQ */ + pci_enable_mirq(0); - /* Port 92 & SMRAM */ - dev->port_92 = device_add(&port_92_pci_device); - dev->smram = smram_add(); + /* Port 92 & SMRAM */ + dev->port_92 = device_add(&port_92_pci_device); + dev->smram = smram_add(); - /* SFF IDE */ - dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1); - dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2); + /* SFF IDE */ + dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1); + dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2); - /* USB */ - dev->usb = device_add(&usb_device); + /* USB */ + dev->usb = device_add(&usb_device); - sis_5571_reset(dev); + sis_5571_reset(dev); - return dev; + return dev; } const device_t sis_5571_device = { - .name = "SiS 5571", + .name = "SiS 5571", .internal_name = "sis_5571", - .flags = DEVICE_PCI, - .local = 0, - .init = sis_5571_init, - .close = sis_5571_close, - .reset = sis_5571_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = sis_5571_init, + .close = sis_5571_close, + .reset = sis_5571_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_85c310.c b/src/chipset/sis_85c310.c index 2e83e3367..c3015e35b 100644 --- a/src/chipset/sis_85c310.c +++ b/src/chipset/sis_85c310.c @@ -12,27 +12,25 @@ #include <86box/mem.h> #include <86box/chipset.h> - typedef struct { - uint8_t cur_reg, tries, - regs[258]; + uint8_t cur_reg, tries, + regs[258]; } rabbit_t; - static void rabbit_recalcmapping(rabbit_t *dev) { uint32_t shread, shwrite; uint32_t shflags = 0; - shread = !!(dev->regs[0x101] & 0x40); + shread = !!(dev->regs[0x101] & 0x40); shwrite = !!(dev->regs[0x100] & 0x02); shflags = shread ? MEM_READ_INTERNAL : MEM_READ_EXTANY; shflags |= shwrite ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - shadowbios = !!shread; + shadowbios = !!shread; shadowbios_write = !!shwrite; #ifdef USE_SHADOW_C0000 @@ -42,79 +40,76 @@ rabbit_recalcmapping(rabbit_t *dev) #endif switch (dev->regs[0x100] & 0x09) { - case 0x01: + case 0x01: /* The one BIOS we use seems to use something else to control C0000-DFFFF shadow, no idea what. */ #ifdef USE_SHADOW_C0000 - /* 64K at 0C0000-0CFFFF */ - mem_set_mem_state(0x000c0000, 0x00010000, shflags); - /* FALLTHROUGH */ + /* 64K at 0C0000-0CFFFF */ + mem_set_mem_state(0x000c0000, 0x00010000, shflags); + /* FALLTHROUGH */ #endif - case 0x00: - /* 64K at 0F0000-0FFFFF */ - mem_set_mem_state(0x000f0000, 0x00010000, shflags); - break; + case 0x00: + /* 64K at 0F0000-0FFFFF */ + mem_set_mem_state(0x000f0000, 0x00010000, shflags); + break; - case 0x09: + case 0x09: #ifdef USE_SHADOW_C0000 - /* 128K at 0C0000-0DFFFF */ - mem_set_mem_state(0x000c0000, 0x00020000, shflags); - /* FALLTHROUGH */ + /* 128K at 0C0000-0DFFFF */ + mem_set_mem_state(0x000c0000, 0x00020000, shflags); + /* FALLTHROUGH */ #endif - case 0x08: - /* 128K at 0E0000-0FFFFF */ - mem_set_mem_state(0x000e0000, 0x00020000, shflags); - break; + case 0x08: + /* 128K at 0E0000-0FFFFF */ + mem_set_mem_state(0x000e0000, 0x00020000, shflags); + break; } flushmmucache(); } - static void rabbit_write(uint16_t addr, uint8_t val, void *priv) { rabbit_t *dev = (rabbit_t *) priv; switch (addr) { - case 0x22: - dev->cur_reg = val; - dev->tries = 0; - break; - case 0x23: - if (dev->cur_reg == 0x83) { - if (dev->tries < 0x02) { - dev->regs[dev->tries++ | 0x100] = val; - if (dev->tries == 0x02) - rabbit_recalcmapping(dev); - } - } else - dev->regs[dev->cur_reg] = val; - break; + case 0x22: + dev->cur_reg = val; + dev->tries = 0; + break; + case 0x23: + if (dev->cur_reg == 0x83) { + if (dev->tries < 0x02) { + dev->regs[dev->tries++ | 0x100] = val; + if (dev->tries == 0x02) + rabbit_recalcmapping(dev); + } + } else + dev->regs[dev->cur_reg] = val; + break; } } - static uint8_t rabbit_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; rabbit_t *dev = (rabbit_t *) priv; switch (addr) { - case 0x23: - if (dev->cur_reg == 0x83) { - if (dev->tries < 0x02) - ret = dev->regs[dev->tries++ | 0x100]; - } else - ret = dev->regs[dev->cur_reg]; - break; + case 0x23: + if (dev->cur_reg == 0x83) { + if (dev->tries < 0x02) + ret = dev->regs[dev->tries++ | 0x100]; + } else + ret = dev->regs[dev->cur_reg]; + break; } return ret; } - static void rabbit_close(void *priv) { @@ -123,7 +118,6 @@ rabbit_close(void *priv) free(dev); } - static void * rabbit_init(const device_t *info) { @@ -136,15 +130,15 @@ rabbit_init(const device_t *info) } const device_t rabbit_device = { - .name = "SiS Rabbit", + .name = "SiS Rabbit", .internal_name = "rabbit", - .flags = 0, - .local = 0, - .init = rabbit_init, - .close = rabbit_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = rabbit_init, + .close = rabbit_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c index 36d1f2030..e6e32c4b6 100644 --- a/src/chipset/sis_85c496.c +++ b/src/chipset/sis_85c496.c @@ -38,39 +38,34 @@ #include <86box/chipset.h> #include <86box/spd.h> - -typedef struct sis_85c496_t -{ - uint8_t cur_reg, rmsmiblk_count, - regs[127], - pci_conf[256]; - smram_t *smram; - pc_timer_t rmsmiblk_timer; - port_92_t * port_92; - nvr_t * nvr; +typedef struct sis_85c496_t { + uint8_t cur_reg, rmsmiblk_count, + regs[127], + pci_conf[256]; + smram_t *smram; + pc_timer_t rmsmiblk_timer; + port_92_t *port_92; + nvr_t *nvr; } sis_85c496_t; - #ifdef ENABLE_SIS_85C496_LOG int sis_85c496_do_log = ENABLE_SIS_85C496_LOG; - void sis_85c496_log(const char *fmt, ...) { va_list ap; if (sis_85c496_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define sis_85c496_log(fmt, ...) +# define sis_85c496_log(fmt, ...) #endif - static void sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv) { @@ -79,75 +74,74 @@ sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv) sis_85c496_log("[%04X:%08X] ISA Write %02X to %04X\n", CS, cpu_state.pc, val, port); if (port == 0x22) - dev->cur_reg = val; - else if (port == 0x23) switch (dev->cur_reg) { - case 0x01: /* Built-in 206 Timing Control */ - dev->regs[dev->cur_reg] = val; - break; - case 0x70: /* ISA Bus Clock Selection */ - dev->regs[dev->cur_reg] = val & 0xc0; - break; - case 0x71: /* ISA Bus Timing Control */ - dev->regs[dev->cur_reg] = val & 0xf6; - break; - case 0x72: case 0x76: /* SMOUT */ - case 0x74: /* BIOS Timer */ - dev->regs[dev->cur_reg] = val; - break; - case 0x73: /* BIOS Timer */ - dev->regs[dev->cur_reg] = val & 0xfd; - break; - case 0x75: /* DMA / Deturbo Control */ - dev->regs[dev->cur_reg] = val & 0xfc; - dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff); - break; - } + dev->cur_reg = val; + else if (port == 0x23) + switch (dev->cur_reg) { + case 0x01: /* Built-in 206 Timing Control */ + dev->regs[dev->cur_reg] = val; + break; + case 0x70: /* ISA Bus Clock Selection */ + dev->regs[dev->cur_reg] = val & 0xc0; + break; + case 0x71: /* ISA Bus Timing Control */ + dev->regs[dev->cur_reg] = val & 0xf6; + break; + case 0x72: + case 0x76: /* SMOUT */ + case 0x74: /* BIOS Timer */ + dev->regs[dev->cur_reg] = val; + break; + case 0x73: /* BIOS Timer */ + dev->regs[dev->cur_reg] = val & 0xfd; + break; + case 0x75: /* DMA / Deturbo Control */ + dev->regs[dev->cur_reg] = val & 0xfc; + dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff); + break; + } } - static uint8_t sis_85c497_isa_read(uint16_t port, void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (port == 0x23) - ret = dev->regs[dev->cur_reg]; + ret = dev->regs[dev->cur_reg]; else if (port == 0x33) - ret = 0x3c /*random_generate()*/; + ret = 0x3c /*random_generate()*/; sis_85c496_log("[%04X:%08X] ISA Read %02X from %04X\n", CS, cpu_state.pc, ret, port); return ret; } - static void sis_85c496_recalcmapping(sis_85c496_t *dev) { uint32_t base; uint32_t i, shflags = 0; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; for (i = 0; i < 8; i++) { - base = 0xc0000 + (i << 15); + base = 0xc0000 + (i << 15); - if (dev->pci_conf[0x44] & (1 << i)) { - shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02); - shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01); - shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL; - mem_set_mem_state_both(base, 0x8000, shflags); - } else - mem_set_mem_state_both(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + if (dev->pci_conf[0x44] & (1 << i)) { + shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02); + shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01); + shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL; + mem_set_mem_state_both(base, 0x8000, shflags); + } else + mem_set_mem_state_both(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); } flushmmucache_nopc(); } - static void sis_85c496_ide_handler(sis_85c496_t *dev) { @@ -160,308 +154,330 @@ sis_85c496_ide_handler(sis_85c496_t *dev) ide_sec_disable(); if (ide_cfg[1] & 0x02) { - ide_set_base(0, 0x0170); - ide_set_side(0, 0x0376); - ide_set_base(1, 0x01f0); - ide_set_side(1, 0x03f6); + ide_set_base(0, 0x0170); + ide_set_side(0, 0x0376); + ide_set_base(1, 0x01f0); + ide_set_side(1, 0x03f6); - if (ide_cfg[1] & 0x01) { - if (!(ide_cfg[0] & 0x40)) - ide_pri_enable(); - if (!(ide_cfg[0] & 0x80)) - ide_sec_enable(); - } + if (ide_cfg[1] & 0x01) { + if (!(ide_cfg[0] & 0x40)) + ide_pri_enable(); + if (!(ide_cfg[0] & 0x80)) + ide_sec_enable(); + } } else { - ide_set_base(0, 0x01f0); - ide_set_side(0, 0x03f6); - ide_set_base(1, 0x0170); - ide_set_side(1, 0x0376); + ide_set_base(0, 0x01f0); + ide_set_side(0, 0x03f6); + ide_set_base(1, 0x0170); + ide_set_side(1, 0x0376); - if (ide_cfg[1] & 0x01) { - if (!(ide_cfg[0] & 0x40)) - ide_sec_enable(); - if (!(ide_cfg[0] & 0x80)) - ide_pri_enable(); - } + if (ide_cfg[1] & 0x01) { + if (!(ide_cfg[0] & 0x40)) + ide_sec_enable(); + if (!(ide_cfg[0] & 0x80)) + ide_pri_enable(); + } } } - /* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */ static void sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; - uint8_t old, valxor; - uint8_t smm_irq[4] = { 10, 11, 12, 15 }; - uint32_t host_base, ram_base, size; + uint8_t old, valxor; + uint8_t smm_irq[4] = { 10, 11, 12, 15 }; + uint32_t host_base, ram_base, size; - old = dev->pci_conf[addr]; + old = dev->pci_conf[addr]; valxor = (dev->pci_conf[addr]) ^ val; sis_85c496_log("[%04X:%08X] PCI Write %02X to %02X:%02X\n", CS, cpu_state.pc, val, func, addr); switch (addr) { - /* PCI Configuration Header Registers (00h ~ 3Fh) */ - case 0x04: /* PCI Device Command */ - dev->pci_conf[addr] = val & 0x40; - break; - case 0x05: /* PCI Device Command */ - dev->pci_conf[addr] = val & 0x03; - break; - case 0x07: /* Device Status */ - dev->pci_conf[addr] &= ~(val & 0xf1); - break; + /* PCI Configuration Header Registers (00h ~ 3Fh) */ + case 0x04: /* PCI Device Command */ + dev->pci_conf[addr] = val & 0x40; + break; + case 0x05: /* PCI Device Command */ + dev->pci_conf[addr] = val & 0x03; + break; + case 0x07: /* Device Status */ + dev->pci_conf[addr] &= ~(val & 0xf1); + break; - /* 86C496 Specific Registers (40h ~ 7Fh) */ - case 0x40: /* CPU Configuration */ - dev->pci_conf[addr] = val & 0x7f; - break; - case 0x41: /* DRAM Configuration */ - dev->pci_conf[addr] = val; - break; - case 0x42: /* Cache Configure */ - dev->pci_conf[addr] = val; - cpu_cache_ext_enabled = (val & 0x01); - cpu_update_waitstates(); - break; - case 0x43: /* Cache Configure */ - dev->pci_conf[addr] = val & 0x8f; - break; - case 0x44: /* Shadow Configure */ - dev->pci_conf[addr] = val; - if (valxor & 0xff) { - sis_85c496_recalcmapping(dev); - if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x30)) - flushmmucache_nopc(); - else if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x00)) - flushmmucache_nopc(); - else - flushmmucache(); - } - break; - case 0x45: /* Shadow Configure */ - dev->pci_conf[addr] = val & 0x0f; - if (valxor & 0x03) - sis_85c496_recalcmapping(dev); - break; - case 0x46: /* Cacheable Control */ - dev->pci_conf[addr] = val; - break; - case 0x47: /* 85C496 Address Decoder */ - dev->pci_conf[addr] = val & 0x1f; - break; - case 0x48: case 0x49: case 0x4a: case 0x4b: /* DRAM Boundary */ - case 0x4c: case 0x4d: case 0x4e: case 0x4f: - // dev->pci_conf[addr] = val; - spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1); - break; - case 0x50: case 0x51: /* Exclusive Area 0 Setup */ - dev->pci_conf[addr] = val; - break; - case 0x52: case 0x53: /* Exclusive Area 1 Setup */ - dev->pci_conf[addr] = val; - break; - case 0x54: /* Exclusive Area 2 Setup */ - dev->pci_conf[addr] = val; - break; - case 0x55: /* Exclusive Area 3 Setup */ - dev->pci_conf[addr] = val & 0xf0; - break; - case 0x56: /* PCI / Keyboard Configure */ - dev->pci_conf[addr] = val; - if (valxor & 0x02) { - port_92_remove(dev->port_92); - if (val & 0x02) - port_92_add(dev->port_92); - } - break; - case 0x57: /* Output Pin Configuration */ - dev->pci_conf[addr] = val; - break; - case 0x58: /* Build-in IDE Controller / VESA Bus Configuration */ - dev->pci_conf[addr] = val & 0xd7; - if (valxor & 0xc0) - sis_85c496_ide_handler(dev); - break; - case 0x59: /* Build-in IDE Controller / VESA Bus Configuration */ - dev->pci_conf[addr] = val; - if (valxor & 0x03) - sis_85c496_ide_handler(dev); - break; - case 0x5a: /* SMRAM Remapping Configuration */ - dev->pci_conf[addr] = val & 0xbe; - if (valxor & 0x3e) { - unmask_a20_in_smm = !!(val & 0x20); + /* 86C496 Specific Registers (40h ~ 7Fh) */ + case 0x40: /* CPU Configuration */ + dev->pci_conf[addr] = val & 0x7f; + break; + case 0x41: /* DRAM Configuration */ + dev->pci_conf[addr] = val; + break; + case 0x42: /* Cache Configure */ + dev->pci_conf[addr] = val; + cpu_cache_ext_enabled = (val & 0x01); + cpu_update_waitstates(); + break; + case 0x43: /* Cache Configure */ + dev->pci_conf[addr] = val & 0x8f; + break; + case 0x44: /* Shadow Configure */ + dev->pci_conf[addr] = val; + if (valxor & 0xff) { + sis_85c496_recalcmapping(dev); + if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x30)) + flushmmucache_nopc(); + else if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x00)) + flushmmucache_nopc(); + else + flushmmucache(); + } + break; + case 0x45: /* Shadow Configure */ + dev->pci_conf[addr] = val & 0x0f; + if (valxor & 0x03) + sis_85c496_recalcmapping(dev); + break; + case 0x46: /* Cacheable Control */ + dev->pci_conf[addr] = val; + break; + case 0x47: /* 85C496 Address Decoder */ + dev->pci_conf[addr] = val & 0x1f; + break; + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: /* DRAM Boundary */ + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + // dev->pci_conf[addr] = val; + spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1); + break; + case 0x50: + case 0x51: /* Exclusive Area 0 Setup */ + dev->pci_conf[addr] = val; + break; + case 0x52: + case 0x53: /* Exclusive Area 1 Setup */ + dev->pci_conf[addr] = val; + break; + case 0x54: /* Exclusive Area 2 Setup */ + dev->pci_conf[addr] = val; + break; + case 0x55: /* Exclusive Area 3 Setup */ + dev->pci_conf[addr] = val & 0xf0; + break; + case 0x56: /* PCI / Keyboard Configure */ + dev->pci_conf[addr] = val; + if (valxor & 0x02) { + port_92_remove(dev->port_92); + if (val & 0x02) + port_92_add(dev->port_92); + } + break; + case 0x57: /* Output Pin Configuration */ + dev->pci_conf[addr] = val; + break; + case 0x58: /* Build-in IDE Controller / VESA Bus Configuration */ + dev->pci_conf[addr] = val & 0xd7; + if (valxor & 0xc0) + sis_85c496_ide_handler(dev); + break; + case 0x59: /* Build-in IDE Controller / VESA Bus Configuration */ + dev->pci_conf[addr] = val; + if (valxor & 0x03) + sis_85c496_ide_handler(dev); + break; + case 0x5a: /* SMRAM Remapping Configuration */ + dev->pci_conf[addr] = val & 0xbe; + if (valxor & 0x3e) { + unmask_a20_in_smm = !!(val & 0x20); - smram_disable_all(); + smram_disable_all(); - if (val & 0x02) { - host_base = 0x00060000; - ram_base = 0x000a0000; - size = 0x00010000; - switch ((val >> 3) & 0x03) { - case 0x00: - host_base = 0x00060000; - ram_base = 0x000a0000; - break; - case 0x01: - host_base = 0x00060000; - ram_base = 0x000b0000; - break; - case 0x02: - host_base = 0x000e0000; - ram_base = 0x000a0000; - break; - case 0x03: - host_base = 0x000e0000; - ram_base = 0x000b0000; - break; - } + if (val & 0x02) { + host_base = 0x00060000; + ram_base = 0x000a0000; + size = 0x00010000; + switch ((val >> 3) & 0x03) { + case 0x00: + host_base = 0x00060000; + ram_base = 0x000a0000; + break; + case 0x01: + host_base = 0x00060000; + ram_base = 0x000b0000; + break; + case 0x02: + host_base = 0x000e0000; + ram_base = 0x000a0000; + break; + case 0x03: + host_base = 0x000e0000; + ram_base = 0x000b0000; + break; + } - smram_enable(dev->smram, host_base, ram_base, size, - ((val & 0x06) == 0x06), (val & 0x02)); - } - } - break; - case 0x5b: /* Programmable I/O Traps Configure */ - case 0x5c: case 0x5d: /* Programmable I/O Trap 0 Base */ - case 0x5e: case 0x5f: /* Programmable I/O Trap 0 Base */ - case 0x60: case 0x61: /* IDE Controller Channel 0 Configuration */ - case 0x62: case 0x63: /* IDE Controller Channel 1 Configuration */ - case 0x64: case 0x65: /* Exclusive Area 3 Setup */ - case 0x66: /* EDO DRAM Configuration */ - case 0x68: case 0x69: /* Asymmetry DRAM Configuration */ - dev->pci_conf[addr] = val; - break; - case 0x67: /* Miscellaneous Control */ - dev->pci_conf[addr] = val & 0xf9; - if (valxor & 0x60) - port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40)); - break; + smram_enable(dev->smram, host_base, ram_base, size, + ((val & 0x06) == 0x06), (val & 0x02)); + } + } + break; + case 0x5b: /* Programmable I/O Traps Configure */ + case 0x5c: + case 0x5d: /* Programmable I/O Trap 0 Base */ + case 0x5e: + case 0x5f: /* Programmable I/O Trap 0 Base */ + case 0x60: + case 0x61: /* IDE Controller Channel 0 Configuration */ + case 0x62: + case 0x63: /* IDE Controller Channel 1 Configuration */ + case 0x64: + case 0x65: /* Exclusive Area 3 Setup */ + case 0x66: /* EDO DRAM Configuration */ + case 0x68: + case 0x69: /* Asymmetry DRAM Configuration */ + dev->pci_conf[addr] = val; + break; + case 0x67: /* Miscellaneous Control */ + dev->pci_conf[addr] = val & 0xf9; + if (valxor & 0x60) + port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40)); + break; - /* 86C497 Specific Registers (80h ~ FFh) */ - case 0x80: /* PMU Configuration */ - case 0x85: /* STPCLK# Event Control */ - case 0x86: case 0x87: /* STPCLK# Deassertion IRQ Selection */ - case 0x89: /* Fast Timer Count */ - case 0x8a: /* Generic Timer Count */ - case 0x8b: /* Slow Timer Count */ - case 0x8e: /* Clock Throttling On Timer Count */ - case 0x8f: /* Clock Throttling Off Timer Count */ - case 0x90: /* Clock Throttling On Timer Reload Condition */ - case 0x92: /* Fast Timer Reload Condition */ - case 0x94: /* Generic Timer Reload Condition */ - case 0x96: /* Slow Timer Reload Condition */ - case 0x98: case 0x99: /* Fast Timer Reload IRQ Selection */ - case 0x9a: case 0x9b: /* Generic Timer Reload IRQ Selection */ - case 0x9c: case 0x9d: /* Slow Timer Reload IRQ Selection */ - case 0xa2: /* SMI Request Status Selection */ - case 0xa4: case 0xa5: /* SMI Request IRQ Selection */ - case 0xa6: case 0xa7: /* Clock Throttlign On Timer Reload IRQ Selection */ - case 0xa8: /* GPIO Control */ - case 0xaa: /* GPIO DeBounce Count */ - case 0xd2: /* Exclusive Area 2 Base Address */ - dev->pci_conf[addr] = val; - break; - case 0x81: /* PMU CPU Type Configuration */ - dev->pci_conf[addr] = val & 0x9f; - break; - case 0x88: /* Timer Control */ - dev->pci_conf[addr] = val & 0x3f; - break; - case 0x8d: /* RMSMIBLK Timer Count */ - dev->pci_conf[addr] = val; - dev->rmsmiblk_count = val; - timer_stop(&dev->rmsmiblk_timer); - if (val >= 0x02) - timer_on_auto(&dev->rmsmiblk_timer, 35.0); - break; - case 0x91: /* Clock Throttling On Timer Reload Condition */ - case 0x93: /* Fast Timer Reload Condition */ - case 0x95: /* Generic Timer Reload Condition */ - dev->pci_conf[addr] = val & 0x03; - break; - case 0x97: /* Slow Timer Reload Condition */ - dev->pci_conf[addr] = val & 0xc3; - break; - case 0x9e: /* Soft-SMI Generation / RMSMIBLK Trigger */ - if (!smi_block && (val & 0x01) && (dev->pci_conf[0x80] & 0x80) && (dev->pci_conf[0xa2] & 0x10)) { - if (dev->pci_conf[0x80] & 0x10) - picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]); - else - smi_raise(); - smi_block = 1; - dev->pci_conf[0xa0] |= 0x10; - } - if (val & 0x02) { - timer_stop(&dev->rmsmiblk_timer); - if (dev->rmsmiblk_count >= 0x02) - timer_on_auto(&dev->rmsmiblk_timer, 35.0); - } - break; - case 0xa0: case 0xa1: /* SMI Request Status */ - dev->pci_conf[addr] &= ~val; - break; - case 0xa3: /* SMI Request Status Selection */ - dev->pci_conf[addr] = val & 0x7f; - break; - case 0xa9: /* GPIO SMI Request Status */ - dev->pci_conf[addr] = ~(val & 0x03); - break; - case 0xc0: /* PCI INTA# -to-IRQ Link */ - case 0xc1: /* PCI INTB# -to-IRQ Link */ - case 0xc2: /* PCI INTC# -to-IRQ Link */ - case 0xc3: /* PCI INTD# -to-IRQ Link */ - dev->pci_conf[addr] = val & 0x8f; - if (val & 0x80) - pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); - else - pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); - break; - case 0xc6: /* 85C497 Post / INIT Configuration */ - dev->pci_conf[addr] = val & 0x0f; - break; - case 0xc8: case 0xc9: case 0xca: case 0xcb: /* Mail Box */ - dev->pci_conf[addr] = val; - break; - case 0xd0: /* ISA BIOS Configuration */ - dev->pci_conf[addr] = val & 0xfb; - break; - case 0xd1: /* ISA Address Decoder */ - if (dev->pci_conf[0xd0] & 0x01) - dev->pci_conf[addr] = val; - break; - case 0xd3: /* Exclusive Area 2 Base Address */ - dev->pci_conf[addr] = val & 0xf0; - break; - case 0xd4: /* Miscellaneous Configuration */ - dev->pci_conf[addr] = val & 0x6e; - nvr_bank_set(0, !!(val & 0x40), dev->nvr); - break; + /* 86C497 Specific Registers (80h ~ FFh) */ + case 0x80: /* PMU Configuration */ + case 0x85: /* STPCLK# Event Control */ + case 0x86: + case 0x87: /* STPCLK# Deassertion IRQ Selection */ + case 0x89: /* Fast Timer Count */ + case 0x8a: /* Generic Timer Count */ + case 0x8b: /* Slow Timer Count */ + case 0x8e: /* Clock Throttling On Timer Count */ + case 0x8f: /* Clock Throttling Off Timer Count */ + case 0x90: /* Clock Throttling On Timer Reload Condition */ + case 0x92: /* Fast Timer Reload Condition */ + case 0x94: /* Generic Timer Reload Condition */ + case 0x96: /* Slow Timer Reload Condition */ + case 0x98: + case 0x99: /* Fast Timer Reload IRQ Selection */ + case 0x9a: + case 0x9b: /* Generic Timer Reload IRQ Selection */ + case 0x9c: + case 0x9d: /* Slow Timer Reload IRQ Selection */ + case 0xa2: /* SMI Request Status Selection */ + case 0xa4: + case 0xa5: /* SMI Request IRQ Selection */ + case 0xa6: + case 0xa7: /* Clock Throttlign On Timer Reload IRQ Selection */ + case 0xa8: /* GPIO Control */ + case 0xaa: /* GPIO DeBounce Count */ + case 0xd2: /* Exclusive Area 2 Base Address */ + dev->pci_conf[addr] = val; + break; + case 0x81: /* PMU CPU Type Configuration */ + dev->pci_conf[addr] = val & 0x9f; + break; + case 0x88: /* Timer Control */ + dev->pci_conf[addr] = val & 0x3f; + break; + case 0x8d: /* RMSMIBLK Timer Count */ + dev->pci_conf[addr] = val; + dev->rmsmiblk_count = val; + timer_stop(&dev->rmsmiblk_timer); + if (val >= 0x02) + timer_on_auto(&dev->rmsmiblk_timer, 35.0); + break; + case 0x91: /* Clock Throttling On Timer Reload Condition */ + case 0x93: /* Fast Timer Reload Condition */ + case 0x95: /* Generic Timer Reload Condition */ + dev->pci_conf[addr] = val & 0x03; + break; + case 0x97: /* Slow Timer Reload Condition */ + dev->pci_conf[addr] = val & 0xc3; + break; + case 0x9e: /* Soft-SMI Generation / RMSMIBLK Trigger */ + if (!smi_block && (val & 0x01) && (dev->pci_conf[0x80] & 0x80) && (dev->pci_conf[0xa2] & 0x10)) { + if (dev->pci_conf[0x80] & 0x10) + picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]); + else + smi_raise(); + smi_block = 1; + dev->pci_conf[0xa0] |= 0x10; + } + if (val & 0x02) { + timer_stop(&dev->rmsmiblk_timer); + if (dev->rmsmiblk_count >= 0x02) + timer_on_auto(&dev->rmsmiblk_timer, 35.0); + } + break; + case 0xa0: + case 0xa1: /* SMI Request Status */ + dev->pci_conf[addr] &= ~val; + break; + case 0xa3: /* SMI Request Status Selection */ + dev->pci_conf[addr] = val & 0x7f; + break; + case 0xa9: /* GPIO SMI Request Status */ + dev->pci_conf[addr] = ~(val & 0x03); + break; + case 0xc0: /* PCI INTA# -to-IRQ Link */ + case 0xc1: /* PCI INTB# -to-IRQ Link */ + case 0xc2: /* PCI INTC# -to-IRQ Link */ + case 0xc3: /* PCI INTD# -to-IRQ Link */ + dev->pci_conf[addr] = val & 0x8f; + if (val & 0x80) + pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf); + else + pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED); + break; + case 0xc6: /* 85C497 Post / INIT Configuration */ + dev->pci_conf[addr] = val & 0x0f; + break; + case 0xc8: + case 0xc9: + case 0xca: + case 0xcb: /* Mail Box */ + dev->pci_conf[addr] = val; + break; + case 0xd0: /* ISA BIOS Configuration */ + dev->pci_conf[addr] = val & 0xfb; + break; + case 0xd1: /* ISA Address Decoder */ + if (dev->pci_conf[0xd0] & 0x01) + dev->pci_conf[addr] = val; + break; + case 0xd3: /* Exclusive Area 2 Base Address */ + dev->pci_conf[addr] = val & 0xf0; + break; + case 0xd4: /* Miscellaneous Configuration */ + dev->pci_conf[addr] = val & 0x6e; + nvr_bank_set(0, !!(val & 0x40), dev->nvr); + break; } } - static uint8_t sis_85c49x_pci_read(int func, int addr, void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; - uint8_t ret = dev->pci_conf[addr]; + uint8_t ret = dev->pci_conf[addr]; switch (addr) { - case 0xa0: - ret &= 0x10; - break; - case 0xa1: - ret = 0x00; - break; - case 0x82: /*Port 22h Mirror*/ - ret = dev->cur_reg; - break; - case 0x83: /*Port 70h Mirror*/ - ret = inb(0x70); - break; + case 0xa0: + ret &= 0x10; + break; + case 0xa1: + ret = 0x00; + break; + case 0x82: /*Port 22h Mirror*/ + ret = dev->cur_reg; + break; + case 0x83: /*Port 70h Mirror*/ + ret = inb(0x70); + break; } sis_85c496_log("[%04X:%08X] PCI Read %02X from %02X:%02X\n", CS, cpu_state.pc, ret, func, addr); @@ -469,7 +485,6 @@ sis_85c49x_pci_read(int func, int addr, void *priv) return ret; } - static void sis_85c496_rmsmiblk_count(void *priv) { @@ -478,14 +493,13 @@ sis_85c496_rmsmiblk_count(void *priv) dev->rmsmiblk_count--; if (dev->rmsmiblk_count == 1) { - smi_block = 0; - dev->rmsmiblk_count = 0; - timer_stop(&dev->rmsmiblk_timer); + smi_block = 0; + dev->rmsmiblk_count = 0; + timer_stop(&dev->rmsmiblk_timer); } else - timer_on_auto(&dev->rmsmiblk_timer, 35.0); + timer_on_auto(&dev->rmsmiblk_timer, 35.0); } - static void sis_85c497_isa_reset(sis_85c496_t *dev) { @@ -499,21 +513,20 @@ sis_85c497_isa_reset(sis_85c496_t *dev) dma_set_mask(0x00ffffff); io_removehandler(0x0022, 0x0002, - sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); + sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); io_removehandler(0x0033, 0x0001, - sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); + sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); io_sethandler(0x0022, 0x0002, - sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); + sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); io_sethandler(0x0033, 0x0001, - sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); + sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev); } - static void sis_85c496_reset(void *priv) { sis_85c496_t *dev = (sis_85c496_t *) priv; - int i; + int i; sis_85c49x_pci_write(0, 0x44, 0x00, dev); sis_85c49x_pci_write(0, 0x45, 0x00, dev); @@ -523,7 +536,7 @@ sis_85c496_reset(void *priv) // sis_85c49x_pci_write(0, 0x5a, 0x06, dev); for (i = 0; i < 8; i++) - sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev); + sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev); sis_85c49x_pci_write(0, 0x80, 0x00, dev); sis_85c49x_pci_write(0, 0x81, 0x00, dev); @@ -553,20 +566,19 @@ sis_85c496_reset(void *priv) sis_85c497_isa_reset(dev); } - static void sis_85c496_close(void *p) { - sis_85c496_t *dev = (sis_85c496_t *)p; + sis_85c496_t *dev = (sis_85c496_t *) p; smram_del(dev->smram); free(dev); } - static void -*sis_85c496_init(const device_t *info) + * + sis_85c496_init(const device_t *info) { sis_85c496_t *dev = malloc(sizeof(sis_85c496_t)); memset(dev, 0x00, sizeof(sis_85c496_t)); @@ -574,21 +586,21 @@ static void dev->smram = smram_add(); /* PCI Configuration Header Registers (00h ~ 3Fh) */ - dev->pci_conf[0x00] = 0x39; /* SiS */ + dev->pci_conf[0x00] = 0x39; /* SiS */ dev->pci_conf[0x01] = 0x10; - dev->pci_conf[0x02] = 0x96; /* 496/497 */ + dev->pci_conf[0x02] = 0x96; /* 496/497 */ dev->pci_conf[0x03] = 0x04; dev->pci_conf[0x04] = 0x07; dev->pci_conf[0x06] = 0x80; dev->pci_conf[0x07] = 0x02; - dev->pci_conf[0x08] = 0x02; /* Device revision */ - dev->pci_conf[0x09] = 0x00; /* Device class (PCI bridge) */ + dev->pci_conf[0x08] = 0x02; /* Device revision */ + dev->pci_conf[0x09] = 0x00; /* Device class (PCI bridge) */ dev->pci_conf[0x0b] = 0x06; /* 86C496 Specific Registers (40h ~ 7Fh) */ /* 86C497 Specific Registers (80h ~ FFh) */ - dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */ + dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */ dev->pci_conf[0xd1] = 0xff; pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev); @@ -605,9 +617,9 @@ static void ide_sec_disable(); if (info->local) - dev->nvr = device_add(&ami_1994_nvr_device); + dev->nvr = device_add(&ami_1994_nvr_device); else - dev->nvr = device_add(&at_nvr_device); + dev->nvr = device_add(&at_nvr_device); dma_high_page_init(); @@ -619,29 +631,29 @@ static void } const device_t sis_85c496_device = { - .name = "SiS 85c496/85c497", + .name = "SiS 85c496/85c497", .internal_name = "sis_85c496", - .flags = DEVICE_PCI, - .local = 0, - .init = sis_85c496_init, - .close = sis_85c496_close, - .reset = sis_85c496_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = sis_85c496_init, + .close = sis_85c496_close, + .reset = sis_85c496_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sis_85c496_ls486e_device = { - .name = "SiS 85c496/85c497 (Lucky Star LS-486E)", + .name = "SiS 85c496/85c497 (Lucky Star LS-486E)", .internal_name = "sis_85c496_ls486e", - .flags = DEVICE_PCI, - .local = 1, - .init = sis_85c496_init, - .close = sis_85c496_close, - .reset = sis_85c496_reset, + .flags = DEVICE_PCI, + .local = 1, + .init = sis_85c496_init, + .close = sis_85c496_close, + .reset = sis_85c496_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_85c4xx.c b/src/chipset/sis_85c4xx.c index 508f653e2..ba830ef0a 100644 --- a/src/chipset/sis_85c4xx.c +++ b/src/chipset/sis_85c4xx.c @@ -33,278 +33,275 @@ #include <86box/machine.h> #include <86box/chipset.h> - typedef struct { - uint8_t cur_reg, tries, - reg_base, reg_last, - reg_00, is_471, - regs[39], scratch[2]; - uint32_t mem_state[8]; - smram_t *smram; - port_92_t *port_92; + uint8_t cur_reg, tries, + reg_base, reg_last, + reg_00, is_471, + regs[39], scratch[2]; + uint32_t mem_state[8]; + smram_t *smram; + port_92_t *port_92; } sis_85c4xx_t; - static void sis_85c4xx_recalcmapping(sis_85c4xx_t *dev) { - uint32_t base, n = 0; + uint32_t base, n = 0; uint32_t i, shflags = 0; uint32_t readext, writeext; - uint8_t romcs = 0xc0, cur_romcs; + uint8_t romcs = 0xc0, cur_romcs; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; if (dev->regs[0x03] & 0x40) - romcs |= 0x01; + romcs |= 0x01; if (dev->regs[0x03] & 0x80) - romcs |= 0x30; + romcs |= 0x30; if (dev->regs[0x08] & 0x04) - romcs |= 0x02; + romcs |= 0x02; for (i = 0; i < 8; i++) { - base = 0xc0000 + (i << 15); - cur_romcs = romcs & (1 << i); - readext = cur_romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; - writeext = cur_romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; + base = 0xc0000 + (i << 15); + cur_romcs = romcs & (1 << i); + readext = cur_romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL; + writeext = cur_romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL; - if ((i > 5) || (dev->regs[0x02] & (1 << i))) { - shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80); - shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40); - shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : readext; - shflags |= (dev->regs[0x02] & 0x40) ? writeext : MEM_WRITE_INTERNAL; - if (dev->mem_state[i] != shflags) { - n++; - mem_set_mem_state(base, 0x8000, shflags); - if ((base >= 0xf0000) && (dev->mem_state[i] & MEM_READ_INTERNAL) && !(shflags & MEM_READ_INTERNAL)) - mem_invalidate_range(base, base + 0x7fff); - dev->mem_state[i] = shflags; - } - } else { - shflags = readext | writeext; - if (dev->mem_state[i] != shflags) { - n++; - mem_set_mem_state(base, 0x8000, shflags); - dev->mem_state[i] = shflags; - } - } + if ((i > 5) || (dev->regs[0x02] & (1 << i))) { + shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80); + shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40); + shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : readext; + shflags |= (dev->regs[0x02] & 0x40) ? writeext : MEM_WRITE_INTERNAL; + if (dev->mem_state[i] != shflags) { + n++; + mem_set_mem_state(base, 0x8000, shflags); + if ((base >= 0xf0000) && (dev->mem_state[i] & MEM_READ_INTERNAL) && !(shflags & MEM_READ_INTERNAL)) + mem_invalidate_range(base, base + 0x7fff); + dev->mem_state[i] = shflags; + } + } else { + shflags = readext | writeext; + if (dev->mem_state[i] != shflags) { + n++; + mem_set_mem_state(base, 0x8000, shflags); + dev->mem_state[i] = shflags; + } + } } if (n > 0) - flushmmucache_nopc(); + flushmmucache_nopc(); } - static void sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv) { sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; if (dev->regs[0x18] & 0x02) { - if (dev->regs[0x0b] & 0x10) - smi_raise(); - else - picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12)); - soft_reset_mask = 1; - dev->regs[0x19] |= 0x02; + if (dev->regs[0x0b] & 0x10) + smi_raise(); + else + picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12)); + soft_reset_mask = 1; + dev->regs[0x19] |= 0x02; } } - static void sis_85c4xx_sw_smi_handler(sis_85c4xx_t *dev) { uint16_t addr; if (!dev->is_471) - return; + return; addr = dev->regs[0x14] | (dev->regs[0x15] << 8); io_handler((dev->regs[0x0b] & 0x80) && (dev->regs[0x18] & 0x02), addr, 0x0001, - NULL, NULL, NULL, sis_85c4xx_sw_smi_out, NULL, NULL, dev); + NULL, NULL, NULL, sis_85c4xx_sw_smi_out, NULL, NULL, dev); } - static void sis_85c4xx_out(uint16_t port, uint8_t val, void *priv) { - sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; - uint8_t rel_reg = dev->cur_reg - dev->reg_base; - uint8_t valxor = 0x00; - uint32_t host_base = 0x000e0000, ram_base = 0x000a0000; + sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; + uint8_t rel_reg = dev->cur_reg - dev->reg_base; + uint8_t valxor = 0x00; + uint32_t host_base = 0x000e0000, ram_base = 0x000a0000; switch (port) { - case 0x22: - dev->cur_reg = val; - break; - case 0x23: - if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) { - valxor = val ^ dev->regs[rel_reg]; - if (rel_reg == 0x19) - dev->regs[rel_reg] &= ~val; - else - dev->regs[rel_reg] = val; + case 0x22: + dev->cur_reg = val; + break; + case 0x23: + if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) { + valxor = val ^ dev->regs[rel_reg]; + if (rel_reg == 0x19) + dev->regs[rel_reg] &= ~val; + else + dev->regs[rel_reg] = val; - switch (rel_reg) { - case 0x01: - cpu_cache_ext_enabled = ((val & 0x84) == 0x84); - cpu_update_waitstates(); - break; + switch (rel_reg) { + case 0x01: + cpu_cache_ext_enabled = ((val & 0x84) == 0x84); + cpu_update_waitstates(); + break; - case 0x02: case 0x03: - case 0x08: - if (valxor) - sis_85c4xx_recalcmapping(dev); - break; + case 0x02: + case 0x03: + case 0x08: + if (valxor) + sis_85c4xx_recalcmapping(dev); + break; - case 0x0b: - sis_85c4xx_sw_smi_handler(dev); - if (dev->is_471 && (valxor & 0x02)) { - if (val & 0x02) - mem_remap_top(0); - else - mem_remap_top(256); - } - break; + case 0x0b: + sis_85c4xx_sw_smi_handler(dev); + if (dev->is_471 && (valxor & 0x02)) { + if (val & 0x02) + mem_remap_top(0); + else + mem_remap_top(256); + } + break; - case 0x13: - if (dev->is_471 && (valxor & 0xf0)) { - smram_disable(dev->smram); - host_base = (val & 0x80) ? 0x00060000 : 0x000e0000; - switch ((val >> 5) & 0x03) { - case 0x00: - ram_base = 0x000a0000; - break; - case 0x01: - ram_base = 0x000b0000; - break; - case 0x02: - ram_base = (val & 0x80) ? 0x00000000 : 0x000e0000; - break; - default: - ram_base = 0x00000000; - break; - } - if (ram_base != 0x00000000) - smram_enable(dev->smram, host_base, ram_base, 0x00010000, (val & 0x10), 1); - } - break; + case 0x13: + if (dev->is_471 && (valxor & 0xf0)) { + smram_disable(dev->smram); + host_base = (val & 0x80) ? 0x00060000 : 0x000e0000; + switch ((val >> 5) & 0x03) { + case 0x00: + ram_base = 0x000a0000; + break; + case 0x01: + ram_base = 0x000b0000; + break; + case 0x02: + ram_base = (val & 0x80) ? 0x00000000 : 0x000e0000; + break; + default: + ram_base = 0x00000000; + break; + } + if (ram_base != 0x00000000) + smram_enable(dev->smram, host_base, ram_base, 0x00010000, (val & 0x10), 1); + } + break; - case 0x14: case 0x15: - case 0x18: - sis_85c4xx_sw_smi_handler(dev); - break; + case 0x14: + case 0x15: + case 0x18: + sis_85c4xx_sw_smi_handler(dev); + break; - case 0x1c: - if (dev->is_471) - soft_reset_mask = 0; - break; + case 0x1c: + if (dev->is_471) + soft_reset_mask = 0; + break; - case 0x22: - if (dev->is_471 && (valxor & 0x01)) { - port_92_remove(dev->port_92); - if (val & 0x01) - port_92_add(dev->port_92); - } - break; - } - } else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00)) - dev->reg_00 = val; - dev->cur_reg = 0x00; - break; + case 0x22: + if (dev->is_471 && (valxor & 0x01)) { + port_92_remove(dev->port_92); + if (val & 0x01) + port_92_add(dev->port_92); + } + break; + } + } else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00)) + dev->reg_00 = val; + dev->cur_reg = 0x00; + break; - case 0xe1: case 0xe2: - dev->scratch[port - 0xe1] = val; - return; + case 0xe1: + case 0xe2: + dev->scratch[port - 0xe1] = val; + return; } } - static uint8_t sis_85c4xx_in(uint16_t port, void *priv) { - sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; - uint8_t rel_reg = dev->cur_reg - dev->reg_base; - uint8_t ret = 0xff; + sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; + uint8_t rel_reg = dev->cur_reg - dev->reg_base; + uint8_t ret = 0xff; switch (port) { - case 0x23: - if (dev->is_471 && (dev->cur_reg == 0x1c)) - ret = inb(0x70); - /* On the SiS 40x, the shadow RAM read and write enable bits are write-only! */ - if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x62)) - ret = dev->regs[rel_reg] & 0x3f; - else if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) - ret = dev->regs[rel_reg]; - else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00)) - ret = dev->reg_00; - if (dev->reg_base != 0x60) - dev->cur_reg = 0x00; - break; + case 0x23: + if (dev->is_471 && (dev->cur_reg == 0x1c)) + ret = inb(0x70); + /* On the SiS 40x, the shadow RAM read and write enable bits are write-only! */ + if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x62)) + ret = dev->regs[rel_reg] & 0x3f; + else if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) + ret = dev->regs[rel_reg]; + else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00)) + ret = dev->reg_00; + if (dev->reg_base != 0x60) + dev->cur_reg = 0x00; + break; - case 0xe1: case 0xe2: - ret = dev->scratch[port - 0xe1]; + case 0xe1: + case 0xe2: + ret = dev->scratch[port - 0xe1]; } return ret; } - static void sis_85c4xx_reset(void *priv) { - sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; - int mem_size_mb = mem_size >> 10; + sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; + int mem_size_mb = mem_size >> 10; static uint8_t ram_4xx[64] = { 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x00, 0x0b, 0x00, 0x00, 0x00, - 0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09, 0x04, 0x04, 0x05, 0x05, 0x0b, 0x0b, 0x0b, 0x0b, - 0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, - 0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, - 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e }; + 0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, + 0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, + 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e }; memset(dev->regs, 0x00, sizeof(dev->regs)); if (cpu_s->rspeed < 25000000) - dev->regs[0x08] = 0x80; + dev->regs[0x08] = 0x80; if (dev->is_471) { - dev->regs[0x09] = 0x40; - if (mem_size_mb >= 64) { - if ((mem_size_mb >= 65) && (mem_size_mb < 68)) - dev->regs[0x09] |= 0x22; - else - dev->regs[0x09] |= 0x24; - } else - dev->regs[0x09] |= ram_471[mem_size_mb]; + dev->regs[0x09] = 0x40; + if (mem_size_mb >= 64) { + if ((mem_size_mb >= 65) && (mem_size_mb < 68)) + dev->regs[0x09] |= 0x22; + else + dev->regs[0x09] |= 0x24; + } else + dev->regs[0x09] |= ram_471[mem_size_mb]; - dev->regs[0x11] = 0x09; - dev->regs[0x12] = 0xff; - dev->regs[0x1f] = 0x20; /* Video access enabled. */ - dev->regs[0x23] = 0xf0; - dev->regs[0x26] = 0x01; + dev->regs[0x11] = 0x09; + dev->regs[0x12] = 0xff; + dev->regs[0x1f] = 0x20; /* Video access enabled. */ + dev->regs[0x23] = 0xf0; + dev->regs[0x26] = 0x01; - smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1); + smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1); - port_92_remove(dev->port_92); + port_92_remove(dev->port_92); - mem_remap_top(256); - soft_reset_mask = 0; + mem_remap_top(256); + soft_reset_mask = 0; } else { - /* Bits 6 and 7 must be clear on the SiS 40x. */ - if (dev->reg_base == 0x60) - dev->reg_00 = 0x24; + /* Bits 6 and 7 must be clear on the SiS 40x. */ + if (dev->reg_base == 0x60) + dev->reg_00 = 0x24; - if (mem_size_mb == 64) - dev->regs[0x00] = 0x1f; - else if (mem_size_mb < 64) - dev->regs[0x00] = ram_4xx[mem_size_mb]; + if (mem_size_mb == 64) + dev->regs[0x00] = 0x1f; + else if (mem_size_mb < 64) + dev->regs[0x00] = ram_4xx[mem_size_mb]; - dev->regs[0x11] = 0x01; + dev->regs[0x11] = 0x01; } dev->scratch[0] = dev->scratch[1] = 0xff; @@ -315,19 +312,17 @@ sis_85c4xx_reset(void *priv) sis_85c4xx_recalcmapping(dev); } - static void sis_85c4xx_close(void *priv) { sis_85c4xx_t *dev = (sis_85c4xx_t *) priv; if (dev->is_471) - smram_del(dev->smram); + smram_del(dev->smram); free(dev); } - static void * sis_85c4xx_init(const device_t *info) { @@ -339,19 +334,19 @@ sis_85c4xx_init(const device_t *info) dev->reg_base = info->local & 0xff; if (dev->is_471) { - dev->reg_last = dev->reg_base + 0x76; + dev->reg_last = dev->reg_base + 0x76; - dev->smram = smram_add(); + dev->smram = smram_add(); - dev->port_92 = device_add(&port_92_device); + dev->port_92 = device_add(&port_92_device); } else - dev->reg_last = dev->reg_base + 0x11; + dev->reg_last = dev->reg_base + 0x11; io_sethandler(0x0022, 0x0002, - sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev); + sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev); io_sethandler(0x00e1, 0x0002, - sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev); + sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev); sis_85c4xx_reset(dev); @@ -359,58 +354,58 @@ sis_85c4xx_init(const device_t *info) } const device_t sis_85c401_device = { - .name = "SiS 85c401/85c402", + .name = "SiS 85c401/85c402", .internal_name = "sis_85c401", - .flags = 0, - .local = 0x060, - .init = sis_85c4xx_init, - .close = sis_85c4xx_close, - .reset = sis_85c4xx_reset, + .flags = 0, + .local = 0x060, + .init = sis_85c4xx_init, + .close = sis_85c4xx_close, + .reset = sis_85c4xx_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sis_85c460_device = { - .name = "SiS 85c460", + .name = "SiS 85c460", .internal_name = "sis_85c460", - .flags = 0, - .local = 0x050, - .init = sis_85c4xx_init, - .close = sis_85c4xx_close, - .reset = sis_85c4xx_reset, + .flags = 0, + .local = 0x050, + .init = sis_85c4xx_init, + .close = sis_85c4xx_close, + .reset = sis_85c4xx_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; /* TODO: Log to make sure the registers are correct. */ const device_t sis_85c461_device = { - .name = "SiS 85c461", + .name = "SiS 85c461", .internal_name = "sis_85c461", - .flags = 0, - .local = 0x050, - .init = sis_85c4xx_init, - .close = sis_85c4xx_close, - .reset = sis_85c4xx_reset, + .flags = 0, + .local = 0x050, + .init = sis_85c4xx_init, + .close = sis_85c4xx_close, + .reset = sis_85c4xx_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t sis_85c471_device = { - .name = "SiS 85c407/85c471", + .name = "SiS 85c407/85c471", .internal_name = "sis_85c471", - .flags = 0, - .local = 0x150, - .init = sis_85c4xx_init, - .close = sis_85c4xx_close, - .reset = sis_85c4xx_reset, + .flags = 0, + .local = 0x150, + .init = sis_85c4xx_init, + .close = sis_85c4xx_close, + .reset = sis_85c4xx_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/sis_85c50x.c b/src/chipset/sis_85c50x.c index 1c46074b1..f0209bf90 100644 --- a/src/chipset/sis_85c50x.c +++ b/src/chipset/sis_85c50x.c @@ -36,7 +36,6 @@ #include <86box/chipset.h> - #ifdef ENABLE_SIS_85C50X_LOG int sis_85c50x_do_log = ENABLE_SIS_85C50X_LOG; static void @@ -45,264 +44,272 @@ sis_85c50x_log(const char *fmt, ...) va_list ap; if (sis_85c50x_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define sis_85c50x_log(fmt, ...) +# define sis_85c50x_log(fmt, ...) #endif +typedef struct sis_85c50x_t { + uint8_t index, + pci_conf[256], pci_conf_sb[256], + regs[256]; -typedef struct sis_85c50x_t -{ - uint8_t index, - pci_conf[256], pci_conf_sb[256], - regs[256]; - - smram_t * smram; - port_92_t * port_92; + smram_t *smram; + port_92_t *port_92; } sis_85c50x_t; - static void sis_85c50x_shadow_recalc(sis_85c50x_t *dev) { uint32_t base, i, can_read, can_write; - can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL; if (!can_read) - can_write = MEM_WRITE_EXTANY; + can_write = MEM_WRITE_EXTANY; mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write); - shadowbios = 1; + shadowbios = 1; shadowbios_write = 1; for (i = 0; i < 4; i++) { - base = 0xe0000 + (i << 14); - mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x54] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); - base = 0xd0000 + (i << 14); - mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x55] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); - base = 0xc0000 + (i << 14); - mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); + base = 0xe0000 + (i << 14); + mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x54] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); + base = 0xd0000 + (i << 14); + mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x55] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); + base = 0xc0000 + (i << 14); + mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY)); } flushmmucache_nopc(); } - static void sis_85c50x_smm_recalc(sis_85c50x_t *dev) { /* NOTE: Naming mismatch - what the datasheet calls "host address" is what we call ram_base. */ - uint32_t ram_base = (dev->pci_conf[0x64] << 20) | - ((dev->pci_conf[0x65] & 0x07) << 28); + uint32_t ram_base = (dev->pci_conf[0x64] << 20) | ((dev->pci_conf[0x65] & 0x07) << 28); smram_disable(dev->smram); if ((((dev->pci_conf[0x65] & 0xe0) >> 5) != 0x00) && (ram_base == 0x00000000)) - return; + return; switch ((dev->pci_conf[0x65] & 0xe0) >> 5) { - case 0x00: - smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); - break; - case 0x01: - smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1); - break; - case 0x02: - smram_enable(dev->smram, 0xa0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1); - break; - case 0x04: - smram_enable(dev->smram, 0xa0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); - break; - case 0x06: - smram_enable(dev->smram, 0xb0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); - break; + case 0x00: + smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); + break; + case 0x01: + smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1); + break; + case 0x02: + smram_enable(dev->smram, 0xa0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1); + break; + case 0x04: + smram_enable(dev->smram, 0xa0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); + break; + case 0x06: + smram_enable(dev->smram, 0xb0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1); + break; } } - static void sis_85c50x_write(int func, int addr, uint8_t val, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; - uint8_t valxor = (val ^ dev->pci_conf[addr]); + sis_85c50x_t *dev = (sis_85c50x_t *) priv; + uint8_t valxor = (val ^ dev->pci_conf[addr]); switch (addr) { - case 0x04: /* Command - low byte */ - dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b); - break; - case 0x07: /* Status - high byte */ - dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06); - break; - case 0x50: - dev->pci_conf[addr] = val; - break; - case 0x51: /* Cache */ - dev->pci_conf[addr] = val; - cpu_cache_ext_enabled = (val & 0x40); - cpu_update_waitstates(); - break; - case 0x52: - dev->pci_conf[addr] = val; - break; - case 0x53: /* Shadow RAM */ - case 0x54: - case 0x55: - case 0x56: - dev->pci_conf[addr] = val; - sis_85c50x_shadow_recalc(dev); - if (addr == 0x54) - sis_85c50x_smm_recalc(dev); - break; - case 0x57: case 0x58: case 0x59: case 0x5a: - case 0x5c: case 0x5d: case 0x5e: case 0x61: - case 0x62: case 0x63: case 0x67: case 0x68: - case 0x6a: case 0x6b: case 0x6c: case 0x6d: - case 0x6e: case 0x6f: - dev->pci_conf[addr] = val; - break; - case 0x5f: - dev->pci_conf[addr] = val & 0xfe; - break; - case 0x5b: - dev->pci_conf[addr] = val; - if (valxor & 0xc0) - port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80)); - break; - case 0x60: /* SMI */ - if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) { - dev->pci_conf[0x69] |= 0x01; - smi_raise(); - } - dev->pci_conf[addr] = val & 0x3e; - break; - case 0x64: /* SMRAM */ - case 0x65: - dev->pci_conf[addr] = val; - sis_85c50x_smm_recalc(dev); - break; - case 0x66: - dev->pci_conf[addr] = (val & 0x7f); - break; - case 0x69: - dev->pci_conf[addr] &= ~(val); - break; + case 0x04: /* Command - low byte */ + dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b); + break; + case 0x07: /* Status - high byte */ + dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06); + break; + case 0x50: + dev->pci_conf[addr] = val; + break; + case 0x51: /* Cache */ + dev->pci_conf[addr] = val; + cpu_cache_ext_enabled = (val & 0x40); + cpu_update_waitstates(); + break; + case 0x52: + dev->pci_conf[addr] = val; + break; + case 0x53: /* Shadow RAM */ + case 0x54: + case 0x55: + case 0x56: + dev->pci_conf[addr] = val; + sis_85c50x_shadow_recalc(dev); + if (addr == 0x54) + sis_85c50x_smm_recalc(dev); + break; + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x61: + case 0x62: + case 0x63: + case 0x67: + case 0x68: + case 0x6a: + case 0x6b: + case 0x6c: + case 0x6d: + case 0x6e: + case 0x6f: + dev->pci_conf[addr] = val; + break; + case 0x5f: + dev->pci_conf[addr] = val & 0xfe; + break; + case 0x5b: + dev->pci_conf[addr] = val; + if (valxor & 0xc0) + port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80)); + break; + case 0x60: /* SMI */ + if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) { + dev->pci_conf[0x69] |= 0x01; + smi_raise(); + } + dev->pci_conf[addr] = val & 0x3e; + break; + case 0x64: /* SMRAM */ + case 0x65: + dev->pci_conf[addr] = val; + sis_85c50x_smm_recalc(dev); + break; + case 0x66: + dev->pci_conf[addr] = (val & 0x7f); + break; + case 0x69: + dev->pci_conf[addr] &= ~(val); + break; } sis_85c50x_log("85C501: dev->pci_conf[%02x] = %02x\n", addr, val); } - static uint8_t sis_85c50x_read(int func, int addr, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; sis_85c50x_log("85C501: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]); return dev->pci_conf[addr]; } - static void sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; switch (addr) { - case 0x04: /* Command */ - dev->pci_conf_sb[addr] = val & 0x0f; - break; - case 0x07: /* Status */ - dev->pci_conf_sb[addr] &= ~(val & 0x30); - break; - case 0x40: /* BIOS Control Register */ - dev->pci_conf_sb[addr] = val & 0x3f; - break; - case 0x41: case 0x42: case 0x43: case 0x44: - /* INTA/B/C/D# Remapping Control Register */ - dev->pci_conf_sb[addr] = val & 0x8f; - if (val & 0x80) - pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED); - else - pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf); - break; - case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ - case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ - case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ - case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ - dev->pci_conf_sb[addr] = val; - break; + case 0x04: /* Command */ + dev->pci_conf_sb[addr] = val & 0x0f; + break; + case 0x07: /* Status */ + dev->pci_conf_sb[addr] &= ~(val & 0x30); + break; + case 0x40: /* BIOS Control Register */ + dev->pci_conf_sb[addr] = val & 0x3f; + break; + case 0x41: + case 0x42: + case 0x43: + case 0x44: + /* INTA/B/C/D# Remapping Control Register */ + dev->pci_conf_sb[addr] = val & 0x8f; + if (val & 0x80) + pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED); + else + pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf); + break; + case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */ + case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */ + case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */ + case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */ + dev->pci_conf_sb[addr] = val; + break; } sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] = %02x\n", addr, val); } - static uint8_t sis_85c50x_sb_read(int func, int addr, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] (%02x)\n", addr, dev->pci_conf_sb[addr]); return dev->pci_conf_sb[addr]; } - static void sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; switch (addr) { - case 0x22: - dev->index = val; - break; + case 0x22: + dev->index = val; + break; - case 0x23: - switch (dev->index) { - case 0x80: - dev->regs[dev->index] = val & 0xe7; - break; - case 0x81: - dev->regs[dev->index] = val & 0xf4; - break; - case 0x84: case 0x88: case 0x9: case 0x8a: - case 0x8b: - dev->regs[dev->index] = val; - break; - case 0x85: - outb(0x70, val); - break; - } - break; + case 0x23: + switch (dev->index) { + case 0x80: + dev->regs[dev->index] = val & 0xe7; + break; + case 0x81: + dev->regs[dev->index] = val & 0xf4; + break; + case 0x84: + case 0x88: + case 0x9: + case 0x8a: + case 0x8b: + dev->regs[dev->index] = val; + break; + case 0x85: + outb(0x70, val); + break; + } + break; } sis_85c50x_log("85C501-ISA: dev->regs[%02x] = %02x\n", addr, val); } - static uint8_t sis_85c50x_isa_read(uint16_t addr, void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; - uint8_t ret = 0xff; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; + uint8_t ret = 0xff; switch (addr) { - case 0x22: - ret = dev->index; - break; + case 0x22: + ret = dev->index; + break; - case 0x23: - if (dev->index == 0x85) - ret = inb(0x70); - else - ret = dev->regs[dev->index]; - break; + case 0x23: + if (dev->index == 0x85) + ret = inb(0x70); + else + ret = dev->regs[dev->index]; + break; } sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, ret); @@ -310,11 +317,10 @@ sis_85c50x_isa_read(uint16_t addr, void *priv) return ret; } - static void sis_85c50x_reset(void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; /* North Bridge (SiS 85C501/502) */ dev->pci_conf[0x00] = 0x39; @@ -358,21 +364,19 @@ sis_85c50x_reset(void *priv) sis_85c50x_write(0, 0x44, 0x80, dev); } - static void sis_85c50x_close(void *priv) { - sis_85c50x_t *dev = (sis_85c50x_t *)priv; + sis_85c50x_t *dev = (sis_85c50x_t *) priv; smram_del(dev->smram); free(dev); } - static void * sis_85c50x_init(const device_t *info) { - sis_85c50x_t *dev = (sis_85c50x_t *)malloc(sizeof(sis_85c50x_t)); + sis_85c50x_t *dev = (sis_85c50x_t *) malloc(sizeof(sis_85c50x_t)); memset(dev, 0x00, sizeof(sis_85c50x_t)); /* 501/502 (Northbridge) */ @@ -382,7 +386,7 @@ sis_85c50x_init(const device_t *info) pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev); io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev); - dev->smram = smram_add(); + dev->smram = smram_add(); dev->port_92 = device_add(&port_92_device); sis_85c50x_reset(dev); @@ -391,15 +395,15 @@ sis_85c50x_init(const device_t *info) } const device_t sis_85c50x_device = { - .name = "SiS 85C50x", + .name = "SiS 85C50x", .internal_name = "sis_85c50x", - .flags = DEVICE_PCI, - .local = 0, - .init = sis_85c50x_init, - .close = sis_85c50x_close, - .reset = sis_85c50x_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = sis_85c50x_init, + .close = sis_85c50x_close, + .reset = sis_85c50x_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/stpc.c b/src/chipset/stpc.c index f9bd8faff..b36010699 100644 --- a/src/chipset/stpc.c +++ b/src/chipset/stpc.c @@ -38,122 +38,113 @@ #include <86box/lpt.h> #include <86box/chipset.h> +#define STPC_CONSUMER2 0x104a020b +#define STPC_ATLAS 0x104a0210 +#define STPC_ELITE 0x104a021a +#define STPC_CLIENT 0x100e55cc -#define STPC_CONSUMER2 0x104a020b -#define STPC_ATLAS 0x104a0210 -#define STPC_ELITE 0x104a021a -#define STPC_CLIENT 0x100e55cc - - -typedef struct stpc_t -{ - uint32_t local; +typedef struct stpc_t { + uint32_t local; /* Main registers (port 22h/23h) */ - uint8_t reg_offset; - uint8_t regs[256]; + uint8_t reg_offset; + uint8_t regs[256]; /* Host bus interface */ - uint16_t host_base; - uint8_t host_offset; - uint8_t host_regs[256]; + uint16_t host_base; + uint8_t host_offset; + uint8_t host_regs[256]; /* Local bus */ - uint16_t localbus_base; - uint8_t localbus_offset; - uint8_t localbus_regs[256]; + uint16_t localbus_base; + uint8_t localbus_offset; + uint8_t localbus_regs[256]; /* PCI devices */ - uint8_t pci_conf[4][256]; - smram_t *smram; - usb_t *usb; - int ide_slot; - sff8038i_t *bm[2]; + uint8_t pci_conf[4][256]; + smram_t *smram; + usb_t *usb; + int ide_slot; + sff8038i_t *bm[2]; } stpc_t; -typedef struct stpc_serial_t -{ - serial_t *uart[2]; +typedef struct stpc_serial_t { + serial_t *uart[2]; } stpc_serial_t; -typedef struct stpc_lpt_t -{ - uint8_t unlocked; - uint8_t offset; - uint8_t reg1; - uint8_t reg4; +typedef struct stpc_lpt_t { + uint8_t unlocked; + uint8_t offset; + uint8_t reg1; + uint8_t reg4; } stpc_lpt_t; - #ifdef ENABLE_STPC_LOG int stpc_do_log = ENABLE_STPC_LOG; - static void stpc_log(const char *fmt, ...) { va_list ap; if (stpc_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define stpc_log(fmt, ...) +# define stpc_log(fmt, ...) #endif - static void stpc_recalcmapping(stpc_t *dev) { - uint8_t reg, bitpair; + uint8_t reg, bitpair; uint32_t base, size; - int state; + int state; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; for (reg = 0; reg <= 3; reg++) { - for (bitpair = 0; bitpair <= ((reg == 3) ? 0 : 3); bitpair++) { - if (reg == 3) { - size = 0x10000; - base = 0xf0000; - } else { - size = 0x4000; - base = 0xc0000 + (size * ((reg * 4) + bitpair)); - } - stpc_log("STPC: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1)); + for (bitpair = 0; bitpair <= ((reg == 3) ? 0 : 3); bitpair++) { + if (reg == 3) { + size = 0x10000; + base = 0xf0000; + } else { + size = 0x4000; + base = 0xc0000 + (size * ((reg * 4) + bitpair)); + } + stpc_log("STPC: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1)); - state = 0; - if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) { - stpc_log(" w on"); - state |= MEM_WRITE_INTERNAL; - if (base >= 0xe0000) - shadowbios_write |= 1; - } else { - stpc_log(" w off"); - state |= MEM_WRITE_EXTANY; - } - if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) { - stpc_log("; r on\n"); - state |= MEM_READ_INTERNAL; - if (base >= 0xe0000) - shadowbios |= 1; - } else { - stpc_log("; r off\n"); - state |= MEM_READ_EXTANY; - } + state = 0; + if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) { + stpc_log(" w on"); + state |= MEM_WRITE_INTERNAL; + if (base >= 0xe0000) + shadowbios_write |= 1; + } else { + stpc_log(" w off"); + state |= MEM_WRITE_EXTANY; + } + if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) { + stpc_log("; r on\n"); + state |= MEM_READ_INTERNAL; + if (base >= 0xe0000) + shadowbios |= 1; + } else { + stpc_log("; r off\n"); + state |= MEM_READ_EXTANY; + } - mem_set_mem_state(base, size, state); - } + mem_set_mem_state(base, size, state); + } } flushmmucache_nopc(); } - static void stpc_host_write(uint16_t addr, uint8_t val, void *priv) { @@ -162,12 +153,11 @@ stpc_host_write(uint16_t addr, uint8_t val, void *priv) stpc_log("STPC: host_write(%04X, %02X)\n", addr, val); if (addr == dev->host_base) - dev->host_offset = val; + dev->host_offset = val; else if (addr == (dev->host_base + 4)) - dev->host_regs[dev->host_offset] = val; + dev->host_regs[dev->host_offset] = val; } - static uint8_t stpc_host_read(uint16_t addr, void *priv) { @@ -175,17 +165,16 @@ stpc_host_read(uint16_t addr, void *priv) uint8_t ret; if (addr == dev->host_base) - ret = dev->host_offset; + ret = dev->host_offset; else if (addr == (dev->host_base + 4)) - ret = dev->host_regs[dev->host_offset]; + ret = dev->host_regs[dev->host_offset]; else - ret = 0xff; + ret = 0xff; stpc_log("STPC: host_read(%04X) = %02X\n", addr, ret); return ret; } - static void stpc_localbus_write(uint16_t addr, uint8_t val, void *priv) { @@ -194,12 +183,11 @@ stpc_localbus_write(uint16_t addr, uint8_t val, void *priv) stpc_log("STPC: localbus_write(%04X, %02X)\n", addr, val); if (addr == dev->localbus_base) - dev->localbus_offset = val; + dev->localbus_offset = val; else if (addr == (dev->localbus_base + 4)) - dev->localbus_regs[addr] = val; + dev->localbus_regs[addr] = val; } - static uint8_t stpc_localbus_read(uint16_t addr, void *priv) { @@ -207,17 +195,16 @@ stpc_localbus_read(uint16_t addr, void *priv) uint8_t ret; if (addr == dev->localbus_base) - ret = dev->localbus_offset; + ret = dev->localbus_offset; else if (addr == (dev->localbus_base + 4)) - ret = dev->localbus_regs[dev->localbus_offset]; + ret = dev->localbus_regs[dev->localbus_offset]; else - ret = 0xff; + ret = 0xff; stpc_log("STPC: localbus_read(%04X) = %02X\n", addr, ret); return ret; } - static void stpc_nb_write(int func, int addr, uint8_t val, void *priv) { @@ -226,32 +213,42 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv) stpc_log("STPC: nb_write(%d, %02X, %02X)\n", func, addr, val); if (func > 0) - return; + return; switch (addr) { - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x04: case 0x06: case 0x07: case 0x08: - case 0x09: case 0x0a: case 0x0b: case 0x0e: - case 0x51: case 0x53: case 0x54: - return; + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0e: + case 0x51: + case 0x53: + case 0x54: + return; - case 0x05: - val &= 0x01; - break; + case 0x05: + val &= 0x01; + break; - case 0x50: - val &= 0x1f; - break; + case 0x50: + val &= 0x1f; + break; - case 0x52: - val &= 0x70; - break; + case 0x52: + val &= 0x70; + break; } dev->pci_conf[0][addr] = val; } - static uint8_t stpc_nb_read(int func, int addr, void *priv) { @@ -259,68 +256,66 @@ stpc_nb_read(int func, int addr, void *priv) uint8_t ret; if (func > 0) - ret = 0xff; + ret = 0xff; else - ret = dev->pci_conf[0][addr]; + ret = dev->pci_conf[0][addr]; stpc_log("STPC: nb_read(%d, %02X) = %02X\n", func, addr, ret); return ret; } - static void stpc_ide_handlers(stpc_t *dev, int bus) { uint16_t main, side; if (bus & 0x01) { - ide_pri_disable(); + ide_pri_disable(); - if (dev->pci_conf[2][0x09] & 0x01) { - main = (dev->pci_conf[2][0x11] << 8) | (dev->pci_conf[2][0x10] & 0xf8); - side = ((dev->pci_conf[2][0x15] << 8) | (dev->pci_conf[2][0x14] & 0xfc)) + 2; - } else { - main = 0x1f0; - side = 0x3f6; - } + if (dev->pci_conf[2][0x09] & 0x01) { + main = (dev->pci_conf[2][0x11] << 8) | (dev->pci_conf[2][0x10] & 0xf8); + side = ((dev->pci_conf[2][0x15] << 8) | (dev->pci_conf[2][0x14] & 0xfc)) + 2; + } else { + main = 0x1f0; + side = 0x3f6; + } - ide_set_base(0, main); - ide_set_side(0, side); + ide_set_base(0, main); + ide_set_side(0, side); - stpc_log("STPC: IDE primary main %04X side %04X enable ", main, side); - if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x04)) { - stpc_log("1\n"); - ide_pri_enable(); - } else { - stpc_log("0\n"); - } + stpc_log("STPC: IDE primary main %04X side %04X enable ", main, side); + if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x04)) { + stpc_log("1\n"); + ide_pri_enable(); + } else { + stpc_log("0\n"); + } } if (bus & 0x02) { - ide_sec_disable(); + ide_sec_disable(); - if (dev->pci_conf[2][0x09] & 0x04) { - main = (dev->pci_conf[2][0x19] << 8) | (dev->pci_conf[2][0x18] & 0xf8); - side = ((dev->pci_conf[2][0x1d] << 8) | (dev->pci_conf[2][0x1c] & 0xfc)) + 2; - } else { - main = 0x170; - side = 0x376; - } + if (dev->pci_conf[2][0x09] & 0x04) { + main = (dev->pci_conf[2][0x19] << 8) | (dev->pci_conf[2][0x18] & 0xf8); + side = ((dev->pci_conf[2][0x1d] << 8) | (dev->pci_conf[2][0x1c] & 0xfc)) + 2; + } else { + main = 0x170; + side = 0x376; + } - ide_set_base(1, main); - ide_set_side(1, side); + ide_set_base(1, main); + ide_set_side(1, side); - stpc_log("STPC: IDE secondary main %04X side %04X enable ", main, side); - if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x08)) { - stpc_log("1\n"); - ide_sec_enable(); - } else { - stpc_log("0\n"); - } + stpc_log("STPC: IDE secondary main %04X side %04X enable ", main, side); + if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x08)) { + stpc_log("1\n"); + ide_sec_enable(); + } else { + stpc_log("0\n"); + } } } - static void stpc_ide_bm_handlers(stpc_t *dev) { @@ -330,7 +325,6 @@ stpc_ide_bm_handlers(stpc_t *dev) sff_bus_master_handler(dev->bm[1], dev->pci_conf[2][0x04] & 1, base + 8); } - static void stpc_ide_write(int func, int addr, uint8_t val, void *priv) { @@ -339,98 +333,103 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv) stpc_log("STPC: ide_write(%d, %02X, %02X)\n", func, addr, val); if (func > 0) - return; + return; switch (addr) { - case 0x04: - dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0xbe) | (val & 0x41); - stpc_ide_handlers(dev, 0x03); - stpc_ide_bm_handlers(dev); - break; + case 0x04: + dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0xbe) | (val & 0x41); + stpc_ide_handlers(dev, 0x03); + stpc_ide_bm_handlers(dev); + break; - case 0x05: - dev->pci_conf[2][addr] = val & 0x01; - break; + case 0x05: + dev->pci_conf[2][addr] = val & 0x01; + break; - case 0x07: - dev->pci_conf[2][addr] &= ~(val & 0x70); - break; + case 0x07: + dev->pci_conf[2][addr] &= ~(val & 0x70); + break; - case 0x09: - dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0x8a) | (val & 0x05); - stpc_ide_handlers(dev, 0x03); - break; + case 0x09: + dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0x8a) | (val & 0x05); + stpc_ide_handlers(dev, 0x03); + break; - case 0x10: - dev->pci_conf[2][addr] = (val & 0xf8) | 1; - stpc_ide_handlers(dev, 0x01); - break; - case 0x11: - dev->pci_conf[2][addr] = val; - stpc_ide_handlers(dev, 0x01); - break; + case 0x10: + dev->pci_conf[2][addr] = (val & 0xf8) | 1; + stpc_ide_handlers(dev, 0x01); + break; + case 0x11: + dev->pci_conf[2][addr] = val; + stpc_ide_handlers(dev, 0x01); + break; - case 0x14: - dev->pci_conf[2][addr] = (val & 0xfc) | 1; - stpc_ide_handlers(dev, 0x01); - break; - case 0x15: - dev->pci_conf[2][addr] = val; - stpc_ide_handlers(dev, 0x01); - break; + case 0x14: + dev->pci_conf[2][addr] = (val & 0xfc) | 1; + stpc_ide_handlers(dev, 0x01); + break; + case 0x15: + dev->pci_conf[2][addr] = val; + stpc_ide_handlers(dev, 0x01); + break; - case 0x18: - dev->pci_conf[2][addr] = (val & 0xf8) | 1; - stpc_ide_handlers(dev, 0x02); - break; - case 0x19: - dev->pci_conf[2][addr] = val; - stpc_ide_handlers(dev, 0x02); - break; + case 0x18: + dev->pci_conf[2][addr] = (val & 0xf8) | 1; + stpc_ide_handlers(dev, 0x02); + break; + case 0x19: + dev->pci_conf[2][addr] = val; + stpc_ide_handlers(dev, 0x02); + break; - case 0x1c: - dev->pci_conf[2][addr] = (val & 0xfc) | 1; - stpc_ide_handlers(dev, 0x02); - break; - case 0x1d: - dev->pci_conf[2][addr] = val; - stpc_ide_handlers(dev, 0x02); - break; + case 0x1c: + dev->pci_conf[2][addr] = (val & 0xfc) | 1; + stpc_ide_handlers(dev, 0x02); + break; + case 0x1d: + dev->pci_conf[2][addr] = val; + stpc_ide_handlers(dev, 0x02); + break; - case 0x20: - dev->pci_conf[2][0x20] = (val & 0xf0) | 1; - stpc_ide_bm_handlers(dev); - break; - case 0x21: - dev->pci_conf[2][0x21] = val; - stpc_ide_bm_handlers(dev); - break; + case 0x20: + dev->pci_conf[2][0x20] = (val & 0xf0) | 1; + stpc_ide_bm_handlers(dev); + break; + case 0x21: + dev->pci_conf[2][0x21] = val; + stpc_ide_bm_handlers(dev); + break; - case 0x3c: - dev->pci_conf[2][addr] = val; - break; + case 0x3c: + dev->pci_conf[2][addr] = val; + break; - case 0x40: case 0x41: case 0x42: case 0x43: - case 0x44: case 0x45: case 0x46: case 0x47: - dev->pci_conf[2][addr] = val; - break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + dev->pci_conf[2][addr] = val; + break; - case 0x48: - dev->pci_conf[2][addr] = (val & 0x8c) & ~(val & 0x03); - stpc_ide_handlers(dev, 0x03); - if (val & 0x02) { - sff_bus_master_set_irq(0x01, dev->bm[0]); - sff_bus_master_set_irq(0x01, dev->bm[1]); - } - if (val & 0x01) { - sff_bus_master_set_irq(0x00, dev->bm[0]); - sff_bus_master_set_irq(0x00, dev->bm[1]); - } - break; + case 0x48: + dev->pci_conf[2][addr] = (val & 0x8c) & ~(val & 0x03); + stpc_ide_handlers(dev, 0x03); + if (val & 0x02) { + sff_bus_master_set_irq(0x01, dev->bm[0]); + sff_bus_master_set_irq(0x01, dev->bm[1]); + } + if (val & 0x01) { + sff_bus_master_set_irq(0x00, dev->bm[0]); + sff_bus_master_set_irq(0x00, dev->bm[1]); + } + break; } } - static uint8_t stpc_ide_read(int func, int addr, void *priv) { @@ -438,51 +437,58 @@ stpc_ide_read(int func, int addr, void *priv) uint8_t ret; if (func > 0) - ret = 0xff; + ret = 0xff; else { - ret = dev->pci_conf[2][addr]; - if (addr == 0x48) { - ret &= 0xfc; - ret |= !!(dev->bm[0]->status & 0x04); - ret |= (!!(dev->bm[1]->status & 0x04)) << 1; - } + ret = dev->pci_conf[2][addr]; + if (addr == 0x48) { + ret &= 0xfc; + ret |= !!(dev->bm[0]->status & 0x04); + ret |= (!!(dev->bm[1]->status & 0x04)) << 1; + } } stpc_log("STPC: ide_read(%d, %02X) = %02X\n", func, addr, ret); return ret; } - static void stpc_isab_write(int func, int addr, uint8_t val, void *priv) { stpc_t *dev = (stpc_t *) priv; if ((func == 1) && (dev->local != STPC_ATLAS)) { - stpc_ide_write(0, addr, val, priv); - return; + stpc_ide_write(0, addr, val, priv); + return; } stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val); if (func > 0) - return; + return; switch (addr) { - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x04: case 0x06: case 0x07: case 0x08: - case 0x09: case 0x0a: case 0x0b: case 0x0e: - return; + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0e: + return; - case 0x05: - val &= 0x01; - break; + case 0x05: + val &= 0x01; + break; } dev->pci_conf[1][addr] = val; } - static uint8_t stpc_isab_read(int func, int addr, void *priv) { @@ -490,17 +496,16 @@ stpc_isab_read(int func, int addr, void *priv) uint8_t ret; if ((func == 1) && (dev->local != STPC_ATLAS)) - ret = stpc_ide_read(0, addr, priv); + ret = stpc_ide_read(0, addr, priv); else if (func > 0) - ret = 0xff; + ret = 0xff; else - ret = dev->pci_conf[1][addr]; + ret = dev->pci_conf[1][addr]; stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret); return ret; } - static void stpc_usb_write(int func, int addr, uint8_t val, void *priv) { @@ -509,34 +514,43 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv) stpc_log("STPC: usb_write(%d, %02X, %02X)\n", func, addr, val); if (func > 0) - return; + return; switch (addr) { - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x04: case 0x06: case 0x07: case 0x08: - case 0x09: case 0x0a: case 0x0b: case 0x0e: - case 0x10: - return; + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0e: + case 0x10: + return; - case 0x05: - val &= 0x01; - break; + case 0x05: + val &= 0x01; + break; - case 0x11: - dev->pci_conf[3][addr] = val & 0xf0; - ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); - break; + case 0x11: + dev->pci_conf[3][addr] = val & 0xf0; + ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); + break; - case 0x12: case 0x13: - dev->pci_conf[3][addr] = val; - ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); - break; + case 0x12: + case 0x13: + dev->pci_conf[3][addr] = val; + ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); + break; } dev->pci_conf[3][addr] = val; } - static uint8_t stpc_usb_read(int func, int addr, void *priv) { @@ -544,77 +558,74 @@ stpc_usb_read(int func, int addr, void *priv) uint8_t ret; if (func > 0) - ret = 0xff; + ret = 0xff; else - ret = dev->pci_conf[3][addr]; + ret = dev->pci_conf[3][addr]; stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret); return ret; } - static void stpc_remap_host(stpc_t *dev, uint16_t host_base) { stpc_log("STPC: Remapping host bus from %04X to %04X\n", dev->host_base, host_base); io_removehandler(dev->host_base, 5, - stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); + stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); if (host_base) { - io_sethandler(host_base, 5, - stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); + io_sethandler(host_base, 5, + stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); } dev->host_base = host_base; } - static void stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base) { stpc_log("STPC: Remapping local bus from %04X to %04X\n", dev->localbus_base, localbus_base); io_removehandler(dev->localbus_base, 5, - stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); + stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); if (localbus_base) { - io_sethandler(localbus_base, 5, - stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); + io_sethandler(localbus_base, 5, + stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); } dev->localbus_base = localbus_base; } - static uint8_t stpc_serial_handlers(uint8_t val) { stpc_serial_t *dev = device_get_priv(&stpc_serial_device); if (!dev) { - stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val); - return 0; + stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val); + return 0; } uint16_t uart0_io = 0x3f8, uart1_io = 0x3f8; - uint8_t uart0_irq = 4, uart1_irq = 3; + uint8_t uart0_irq = 4, uart1_irq = 3; if (val & 0x10) - uart1_io &= 0xfeff; + uart1_io &= 0xfeff; if (val & 0x20) - uart1_io &= 0xffef; + uart1_io &= 0xffef; if (val & 0x40) - uart0_io &= 0xfeff; + uart0_io &= 0xfeff; if (val & 0x80) - uart0_io &= 0xffef; + uart0_io &= 0xffef; if (uart0_io == uart1_io) { - /* Apply defaults if both UARTs are set to the same address. */ - stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io); - uart0_io = 0x3f8; - uart1_io = 0x2f8; + /* Apply defaults if both UARTs are set to the same address. */ + stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io); + uart0_io = 0x3f8; + uart1_io = 0x2f8; } if (!(uart0_io & 0x100)) { - /* The address for UART0 establishes the IRQs for both ports. */ - uart0_irq = 3; - uart1_irq = 4; + /* The address for UART0 establishes the IRQs for both ports. */ + uart0_irq = 3; + uart1_irq = 4; } stpc_log("STPC: Remapping UART0 to %04X %d and UART1 to %04X %d (raw %02X)\n", uart0_io, uart0_irq, uart1_io, uart1_irq, val); @@ -627,7 +638,6 @@ stpc_serial_handlers(uint8_t val) return 1; } - static void stpc_reg_write(uint16_t addr, uint8_t val, void *priv) { @@ -636,73 +646,79 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv) stpc_log("STPC: reg_write(%04X, %02X)\n", addr, val); if (addr == 0x22) { - dev->reg_offset = val; + dev->reg_offset = val; } else { - stpc_log("STPC: regs[%02X] = %02X\n", dev->reg_offset, val); + stpc_log("STPC: regs[%02X] = %02X\n", dev->reg_offset, val); - switch (dev->reg_offset) { - case 0x12: - if (dev->regs[0x10] == 0x07) - stpc_remap_host(dev, (dev->host_base & 0xff00) | val); - else if (dev->regs[0x10] == 0x06) - stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val); - break; + switch (dev->reg_offset) { + case 0x12: + if (dev->regs[0x10] == 0x07) + stpc_remap_host(dev, (dev->host_base & 0xff00) | val); + else if (dev->regs[0x10] == 0x06) + stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val); + break; - case 0x13: - if (dev->regs[0x10] == 0x07) - stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8)); - else if (dev->regs[0x10] == 0x06) - stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8)); - break; + case 0x13: + if (dev->regs[0x10] == 0x07) + stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8)); + else if (dev->regs[0x10] == 0x06) + stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8)); + break; - case 0x21: - val &= 0xfe; - break; + case 0x21: + val &= 0xfe; + break; - case 0x22: - val &= 0x7f; - break; + case 0x22: + val &= 0x7f; + break; - case 0x25: case 0x26: case 0x27: case 0x28: - if (dev->reg_offset == 0x28) { - val &= 0xe3; - smram_state_change(dev->smram, 0, !!(val & 0x80)); - } - dev->regs[dev->reg_offset] = val; - stpc_recalcmapping(dev); - break; + case 0x25: + case 0x26: + case 0x27: + case 0x28: + if (dev->reg_offset == 0x28) { + val &= 0xe3; + smram_state_change(dev->smram, 0, !!(val & 0x80)); + } + dev->regs[dev->reg_offset] = val; + stpc_recalcmapping(dev); + break; - case 0x29: - val &= 0x0f; - break; + case 0x29: + val &= 0x0f; + break; - case 0x36: - val &= 0x3f; - break; + case 0x36: + val &= 0x3f; + break; - case 0x52: case 0x53: case 0x54: case 0x55: - stpc_log("STPC: Set IRQ routing: INT %c -> %d\n", 0x41 + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : -1); - val &= 0x8f; - pci_set_irq_routing(PCI_INTA + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : PCI_IRQ_DISABLED); - break; + case 0x52: + case 0x53: + case 0x54: + case 0x55: + stpc_log("STPC: Set IRQ routing: INT %c -> %d\n", 0x41 + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : -1); + val &= 0x8f; + pci_set_irq_routing(PCI_INTA + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : PCI_IRQ_DISABLED); + break; - case 0x56: case 0x57: - pic_elcr_write(dev->reg_offset, val, (dev->reg_offset & 1) ? &pic2 : &pic); - if (dev->reg_offset == 0x57) - refresh_at_enable = (val & 0x01); - break; + case 0x56: + case 0x57: + pic_elcr_write(dev->reg_offset, val, (dev->reg_offset & 1) ? &pic2 : &pic); + if (dev->reg_offset == 0x57) + refresh_at_enable = (val & 0x01); + break; - case 0x59: - val &= 0xf1; - stpc_serial_handlers(val); - break; - } + case 0x59: + val &= 0xf1; + stpc_serial_handlers(val); + break; + } - dev->regs[dev->reg_offset] = val; + dev->regs[dev->reg_offset] = val; } } - static uint8_t stpc_reg_read(uint16_t addr, void *priv) { @@ -710,22 +726,21 @@ stpc_reg_read(uint16_t addr, void *priv) uint8_t ret; if (addr == 0x22) - ret = dev->reg_offset; + ret = dev->reg_offset; else if (dev->reg_offset >= 0xc0) - return 0xff; /* let the CPU code handle Cyrix CPU registers */ + return 0xff; /* let the CPU code handle Cyrix CPU registers */ else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) { - /* ELCR registers. */ - ret = pic_elcr_read(dev->reg_offset, (dev->reg_offset & 1) ? &pic2 : &pic); - if (dev->reg_offset == 0x57) - ret |= (dev->regs[dev->reg_offset] & 0x01); + /* ELCR registers. */ + ret = pic_elcr_read(dev->reg_offset, (dev->reg_offset & 1) ? &pic2 : &pic); + if (dev->reg_offset == 0x57) + ret |= (dev->regs[dev->reg_offset] & 0x01); } else - ret = dev->regs[dev->reg_offset]; + ret = dev->regs[dev->reg_offset]; stpc_log("STPC: reg_read(%04X) = %02X\n", dev->reg_offset, ret); return ret; } - static void stpc_reset(void *priv) { @@ -736,12 +751,11 @@ stpc_reset(void *priv) memset(dev->regs, 0, sizeof(dev->regs)); dev->regs[0x7b] = 0xff; if (device_get_priv(&stpc_lpt_device)) - dev->regs[0x4c] |= 0x80; /* LPT strap */ + dev->regs[0x4c] |= 0x80; /* LPT strap */ if (stpc_serial_handlers(0x00)) - dev->regs[0x4c] |= 0x03; /* UART straps */ + dev->regs[0x4c] |= 0x03; /* UART straps */ } - static void stpc_setup(stpc_t *dev) { @@ -749,19 +763,19 @@ stpc_setup(stpc_t *dev) /* Main register interface */ io_sethandler(0x22, 2, - stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev); + stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev); /* Northbridge */ if (dev->local & STPC_CLIENT) { - dev->pci_conf[0][0x00] = 0x0e; - dev->pci_conf[0][0x01] = 0x10; - dev->pci_conf[0][0x02] = 0x64; - dev->pci_conf[0][0x03] = 0x05; + dev->pci_conf[0][0x00] = 0x0e; + dev->pci_conf[0][0x01] = 0x10; + dev->pci_conf[0][0x02] = 0x64; + dev->pci_conf[0][0x03] = 0x05; } else { - dev->pci_conf[0][0x00] = 0x4a; - dev->pci_conf[0][0x01] = 0x10; - dev->pci_conf[0][0x02] = 0x0a; - dev->pci_conf[0][0x03] = 0x02; + dev->pci_conf[0][0x00] = 0x4a; + dev->pci_conf[0][0x01] = 0x10; + dev->pci_conf[0][0x02] = 0x0a; + dev->pci_conf[0][0x03] = 0x02; } dev->pci_conf[0][0x04] = 0x07; @@ -786,8 +800,8 @@ stpc_setup(stpc_t *dev) dev->pci_conf[1][0x0b] = 0x06; /* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other - STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual - indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ + STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual + indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ dev->pci_conf[1][0x0e] = /*0x40*/ 0x80; /* IDE */ @@ -795,11 +809,11 @@ stpc_setup(stpc_t *dev) dev->pci_conf[2][0x01] = dev->local >> 24; if (dev->local == STPC_ATLAS) { - dev->pci_conf[2][0x02] = 0x28; - dev->pci_conf[2][0x03] = 0x02; + dev->pci_conf[2][0x02] = 0x28; + dev->pci_conf[2][0x03] = 0x02; } else { - dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02]; - dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03]; + dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02]; + dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03]; } dev->pci_conf[2][0x06] = 0x80; @@ -810,8 +824,8 @@ stpc_setup(stpc_t *dev) dev->pci_conf[2][0x0b] = 0x01; /* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other - STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual - indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ + STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual + indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ dev->pci_conf[2][0x0e] = /*0x40*/ 0x80; dev->pci_conf[2][0x10] = 0x01; @@ -831,22 +845,22 @@ stpc_setup(stpc_t *dev) /* USB */ if (dev->usb) { - dev->pci_conf[3][0x00] = dev->local >> 16; - dev->pci_conf[3][0x01] = dev->local >> 24; - dev->pci_conf[3][0x02] = 0x30; - dev->pci_conf[3][0x03] = 0x02; + dev->pci_conf[3][0x00] = dev->local >> 16; + dev->pci_conf[3][0x01] = dev->local >> 24; + dev->pci_conf[3][0x02] = 0x30; + dev->pci_conf[3][0x03] = 0x02; - dev->pci_conf[3][0x06] = 0x80; - dev->pci_conf[3][0x07] = 0x02; + dev->pci_conf[3][0x06] = 0x80; + dev->pci_conf[3][0x07] = 0x02; - dev->pci_conf[3][0x09] = 0x10; - dev->pci_conf[3][0x0a] = 0x03; - dev->pci_conf[3][0x0b] = 0x0c; + dev->pci_conf[3][0x09] = 0x10; + dev->pci_conf[3][0x0a] = 0x03; + dev->pci_conf[3][0x0b] = 0x0c; - /* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other - STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual - indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ - dev->pci_conf[3][0x0e] = /*0x40*/ 0x80; + /* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other + STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual + indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */ + dev->pci_conf[3][0x0e] = /*0x40*/ 0x80; } /* PCI setup */ @@ -856,7 +870,6 @@ stpc_setup(stpc_t *dev) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); } - static void stpc_close(void *priv) { @@ -869,7 +882,6 @@ stpc_close(void *priv) free(dev); } - static void * stpc_init(const device_t *info) { @@ -883,9 +895,9 @@ stpc_init(const device_t *info) pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev); dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev); if (dev->local == STPC_ATLAS) { - dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_ide_read, stpc_ide_write, dev); - dev->usb = device_add(&usb_device); - pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_usb_read, stpc_usb_write, dev); + dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_ide_read, stpc_ide_write, dev); + dev->usb = device_add(&usb_device); + pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_usb_read, stpc_usb_write, dev); } dev->bm[0] = device_add_inst(&sff8038i_device, 1); @@ -912,7 +924,6 @@ stpc_init(const device_t *info) return dev; } - static void stpc_serial_close(void *priv) { @@ -923,7 +934,6 @@ stpc_serial_close(void *priv) free(dev); } - static void * stpc_serial_init(const device_t *info) { @@ -940,45 +950,44 @@ stpc_serial_init(const device_t *info) return dev; } - static void stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val) { uint8_t old_addr = (dev->reg1 & 0x03), new_addr = (val & 0x03); switch (old_addr) { - case 0x1: - lpt3_remove(); - break; + case 0x1: + lpt3_remove(); + break; - case 0x2: - lpt1_remove(); - break; + case 0x2: + lpt1_remove(); + break; - case 0x3: - lpt2_remove(); - break; + case 0x3: + lpt2_remove(); + break; } switch (new_addr) { - case 0x1: - stpc_log("STPC: Remapping parallel port to LPT3\n"); - lpt3_init(0x3bc); - break; + case 0x1: + stpc_log("STPC: Remapping parallel port to LPT3\n"); + lpt3_init(0x3bc); + break; - case 0x2: - stpc_log("STPC: Remapping parallel port to LPT1\n"); - lpt1_init(0x378); - break; + case 0x2: + stpc_log("STPC: Remapping parallel port to LPT1\n"); + lpt1_init(0x378); + break; - case 0x3: - stpc_log("STPC: Remapping parallel port to LPT2\n"); - lpt2_init(0x278); - break; + case 0x3: + stpc_log("STPC: Remapping parallel port to LPT2\n"); + lpt2_init(0x278); + break; - default: - stpc_log("STPC: Disabling parallel port\n"); - break; + default: + stpc_log("STPC: Disabling parallel port\n"); + break; } dev->reg1 = (val & 0x08); @@ -986,33 +995,31 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val) dev->reg1 |= 0x84; /* reserved bits that default to 1; hardwired? */ } - static void stpc_lpt_write(uint16_t addr, uint8_t val, void *priv) { stpc_lpt_t *dev = (stpc_lpt_t *) priv; if (dev->unlocked < 2) { - /* Cheat a little bit: in reality, any write to any - I/O port is supposed to reset the unlock counter. */ - if ((addr == 0x3f0) && (val == 0x55)) - dev->unlocked++; - else - dev->unlocked = 0; + /* Cheat a little bit: in reality, any write to any + I/O port is supposed to reset the unlock counter. */ + if ((addr == 0x3f0) && (val == 0x55)) + dev->unlocked++; + else + dev->unlocked = 0; } else if (addr == 0x3f0) { - if (val == 0xaa) - dev->unlocked = 0; - else - dev->offset = val; + if (val == 0xaa) + dev->unlocked = 0; + else + dev->offset = val; } else if (dev->offset == 1) { - /* dev->reg1 is set by stpc_lpt_handlers */ - stpc_lpt_handlers(dev, val); + /* dev->reg1 is set by stpc_lpt_handlers */ + stpc_lpt_handlers(dev, val); } else if (dev->offset == 4) { - dev->reg4 = (val & 0x03); + dev->reg4 = (val & 0x03); } } - static void stpc_lpt_reset(void *priv) { @@ -1021,13 +1028,12 @@ stpc_lpt_reset(void *priv) stpc_log("STPC: lpt_reset()\n"); dev->unlocked = 0; - dev->offset = 0x00; - dev->reg1 = 0x9f; - dev->reg4 = 0x00; + dev->offset = 0x00; + dev->reg1 = 0x9f; + dev->reg4 = 0x00; stpc_lpt_handlers(dev, dev->reg1); } - static void stpc_lpt_close(void *priv) { @@ -1038,7 +1044,6 @@ stpc_lpt_close(void *priv) free(dev); } - static void * stpc_lpt_init(const device_t *info) { @@ -1050,93 +1055,93 @@ stpc_lpt_init(const device_t *info) stpc_lpt_reset(dev); io_sethandler(0x3f0, 2, - NULL, NULL, NULL, stpc_lpt_write, NULL, NULL, dev); + NULL, NULL, NULL, stpc_lpt_write, NULL, NULL, dev); return dev; } /* STPC SoCs */ const device_t stpc_client_device = { - .name = "STPC Client", + .name = "STPC Client", .internal_name = "stpc_client", - .flags = DEVICE_PCI, - .local = STPC_CLIENT, - .init = stpc_init, - .close = stpc_close, - .reset = stpc_reset, + .flags = DEVICE_PCI, + .local = STPC_CLIENT, + .init = stpc_init, + .close = stpc_close, + .reset = stpc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t stpc_consumer2_device = { - .name = "STPC Consumer-II", + .name = "STPC Consumer-II", .internal_name = "stpc_consumer2", - .flags = DEVICE_PCI, - .local = STPC_CONSUMER2, - .init = stpc_init, - .close = stpc_close, - .reset = stpc_reset, + .flags = DEVICE_PCI, + .local = STPC_CONSUMER2, + .init = stpc_init, + .close = stpc_close, + .reset = stpc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t stpc_elite_device = { - .name = "STPC Elite", + .name = "STPC Elite", .internal_name = "stpc_elite", - .flags = DEVICE_PCI, - .local = STPC_ELITE, - .init = stpc_init, - .close = stpc_close, - .reset = stpc_reset, + .flags = DEVICE_PCI, + .local = STPC_ELITE, + .init = stpc_init, + .close = stpc_close, + .reset = stpc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t stpc_atlas_device = { - .name = "STPC Atlas", + .name = "STPC Atlas", .internal_name = "stpc_atlas", - .flags = DEVICE_PCI, - .local = STPC_ATLAS, - .init = stpc_init, - .close = stpc_close, - .reset = stpc_reset, + .flags = DEVICE_PCI, + .local = STPC_ATLAS, + .init = stpc_init, + .close = stpc_close, + .reset = stpc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; /* Auxiliary devices */ const device_t stpc_serial_device = { - .name = "STPC Serial UARTs", + .name = "STPC Serial UARTs", .internal_name = "stpc_serial", - .flags = 0, - .local = 0, - .init = stpc_serial_init, - .close = stpc_serial_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = stpc_serial_init, + .close = stpc_serial_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t stpc_lpt_device = { - .name = "STPC Parallel Port", + .name = "STPC Parallel Port", .internal_name = "stpc_lpt", - .flags = 0, - .local = 0, - .init = stpc_lpt_init, - .close = stpc_lpt_close, - .reset = stpc_lpt_reset, + .flags = 0, + .local = 0, + .init = stpc_lpt_init, + .close = stpc_lpt_close, + .reset = stpc_lpt_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/umc_8886.c b/src/chipset/umc_8886.c index ba11ba829..47501dfb4 100644 --- a/src/chipset/umc_8886.c +++ b/src/chipset/umc_8886.c @@ -48,16 +48,16 @@ 1 0 PCICLK/2 Function 0 Register A2 - non-software SMI# status register - (documented by Miran Grca): + (documented by Miran Grca): Bit 4: I set, graphics card goes into sleep mode This register is most likely R/WC Function 0 Register A3 (added more details by Miran Grca): Bit 7: Unlock SMM Bit 6: Software SMI trigger (also doubles as software SMI# status register, - cleared by writing a 0 to it - see the handler used by Phoenix BIOS'es): - If Function 0 Register 46 Bit 6 is set, it raises the specified IRQ (15 - or 10) instead. + cleared by writing a 0 to it - see the handler used by Phoenix BIOS'es): + If Function 0 Register 46 Bit 6 is set, it raises the specified IRQ (15 + or 10) instead. Function 0 Register A4: Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half) @@ -87,52 +87,45 @@ #include <86box/chipset.h> - -#define IDE_BIT 0x01 - +#define IDE_BIT 0x01 #ifdef ENABLE_UMC_8886_LOG int umc_8886_do_log = ENABLE_UMC_8886_LOG; - static void umc_8886_log(const char *fmt, ...) { va_list ap; if (umc_8886_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define umc_8886_log(fmt, ...) +# define umc_8886_log(fmt, ...) #endif - /* PCI IRQ Flags */ -#define INTA (PCI_INTA + (2 * !(addr & 1))) -#define INTB (PCI_INTB + (2 * !(addr & 1))) -#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED) -#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED) +#define INTA (PCI_INTA + (2 * !(addr & 1))) +#define INTB (PCI_INTB + (2 * !(addr & 1))) +#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED) +#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED) /* Disable Internal IDE Flag needed for the AF or BF Southbridge variant */ -#define HAS_IDE dev->has_ide +#define HAS_IDE dev->has_ide /* Southbridge Revision */ -#define SB_ID dev->sb_id +#define SB_ID dev->sb_id - -typedef struct umc_8886_t -{ - uint8_t max_func, /* Last function number */ - pci_conf_sb[2][256]; /* PCI Registers */ - uint16_t sb_id; /* Southbridge Revision */ - int has_ide; /* Check if Southbridge Revision is AF or F */ +typedef struct umc_8886_t { + uint8_t max_func, /* Last function number */ + pci_conf_sb[2][256]; /* PCI Registers */ + uint16_t sb_id; /* Southbridge Revision */ + int has_ide; /* Check if Southbridge Revision is AF or F */ } umc_8886_t; - static void umc_8886_ide_handler(int status) { @@ -140,164 +133,172 @@ umc_8886_ide_handler(int status) ide_sec_disable(); if (status) { - ide_pri_enable(); - ide_sec_enable(); + ide_pri_enable(); + ide_sec_enable(); } } - static void umc_8886_write(int func, int addr, uint8_t val, void *priv) { - umc_8886_t *dev = (umc_8886_t *)priv; + umc_8886_t *dev = (umc_8886_t *) priv; - if (func <= dev->max_func) switch (func) { - case 0: /* PCI to ISA Bridge */ - umc_8886_log("UM8886: dev->regs[%02x] = %02x POST %02x\n", addr, val, inb(0x80)); + if (func <= dev->max_func) + switch (func) { + case 0: /* PCI to ISA Bridge */ + umc_8886_log("UM8886: dev->regs[%02x] = %02x POST %02x\n", addr, val, inb(0x80)); - switch (addr) { - case 0x04: case 0x05: - dev->pci_conf_sb[func][addr] = val; - break; + switch (addr) { + case 0x04: + case 0x05: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x07: - dev->pci_conf_sb[func][addr] &= ~(val & 0xf9); - break; + case 0x07: + dev->pci_conf_sb[func][addr] &= ~(val & 0xf9); + break; - case 0x0c: case 0x0d: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x0c: + case 0x0d: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x40: case 0x41: - case 0x42: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x40: + case 0x41: + case 0x42: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x43: case 0x44: - dev->pci_conf_sb[func][addr] = val; - pci_set_irq_routing(INTA, IRQRECALCA); - pci_set_irq_routing(INTB, IRQRECALCB); - break; + case 0x43: + case 0x44: + dev->pci_conf_sb[func][addr] = val; + pci_set_irq_routing(INTA, IRQRECALCA); + pci_set_irq_routing(INTB, IRQRECALCB); + break; - case 0x45: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x45: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x46: - /* Bit 6 seems to be the IRQ/SMI# toggle, 1 = IRQ, 0 = SMI#. */ - dev->pci_conf_sb[func][addr] = val; - break; + case 0x46: + /* Bit 6 seems to be the IRQ/SMI# toggle, 1 = IRQ, 0 = SMI#. */ + dev->pci_conf_sb[func][addr] = val; + break; - case 0x47: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x47: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x50: case 0x51: case 0x52: case 0x53: - case 0x54: case 0x55: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + dev->pci_conf_sb[func][addr] = val; + break; - case 0x56: - dev->pci_conf_sb[func][addr] = val; + case 0x56: + dev->pci_conf_sb[func][addr] = val; - switch (val & 2) { - case 0: - cpu_set_isa_pci_div(3); - break; - case 1: - cpu_set_isa_pci_div(4); - break; - case 2: - cpu_set_isa_pci_div(2); - break; - } + switch (val & 2) { + case 0: + cpu_set_isa_pci_div(3); + break; + case 1: + cpu_set_isa_pci_div(4); + break; + case 2: + cpu_set_isa_pci_div(2); + break; + } - break; + break; - case 0x57: - case 0x70 ... 0x76: - case 0x80: case 0x81: - case 0x90 ... 0x92: - case 0xa0 ... 0xa1: - dev->pci_conf_sb[func][addr] = val; - break; + case 0x57: + case 0x70 ... 0x76: + case 0x80: + case 0x81: + case 0x90 ... 0x92: + case 0xa0 ... 0xa1: + dev->pci_conf_sb[func][addr] = val; + break; - case 0xa2: - dev->pci_conf_sb[func][addr] &= ~val; - break; + case 0xa2: + dev->pci_conf_sb[func][addr] &= ~val; + break; - case 0xa3: - /* SMI Provocation (Bit 7 Enable SMM + Bit 6 Software SMI) */ - if (((val & 0xc0) == 0xc0) && !(dev->pci_conf_sb[0][0xa3] & 0x40)) { - if (dev->pci_conf_sb[0][0x46] & 0x40) - picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10)); - else - smi_raise(); - dev->pci_conf_sb[0][0xa3] |= 0x04; - } + case 0xa3: + /* SMI Provocation (Bit 7 Enable SMM + Bit 6 Software SMI) */ + if (((val & 0xc0) == 0xc0) && !(dev->pci_conf_sb[0][0xa3] & 0x40)) { + if (dev->pci_conf_sb[0][0x46] & 0x40) + picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10)); + else + smi_raise(); + dev->pci_conf_sb[0][0xa3] |= 0x04; + } - dev->pci_conf_sb[func][addr] = val; - break; + dev->pci_conf_sb[func][addr] = val; + break; - case 0xa4: - dev->pci_conf_sb[func][addr] = val; - cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2)); - break; + case 0xa4: + dev->pci_conf_sb[func][addr] = val; + cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2)); + break; - case 0xa5 ... 0xa8: - dev->pci_conf_sb[func][addr] = val; - break; - } - break; + case 0xa5 ... 0xa8: + dev->pci_conf_sb[func][addr] = val; + break; + } + break; - case 1: /* IDE Controller */ - umc_8886_log("UM8886-IDE: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80)); + case 1: /* IDE Controller */ + umc_8886_log("UM8886-IDE: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80)); - switch (addr) { - case 0x04: - dev->pci_conf_sb[func][addr] = val; - umc_8886_ide_handler(val & 1); - break; + switch (addr) { + case 0x04: + dev->pci_conf_sb[func][addr] = val; + umc_8886_ide_handler(val & 1); + break; - case 0x07: - dev->pci_conf_sb[func][addr] &= ~(val & 0xf9); - break; + case 0x07: + dev->pci_conf_sb[func][addr] &= ~(val & 0xf9); + break; - case 0x3c: - case 0x40: case 0x41: - dev->pci_conf_sb[func][addr] = val; - break; - } - break; - } + case 0x3c: + case 0x40: + case 0x41: + dev->pci_conf_sb[func][addr] = val; + break; + } + break; + } } - static uint8_t umc_8886_read(int func, int addr, void *priv) { - umc_8886_t *dev = (umc_8886_t *)priv; - uint8_t ret = 0xff; + umc_8886_t *dev = (umc_8886_t *) priv; + uint8_t ret = 0xff; if (func <= dev->max_func) - ret = dev->pci_conf_sb[func][addr]; + ret = dev->pci_conf_sb[func][addr]; return ret; } - static void umc_8886_reset(void *priv) { - umc_8886_t *dev = (umc_8886_t *)priv; + umc_8886_t *dev = (umc_8886_t *) priv; memset(dev->pci_conf_sb[0], 0x00, sizeof(dev->pci_conf_sb[0])); memset(dev->pci_conf_sb[1], 0x00, sizeof(dev->pci_conf_sb[1])); - dev->pci_conf_sb[0][0] = 0x60; /* UMC */ + dev->pci_conf_sb[0][0] = 0x60; /* UMC */ dev->pci_conf_sb[0][1] = 0x10; - dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */ + dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */ dev->pci_conf_sb[0][3] = ((SB_ID >> 8) & 0xff); dev->pci_conf_sb[0][4] = 0x0f; @@ -321,43 +322,41 @@ umc_8886_reset(void *priv) dev->pci_conf_sb[0][0xa8] = 0x20; if (HAS_IDE) { - dev->pci_conf_sb[1][0] = 0x60; /* UMC */ - dev->pci_conf_sb[1][1] = 0x10; + dev->pci_conf_sb[1][0] = 0x60; /* UMC */ + dev->pci_conf_sb[1][1] = 0x10; - dev->pci_conf_sb[1][2] = 0x3a; /* 8886BF IDE */ - dev->pci_conf_sb[1][3] = 0x67; + dev->pci_conf_sb[1][2] = 0x3a; /* 8886BF IDE */ + dev->pci_conf_sb[1][3] = 0x67; - dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */ + dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */ - dev->pci_conf_sb[1][8] = 0x10; + dev->pci_conf_sb[1][8] = 0x10; - dev->pci_conf_sb[1][0x09] = 0x0f; - dev->pci_conf_sb[1][0x0a] = dev->pci_conf_sb[1][0x0b] = 1; + dev->pci_conf_sb[1][0x09] = 0x0f; + dev->pci_conf_sb[1][0x0a] = dev->pci_conf_sb[1][0x0b] = 1; - umc_8886_ide_handler(1); + umc_8886_ide_handler(1); } - for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */ - pci_set_irq_routing(i, PCI_IRQ_DISABLED); + for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */ + pci_set_irq_routing(i, PCI_IRQ_DISABLED); cpu_set_isa_pci_div(3); cpu_set_pci_speed(cpu_busspeed / 2); } - static void umc_8886_close(void *priv) { - umc_8886_t *dev = (umc_8886_t *)priv; + umc_8886_t *dev = (umc_8886_t *) priv; free(dev); } - static void * umc_8886_init(const device_t *info) { - umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t)); + umc_8886_t *dev = (umc_8886_t *) malloc(sizeof(umc_8886_t)); memset(dev, 0, sizeof(umc_8886_t)); dev->has_ide = !!(info->local == 0x886a); @@ -365,7 +364,7 @@ umc_8886_init(const device_t *info) /* Add IDE if UM8886AF variant */ if (HAS_IDE) - device_add(&ide_pci_2ch_device); + device_add(&ide_pci_2ch_device); dev->max_func = (HAS_IDE) ? 1 : 0; @@ -378,29 +377,29 @@ umc_8886_init(const device_t *info) } const device_t umc_8886f_device = { - .name = "UMC 8886F", + .name = "UMC 8886F", .internal_name = "umc_8886f", - .flags = DEVICE_PCI, - .local = 0x8886, - .init = umc_8886_init, - .close = umc_8886_close, - .reset = umc_8886_reset, + .flags = DEVICE_PCI, + .local = 0x8886, + .init = umc_8886_init, + .close = umc_8886_close, + .reset = umc_8886_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t umc_8886af_device = { - .name = "UMC 8886AF/8886BF", + .name = "UMC 8886AF/8886BF", .internal_name = "umc_8886af", - .flags = DEVICE_PCI, - .local = 0x886a, - .init = umc_8886_init, - .close = umc_8886_close, - .reset = umc_8886_reset, + .flags = DEVICE_PCI, + .local = 0x886a, + .init = umc_8886_init, + .close = umc_8886_close, + .reset = umc_8886_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/umc_hb4.c b/src/chipset/umc_hb4.c index 4440b7eef..0179bdc72 100644 --- a/src/chipset/umc_hb4.c +++ b/src/chipset/umc_hb4.c @@ -85,7 +85,7 @@ Register 60: Bit 5: If set and SMRAM is enabled, data cycles go to PCI and code cycles go to DRAM Bit 0: SMRAM Local Access Enable - if set, SMRAM is also enabled outside SMM - SMRAM appears to always be enabled in SMM, and always set to A0000-BFFFF. + SMRAM appears to always be enabled in SMM, and always set to A0000-BFFFF. */ #include @@ -108,56 +108,50 @@ #include <86box/smram.h> #ifdef USE_DYNAREC -# include "codegen_public.h" +# include "codegen_public.h" #else -#ifdef USE_NEW_DYNAREC -# define PAGE_MASK_SHIFT 6 -#else -# define PAGE_MASK_INDEX_MASK 3 -# define PAGE_MASK_INDEX_SHIFT 10 -# define PAGE_MASK_SHIFT 4 -#endif -# define PAGE_MASK_MASK 63 +# ifdef USE_NEW_DYNAREC +# define PAGE_MASK_SHIFT 6 +# else +# define PAGE_MASK_INDEX_MASK 3 +# define PAGE_MASK_INDEX_SHIFT 10 +# define PAGE_MASK_SHIFT 4 +# endif +# define PAGE_MASK_MASK 63 #endif #include <86box/chipset.h> - #ifdef ENABLE_HB4_LOG int hb4_do_log = ENABLE_HB4_LOG; - static void hb4_log(const char *fmt, ...) { va_list ap; if (hb4_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define hb4_log(fmt, ...) +# define hb4_log(fmt, ...) #endif - -typedef struct hb4_t -{ - uint8_t shadow, - shadow_read, shadow_write, - pci_conf[256]; /* PCI Registers */ - int mem_state[9]; - smram_t *smram[3]; /* SMRAM Handlers */ +typedef struct hb4_t { + uint8_t shadow, + shadow_read, shadow_write, + pci_conf[256]; /* PCI Registers */ + int mem_state[9]; + smram_t *smram[3]; /* SMRAM Handlers */ } hb4_t; - -static int shadow_bios[4] = { (MEM_READ_EXTANY | MEM_WRITE_INTERNAL), (MEM_READ_EXTANY | MEM_WRITE_EXTANY), - (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL), (MEM_READ_INTERNAL | MEM_WRITE_EXTANY) }; -static int shadow_read[2] = { MEM_READ_EXTANY, MEM_READ_INTERNAL }; +static int shadow_bios[4] = { (MEM_READ_EXTANY | MEM_WRITE_INTERNAL), (MEM_READ_EXTANY | MEM_WRITE_EXTANY), + (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL), (MEM_READ_INTERNAL | MEM_WRITE_EXTANY) }; +static int shadow_read[2] = { MEM_READ_EXTANY, MEM_READ_INTERNAL }; static int shadow_write[2] = { MEM_WRITE_INTERNAL, MEM_WRITE_EXTANY }; - int hb4_shadow_bios_high(hb4_t *dev) { @@ -166,17 +160,16 @@ hb4_shadow_bios_high(hb4_t *dev) state = shadow_bios[dev->pci_conf[0x55] >> 6]; if (state != dev->mem_state[8]) { - mem_set_mem_state_both(0xf0000, 0x10000, state); - if ((dev->mem_state[8] & MEM_READ_INTERNAL) && !(state & MEM_READ_INTERNAL)) - mem_invalidate_range(0xf0000, 0xfffff); - dev->mem_state[8] = state; - return 1; + mem_set_mem_state_both(0xf0000, 0x10000, state); + if ((dev->mem_state[8] & MEM_READ_INTERNAL) && !(state & MEM_READ_INTERNAL)) + mem_invalidate_range(0xf0000, 0xfffff); + dev->mem_state[8] = state; + return 1; } return 0; } - int hb4_shadow_bios_low(hb4_t *dev) { @@ -185,15 +178,14 @@ hb4_shadow_bios_low(hb4_t *dev) state = shadow_bios[(dev->pci_conf[0x55] >> 6) & (dev->shadow | 0x01)]; if (state != dev->mem_state[7]) { - mem_set_mem_state_both(0xe0000, 0x10000, state); - dev->mem_state[7] = state; - return 1; + mem_set_mem_state_both(0xe0000, 0x10000, state); + dev->mem_state[7] = state; + return 1; } return 0; } - int hb4_shadow_main(hb4_t *dev) { @@ -201,38 +193,34 @@ hb4_shadow_main(hb4_t *dev) int n = 0; for (i = 0; i < 6; i++) { - state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> (i + 2)) & 0x01)] | - shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; + state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> (i + 2)) & 0x01)] | shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; - if (state != dev->mem_state[i + 1]) { - n++; - mem_set_mem_state_both(0xc8000 + (i << 14), 0x4000, state); - dev->mem_state[i + 1] = state; - } + if (state != dev->mem_state[i + 1]) { + n++; + mem_set_mem_state_both(0xc8000 + (i << 14), 0x4000, state); + dev->mem_state[i + 1] = state; + } } return n; } - int hb4_shadow_video(hb4_t *dev) { int state; - state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> 1) & 0x01)] | - shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; + state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> 1) & 0x01)] | shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01]; if (state != dev->mem_state[0]) { - mem_set_mem_state_both(0xc0000, 0x8000, state); - dev->mem_state[0] = state; - return 1; + mem_set_mem_state_both(0xc0000, 0x8000, state); + dev->mem_state[0] = state; + return 1; } return 0; } - void hb4_shadow(hb4_t *dev) { @@ -245,10 +233,9 @@ hb4_shadow(hb4_t *dev) n += hb4_shadow_video(dev); if (n > 0) - flushmmucache_nopc(); + flushmmucache_nopc(); } - static void hb4_smram(hb4_t *dev) { @@ -265,93 +252,93 @@ hb4_smram(hb4_t *dev) /* Bit 5 seems to set data to go to PCI and code to DRAM. The Samsung SPC7700P-LW uses this. */ if (dev->pci_conf[0x60] & 0x20) { - if (dev->pci_conf[0x60] & 0x01) - mem_set_mem_state_smram_ex(0, 0x000a0000, 0x20000, 0x02); - mem_set_mem_state_smram_ex(1, 0x000a0000, 0x20000, 0x02); + if (dev->pci_conf[0x60] & 0x01) + mem_set_mem_state_smram_ex(0, 0x000a0000, 0x20000, 0x02); + mem_set_mem_state_smram_ex(1, 0x000a0000, 0x20000, 0x02); } } - static void hb4_write(int func, int addr, uint8_t val, void *priv) { - hb4_t *dev = (hb4_t *)priv; + hb4_t *dev = (hb4_t *) priv; hb4_log("UM8881: dev->regs[%02x] = %02x POST: %02x \n", addr, val, inb(0x80)); switch (addr) { - case 0x04: case 0x05: - dev->pci_conf[addr] = val; - break; + case 0x04: + case 0x05: + dev->pci_conf[addr] = val; + break; - case 0x07: - dev->pci_conf[addr] &= ~(val & 0xf9); - break; + case 0x07: + dev->pci_conf[addr] &= ~(val & 0xf9); + break; - case 0x0c: case 0x0d: - dev->pci_conf[addr] = val; - break; + case 0x0c: + case 0x0d: + dev->pci_conf[addr] = val; + break; - case 0x50: - dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */ - cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/ - cpu_update_waitstates(); - break; + case 0x50: + dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */ + cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/ + cpu_update_waitstates(); + break; - case 0x51: case 0x52: - dev->pci_conf[addr] = val; - break; + case 0x51: + case 0x52: + dev->pci_conf[addr] = val; + break; - case 0x53: - dev->pci_conf[addr] = val; - hb4_log("HB53: %02X\n", val); - break; + case 0x53: + dev->pci_conf[addr] = val; + hb4_log("HB53: %02X\n", val); + break; - case 0x55: - dev->shadow_read = (val & 0x80); - dev->shadow_write = (val & 0x40); - dev->pci_conf[addr] = val; - hb4_shadow(dev); - break; - case 0x54: - dev->shadow = (val & 0x01) << 1; - dev->pci_conf[addr] = val; - hb4_shadow(dev); - break; + case 0x55: + dev->shadow_read = (val & 0x80); + dev->shadow_write = (val & 0x40); + dev->pci_conf[addr] = val; + hb4_shadow(dev); + break; + case 0x54: + dev->shadow = (val & 0x01) << 1; + dev->pci_conf[addr] = val; + hb4_shadow(dev); + break; - case 0x56 ... 0x5f: - dev->pci_conf[addr] = val; - break; + case 0x56 ... 0x5f: + dev->pci_conf[addr] = val; + break; - case 0x60: - dev->pci_conf[addr] = val; - hb4_smram(dev); - break; + case 0x60: + dev->pci_conf[addr] = val; + hb4_smram(dev); + break; - case 0x61: - dev->pci_conf[addr] = val; - break; + case 0x61: + dev->pci_conf[addr] = val; + break; } } - static uint8_t hb4_read(int func, int addr, void *priv) { - hb4_t *dev = (hb4_t *)priv; + hb4_t *dev = (hb4_t *) priv; uint8_t ret = 0xff; if (func == 0) - ret = dev->pci_conf[addr]; + ret = dev->pci_conf[addr]; return ret; } - static void hb4_reset(void *priv) { - hb4_t *dev = (hb4_t *)priv; + hb4_t *dev = (hb4_t *) priv; memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf)); dev->pci_conf[0] = 0x60; /* UMC */ @@ -385,23 +372,21 @@ hb4_reset(void *priv) memset(dev->mem_state, 0x00, sizeof(dev->mem_state)); } - static void hb4_close(void *priv) { - hb4_t *dev = (hb4_t *)priv; + hb4_t *dev = (hb4_t *) priv; free(dev); } - static void * hb4_init(const device_t *info) { - hb4_t *dev = (hb4_t *)malloc(sizeof(hb4_t)); + hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t)); memset(dev, 0, sizeof(hb4_t)); - pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev); /* Device 10: UMC 8881x */ + pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev); /* Device 10: UMC 8881x */ /* Port 92 */ device_add(&port_92_pci_device); @@ -417,15 +402,15 @@ hb4_init(const device_t *info) } const device_t umc_hb4_device = { - .name = "UMC HB4(8881F)", + .name = "UMC HB4(8881F)", .internal_name = "umc_hb4", - .flags = DEVICE_PCI, - .local = 0x886a, - .init = hb4_init, - .close = hb4_close, - .reset = hb4_reset, + .flags = DEVICE_PCI, + .local = 0x886a, + .init = hb4_init, + .close = hb4_close, + .reset = hb4_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/via_apollo.c b/src/chipset/via_apollo.c index bb30a0264..db137bc63 100644 --- a/src/chipset/via_apollo.c +++ b/src/chipset/via_apollo.c @@ -44,50 +44,46 @@ #define VIA_694 0x0691c200 #define VIA_8601 0x86010500 -typedef struct via_apollo_t -{ - uint32_t id; - uint8_t drb_unit; - uint8_t pci_conf[256]; +typedef struct via_apollo_t { + uint32_t id; + uint8_t drb_unit; + uint8_t pci_conf[256]; smram_t *smram; agpgart_t *agpgart; } via_apollo_t; - static void apollo_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { - case 0: - mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; + case 0: + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 2: + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 3: + mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; } flushmmucache_nopc(); } - static void apollo_smram_map(via_apollo_t *dev, int smm, uint32_t host_base, uint32_t size, int is_smram) { if (((is_smram & 0x03) == 0x01) || ((is_smram & 0x03) == 0x02)) - smram_enable(dev->smram, host_base, 0x000a0000, size, 0, 1); + smram_enable(dev->smram, host_base, 0x000a0000, size, 0, 1); mem_set_mem_state_smram_ex(smm, host_base, size, is_smram & 0x03); flushmmucache(); } - static void apollo_agp_map(via_apollo_t *dev) { @@ -96,17 +92,16 @@ apollo_agp_map(via_apollo_t *dev) dev->pci_conf[0x13] &= 0xf0 | (dev->pci_conf[0x84] >> 4); if (!dev->agpgart) - return; + return; /* Map aperture and GART. */ agpgart_set_aperture(dev->agpgart, - (dev->pci_conf[0x12] << 16) | (dev->pci_conf[0x13] << 24), - ((uint32_t) (uint8_t) ~dev->pci_conf[0x84] + 1) << 20, - !!(dev->pci_conf[0x88] & 0x02)); + (dev->pci_conf[0x12] << 16) | (dev->pci_conf[0x13] << 24), + ((uint32_t) (uint8_t) ~dev->pci_conf[0x84] + 1) << 20, + !!(dev->pci_conf[0x88] & 0x02)); agpgart_set_gart(dev->agpgart, (dev->pci_conf[0x89] << 8) | (dev->pci_conf[0x8a] << 16) | (dev->pci_conf[0x8b] << 24)); } - static void via_apollo_setup(via_apollo_t *dev) { @@ -120,9 +115,9 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x05] = 0; if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x06] = 0xa0; + dev->pci_conf[0x06] = 0xa0; else - dev->pci_conf[0x06] = 0x90; + dev->pci_conf[0x06] = 0x90; dev->pci_conf[0x07] = 0x02; @@ -136,30 +131,30 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x0f] = 0; if (dev->id >= VIA_597) { - dev->pci_conf[0x10] = 0x08; - dev->pci_conf[0x34] = 0xa0; + dev->pci_conf[0x10] = 0x08; + dev->pci_conf[0x34] = 0xa0; } if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x52] = 0x02; + dev->pci_conf[0x52] = 0x02; else if (dev->id >= VIA_694) - dev->pci_conf[0x52] = (dev->id == VIA_694) ? 0x90 : 0x10; + dev->pci_conf[0x52] = (dev->id == VIA_694) ? 0x90 : 0x10; if (dev->id >= VIA_693A) - dev->pci_conf[0x53] = 0x10; + dev->pci_conf[0x53] = 0x10; if (dev->id == VIA_691) { - dev->pci_conf[0x56] = 0x01; - dev->pci_conf[0x57] = 0x01; + dev->pci_conf[0x56] = 0x01; + dev->pci_conf[0x57] = 0x01; } if (dev->id >= VIA_694) - dev->pci_conf[0x58] = 0x40; + dev->pci_conf[0x58] = 0x40; else if (dev->id >= VIA_585) - dev->pci_conf[0x58] = 0x05; + dev->pci_conf[0x58] = 0x05; if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x59] = 0x02; + dev->pci_conf[0x59] = 0x02; dev->pci_conf[0x5a] = 0x01; dev->pci_conf[0x5b] = 0x01; @@ -170,526 +165,529 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x64] = ((dev->id >= VIA_585) || (dev->id < VIA_597)) ? 0xab : 0xec; if (dev->id >= VIA_597) { - dev->pci_conf[0x65] = 0xec; - dev->pci_conf[0x66] = 0xec; + dev->pci_conf[0x65] = 0xec; + dev->pci_conf[0x66] = 0xec; } if (dev->id >= VIA_691) - dev->pci_conf[0x67] = 0xec; /* DRAM Timing for Banks 6, 7 */ + dev->pci_conf[0x67] = 0xec; /* DRAM Timing for Banks 6, 7 */ if (dev->id >= VIA_693A) { - if (cpu_busspeed < 95000000) { /* 66 MHz */ - cpu_set_pci_speed(cpu_busspeed / 2); - cpu_set_agp_speed(cpu_busspeed); - dev->pci_conf[0x68] |= 0x00; - } else if (cpu_busspeed < 124000000) { /* 100 MHz */ - cpu_set_pci_speed(cpu_busspeed / 3); - cpu_set_agp_speed(cpu_busspeed / 1.5); - dev->pci_conf[0x68] |= 0x01; - } else { /* 133 MHz */ - cpu_set_pci_speed(cpu_busspeed / 4); - cpu_set_agp_speed(cpu_busspeed / 2); - dev->pci_conf[0x68] |= (dev->id == VIA_8601) ? 0x03 : 0x02; - } + if (cpu_busspeed < 95000000) { /* 66 MHz */ + cpu_set_pci_speed(cpu_busspeed / 2); + cpu_set_agp_speed(cpu_busspeed); + dev->pci_conf[0x68] |= 0x00; + } else if (cpu_busspeed < 124000000) { /* 100 MHz */ + cpu_set_pci_speed(cpu_busspeed / 3); + cpu_set_agp_speed(cpu_busspeed / 1.5); + dev->pci_conf[0x68] |= 0x01; + } else { /* 133 MHz */ + cpu_set_pci_speed(cpu_busspeed / 4); + cpu_set_agp_speed(cpu_busspeed / 2); + dev->pci_conf[0x68] |= (dev->id == VIA_8601) ? 0x03 : 0x02; + } } else if (dev->id >= VIA_598) { - if (cpu_busspeed < ((dev->id >= VIA_691) ? 100000000 : 75000000)) { /* 66 MHz */ - cpu_set_pci_speed(cpu_busspeed / 2); - cpu_set_agp_speed(cpu_busspeed); - dev->pci_conf[0x68] |= 0x00; - } else if (cpu_busspeed < 100000000) { /* 75/83 MHz (not available on 691) */ - cpu_set_pci_speed(cpu_busspeed / 2.5); - cpu_set_agp_speed(cpu_busspeed / 1.25); - dev->pci_conf[0x68] |= 0x03; - } else { /* 100 MHz */ - cpu_set_pci_speed(cpu_busspeed / 3); - cpu_set_agp_speed(cpu_busspeed / 1.5); - dev->pci_conf[0x68] |= 0x01; - } + if (cpu_busspeed < ((dev->id >= VIA_691) ? 100000000 : 75000000)) { /* 66 MHz */ + cpu_set_pci_speed(cpu_busspeed / 2); + cpu_set_agp_speed(cpu_busspeed); + dev->pci_conf[0x68] |= 0x00; + } else if (cpu_busspeed < 100000000) { /* 75/83 MHz (not available on 691) */ + cpu_set_pci_speed(cpu_busspeed / 2.5); + cpu_set_agp_speed(cpu_busspeed / 1.25); + dev->pci_conf[0x68] |= 0x03; + } else { /* 100 MHz */ + cpu_set_pci_speed(cpu_busspeed / 3); + cpu_set_agp_speed(cpu_busspeed / 1.5); + dev->pci_conf[0x68] |= 0x01; + } } dev->pci_conf[0x6b] = 0x01; if (dev->id >= VIA_597) { - dev->pci_conf[0xa0] = 0x02; - dev->pci_conf[0xa2] = 0x10; - dev->pci_conf[0xa4] = 0x03; - dev->pci_conf[0xa5] = 0x02; - dev->pci_conf[0xa7] = 0x07; + dev->pci_conf[0xa0] = 0x02; + dev->pci_conf[0xa2] = 0x10; + dev->pci_conf[0xa4] = 0x03; + dev->pci_conf[0xa5] = 0x02; + dev->pci_conf[0xa7] = 0x07; - if (dev->id == VIA_693A) { - dev->pci_conf[0xac] = 0x08; - dev->pci_conf[0xad] = 0x02; - } + if (dev->id == VIA_693A) { + dev->pci_conf[0xac] = 0x08; + dev->pci_conf[0xad] = 0x02; + } - if (dev->id == VIA_694) { - dev->pci_conf[0xb0] = 0x80; /* The datasheet refers it as 8xh */ - dev->pci_conf[0xb1] = 0x63; - } + if (dev->id == VIA_694) { + dev->pci_conf[0xb0] = 0x80; /* The datasheet refers it as 8xh */ + dev->pci_conf[0xb1] = 0x63; + } } } - static void via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) { via_apollo_t *dev = (via_apollo_t *) priv; if (func) - return; + return; /*Read-only addresses*/ - if ((addr < 4) || ((addr > 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || - ((addr >= 0xe) && (addr != 0x0f) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) || - ((addr > 0x7a) && (addr < 0x7e)) || ((addr >= 0x81) && (addr < 0x84)) || - ((addr >= 0x85) && (addr < 0x88)) || ((addr >= 0x8c) && (addr < 0xa8)) || - ((addr >= 0xaa) && (addr < 0xac)) || ((addr > 0xad) && (addr < 0xf0)) || - ((addr >= 0xf8) && (addr < 0xfc))) - return; + if ((addr < 4) || ((addr > 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr != 0x0f) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) || ((addr > 0x7a) && (addr < 0x7e)) || ((addr >= 0x81) && (addr < 0x84)) || ((addr >= 0x85) && (addr < 0x88)) || ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xaa) && (addr < 0xac)) || ((addr > 0xad) && (addr < 0xf0)) || ((addr >= 0xf8) && (addr < 0xfc))) + return; if (((addr == 0x12) || (addr == 0x13)) && (dev->id < VIA_597)) - return; + return; if (((addr == 0x78) || (addr >= 0xad)) && (dev->id == VIA_597)) - return; + return; if (((addr == 0x67) || ((addr >= 0xf0) && (addr < 0xfc))) && (dev->id < VIA_691)) - return; + return; - switch(addr) { - case 0x04: - dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40); - break; + switch (addr) { + case 0x04: + dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40); + break; - case 0x05: - if((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x05] = (dev->pci_conf[0x05] & ~0x03) | (val & 0x03); - else - dev->pci_conf[0x05] = val; - break; + case 0x05: + if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x05] = (dev->pci_conf[0x05] & ~0x03) | (val & 0x03); + else + dev->pci_conf[0x05] = val; + break; - case 0x07: - dev->pci_conf[0x07] &= ~(val & 0xb0); - break; - case 0x0d: - if(dev->id == VIA_8601) - dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07); - else if(dev->id == VIA_694) - dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0xf8) | (val & 0xf8); - else - dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07); + case 0x07: + dev->pci_conf[0x07] &= ~(val & 0xb0); + break; + case 0x0d: + if (dev->id == VIA_8601) + dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07); + else if (dev->id == VIA_694) + dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0xf8) | (val & 0xf8); + else + dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07); - dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0x30) | ((val & 0x06) << 3); - break; + dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0x30) | ((val & 0x06) << 3); + break; - case 0x0f: - if((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x0f] = (dev->pci_conf[0x0f] & ~0xcf) | (val & 0x0cf); - else - dev->pci_conf[0x0f] = val; - break; - case 0x12: /* Graphics Aperture Base */ - dev->pci_conf[0x12] = (val & 0xf0); - apollo_agp_map(dev); - break; - case 0x13: /* Graphics Aperture Base */ - dev->pci_conf[0x13] = val; - apollo_agp_map(dev); - break; + case 0x0f: + if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x0f] = (dev->pci_conf[0x0f] & ~0xcf) | (val & 0x0cf); + else + dev->pci_conf[0x0f] = val; + break; + case 0x12: /* Graphics Aperture Base */ + dev->pci_conf[0x12] = (val & 0xf0); + apollo_agp_map(dev); + break; + case 0x13: /* Graphics Aperture Base */ + dev->pci_conf[0x13] = val; + apollo_agp_map(dev); + break; - case 0x50: /* Cache Control 1 */ - if (dev->id == VIA_8601) - dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd3) | (val & 0xd3); - else if (dev->id >= VIA_693A) - dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd1) | (val & 0xd1); - else if (dev->id == VIA_595) - dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xfb) | (val & 0xfb); - else if ((dev->id == VIA_585) || (dev->id == VIA_691)) - dev->pci_conf[0x50] = val; - else - dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xf8) | (val & 0xf8); - break; - case 0x51: /* Cache Control 2 */ - if (dev->id == VIA_694) - dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xdd) | (val & 0xdd); - else if (dev->id >= VIA_693A) - dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xd9) | (val & 0xd9); - else if (dev->id >= VIA_691) - dev->pci_conf[0x51] = val; - else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0x2b) | (val & 0x2b); - else - dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xeb) | (val & 0xeb); - break; - case 0x52: /* Non_Cacheable Control */ - if (dev->id == VIA_8601) - dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xdf) | (val & 0xdf); - else if (dev->id >= VIA_693A) - dev->pci_conf[0x52] = val; - else if (dev->id == VIA_691) - dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0x9f) | (val & 0x9f); - else - dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xf5) | (val & 0xf5); - break; - case 0x53: /* System Performance Control */ - if (dev->id == VIA_8601) - dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xfc) | (val & 0xfc); - else if ((dev->id == VIA_691) || (dev->id == VIA_694)) - dev->pci_conf[0x53] = val; - else if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_693A)) - dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf8) | (val & 0xf8); - else - dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0); - break; - case 0x54: - if (dev->id == VIA_585) - dev->pci_conf[0x54] = val; - else - dev->pci_conf[0x54] = (dev->pci_conf[0x54] & ~0x07) | (val & 0x07); - break; + case 0x50: /* Cache Control 1 */ + if (dev->id == VIA_8601) + dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd3) | (val & 0xd3); + else if (dev->id >= VIA_693A) + dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd1) | (val & 0xd1); + else if (dev->id == VIA_595) + dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xfb) | (val & 0xfb); + else if ((dev->id == VIA_585) || (dev->id == VIA_691)) + dev->pci_conf[0x50] = val; + else + dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xf8) | (val & 0xf8); + break; + case 0x51: /* Cache Control 2 */ + if (dev->id == VIA_694) + dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xdd) | (val & 0xdd); + else if (dev->id >= VIA_693A) + dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xd9) | (val & 0xd9); + else if (dev->id >= VIA_691) + dev->pci_conf[0x51] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0x2b) | (val & 0x2b); + else + dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xeb) | (val & 0xeb); + break; + case 0x52: /* Non_Cacheable Control */ + if (dev->id == VIA_8601) + dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xdf) | (val & 0xdf); + else if (dev->id >= VIA_693A) + dev->pci_conf[0x52] = val; + else if (dev->id == VIA_691) + dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0x9f) | (val & 0x9f); + else + dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xf5) | (val & 0xf5); + break; + case 0x53: /* System Performance Control */ + if (dev->id == VIA_8601) + dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xfc) | (val & 0xfc); + else if ((dev->id == VIA_691) || (dev->id == VIA_694)) + dev->pci_conf[0x53] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_693A)) + dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf8) | (val & 0xf8); + else + dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0); + break; + case 0x54: + if (dev->id == VIA_585) + dev->pci_conf[0x54] = val; + else + dev->pci_conf[0x54] = (dev->pci_conf[0x54] & ~0x07) | (val & 0x07); + break; - case 0x56: case 0x57: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: /* DRAM Row Ending Address */ - if ((dev->id >= VIA_691) && (dev->id != VIA_8601)) - spd_write_drbs(dev->pci_conf, 0x5a, 0x56, dev->drb_unit); - else if (addr >= 0x5a) - spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, dev->drb_unit); - break; + case 0x56: + case 0x57: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: /* DRAM Row Ending Address */ + if ((dev->id >= VIA_691) && (dev->id != VIA_8601)) + spd_write_drbs(dev->pci_conf, 0x5a, 0x56, dev->drb_unit); + else if (addr >= 0x5a) + spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, dev->drb_unit); + break; - case 0x58: - if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_597) || ((dev->id >= VIA_693A) || (dev->id < VIA_8601))) - dev->pci_conf[0x58] = (dev->pci_conf[0x58] & ~0xee) | (val & 0xee); - else - dev->pci_conf[0x58] = val; - break; - case 0x59: - if (dev->id >= VIA_693A) - dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xee) | (val & 0xee); - else if (dev->id == VIA_691) - dev->pci_conf[0x59] = val; - else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xe7) | (val & 0xe7); - else - dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xf0) | (val & 0xf0); - break; + case 0x58: + if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_597) || ((dev->id >= VIA_693A) || (dev->id < VIA_8601))) + dev->pci_conf[0x58] = (dev->pci_conf[0x58] & ~0xee) | (val & 0xee); + else + dev->pci_conf[0x58] = val; + break; + case 0x59: + if (dev->id >= VIA_693A) + dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xee) | (val & 0xee); + else if (dev->id == VIA_691) + dev->pci_conf[0x59] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xe7) | (val & 0xe7); + else + dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xf0) | (val & 0xf0); + break; - case 0x61: /* Shadow RAM Control 1 */ - apollo_map(0xc0000, 0x04000, val & 0x03); - apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2); - apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4); - apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6); + case 0x61: /* Shadow RAM Control 1 */ + apollo_map(0xc0000, 0x04000, val & 0x03); + apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2); + apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4); + apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0x61] = val; - break; - case 0x62: /* Shadow RAM Control 2 */ - apollo_map(0xd0000, 0x04000, val & 0x03); - apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2); - apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4); - apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6); + dev->pci_conf[0x61] = val; + break; + case 0x62: /* Shadow RAM Control 2 */ + apollo_map(0xd0000, 0x04000, val & 0x03); + apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2); + apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4); + apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0x62] = val; - break; - case 0x63: /* Shadow RAM Control 3 */ - shadowbios = 0; - shadowbios_write = 0; + dev->pci_conf[0x62] = val; + break; + case 0x63: /* Shadow RAM Control 3 */ + shadowbios = 0; + shadowbios_write = 0; - apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4); - shadowbios = (((val & 0x30) >> 4) & 0x02); - shadowbios_write = (((val & 0x30) >> 4) & 0x01); + apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4); + shadowbios = (((val & 0x30) >> 4) & 0x02); + shadowbios_write = (((val & 0x30) >> 4) & 0x01); - apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6); - shadowbios |= (((val & 0xc0) >> 6) & 0x02); - shadowbios_write |= (((val & 0xc0) >> 6) & 0x01); + apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6); + shadowbios |= (((val & 0xc0) >> 6) & 0x02); + shadowbios_write |= (((val & 0xc0) >> 6) & 0x01); - dev->pci_conf[0x63] = val; - smram_disable_all(); - if (dev->id >= VIA_691) switch (val & 0x03) { - case 0x00: - default: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */ - break; - case 0x01: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); /* Non-SMM: Code DRAM, Data DRAM */ - break; - case 0x02: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); /* SMM: Code Invalid, Data Invalid */ - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 2); /* Non-SMM: Code DRAM, Data PCI */ - break; - case 0x03: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */ - break; - } else if (dev->id >= VIA_597) switch (val & 0x03) { - case 0x00: - default: - /* Disable SMI Address Redirection (default) */ - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); - break; - case 0x01: - /* Allow access to DRAM Axxxx-Bxxxx for both normal and SMI cycles */ - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); - break; - case 0x02: - /* Reserved */ - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); - if (dev->id == VIA_597) { - /* SMI 3xxxx-4xxxx redirect to Axxxx-Bxxxx. */ - apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); - } - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); - break; - case 0x03: - /* Allow SMI Axxxx-Bxxxx DRAM access */ - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); - break; - } else switch(val & 0x03) { - case 0x00: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); - break; - case 0x01: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); - break; - case 0x02: - apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); - break; - case 0x03: - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); - apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); - break; - } - break; - case 0x65: - if (dev->id == VIA_585) - dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xfd) | (val & 0xfd); - else if (dev->id == VIA_595) - dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xf9) | (val & 0xf9); - else - dev->pci_conf[0x65] = val; - break; - case 0x66: - if (dev->id == VIA_585) - dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0xaf) | (val & 0xaf); - else if (dev->id == VIA_595) - dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0x8f) | (val & 0x8f); - else - dev->pci_conf[0x66] = val; - break; - case 0x68: - if (dev->id != VIA_595) { - if (dev->id == VIA_597) - dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfe) | (val & 0xfe); - else if ((dev->id == VIA_693A) || (dev->id == VIA_694)) - dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xdc) | (val & 0xdc); - else - dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfc) | (val & 0xfc); - } - break; - case 0x69: - if ((dev->id != VIA_585) || (dev->id != VIA_595)){ - if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) - dev->pci_conf[0x69] = (dev->pci_conf[0x69] & ~0xfe) | (val & 0xfe); - else - dev->pci_conf[0x69] = val; - } - break; - case 0x6b: - if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) - dev->pci_conf[0x6b] = val; - else if (dev->id == VIA_691) - dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xcf) | (val & 0xcf); - else if (dev->id == VIA_595) - dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc0) | (val & 0xc0); - else if (dev->id == VIA_585) - dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc4) | (val & 0xc4); - else - dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc1) | (val & 0xc1); - break; - case 0x6c: - if ((dev->id == VIA_597) || ((dev->id == VIA_693A) || (dev->id < VIA_8601))) - dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x1f) | (val & 0x1f); - else if (dev->id == VIA_598) - dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x7f) | (val & 0x7f); - else if (dev->id == VIA_585) - dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0xef) | (val & 0xef); - else - dev->pci_conf[0x6c] = val; - break; - case 0x6d: - if ((dev->id == VIA_597) || (dev->id == VIA_694)) - dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x0f) | (val & 0x0f); - else if ((dev->id == VIA_598) || (dev->id == VIA_693A) || (dev->id == VIA_8601)) - dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x7f) | (val & 0x7f); - else - dev->pci_conf[0x6d] = val; - break; - case 0x6e: - if((dev->id == VIA_595) || (dev->id == VIA_694)) - dev->pci_conf[0x6e] = val; - else - dev->pci_conf[0x6e] = (dev->pci_conf[0x6e] & ~0xb7) | (val & 0xb7); - break; + dev->pci_conf[0x63] = val; + smram_disable_all(); + if (dev->id >= VIA_691) + switch (val & 0x03) { + case 0x00: + default: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */ + break; + case 0x01: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); /* Non-SMM: Code DRAM, Data DRAM */ + break; + case 0x02: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); /* SMM: Code Invalid, Data Invalid */ + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 2); /* Non-SMM: Code DRAM, Data PCI */ + break; + case 0x03: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */ + break; + } + else if (dev->id >= VIA_597) + switch (val & 0x03) { + case 0x00: + default: + /* Disable SMI Address Redirection (default) */ + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + case 0x01: + /* Allow access to DRAM Axxxx-Bxxxx for both normal and SMI cycles */ + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); + break; + case 0x02: + /* Reserved */ + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); + if (dev->id == VIA_597) { + /* SMI 3xxxx-4xxxx redirect to Axxxx-Bxxxx. */ + apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); + } + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); + break; + case 0x03: + /* Allow SMI Axxxx-Bxxxx DRAM access */ + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + } + else + switch (val & 0x03) { + case 0x00: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + case 0x01: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + case 0x02: + apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); + break; + case 0x03: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); + break; + } + break; + case 0x65: + if (dev->id == VIA_585) + dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xfd) | (val & 0xfd); + else if (dev->id == VIA_595) + dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xf9) | (val & 0xf9); + else + dev->pci_conf[0x65] = val; + break; + case 0x66: + if (dev->id == VIA_585) + dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0xaf) | (val & 0xaf); + else if (dev->id == VIA_595) + dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0x8f) | (val & 0x8f); + else + dev->pci_conf[0x66] = val; + break; + case 0x68: + if (dev->id != VIA_595) { + if (dev->id == VIA_597) + dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfe) | (val & 0xfe); + else if ((dev->id == VIA_693A) || (dev->id == VIA_694)) + dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xdc) | (val & 0xdc); + else + dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfc) | (val & 0xfc); + } + break; + case 0x69: + if ((dev->id != VIA_585) || (dev->id != VIA_595)) { + if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) + dev->pci_conf[0x69] = (dev->pci_conf[0x69] & ~0xfe) | (val & 0xfe); + else + dev->pci_conf[0x69] = val; + } + break; + case 0x6b: + if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) + dev->pci_conf[0x6b] = val; + else if (dev->id == VIA_691) + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xcf) | (val & 0xcf); + else if (dev->id == VIA_595) + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc0) | (val & 0xc0); + else if (dev->id == VIA_585) + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc4) | (val & 0xc4); + else + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc1) | (val & 0xc1); + break; + case 0x6c: + if ((dev->id == VIA_597) || ((dev->id == VIA_693A) || (dev->id < VIA_8601))) + dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x1f) | (val & 0x1f); + else if (dev->id == VIA_598) + dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x7f) | (val & 0x7f); + else if (dev->id == VIA_585) + dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0xef) | (val & 0xef); + else + dev->pci_conf[0x6c] = val; + break; + case 0x6d: + if ((dev->id == VIA_597) || (dev->id == VIA_694)) + dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x0f) | (val & 0x0f); + else if ((dev->id == VIA_598) || (dev->id == VIA_693A) || (dev->id == VIA_8601)) + dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x7f) | (val & 0x7f); + else + dev->pci_conf[0x6d] = val; + break; + case 0x6e: + if ((dev->id == VIA_595) || (dev->id == VIA_694)) + dev->pci_conf[0x6e] = val; + else + dev->pci_conf[0x6e] = (dev->pci_conf[0x6e] & ~0xb7) | (val & 0xb7); + break; - case 0x70: - if ((dev->id >= VIA_693A)) - dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xdf) | (val & 0xdf); - else if (dev->id == VIA_597) - dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xf1) | (val & 0xf1); - else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xe3) | (val & 0xe3); - else - dev->pci_conf[0x70] = val; - break; - case 0x71: - if((dev->id >= VIA_585) || (dev->id == VIA_694)) - dev->pci_conf[0x71] = (dev->pci_conf[0x71] & ~0xdf) | (val & 0xdf); - else - dev->pci_conf[0x71] = val; - break; - case 0x73: - if (dev->id >= VIA_693A) - dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0x7f) | (val & 0x7f); - else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0xef) | (val & 0xef); - else - dev->pci_conf[0x73] = val; - break; - case 0x74: - if ((dev->id == VIA_693A) || (dev->id == VIA_8601)) - dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xdf) | (val & 0xdf); - else if (dev->id == VIA_694) - dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0x9f) | (val & 0x9f); - else - dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xc0) | (val & 0xc0); - break; - case 0x75: - if (dev->id >= VIA_693A) - dev->pci_conf[0x75] = val; - else - dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0xcf) | (val & 0xcf); - break; - case 0x76: - if (dev->id >= VIA_693A) - dev->pci_conf[0x76] = val; - else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) - dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xb0) | (val & 0xb0); - else - dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xf0) | (val & 0xf0); - break; - case 0x77: - if (dev->id < VIA_693A) - dev->pci_conf[0x77] = (dev->pci_conf[0x77] & ~0xc0) | (val & 0xc0); - break; - case 0x78: - dev->pci_conf[0x78] = (dev->pci_conf[0x78] & ~0xd5) | (val & 0xd5); - break; - case 0x79: - dev->pci_conf[0x79] = (dev->pci_conf[0x79] & ~0xfc) | (val & 0xfc); - break; - case 0x7a: - dev->pci_conf[0x7a] = (dev->pci_conf[0x7a] & ~0x89) | (val & 0x89); - break; - case 0x7e: - if ((dev->id != VIA_8601) || (dev->id != VIA_694)) - dev->pci_conf[0x7e] = (dev->pci_conf[0x7e] & ~0x3f) | (val & 0x3f); - break; + case 0x70: + if ((dev->id >= VIA_693A)) + dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xdf) | (val & 0xdf); + else if (dev->id == VIA_597) + dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xf1) | (val & 0xf1); + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xe3) | (val & 0xe3); + else + dev->pci_conf[0x70] = val; + break; + case 0x71: + if ((dev->id >= VIA_585) || (dev->id == VIA_694)) + dev->pci_conf[0x71] = (dev->pci_conf[0x71] & ~0xdf) | (val & 0xdf); + else + dev->pci_conf[0x71] = val; + break; + case 0x73: + if (dev->id >= VIA_693A) + dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0x7f) | (val & 0x7f); + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0xef) | (val & 0xef); + else + dev->pci_conf[0x73] = val; + break; + case 0x74: + if ((dev->id == VIA_693A) || (dev->id == VIA_8601)) + dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xdf) | (val & 0xdf); + else if (dev->id == VIA_694) + dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0x9f) | (val & 0x9f); + else + dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xc0) | (val & 0xc0); + break; + case 0x75: + if (dev->id >= VIA_693A) + dev->pci_conf[0x75] = val; + else + dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0xcf) | (val & 0xcf); + break; + case 0x76: + if (dev->id >= VIA_693A) + dev->pci_conf[0x76] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xb0) | (val & 0xb0); + else + dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xf0) | (val & 0xf0); + break; + case 0x77: + if (dev->id < VIA_693A) + dev->pci_conf[0x77] = (dev->pci_conf[0x77] & ~0xc0) | (val & 0xc0); + break; + case 0x78: + dev->pci_conf[0x78] = (dev->pci_conf[0x78] & ~0xd5) | (val & 0xd5); + break; + case 0x79: + dev->pci_conf[0x79] = (dev->pci_conf[0x79] & ~0xfc) | (val & 0xfc); + break; + case 0x7a: + dev->pci_conf[0x7a] = (dev->pci_conf[0x7a] & ~0x89) | (val & 0x89); + break; + case 0x7e: + if ((dev->id != VIA_8601) || (dev->id != VIA_694)) + dev->pci_conf[0x7e] = (dev->pci_conf[0x7e] & ~0x3f) | (val & 0x3f); + break; - case 0x80: - dev->pci_conf[0x80] = (dev->pci_conf[0x80] & ~0x8f) | (val & 0x8f); - break; - case 0x84: - /* The datasheet first mentions 7-0 but then says 3-0 are reserved - - - minimum of 16 MB for the graphics aperture? 8601 datasheet doesn't refer it. */ - if(dev->id >= VIA_693A) - dev->pci_conf[0x84] = val; - else - dev->pci_conf[0x84] = (dev->pci_conf[0x84] & ~0xf0) | (val & 0xf0); - apollo_agp_map(dev); - break; - case 0x88: - if((dev->id == VIA_693A) || (dev->id == VIA_8601)) - dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x06) | (val & 0x06); - else - dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x07) | (val & 0x07); - apollo_agp_map(dev); - break; - case 0x89: - dev->pci_conf[0x89] = val & 0xf0; - apollo_agp_map(dev); - break; - case 0x8a: - case 0x8b: - dev->pci_conf[addr] = val; - apollo_agp_map(dev); - break; + case 0x80: + dev->pci_conf[0x80] = (dev->pci_conf[0x80] & ~0x8f) | (val & 0x8f); + break; + case 0x84: + /* The datasheet first mentions 7-0 but then says 3-0 are reserved - + - minimum of 16 MB for the graphics aperture? 8601 datasheet doesn't refer it. */ + if (dev->id >= VIA_693A) + dev->pci_conf[0x84] = val; + else + dev->pci_conf[0x84] = (dev->pci_conf[0x84] & ~0xf0) | (val & 0xf0); + apollo_agp_map(dev); + break; + case 0x88: + if ((dev->id == VIA_693A) || (dev->id == VIA_8601)) + dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x06) | (val & 0x06); + else + dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x07) | (val & 0x07); + apollo_agp_map(dev); + break; + case 0x89: + dev->pci_conf[0x89] = val & 0xf0; + apollo_agp_map(dev); + break; + case 0x8a: + case 0x8b: + dev->pci_conf[addr] = val; + apollo_agp_map(dev); + break; - case 0xa8: - if(dev->id == VIA_694) - dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x33) | (val & 0x33); - else - dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x03) | (val & 0x03); - break; - case 0xa9: - dev->pci_conf[0xa9] = (dev->pci_conf[0xa9] & ~0x03) | (val & 0x03); - break; - case 0xac: - if(dev->id == VIA_8601) - dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x7f) | (val & 0x7f); - else - dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f); - break; - case 0xad: - dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f); - break; + case 0xa8: + if (dev->id == VIA_694) + dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x33) | (val & 0x33); + else + dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x03) | (val & 0x03); + break; + case 0xa9: + dev->pci_conf[0xa9] = (dev->pci_conf[0xa9] & ~0x03) | (val & 0x03); + break; + case 0xac: + if (dev->id == VIA_8601) + dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x7f) | (val & 0x7f); + else + dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f); + break; + case 0xad: + dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f); + break; - case 0xfc: - if (dev->id == VIA_8601) - dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x03) | (val & 0x03); - else if (dev->id > VIA_597) - dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x01) | (val & 0x01); - break; + case 0xfc: + if (dev->id == VIA_8601) + dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x03) | (val & 0x03); + else if (dev->id > VIA_597) + dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x01) | (val & 0x01); + break; - case 0xfd: - if (dev->id == VIA_8601) - dev->pci_conf[0xfd] = (dev->pci_conf[0xfd] & ~0x07) | (val & 0x07); - else - dev->pci_conf[0xfd] = val; - break; + case 0xfd: + if (dev->id == VIA_8601) + dev->pci_conf[0xfd] = (dev->pci_conf[0xfd] & ~0x07) | (val & 0x07); + else + dev->pci_conf[0xfd] = val; + break; - default: - dev->pci_conf[addr] = val; - break; + default: + dev->pci_conf[addr] = val; + break; } } - static uint8_t via_apollo_read(int func, int addr, void *priv) { via_apollo_t *dev = (via_apollo_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; - switch(func) { + switch (func) { case 0: - ret = dev->pci_conf[addr]; - break; + ret = dev->pci_conf[addr]; + break; } return ret; } - static void via_apollo_write(int func, int addr, uint8_t val, void *priv) { - switch(func) { - case 0: - via_apollo_host_bridge_write(func, addr, val, priv); - break; + switch (func) { + case 0: + via_apollo_host_bridge_write(func, addr, val, priv); + break; } } - static void via_apollo_reset(void *priv) { @@ -698,7 +696,6 @@ via_apollo_reset(void *priv) via_apollo_write(0, 0x63, 0x00, priv); } - static void * via_apollo_init(const device_t *info) { @@ -707,41 +704,41 @@ via_apollo_init(const device_t *info) dev->smram = smram_add(); if (dev->id != VIA_8601) - apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev); dev->id = info->local; switch (dev->id) { - case VIA_597: - device_add(&via_vp3_agp_device); - break; + case VIA_597: + device_add(&via_vp3_agp_device); + break; - case VIA_691: - device_add(&via_apro_agp_device); - break; + case VIA_691: + device_add(&via_apro_agp_device); + break; - case VIA_8601: - device_add(&via_vt8601_agp_device); - break; + case VIA_8601: + device_add(&via_vt8601_agp_device); + break; - case VIA_598: - case VIA_693A: - case VIA_694: - device_add(&via_mvp3_agp_device); - break; + case VIA_598: + case VIA_693A: + case VIA_694: + device_add(&via_mvp3_agp_device); + break; } if (dev->id >= VIA_597) - dev->agpgart = device_add(&agpgart_device); + dev->agpgart = device_add(&agpgart_device); if ((dev->id >= VIA_694) && (dev->id != VIA_8601)) - dev->drb_unit = 16; + dev->drb_unit = 16; else if (dev->id >= VIA_597) - dev->drb_unit = 8; + dev->drb_unit = 8; else - dev->drb_unit = 4; + dev->drb_unit = 4; via_apollo_setup(dev); via_apollo_reset(dev); @@ -749,7 +746,6 @@ via_apollo_init(const device_t *info) return dev; } - static void via_apollo_close(void *priv) { @@ -761,113 +757,113 @@ via_apollo_close(void *priv) } const device_t via_vpx_device = { - .name = "VIA Apollo VPX", + .name = "VIA Apollo VPX", .internal_name = "via_vpx", - .flags = DEVICE_PCI, - .local = VIA_585, /*VT82C585*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_585, /*VT82C585*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t amd640_device = { - .name = "AMD 640 System Controller", + .name = "AMD 640 System Controller", .internal_name = "amd640", - .flags = DEVICE_PCI, - .local = VIA_595, /*VT82C595*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_595, /*VT82C595*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vp3_device = { - .name = "VIA Apollo VP3", + .name = "VIA Apollo VP3", .internal_name = "via_vp3", - .flags = DEVICE_PCI, - .local = VIA_597, /*VT82C597*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_597, /*VT82C597*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_mvp3_device = { - .name = "VIA Apollo MVP3", + .name = "VIA Apollo MVP3", .internal_name = "via_mvp3", - .flags = DEVICE_PCI, - .local = VIA_598, /*VT82C598MVP*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_598, /*VT82C598MVP*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_apro_device = { - .name = "VIA Apollo Pro", + .name = "VIA Apollo Pro", .internal_name = "via_apro", - .flags = DEVICE_PCI, - .local = VIA_691, /*VT82C691*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_691, /*VT82C691*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_apro133_device = { - .name = "VIA Apollo Pro133", + .name = "VIA Apollo Pro133", .internal_name = "via_apro133", - .flags = DEVICE_PCI, - .local = VIA_693A, /*VT82C693A*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_693A, /*VT82C693A*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_apro133a_device = { - .name = "VIA Apollo Pro133A", + .name = "VIA Apollo Pro133A", .internal_name = "via_apro_133a", - .flags = DEVICE_PCI, - .local = VIA_694, /*VT82C694X*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_694, /*VT82C694X*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt8601_device = { - .name = "VIA Apollo ProMedia", + .name = "VIA Apollo ProMedia", .internal_name = "via_vt8601", - .flags = DEVICE_PCI, - .local = VIA_8601, /*VT8601*/ - .init = via_apollo_init, - .close = via_apollo_close, - .reset = via_apollo_reset, + .flags = DEVICE_PCI, + .local = VIA_8601, /*VT8601*/ + .init = via_apollo_init, + .close = via_apollo_close, + .reset = via_apollo_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/via_pipc.c b/src/chipset/via_pipc.c index b8c06b9f4..48cae7e41 100644 --- a/src/chipset/via_pipc.c +++ b/src/chipset/via_pipc.c @@ -58,14 +58,13 @@ /* Most revision numbers (PCI-ISA bridge or otherwise) were lifted from PCI device listings on forums, as VIA's datasheets are not very helpful regarding those. */ -#define VIA_PIPC_586A 0x05862500 -#define VIA_PIPC_586B 0x05864700 -#define VIA_PIPC_596A 0x05960900 -#define VIA_PIPC_596B 0x05962300 -#define VIA_PIPC_686A 0x06861400 -#define VIA_PIPC_686B 0x06864000 -#define VIA_PIPC_8231 0x82311000 - +#define VIA_PIPC_586A 0x05862500 +#define VIA_PIPC_586B 0x05864700 +#define VIA_PIPC_596A 0x05960900 +#define VIA_PIPC_596B 0x05962300 +#define VIA_PIPC_686A 0x06861400 +#define VIA_PIPC_686B 0x06864000 +#define VIA_PIPC_8231 0x82311000 enum { TRAP_DRQ = 0, @@ -106,62 +105,58 @@ enum { typedef struct { struct _pipc_ *dev; - void *trap; - uint32_t *sts_reg, *en_reg, mask; + void *trap; + uint32_t *sts_reg, *en_reg, mask; } pipc_io_trap_t; typedef struct _pipc_ { - uint32_t local; - uint8_t max_func, max_pcs; + uint32_t local; + uint8_t max_func, max_pcs; - uint8_t pci_isa_regs[256], - ide_regs[256], - usb_regs[2][256], - power_regs[256], - ac97_regs[2][256], fmnmi_regs[4]; + uint8_t pci_isa_regs[256], + ide_regs[256], + usb_regs[2][256], + power_regs[256], + ac97_regs[2][256], fmnmi_regs[4]; - sff8038i_t *bm[2]; - nvr_t *nvr; - int nvr_enabled, slot; - ddma_t *ddma; + sff8038i_t *bm[2]; + nvr_t *nvr; + int nvr_enabled, slot; + ddma_t *ddma; smbus_piix4_t *smbus; - usb_t *usb[2]; + usb_t *usb[2]; - acpi_t *acpi; + acpi_t *acpi; pipc_io_trap_t io_traps[TRAP_MAX]; - void *gameport, *ac97, *sio, *hwm; - sb_t *sb; - uint16_t midigame_base, sb_base, fmnmi_base; + void *gameport, *ac97, *sio, *hwm; + sb_t *sb; + uint16_t midigame_base, sb_base, fmnmi_base; } pipc_t; - #ifdef ENABLE_PIPC_LOG int pipc_do_log = ENABLE_PIPC_LOG; - static void pipc_log(const char *fmt, ...) { va_list ap; if (pipc_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define pipc_log(fmt, ...) +# define pipc_log(fmt, ...) #endif - -static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem); -static void pipc_codec_handlers(pipc_t *dev, uint8_t modem); -static void pipc_sb_handlers(pipc_t *dev, uint8_t modem); -static uint8_t pipc_read(int func, int addr, void *priv); -static void pipc_write(int func, int addr, uint8_t val, void *priv); - +static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem); +static void pipc_codec_handlers(pipc_t *dev, uint8_t modem); +static void pipc_sb_handlers(pipc_t *dev, uint8_t modem); +static uint8_t pipc_read(int func, int addr, void *priv); +static void pipc_write(int func, int addr, uint8_t val, void *priv); static void pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv) @@ -169,32 +164,30 @@ pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *pri pipc_io_trap_t *trap = (pipc_io_trap_t *) priv; if (*(trap->en_reg) & trap->mask) { - *(trap->sts_reg) |= trap->mask; - trap->dev->acpi->regs.glbsts |= 0x0001; - if (trap->dev->acpi->regs.glben & 0x0001) - acpi_raise_smi(trap->dev->acpi, 1); + *(trap->sts_reg) |= trap->mask; + trap->dev->acpi->regs.glbsts |= 0x0001; + if (trap->dev->acpi->regs.glben & 0x0001) + acpi_raise_smi(trap->dev->acpi, 1); } } - static void pipc_io_trap_glb(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv) { pipc_io_trap_t *trap = (pipc_io_trap_t *) priv; if (*(trap->en_reg) & trap->mask) { - *(trap->sts_reg) |= trap->mask; - if (trap->dev->local >= VIA_PIPC_686A) { - if (write) - trap->dev->acpi->regs.extsmi_val |= 0x1000; - else - trap->dev->acpi->regs.extsmi_val &= ~0x1000; - } - acpi_raise_smi(trap->dev->acpi, 1); + *(trap->sts_reg) |= trap->mask; + if (trap->dev->local >= VIA_PIPC_686A) { + if (write) + trap->dev->acpi->regs.extsmi_val |= 0x1000; + else + trap->dev->acpi->regs.extsmi_val &= ~0x1000; + } + acpi_raise_smi(trap->dev->acpi, 1); } } - static void pipc_reset_hard(void *priv) { @@ -202,7 +195,7 @@ pipc_reset_hard(void *priv) pipc_log("PIPC: reset_hard()\n"); - pipc_t *dev = (pipc_t *) priv; + pipc_t *dev = (pipc_t *) priv; uint16_t old_base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8); sff_bus_master_reset(dev->bm[0], old_base); @@ -215,7 +208,8 @@ pipc_reset_hard(void *priv) memset(dev->ac97_regs, 0, 512); /* PCI-ISA bridge registers. */ - dev->pci_isa_regs[0x00] = 0x06; dev->pci_isa_regs[0x01] = 0x11; + dev->pci_isa_regs[0x00] = 0x06; + dev->pci_isa_regs[0x01] = 0x11; dev->pci_isa_regs[0x02] = dev->local >> 16; dev->pci_isa_regs[0x03] = dev->local >> 24; dev->pci_isa_regs[0x04] = (dev->local <= VIA_PIPC_586B) ? 0x0f : 0x87; @@ -232,12 +226,12 @@ pipc_reset_hard(void *priv) dev->pci_isa_regs[0x50] = (dev->local >= VIA_PIPC_686A) ? 0x0e : 0x24; /* 686A/B default value does not line up with default bits */ dev->pci_isa_regs[0x59] = 0x04; if (dev->local >= VIA_PIPC_686A) - dev->pci_isa_regs[0x5a] = dev->pci_isa_regs[0x5f] = 0x04; + dev->pci_isa_regs[0x5a] = dev->pci_isa_regs[0x5f] = 0x04; dma_e = 0x00; for (i = 0; i < 8; i++) { - dma[i].ab &= 0xffff000f; - dma[i].ac &= 0xffff000f; + dma[i].ab &= 0xffff000f; + dma[i].ac &= 0xffff000f; } pic_set_shadow(0); @@ -246,229 +240,250 @@ pipc_reset_hard(void *priv) /* IDE registers. */ dev->max_func++; - dev->ide_regs[0x00] = 0x06; dev->ide_regs[0x01] = 0x11; - dev->ide_regs[0x02] = 0x71; dev->ide_regs[0x03] = 0x05; + dev->ide_regs[0x00] = 0x06; + dev->ide_regs[0x01] = 0x11; + dev->ide_regs[0x02] = 0x71; + dev->ide_regs[0x03] = 0x05; dev->ide_regs[0x04] = 0x80; - dev->ide_regs[0x06] = (dev->local == VIA_PIPC_686A) ? 0x90 : 0x80; dev->ide_regs[0x07] = 0x02; + dev->ide_regs[0x06] = (dev->local == VIA_PIPC_686A) ? 0x90 : 0x80; + dev->ide_regs[0x07] = 0x02; dev->ide_regs[0x08] = (dev->local == VIA_PIPC_596B) ? 0x10 : 0x06; /* only 596B has rev 0x10? */ dev->ide_regs[0x09] = 0x85; dev->ide_regs[0x0a] = 0x01; dev->ide_regs[0x0b] = 0x01; - dev->ide_regs[0x10] = 0xf1; dev->ide_regs[0x11] = 0x01; - dev->ide_regs[0x14] = 0xf5; dev->ide_regs[0x15] = 0x03; - dev->ide_regs[0x18] = 0x71; dev->ide_regs[0x19] = 0x01; - dev->ide_regs[0x1c] = 0x75; dev->ide_regs[0x1d] = 0x03; - dev->ide_regs[0x20] = 0x01; dev->ide_regs[0x21] = 0xcc; + dev->ide_regs[0x10] = 0xf1; + dev->ide_regs[0x11] = 0x01; + dev->ide_regs[0x14] = 0xf5; + dev->ide_regs[0x15] = 0x03; + dev->ide_regs[0x18] = 0x71; + dev->ide_regs[0x19] = 0x01; + dev->ide_regs[0x1c] = 0x75; + dev->ide_regs[0x1d] = 0x03; + dev->ide_regs[0x20] = 0x01; + dev->ide_regs[0x21] = 0xcc; if (dev->local >= VIA_PIPC_686A) - dev->ide_regs[0x34] = 0xc0; + dev->ide_regs[0x34] = 0xc0; dev->ide_regs[0x3c] = 0x0e; if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[0x40] = 0x04; + dev->ide_regs[0x40] = 0x04; dev->ide_regs[0x41] = (dev->local == VIA_PIPC_686B) ? 0x06 : 0x02; dev->ide_regs[0x42] = 0x09; dev->ide_regs[0x43] = (dev->local >= VIA_PIPC_686A) ? 0x0a : 0x3a; dev->ide_regs[0x44] = 0x68; if (dev->local == VIA_PIPC_686B) - dev->ide_regs[0x45] = 0x20; + dev->ide_regs[0x45] = 0x20; else if (dev->local >= VIA_PIPC_8231) - dev->ide_regs[0x45] = 0x03; + dev->ide_regs[0x45] = 0x03; dev->ide_regs[0x46] = 0xc0; - dev->ide_regs[0x48] = 0xa8; dev->ide_regs[0x49] = 0xa8; - dev->ide_regs[0x4a] = 0xa8; dev->ide_regs[0x4b] = 0xa8; + dev->ide_regs[0x48] = 0xa8; + dev->ide_regs[0x49] = 0xa8; + dev->ide_regs[0x4a] = 0xa8; + dev->ide_regs[0x4b] = 0xa8; dev->ide_regs[0x4c] = 0xff; if (dev->local != VIA_PIPC_686B) - dev->ide_regs[0x4e] = dev->ide_regs[0x4f] = 0xff; + dev->ide_regs[0x4e] = dev->ide_regs[0x4f] = 0xff; dev->ide_regs[0x50] = dev->ide_regs[0x51] = dev->ide_regs[0x52] = dev->ide_regs[0x53] = ((dev->local == VIA_PIPC_686A) || (dev->local == VIA_PIPC_686B)) ? 0x07 : 0x03; if (dev->local >= VIA_PIPC_596A) - dev->ide_regs[0x54] = ((dev->local == VIA_PIPC_686A) || (dev->local == VIA_PIPC_686B)) ? 0x04 : 0x06; + dev->ide_regs[0x54] = ((dev->local == VIA_PIPC_686A) || (dev->local == VIA_PIPC_686B)) ? 0x04 : 0x06; dev->ide_regs[0x61] = 0x02; dev->ide_regs[0x69] = 0x02; if (dev->local >= VIA_PIPC_686A) { - dev->ide_regs[0xc0] = 0x01; - dev->ide_regs[0xc2] = 0x02; + dev->ide_regs[0xc0] = 0x01; + dev->ide_regs[0xc2] = 0x02; } /* USB registers. */ for (i = 0; i <= (dev->local >= VIA_PIPC_686A); i++) { - dev->max_func++; - dev->usb_regs[i][0x00] = 0x06; dev->usb_regs[i][0x01] = 0x11; - dev->usb_regs[i][0x02] = 0x38; dev->usb_regs[i][0x03] = 0x30; - dev->usb_regs[i][0x04] = 0x00; dev->usb_regs[i][0x05] = 0x00; - dev->usb_regs[i][0x06] = 0x00; dev->usb_regs[i][0x07] = 0x02; - switch (dev->local) { - case VIA_PIPC_586A: - case VIA_PIPC_586B: - case VIA_PIPC_596A: - dev->usb_regs[i][0x08] = 0x02; - break; + dev->max_func++; + dev->usb_regs[i][0x00] = 0x06; + dev->usb_regs[i][0x01] = 0x11; + dev->usb_regs[i][0x02] = 0x38; + dev->usb_regs[i][0x03] = 0x30; + dev->usb_regs[i][0x04] = 0x00; + dev->usb_regs[i][0x05] = 0x00; + dev->usb_regs[i][0x06] = 0x00; + dev->usb_regs[i][0x07] = 0x02; + switch (dev->local) { + case VIA_PIPC_586A: + case VIA_PIPC_586B: + case VIA_PIPC_596A: + dev->usb_regs[i][0x08] = 0x02; + break; - case VIA_PIPC_596B: - dev->usb_regs[i][0x08] = 0x08; - break; + case VIA_PIPC_596B: + dev->usb_regs[i][0x08] = 0x08; + break; - case VIA_PIPC_686A: - dev->usb_regs[i][0x08] = 0x06; - break; + case VIA_PIPC_686A: + dev->usb_regs[i][0x08] = 0x06; + break; - case VIA_PIPC_686B: - dev->usb_regs[i][0x08] = 0x1a; - break; + case VIA_PIPC_686B: + dev->usb_regs[i][0x08] = 0x1a; + break; - case VIA_PIPC_8231: - dev->usb_regs[i][0x08] = 0x1e; - break; - } + case VIA_PIPC_8231: + dev->usb_regs[i][0x08] = 0x1e; + break; + } - dev->usb_regs[i][0x0a] = 0x03; - dev->usb_regs[i][0x0b] = 0x0c; - dev->usb_regs[i][0x0d] = 0x16; - dev->usb_regs[i][0x20] = 0x01; - dev->usb_regs[i][0x21] = 0x03; - if (dev->local == VIA_PIPC_686B) - dev->usb_regs[i][0x34] = 0x80; - dev->usb_regs[i][0x3d] = 0x04; + dev->usb_regs[i][0x0a] = 0x03; + dev->usb_regs[i][0x0b] = 0x0c; + dev->usb_regs[i][0x0d] = 0x16; + dev->usb_regs[i][0x20] = 0x01; + dev->usb_regs[i][0x21] = 0x03; + if (dev->local == VIA_PIPC_686B) + dev->usb_regs[i][0x34] = 0x80; + dev->usb_regs[i][0x3d] = 0x04; - dev->usb_regs[i][0x60] = 0x10; - if (dev->local >= VIA_PIPC_686A) { - dev->usb_regs[i][0x80] = 0x01; - dev->usb_regs[i][0x82] = 0x02; - } - dev->usb_regs[i][0xc1] = 0x20; + dev->usb_regs[i][0x60] = 0x10; + if (dev->local >= VIA_PIPC_686A) { + dev->usb_regs[i][0x80] = 0x01; + dev->usb_regs[i][0x82] = 0x02; + } + dev->usb_regs[i][0xc1] = 0x20; } /* Power management registers. */ if (dev->acpi) { - dev->max_func++; - dev->power_regs[0x00] = 0x06; dev->power_regs[0x01] = 0x11; - if (dev->local >= VIA_PIPC_8231) { - /* The VT8231 preliminary datasheet lists *two* inaccurate - device IDs (3068 and 3057). Real dumps have 8235. */ - dev->power_regs[0x02] = 0x35; dev->power_regs[0x03] = 0x82; - } else { - if (dev->local <= VIA_PIPC_586B) - dev->power_regs[0x02] = 0x40; - else if (dev->local <= VIA_PIPC_596B) - dev->power_regs[0x02] = 0x50; - else - dev->power_regs[0x02] = 0x57; - dev->power_regs[0x03] = 0x30; - } - dev->power_regs[0x04] = 0x00; dev->power_regs[0x05] = 0x00; - dev->power_regs[0x06] = (dev->local == VIA_PIPC_686B) ? 0x90 : 0x80; dev->power_regs[0x07] = 0x02; - switch (dev->local) { - case VIA_PIPC_586B: - case VIA_PIPC_686A: - case VIA_PIPC_8231: - dev->power_regs[0x08] = 0x10; - break; + dev->max_func++; + dev->power_regs[0x00] = 0x06; + dev->power_regs[0x01] = 0x11; + if (dev->local >= VIA_PIPC_8231) { + /* The VT8231 preliminary datasheet lists *two* inaccurate + device IDs (3068 and 3057). Real dumps have 8235. */ + dev->power_regs[0x02] = 0x35; + dev->power_regs[0x03] = 0x82; + } else { + if (dev->local <= VIA_PIPC_586B) + dev->power_regs[0x02] = 0x40; + else if (dev->local <= VIA_PIPC_596B) + dev->power_regs[0x02] = 0x50; + else + dev->power_regs[0x02] = 0x57; + dev->power_regs[0x03] = 0x30; + } + dev->power_regs[0x04] = 0x00; + dev->power_regs[0x05] = 0x00; + dev->power_regs[0x06] = (dev->local == VIA_PIPC_686B) ? 0x90 : 0x80; + dev->power_regs[0x07] = 0x02; + switch (dev->local) { + case VIA_PIPC_586B: + case VIA_PIPC_686A: + case VIA_PIPC_8231: + dev->power_regs[0x08] = 0x10; + break; - case VIA_PIPC_596A: - dev->power_regs[0x08] = 0x20; - break; + case VIA_PIPC_596A: + dev->power_regs[0x08] = 0x20; + break; - case VIA_PIPC_596B: - dev->power_regs[0x08] = 0x30; - break; + case VIA_PIPC_596B: + dev->power_regs[0x08] = 0x30; + break; - case VIA_PIPC_686B: - dev->power_regs[0x08] = 0x40; - break; - } - if (dev->local == VIA_PIPC_686B) - dev->power_regs[0x34] = 0x68; - dev->power_regs[0x40] = 0x20; + case VIA_PIPC_686B: + dev->power_regs[0x08] = 0x40; + break; + } + if (dev->local == VIA_PIPC_686B) + dev->power_regs[0x34] = 0x68; + dev->power_regs[0x40] = 0x20; - dev->power_regs[0x42] = 0x50; - dev->power_regs[0x48] = 0x01; + dev->power_regs[0x42] = 0x50; + dev->power_regs[0x48] = 0x01; - if (dev->local == VIA_PIPC_686B) { - dev->power_regs[0x68] = 0x01; - dev->power_regs[0x6a] = 0x02; - } + if (dev->local == VIA_PIPC_686B) { + dev->power_regs[0x68] = 0x01; + dev->power_regs[0x6a] = 0x02; + } - if (dev->local >= VIA_PIPC_686A) - dev->power_regs[0x70] = 0x01; + if (dev->local >= VIA_PIPC_686A) + dev->power_regs[0x70] = 0x01; - if (dev->local == VIA_PIPC_596A) - dev->power_regs[0x80] = 0x01; - else if (dev->local >= VIA_PIPC_596B) - dev->power_regs[0x90] = 0x01; + if (dev->local == VIA_PIPC_596A) + dev->power_regs[0x80] = 0x01; + else if (dev->local >= VIA_PIPC_596B) + dev->power_regs[0x90] = 0x01; - /* Set up PCS I/O traps. */ - pipc_io_trap_t *trap; - for (i = 0; i <= dev->max_pcs; i++) { - trap = &dev->io_traps[TRAP_GR0 + i]; - trap->dev = dev; - trap->trap = io_trap_add(pipc_io_trap_glb, trap); - if (i & 2) { - trap->sts_reg = (uint32_t *) &dev->acpi->regs.extiotrapsts; - trap->en_reg = (uint32_t *) &dev->acpi->regs.extiotrapen; - trap->mask = 0x01 << (i & 1); - } else { - trap->sts_reg = &dev->acpi->regs.glbsts; - trap->en_reg = &dev->acpi->regs.glben; - trap->mask = 0x4000 << i; - } - } + /* Set up PCS I/O traps. */ + pipc_io_trap_t *trap; + for (i = 0; i <= dev->max_pcs; i++) { + trap = &dev->io_traps[TRAP_GR0 + i]; + trap->dev = dev; + trap->trap = io_trap_add(pipc_io_trap_glb, trap); + if (i & 2) { + trap->sts_reg = (uint32_t *) &dev->acpi->regs.extiotrapsts; + trap->en_reg = (uint32_t *) &dev->acpi->regs.extiotrapen; + trap->mask = 0x01 << (i & 1); + } else { + trap->sts_reg = &dev->acpi->regs.glbsts; + trap->en_reg = &dev->acpi->regs.glben; + trap->mask = 0x4000 << i; + } + } } /* AC97/MC97 registers. */ if (dev->local >= VIA_PIPC_686A) { - for (i = 0; i <= 1; i++) { - dev->max_func++; - dev->ac97_regs[i][0x00] = 0x06; dev->ac97_regs[i][0x01] = 0x11; - dev->ac97_regs[i][0x02] = 0x58 + (0x10 * i); dev->ac97_regs[i][0x03] = 0x30; - dev->ac97_regs[i][0x06] = 0x10 * (1 - i); dev->ac97_regs[i][0x07] = 0x02; - switch (dev->local) { - case VIA_PIPC_686A: - dev->ac97_regs[i][0x08] = (i == 0) ? 0x12 : 0x01; - break; + for (i = 0; i <= 1; i++) { + dev->max_func++; + dev->ac97_regs[i][0x00] = 0x06; + dev->ac97_regs[i][0x01] = 0x11; + dev->ac97_regs[i][0x02] = 0x58 + (0x10 * i); + dev->ac97_regs[i][0x03] = 0x30; + dev->ac97_regs[i][0x06] = 0x10 * (1 - i); + dev->ac97_regs[i][0x07] = 0x02; + switch (dev->local) { + case VIA_PIPC_686A: + dev->ac97_regs[i][0x08] = (i == 0) ? 0x12 : 0x01; + break; - case VIA_PIPC_686B: - dev->ac97_regs[i][0x08] = (i == 0) ? 0x50 : 0x30; - break; + case VIA_PIPC_686B: + dev->ac97_regs[i][0x08] = (i == 0) ? 0x50 : 0x30; + break; - case VIA_PIPC_8231: - dev->ac97_regs[i][0x08] = (i == 0) ? 0x40 : 0x20; - break; - } + case VIA_PIPC_8231: + dev->ac97_regs[i][0x08] = (i == 0) ? 0x40 : 0x20; + break; + } - if (i == 0) { - dev->ac97_regs[i][0x0a] = 0x01; - dev->ac97_regs[i][0x0b] = 0x04; - } else { - dev->ac97_regs[i][0x0a] = 0x80; - dev->ac97_regs[i][0x0b] = 0x07; - } + if (i == 0) { + dev->ac97_regs[i][0x0a] = 0x01; + dev->ac97_regs[i][0x0b] = 0x04; + } else { + dev->ac97_regs[i][0x0a] = 0x80; + dev->ac97_regs[i][0x0b] = 0x07; + } - dev->ac97_regs[i][0x10] = 0x01; - if (i == 0) { - dev->ac97_regs[i][0x14] = 0x01; - dev->ac97_regs[i][0x18] = 0x01; - } - dev->ac97_regs[i][0x1c] = 0x01; + dev->ac97_regs[i][0x10] = 0x01; + if (i == 0) { + dev->ac97_regs[i][0x14] = 0x01; + dev->ac97_regs[i][0x18] = 0x01; + } + dev->ac97_regs[i][0x1c] = 0x01; - dev->ac97_regs[i][0x3d] = 0x03; + dev->ac97_regs[i][0x3d] = 0x03; - if (i == 0) - dev->ac97_regs[i][0x40] = 0x01; + if (i == 0) + dev->ac97_regs[i][0x40] = 0x01; - dev->ac97_regs[i][0x43] = 0x1c; - dev->ac97_regs[i][0x48] = 0x01; - dev->ac97_regs[i][0x4b] = 0x02; + dev->ac97_regs[i][0x43] = 0x1c; + dev->ac97_regs[i][0x48] = 0x01; + dev->ac97_regs[i][0x4b] = 0x02; - pipc_sgd_handlers(dev, i); - pipc_codec_handlers(dev, i); - pipc_sb_handlers(dev, i); - } + pipc_sgd_handlers(dev, i); + pipc_codec_handlers(dev, i); + pipc_sb_handlers(dev, i); + } } if (dev->gameport) - gameport_remap(dev->gameport, 0x200); + gameport_remap(dev->gameport, 0x200); pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); @@ -476,10 +491,10 @@ pipc_reset_hard(void *priv) pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); if (dev->local <= VIA_PIPC_586B) { - pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); - pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); - if (dev->local == VIA_PIPC_586B) - pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED); + pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); + if (dev->local == VIA_PIPC_586B) + pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED); } ide_pri_disable(); @@ -489,7 +504,6 @@ pipc_reset_hard(void *priv) nvr_via_wp_set(0x00, 0x0d, dev->nvr); } - static void pipc_ide_handlers(pipc_t *dev) { @@ -499,44 +513,43 @@ pipc_ide_handlers(pipc_t *dev) ide_sec_disable(); if (dev->ide_regs[0x09] & 0x01) { - main = (dev->ide_regs[0x11] << 8) | (dev->ide_regs[0x10] & 0xf8); - side = ((dev->ide_regs[0x15] << 8) | (dev->ide_regs[0x14] & 0xfc)) + 2; + main = (dev->ide_regs[0x11] << 8) | (dev->ide_regs[0x10] & 0xf8); + side = ((dev->ide_regs[0x15] << 8) | (dev->ide_regs[0x14] & 0xfc)) + 2; } else { - main = 0x1f0; - side = 0x3f6; + main = 0x1f0; + side = 0x3f6; } ide_set_base(0, main); ide_set_side(0, side); if (dev->ide_regs[0x09] & 0x04) { - main = (dev->ide_regs[0x19] << 8) | (dev->ide_regs[0x18] & 0xf8); - side = ((dev->ide_regs[0x1d] << 8) | (dev->ide_regs[0x1c] & 0xfc)) + 2; + main = (dev->ide_regs[0x19] << 8) | (dev->ide_regs[0x18] & 0xf8); + side = ((dev->ide_regs[0x1d] << 8) | (dev->ide_regs[0x1c] & 0xfc)) + 2; } else { - main = 0x170; - side = 0x376; + main = 0x170; + side = 0x376; } ide_set_base(1, main); ide_set_side(1, side); if (dev->ide_regs[0x04] & PCI_COMMAND_IO) { - if (dev->ide_regs[0x40] & 0x02) - ide_pri_enable(); - if (dev->ide_regs[0x40] & 0x01) - ide_sec_enable(); + if (dev->ide_regs[0x40] & 0x02) + ide_pri_enable(); + if (dev->ide_regs[0x40] & 0x01) + ide_sec_enable(); } } - static void pipc_ide_irqs(pipc_t *dev) { int irq_mode[2] = { 0, 0 }; if (dev->ide_regs[0x09] & 0x01) - irq_mode[0] = (dev->ide_regs[0x3d] & 0x01); + irq_mode[0] = (dev->ide_regs[0x3d] & 0x01); if (dev->ide_regs[0x09] & 0x04) - irq_mode[1] = (dev->ide_regs[0x3d] & 0x01); + irq_mode[1] = (dev->ide_regs[0x3d] & 0x01); sff_set_irq_mode(dev->bm[0], 0, irq_mode[0]); sff_set_irq_mode(dev->bm[0], 1, irq_mode[1]); @@ -545,7 +558,6 @@ pipc_ide_irqs(pipc_t *dev) sff_set_irq_mode(dev->bm[1], 1, irq_mode[1]); } - static void pipc_bus_master_handlers(pipc_t *dev) { @@ -555,60 +567,57 @@ pipc_bus_master_handlers(pipc_t *dev) sff_bus_master_handler(dev->bm[1], (dev->ide_regs[0x04] & 1), base + 8); } - static void pipc_pcs_update(pipc_t *dev) { - uint8_t i, io_base_reg, io_mask_reg, io_mask_shift, enable; + uint8_t i, io_base_reg, io_mask_reg, io_mask_shift, enable; uint16_t io_base, io_mask; for (i = 0; i <= dev->max_pcs; i++) { - if (i & 2) { - io_base_reg = 0x8c; - io_mask_reg = 0x8a; - } else { - io_base_reg = 0x78; - io_mask_reg = 0x80; - } - io_base_reg |= (i & 1) << 1; - io_mask_shift = (i & 1) << 2; + if (i & 2) { + io_base_reg = 0x8c; + io_mask_reg = 0x8a; + } else { + io_base_reg = 0x78; + io_mask_reg = 0x80; + } + io_base_reg |= (i & 1) << 1; + io_mask_shift = (i & 1) << 2; - if (dev->local <= VIA_PIPC_596B) - enable = dev->pci_isa_regs[0x76] & (0x10 << i); - else - enable = dev->pci_isa_regs[0x8b] & (0x01 << i); + if (dev->local <= VIA_PIPC_596B) + enable = dev->pci_isa_regs[0x76] & (0x10 << i); + else + enable = dev->pci_isa_regs[0x8b] & (0x01 << i); - io_base = dev->pci_isa_regs[io_base_reg] | (dev->pci_isa_regs[io_base_reg | 1] << 8); - io_mask = (dev->pci_isa_regs[io_mask_reg] >> io_mask_shift) & 0x000f; + io_base = dev->pci_isa_regs[io_base_reg] | (dev->pci_isa_regs[io_base_reg | 1] << 8); + io_mask = (dev->pci_isa_regs[io_mask_reg] >> io_mask_shift) & 0x000f; - pipc_log("PIPC: Mapping PCS%d to %04X-%04X (enable %d)\n", i, io_base, io_base + io_mask, enable); - io_trap_remap(dev->io_traps[TRAP_GR0 + i].trap, enable, io_base & ~io_mask, io_mask + 1); + pipc_log("PIPC: Mapping PCS%d to %04X-%04X (enable %d)\n", i, io_base, io_base + io_mask, enable); + io_trap_remap(dev->io_traps[TRAP_GR0 + i].trap, enable, io_base & ~io_mask, io_mask + 1); } } - static void pipc_trap_update_paden(pipc_t *dev, uint8_t trap_id, - uint32_t paden_mask, uint8_t enable, - uint16_t addr, uint16_t size) + uint32_t paden_mask, uint8_t enable, + uint16_t addr, uint16_t size) { pipc_io_trap_t *trap = &dev->io_traps[trap_id]; - enable = (dev->acpi->regs.paden & paden_mask) && enable; + enable = (dev->acpi->regs.paden & paden_mask) && enable; /* Set up Primary Activity Detect I/O traps dynamically. */ if (enable && !trap->trap) { - trap->dev = dev; - trap->trap = io_trap_add(pipc_io_trap_pact, trap); - trap->sts_reg = &dev->acpi->regs.padsts; - trap->en_reg = &dev->acpi->regs.paden; - trap->mask = paden_mask; + trap->dev = dev; + trap->trap = io_trap_add(pipc_io_trap_pact, trap); + trap->sts_reg = &dev->acpi->regs.padsts; + trap->en_reg = &dev->acpi->regs.paden; + trap->mask = paden_mask; } /* Remap I/O trap. */ io_trap_remap(trap->trap, enable, addr, size); } - static void pipc_trap_update_586(void *priv) { @@ -634,12 +643,11 @@ pipc_trap_update_586(void *priv) pipc_trap_update_paden(dev, TRAP_KBC, 0x00000080, 1, 0x60, 1); } - static void pipc_trap_update_596(void *priv) { pipc_t *dev = (pipc_t *) priv; - int i; + int i; /* TRAP_DRQ (00000001) and TRAP_PIRQ (00000002) not implemented. */ @@ -671,13 +679,13 @@ pipc_trap_update_596(void *priv) It's better to be safe and cover all of them than to assume Intel-like behavior (one range). */ for (i = 0; i < 3; i++) { - pipc_trap_update_paden(dev, TRAP_AUD_MIDI_0 + i, - 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x01), - 0x300 + (0x10 * i), 4); + pipc_trap_update_paden(dev, TRAP_AUD_MIDI_0 + i, + 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x01), + 0x300 + (0x10 * i), 4); - pipc_trap_update_paden(dev, TRAP_AUD_SB_0 + i, - 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x02), - 0x220 + (0x20 * i), 20); + pipc_trap_update_paden(dev, TRAP_AUD_SB_0 + i, + 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x02), + 0x220 + (0x20 * i), 20); } pipc_trap_update_paden(dev, TRAP_AUD_GAME, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x04), 0x200, 8); @@ -688,33 +696,30 @@ pipc_trap_update_596(void *priv) pipc_trap_update_paden(dev, TRAP_AUD_WSS_3, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x08), 0xf40, 8); } - static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem) { if (!dev->ac97) - return; + return; if (modem) - ac97_via_remap_modem_sgd(dev->ac97, dev->ac97_regs[1][0x11] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO); + ac97_via_remap_modem_sgd(dev->ac97, dev->ac97_regs[1][0x11] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO); else - ac97_via_remap_audio_sgd(dev->ac97, dev->ac97_regs[0][0x11] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO); + ac97_via_remap_audio_sgd(dev->ac97, dev->ac97_regs[0][0x11] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO); } - static void pipc_codec_handlers(pipc_t *dev, uint8_t modem) { if (!dev->ac97) - return; + return; if (modem) - ac97_via_remap_modem_codec(dev->ac97, dev->ac97_regs[1][0x1d] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO); + ac97_via_remap_modem_codec(dev->ac97, dev->ac97_regs[1][0x1d] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO); else - ac97_via_remap_audio_codec(dev->ac97, dev->ac97_regs[0][0x1d] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO); + ac97_via_remap_audio_codec(dev->ac97, dev->ac97_regs[0][0x1d] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO); } - static uint8_t pipc_fmnmi_read(uint16_t addr, void *priv) { @@ -725,34 +730,32 @@ pipc_fmnmi_read(uint16_t addr, void *priv) #ifdef VIA_PIPC_FM_EMULATION /* Clear NMI/SMI if enabled. */ - if (dev->ac97_regs[0][0x48] & 0x01) { - if (dev->ac97_regs[0][0x48] & 0x04) - smi_line = 0; - else - nmi = 0; + if (dev->ac97_regs[0][0x48] & 0x01) { + if (dev->ac97_regs[0][0x48] & 0x04) + smi_line = 0; + else + nmi = 0; } #endif return ret; } - static void pipc_fmnmi_handlers(pipc_t *dev, uint8_t modem) { if (!dev->ac97 || modem) - return; + return; if (dev->fmnmi_base) - io_removehandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev); + io_removehandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev); dev->fmnmi_base = (dev->ac97_regs[0][0x15] << 8) | (dev->ac97_regs[0][0x14] & 0xfc); if (dev->fmnmi_base && (dev->ac97_regs[0][0x04] & PCI_COMMAND_IO)) - io_sethandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev); + io_sethandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev); } - static uint8_t pipc_fm_read(uint16_t addr, void *priv) { @@ -768,7 +771,6 @@ pipc_fm_read(uint16_t addr, void *priv) return ret; } - static void pipc_fm_write(uint16_t addr, uint8_t val, void *priv) { @@ -780,36 +782,35 @@ pipc_fm_write(uint16_t addr, uint8_t val, void *priv) /* Real 686B only updates the bank ID register when writing to the index port, and only fires NMI/SMI when writing to the data port. */ if (!(addr & 0x01)) { - dev->fmnmi_regs[0x00] = (addr & 0x02) ? 0x02 : 0x01; - dev->fmnmi_regs[0x01] = val; + dev->fmnmi_regs[0x00] = (addr & 0x02) ? 0x02 : 0x01; + dev->fmnmi_regs[0x01] = val; } else { - dev->fmnmi_regs[0x02] = val; + dev->fmnmi_regs[0x02] = val; - /* Fire NMI/SMI if enabled. */ - if (dev->ac97_regs[0][0x48] & 0x01) { - if (dev->ac97_regs[0][0x48] & 0x04) - smi_raise(); - else - nmi_raise(); - } + /* Fire NMI/SMI if enabled. */ + if (dev->ac97_regs[0][0x48] & 0x01) { + if (dev->ac97_regs[0][0x48] & 0x04) + smi_raise(); + else + nmi_raise(); + } } #else dev->sb->opl.write(addr, val, dev->sb->opl.priv); #endif } - static void pipc_sb_handlers(pipc_t *dev, uint8_t modem) { if (!dev->ac97 || modem) - return; + return; sb_dsp_setaddr(&dev->sb->dsp, 0); if (dev->sb_base) { - io_removehandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); - io_removehandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); - io_removehandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb); + io_removehandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); + io_removehandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); + io_removehandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb); } mpu401_change_addr(dev->sb->mpu, 0); @@ -818,105 +819,101 @@ pipc_sb_handlers(pipc_t *dev, uint8_t modem) io_removehandler(0x388, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); if (dev->ac97_regs[0][0x42] & 0x01) { - dev->sb_base = 0x220 + (0x20 * (dev->ac97_regs[0][0x43] & 0x03)); - sb_dsp_setaddr(&dev->sb->dsp, dev->sb_base); - if (dev->ac97_regs[0][0x42] & 0x04) { - io_sethandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); - io_sethandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); - } - io_sethandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb); + dev->sb_base = 0x220 + (0x20 * (dev->ac97_regs[0][0x43] & 0x03)); + sb_dsp_setaddr(&dev->sb->dsp, dev->sb_base); + if (dev->ac97_regs[0][0x42] & 0x04) { + io_sethandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); + io_sethandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv); + } + io_sethandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb); - uint8_t irq = 5 + (2 * ((dev->ac97_regs[0][0x43] >> 6) & 0x03)); - sb_dsp_setirq(&dev->sb->dsp, (irq == 11) ? 10 : irq); + uint8_t irq = 5 + (2 * ((dev->ac97_regs[0][0x43] >> 6) & 0x03)); + sb_dsp_setirq(&dev->sb->dsp, (irq == 11) ? 10 : irq); - sb_dsp_setdma8(&dev->sb->dsp, (dev->ac97_regs[0][0x43] >> 4) & 0x03); + sb_dsp_setdma8(&dev->sb->dsp, (dev->ac97_regs[0][0x43] >> 4) & 0x03); - /* Set up CD audio filter. This might not actually work if VIAUDIO writes to CD volume through AC97. */ - sound_set_cd_audio_filter(sbpro_filter_cd_audio, dev->sb); + /* Set up CD audio filter. This might not actually work if VIAUDIO writes to CD volume through AC97. */ + sound_set_cd_audio_filter(sbpro_filter_cd_audio, dev->sb); } if (dev->ac97_regs[0][0x42] & 0x02) { - /* BAR 2 is a mess. The MPU and game port remapping registers that VIA claims to be there don't - seem to actually exist on a real 686B. Remapping the MPU to BAR 2 itself does work, though. */ - if (dev->ac97_regs[0][0x42] & 0x80) - mpu401_change_addr(dev->sb->mpu, (dev->ac97_regs[0][0x19] << 8) | (dev->ac97_regs[0][0x18] & 0xfc)); - else - mpu401_change_addr(dev->sb->mpu, 0x300 | ((dev->ac97_regs[0][0x43] << 2) & 0x30)); + /* BAR 2 is a mess. The MPU and game port remapping registers that VIA claims to be there don't + seem to actually exist on a real 686B. Remapping the MPU to BAR 2 itself does work, though. */ + if (dev->ac97_regs[0][0x42] & 0x80) + mpu401_change_addr(dev->sb->mpu, (dev->ac97_regs[0][0x19] << 8) | (dev->ac97_regs[0][0x18] & 0xfc)); + else + mpu401_change_addr(dev->sb->mpu, 0x300 | ((dev->ac97_regs[0][0x43] << 2) & 0x30)); if (!(dev->ac97_regs[0][0x42] & 0x40)) - mpu401_setirq(dev->sb->mpu, dev->sb->dsp.sb_irqnum); + mpu401_setirq(dev->sb->mpu, dev->sb->dsp.sb_irqnum); } if (dev->ac97_regs[0][0x42] & 0x04) { - io_sethandler(0x388, 4, pipc_fm_read, NULL, NULL, pipc_fm_write, NULL, NULL, dev); + io_sethandler(0x388, 4, pipc_fm_read, NULL, NULL, pipc_fm_write, NULL, NULL, dev); } } - static uint8_t pipc_read(int func, int addr, void *priv) { pipc_t *dev = (pipc_t *) priv; uint8_t ret = 0xff; - int c; + int c; uint8_t pm_func = dev->usb[1] ? 4 : 3; if (func > dev->max_func) - return ret; - else if (func == 0) { /* PCI-ISA bridge */ - if ((addr >= 0x60) && (addr <= 0x6f)) { /* DMA shadow registers */ - c = (addr & 0x0e) >> 1; - if (addr & 0x01) - ret = (dma[c].ab & 0x0000ff00) >> 8; - else { - ret = (dma[c].ab & 0x000000f0); - ret |= (!!(dma_e & (1 << c)) << 3); - } - } else - ret = dev->pci_isa_regs[addr]; - } - else if ((func == 1) && !(dev->pci_isa_regs[0x48] & 0x02)) { /* IDE */ - ret = dev->ide_regs[addr]; - if ((addr >= 0x50) && (addr <= 0x53)) { /* UDMA timing registers */ - /* Set or clear bit 5 according to UDMA mode. Documentation is unclear, but a real - 686B does set bit 5 when UDMA is enabled through the method specified in bit 7. */ - c = 0x53 - addr; - if (ret & 0x80) /* bit 7 set = use bit 6 */ - c = ret & 0x40; - else if (ide_drives[c]) /* bit 7 clear = use SET FEATURES mode */ - c = (ide_drives[c]->mdma_mode & 0x300) == 0x300; - else /* no drive here */ - c = 0; - /* 586A/B datasheet claims bit 5 must be clear for UDMA, unlike later models where - it must be set, but the Windows driver doesn't care and always checks if it's set. */ - if (c) - ret |= 0x20; - else - ret &= ~0x20; - } - } - else if ((func < pm_func) && !((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10))) /* USB */ - ret = dev->usb_regs[func - 2][addr]; + return ret; + else if (func == 0) { /* PCI-ISA bridge */ + if ((addr >= 0x60) && (addr <= 0x6f)) { /* DMA shadow registers */ + c = (addr & 0x0e) >> 1; + if (addr & 0x01) + ret = (dma[c].ab & 0x0000ff00) >> 8; + else { + ret = (dma[c].ab & 0x000000f0); + ret |= (!!(dma_e & (1 << c)) << 3); + } + } else + ret = dev->pci_isa_regs[addr]; + } else if ((func == 1) && !(dev->pci_isa_regs[0x48] & 0x02)) { /* IDE */ + ret = dev->ide_regs[addr]; + if ((addr >= 0x50) && (addr <= 0x53)) { /* UDMA timing registers */ + /* Set or clear bit 5 according to UDMA mode. Documentation is unclear, but a real + 686B does set bit 5 when UDMA is enabled through the method specified in bit 7. */ + c = 0x53 - addr; + if (ret & 0x80) /* bit 7 set = use bit 6 */ + c = ret & 0x40; + else if (ide_drives[c]) /* bit 7 clear = use SET FEATURES mode */ + c = (ide_drives[c]->mdma_mode & 0x300) == 0x300; + else /* no drive here */ + c = 0; + /* 586A/B datasheet claims bit 5 must be clear for UDMA, unlike later models where + it must be set, but the Windows driver doesn't care and always checks if it's set. */ + if (c) + ret |= 0x20; + else + ret &= ~0x20; + } + } else if ((func < pm_func) && !((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10))) /* USB */ + ret = dev->usb_regs[func - 2][addr]; else if (func == pm_func) { /* Power */ - ret = dev->power_regs[addr]; - if (addr == 0x42) { - if (dev->nvr->regs[0x0d] & 0x80) - ret |= 0x10; - else - ret &= ~0x10; - } else if ((addr == 0xd2) && (dev->local == VIA_PIPC_686B)) { - /* SMBus clock select bit. */ - if (dev->smbus->clock == 16384) - ret &= ~0x10; - else - ret |= 0x10; - } - } - else if ((func <= (pm_func + 2)) && !(dev->pci_isa_regs[0x85] & ((func == (pm_func + 1)) ? 0x04 : 0x08))) { /* AC97 / MC97 */ - if (addr == 0x40) - ret = ac97_via_read_status(dev->ac97, func - pm_func - 1); - else - ret = dev->ac97_regs[func - pm_func - 1][addr]; + ret = dev->power_regs[addr]; + if (addr == 0x42) { + if (dev->nvr->regs[0x0d] & 0x80) + ret |= 0x10; + else + ret &= ~0x10; + } else if ((addr == 0xd2) && (dev->local == VIA_PIPC_686B)) { + /* SMBus clock select bit. */ + if (dev->smbus->clock == 16384) + ret &= ~0x10; + else + ret |= 0x10; + } + } else if ((func <= (pm_func + 2)) && !(dev->pci_isa_regs[0x85] & ((func == (pm_func + 1)) ? 0x04 : 0x08))) { /* AC97 / MC97 */ + if (addr == 0x40) + ret = ac97_via_read_status(dev->ac97, func - pm_func - 1); + else + ret = dev->ac97_regs[func - pm_func - 1][addr]; } pipc_log("PIPC: read(%d, %02X) = %02X\n", func, addr, ret); @@ -924,587 +921,611 @@ pipc_read(int func, int addr, void *priv) return ret; } - static void nvr_update_io_mapping(pipc_t *dev) { if (dev->nvr_enabled) - nvr_at_handler(0, 0x0074, dev->nvr); + nvr_at_handler(0, 0x0074, dev->nvr); if ((dev->pci_isa_regs[0x5b] & 0x02) || (dev->pci_isa_regs[0x48] & 0x08)) - nvr_at_handler(1, 0x0074, dev->nvr); + nvr_at_handler(1, 0x0074, dev->nvr); } - static void usb_update_io_mapping(pipc_t *dev, int func) { uhci_update_io_mapping(dev->usb[func - 2], dev->usb_regs[func - 2][0x20] & ~0x1f, dev->usb_regs[func - 2][0x21], dev->usb_regs[func - 2][PCI_REG_COMMAND] & PCI_COMMAND_IO); } - static void pipc_ddma_update(pipc_t *dev, int addr) { uint32_t base; if (dev->local >= VIA_PIPC_8231) - return; + return; base = (dev->pci_isa_regs[addr] & 0xf0) | (((uint32_t) dev->pci_isa_regs[addr | 0x01]) << 8); ddma_update_io_mapping(dev->ddma, (addr & 0x0e) >> 1, (dev->pci_isa_regs[addr] & 0xf0), dev->pci_isa_regs[addr | 0x01], (dev->pci_isa_regs[addr] & 0x08) && (base != 0x0000)); } - static void pipc_write(int func, int addr, uint8_t val, void *priv) { pipc_t *dev = (pipc_t *) priv; - int c; + int c; uint8_t pm_func = dev->usb[1] ? 4 : 3; if (func > dev->max_func) - return; + return; pipc_log("PIPC: write(%d, %02X, %02X)\n", func, addr, val); if (func == 0) { /* PCI-ISA bridge */ - /* Read-only addresses. */ - if ((addr < 4) || (addr == 5) || ((addr >= 8) && (addr < 0x40)) || (addr == 0x49) || (addr == 0x4b) || - (addr == 0x53) || ((addr >= 0x5d) && (addr < 0x5f)) || (addr >= 0x90)) - return; + /* Read-only addresses. */ + if ((addr < 4) || (addr == 5) || ((addr >= 8) && (addr < 0x40)) || (addr == 0x49) || (addr == 0x4b) || (addr == 0x53) || ((addr >= 0x5d) && (addr < 0x5f)) || (addr >= 0x90)) + return; - if ((dev->local <= VIA_PIPC_586A) && ((addr >= 0x58) && (addr < 0x80))) - return; + if ((dev->local <= VIA_PIPC_586A) && ((addr >= 0x58) && (addr < 0x80))) + return; - if ((dev->local <= VIA_PIPC_586B) && (addr >= 0x74)) - return; + if ((dev->local <= VIA_PIPC_586B) && (addr >= 0x74)) + return; - if ((dev->local <= VIA_PIPC_596A) && ((addr == 0x51) || (addr == 0x52) || (addr == 0x5f) || (addr == 0x85) || - (addr == 0x86) || ((addr >= 0x8a) && (addr < 0x90)))) - return; + if ((dev->local <= VIA_PIPC_596A) && ((addr == 0x51) || (addr == 0x52) || (addr == 0x5f) || (addr == 0x85) || (addr == 0x86) || ((addr >= 0x8a) && (addr < 0x90)))) + return; - switch (addr) { - case 0x04: - dev->pci_isa_regs[0x04] = (val & 8) | 7; - break; - case 0x07: - dev->pci_isa_regs[0x07] &= ~(val & 0xb0); - break; + switch (addr) { + case 0x04: + dev->pci_isa_regs[0x04] = (val & 8) | 7; + break; + case 0x07: + dev->pci_isa_regs[0x07] &= ~(val & 0xb0); + break; - case 0x42: - dev->pci_isa_regs[0x42] = val & 0xcf; + case 0x42: + dev->pci_isa_regs[0x42] = val & 0xcf; - switch (val & 0xf) { - /* Divisors on the PCI clock. */ - case 0x8: - cpu_set_isa_pci_div(3); - break; + switch (val & 0xf) { + /* Divisors on the PCI clock. */ + case 0x8: + cpu_set_isa_pci_div(3); + break; - case 0x9: - cpu_set_isa_pci_div(2); - break; + case 0x9: + cpu_set_isa_pci_div(2); + break; - /* case 0xa: same as default */ + /* case 0xa: same as default */ - case 0xb: - cpu_set_isa_pci_div(6); - break; + case 0xb: + cpu_set_isa_pci_div(6); + break; - case 0xc: - cpu_set_isa_pci_div(5); - break; + case 0xc: + cpu_set_isa_pci_div(5); + break; - case 0xd: - cpu_set_isa_pci_div(10); - break; + case 0xd: + cpu_set_isa_pci_div(10); + break; - case 0xe: - cpu_set_isa_pci_div(12); - break; + case 0xe: + cpu_set_isa_pci_div(12); + break; - /* Half oscillator clock. */ - case 0xf: - cpu_set_isa_speed(7159091); - break; + /* Half oscillator clock. */ + case 0xf: + cpu_set_isa_speed(7159091); + break; - /* Divisor 4 on the PCI clock whenever bit 3 is clear. */ - default: - cpu_set_isa_pci_div(4); - break; - } + /* Divisor 4 on the PCI clock whenever bit 3 is clear. */ + default: + cpu_set_isa_pci_div(4); + break; + } - break; + break; - case 0x47: - if (val & 0x01) - trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL); - pic_set_shadow(!!(val & 0x10)); - pic_elcr_io_handler(!!(val & 0x20)); - dev->pci_isa_regs[0x47] = val & 0xfe; - break; - case 0x48: - dev->pci_isa_regs[0x48] = val; - nvr_update_io_mapping(dev); - break; + case 0x47: + if (val & 0x01) + trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL); + pic_set_shadow(!!(val & 0x10)); + pic_elcr_io_handler(!!(val & 0x20)); + dev->pci_isa_regs[0x47] = val & 0xfe; + break; + case 0x48: + dev->pci_isa_regs[0x48] = val; + nvr_update_io_mapping(dev); + break; - case 0x50: case 0x51: case 0x52: case 0x85: - dev->pci_isa_regs[addr] = val; - /* Forward Super I/O-related registers to sio_vt82c686.c */ - if (dev->sio) - vt82c686_sio_write(addr, val, dev->sio); - break; + case 0x50: + case 0x51: + case 0x52: + case 0x85: + dev->pci_isa_regs[addr] = val; + /* Forward Super I/O-related registers to sio_vt82c686.c */ + if (dev->sio) + vt82c686_sio_write(addr, val, dev->sio); + break; - case 0x54: - pci_set_irq_level(PCI_INTA, !(val & 8)); - pci_set_irq_level(PCI_INTB, !(val & 4)); - pci_set_irq_level(PCI_INTC, !(val & 2)); - pci_set_irq_level(PCI_INTD, !(val & 1)); - dev->pci_isa_regs[0x54] = val & 0x0f; - break; - case 0x55: - pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'A' : 'D', val >> 4); - pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTA : PCI_INTD, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); - if (dev->local <= VIA_PIPC_586B) { - pipc_log("PIPC: Steering MIRQ0 to IRQ %d\n", val & 0x0f); - pci_set_mirq_routing(PCI_MIRQ0, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); - } - dev->pci_isa_regs[0x55] = val; - break; - case 0x56: - pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'C' : 'A', val >> 4); - pipc_log("PIPC: Steering PIRQB to IRQ %d\n", val & 0x0f); - pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTC : PCI_INTA, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTB, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); - dev->pci_isa_regs[0x56] = val; - break; - case 0x57: - pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'D' : 'C', val >> 4); - pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTD : PCI_INTC, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); - if (dev->local <= VIA_PIPC_586B) { - pipc_log("PIPC: Steering MIRQ1 to IRQ %d\n", val & 0x0f); - pci_set_mirq_routing(PCI_MIRQ1, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); - } - dev->pci_isa_regs[0x57] = val; - break; - case 0x58: - if (dev->local == VIA_PIPC_586B) { - pipc_log("PIPC: Steering MIRQ2 to IRQ %d\n", val & 0x0f); - pci_set_mirq_routing(PCI_MIRQ2, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); - } - dev->pci_isa_regs[0x58] = val; - break; - case 0x5b: - dev->pci_isa_regs[0x5b] = val; - nvr_update_io_mapping(dev); - break; + case 0x54: + pci_set_irq_level(PCI_INTA, !(val & 8)); + pci_set_irq_level(PCI_INTB, !(val & 4)); + pci_set_irq_level(PCI_INTC, !(val & 2)); + pci_set_irq_level(PCI_INTD, !(val & 1)); + dev->pci_isa_regs[0x54] = val & 0x0f; + break; + case 0x55: + pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'A' : 'D', val >> 4); + pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTA : PCI_INTD, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + if (dev->local <= VIA_PIPC_586B) { + pipc_log("PIPC: Steering MIRQ0 to IRQ %d\n", val & 0x0f); + pci_set_mirq_routing(PCI_MIRQ0, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + } + dev->pci_isa_regs[0x55] = val; + break; + case 0x56: + pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'C' : 'A', val >> 4); + pipc_log("PIPC: Steering PIRQB to IRQ %d\n", val & 0x0f); + pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTC : PCI_INTA, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTB, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + dev->pci_isa_regs[0x56] = val; + break; + case 0x57: + pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'D' : 'C', val >> 4); + pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTD : PCI_INTC, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED); + if (dev->local <= VIA_PIPC_586B) { + pipc_log("PIPC: Steering MIRQ1 to IRQ %d\n", val & 0x0f); + pci_set_mirq_routing(PCI_MIRQ1, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + } + dev->pci_isa_regs[0x57] = val; + break; + case 0x58: + if (dev->local == VIA_PIPC_586B) { + pipc_log("PIPC: Steering MIRQ2 to IRQ %d\n", val & 0x0f); + pci_set_mirq_routing(PCI_MIRQ2, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED); + } + dev->pci_isa_regs[0x58] = val; + break; + case 0x5b: + dev->pci_isa_regs[0x5b] = val; + nvr_update_io_mapping(dev); + break; - case 0x60: case 0x62: case 0x64: case 0x66: - case 0x6a: case 0x6c: case 0x6e: - dev->pci_isa_regs[addr] = val & 0xf8; - pipc_ddma_update(dev, addr); - break; - case 0x61: case 0x63: case 0x65: case 0x67: - case 0x6b: case 0x6d: case 0x6f: - dev->pci_isa_regs[addr] = val; - pipc_ddma_update(dev, addr & 0xfe); - break; + case 0x60: + case 0x62: + case 0x64: + case 0x66: + case 0x6a: + case 0x6c: + case 0x6e: + dev->pci_isa_regs[addr] = val & 0xf8; + pipc_ddma_update(dev, addr); + break; + case 0x61: + case 0x63: + case 0x65: + case 0x67: + case 0x6b: + case 0x6d: + case 0x6f: + dev->pci_isa_regs[addr] = val; + pipc_ddma_update(dev, addr & 0xfe); + break; - case 0x70: case 0x71: case 0x72: case 0x73: - dev->pci_isa_regs[(addr - 0x44)] = val; - break; + case 0x70: + case 0x71: + case 0x72: + case 0x73: + dev->pci_isa_regs[(addr - 0x44)] = val; + break; - case 0x74: case 0x8b: - case 0x78: case 0x79: case 0x7a: case 0x7b: - case 0x8c: case 0x8d: case 0x8e: case 0x8f: - case 0x80: case 0x8a: - dev->pci_isa_regs[addr] = val; - pipc_pcs_update(dev); - break; + case 0x74: + case 0x8b: + case 0x78: + case 0x79: + case 0x7a: + case 0x7b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0x8f: + case 0x80: + case 0x8a: + dev->pci_isa_regs[addr] = val; + pipc_pcs_update(dev); + break; - case 0x77: - if ((dev->local >= VIA_PIPC_686A) && (val & 0x10)) - pclog("PIPC: Warning: Internal I/O APIC enabled.\n"); - nvr_via_wp_set(!!(val & 0x04), 0x32, dev->nvr); - nvr_via_wp_set(!!(val & 0x02), 0x0d, dev->nvr); - break; + case 0x77: + if ((dev->local >= VIA_PIPC_686A) && (val & 0x10)) + pclog("PIPC: Warning: Internal I/O APIC enabled.\n"); + nvr_via_wp_set(!!(val & 0x04), 0x32, dev->nvr); + nvr_via_wp_set(!!(val & 0x02), 0x0d, dev->nvr); + break; - default: - dev->pci_isa_regs[addr] = val; - break; - } + default: + dev->pci_isa_regs[addr] = val; + break; + } } else if (func == 1) { /* IDE */ - /* Read-only addresses. */ - if ((addr < 4) || (addr == 5) || (addr == 8) || ((addr >= 0xa) && (addr < 0x0d)) || - ((addr >= 0x0e) && (addr < 0x10)) || ((addr >= 0x12) && (addr < 0x13)) || - ((addr >= 0x16) && (addr < 0x17)) || ((addr >= 0x1a) && (addr < 0x1b)) || - ((addr >= 0x1e) && (addr < 0x1f)) || ((addr >= 0x22) && (addr < 0x3c)) || - ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x55) && (addr < 0x60)) || - ((addr >= 0x62) && (addr < 0x68)) || ((addr >= 0x6a) && (addr < 0x70)) || - (addr == 0x72) || (addr == 0x73) || (addr == 0x76) || (addr == 0x77) || - (addr == 0x7a) || (addr == 0x7b) || (addr == 0x7e) || (addr == 0x7f) || - ((addr >= 0x84) && (addr < 0x88)) || (addr >= 0x8c)) - return; + /* Read-only addresses. */ + if ((addr < 4) || (addr == 5) || (addr == 8) || ((addr >= 0xa) && (addr < 0x0d)) || ((addr >= 0x0e) && (addr < 0x10)) || ((addr >= 0x12) && (addr < 0x13)) || ((addr >= 0x16) && (addr < 0x17)) || ((addr >= 0x1a) && (addr < 0x1b)) || ((addr >= 0x1e) && (addr < 0x1f)) || ((addr >= 0x22) && (addr < 0x3c)) || ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x55) && (addr < 0x60)) || ((addr >= 0x62) && (addr < 0x68)) || ((addr >= 0x6a) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || (addr == 0x76) || (addr == 0x77) || (addr == 0x7a) || (addr == 0x7b) || (addr == 0x7e) || (addr == 0x7f) || ((addr >= 0x84) && (addr < 0x88)) || (addr >= 0x8c)) + return; - if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x54) || (addr >= 0x70))) - return; + if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x54) || (addr >= 0x70))) + return; - /* Check disable bit. */ - if (dev->pci_isa_regs[0x48] & 0x02) - return; + /* Check disable bit. */ + if (dev->pci_isa_regs[0x48] & 0x02) + return; - switch (addr) { - case 0x04: - dev->ide_regs[0x04] = val & 0x85; - pipc_ide_handlers(dev); - pipc_bus_master_handlers(dev); - break; - case 0x07: - dev->ide_regs[0x07] &= ~(val & 0xf1); - break; + switch (addr) { + case 0x04: + dev->ide_regs[0x04] = val & 0x85; + pipc_ide_handlers(dev); + pipc_bus_master_handlers(dev); + break; + case 0x07: + dev->ide_regs[0x07] &= ~(val & 0xf1); + break; - case 0x09: - dev->ide_regs[0x09] = (val & 0x05) | 0x8a; - pipc_ide_handlers(dev); - pipc_ide_irqs(dev); - break; + case 0x09: + dev->ide_regs[0x09] = (val & 0x05) | 0x8a; + pipc_ide_handlers(dev); + pipc_ide_irqs(dev); + break; - case 0x10: - dev->ide_regs[0x10] = (val & 0xf8) | 1; - pipc_ide_handlers(dev); - break; - case 0x11: - dev->ide_regs[0x11] = val; - pipc_ide_handlers(dev); - break; + case 0x10: + dev->ide_regs[0x10] = (val & 0xf8) | 1; + pipc_ide_handlers(dev); + break; + case 0x11: + dev->ide_regs[0x11] = val; + pipc_ide_handlers(dev); + break; - case 0x14: - dev->ide_regs[0x14] = (val & 0xfc) | 1; - pipc_ide_handlers(dev); - break; - case 0x15: - dev->ide_regs[0x15] = val; - pipc_ide_handlers(dev); - break; + case 0x14: + dev->ide_regs[0x14] = (val & 0xfc) | 1; + pipc_ide_handlers(dev); + break; + case 0x15: + dev->ide_regs[0x15] = val; + pipc_ide_handlers(dev); + break; - case 0x18: - dev->ide_regs[0x18] = (val & 0xf8) | 1; - pipc_ide_handlers(dev); - break; - case 0x19: - dev->ide_regs[0x19] = val; - pipc_ide_handlers(dev); - break; + case 0x18: + dev->ide_regs[0x18] = (val & 0xf8) | 1; + pipc_ide_handlers(dev); + break; + case 0x19: + dev->ide_regs[0x19] = val; + pipc_ide_handlers(dev); + break; - case 0x1c: - dev->ide_regs[0x1c] = (val & 0xfc) | 1; - pipc_ide_handlers(dev); - break; - case 0x1d: - dev->ide_regs[0x1d] = val; - pipc_ide_handlers(dev); - break; + case 0x1c: + dev->ide_regs[0x1c] = (val & 0xfc) | 1; + pipc_ide_handlers(dev); + break; + case 0x1d: + dev->ide_regs[0x1d] = val; + pipc_ide_handlers(dev); + break; - case 0x20: - dev->ide_regs[0x20] = (val & 0xf0) | 1; - pipc_bus_master_handlers(dev); - break; - case 0x21: - dev->ide_regs[0x21] = val; - pipc_bus_master_handlers(dev); - break; + case 0x20: + dev->ide_regs[0x20] = (val & 0xf0) | 1; + pipc_bus_master_handlers(dev); + break; + case 0x21: + dev->ide_regs[0x21] = val; + pipc_bus_master_handlers(dev); + break; - case 0x3d: - dev->ide_regs[0x3d] = val & 0x01; - pipc_ide_irqs(dev); - break; + case 0x3d: + dev->ide_regs[0x3d] = val & 0x01; + pipc_ide_irqs(dev); + break; - case 0x40: - if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[0x40] = (val & 0x03) | 0x04; - else - dev->ide_regs[0x40] = val & 0x0f; - pipc_ide_handlers(dev); - break; + case 0x40: + if (dev->local <= VIA_PIPC_586B) + dev->ide_regs[0x40] = (val & 0x03) | 0x04; + else + dev->ide_regs[0x40] = val & 0x0f; + pipc_ide_handlers(dev); + break; - case 0x41: - if (dev->local <= VIA_PIPC_686A) - dev->ide_regs[0x41] = val; - else if (dev->local == VIA_PIPC_8231) - dev->ide_regs[0x41] = val & 0xf6; - else - dev->ide_regs[0x41] = val & 0xf2; - break; + case 0x41: + if (dev->local <= VIA_PIPC_686A) + dev->ide_regs[0x41] = val; + else if (dev->local == VIA_PIPC_8231) + dev->ide_regs[0x41] = val & 0xf6; + else + dev->ide_regs[0x41] = val & 0xf2; + break; - case 0x43: - if (dev->local <= VIA_PIPC_586A) - dev->ide_regs[0x43] = (val & 0x6f) | 0x10; - else if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[0x43] = (val & 0xef) | 0x10; - else - dev->ide_regs[0x43] = val & 0x0f; - break; + case 0x43: + if (dev->local <= VIA_PIPC_586A) + dev->ide_regs[0x43] = (val & 0x6f) | 0x10; + else if (dev->local <= VIA_PIPC_586B) + dev->ide_regs[0x43] = (val & 0xef) | 0x10; + else + dev->ide_regs[0x43] = val & 0x0f; + break; - case 0x44: - if (dev->local <= VIA_PIPC_586A) - dev->ide_regs[0x44] = val & 0x78; - else if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[0x44] = val & 0x7b; - else if (dev->local <= VIA_PIPC_596B) - dev->ide_regs[0x44] = val & 0x7f; - else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) - dev->ide_regs[0x44] = val & 0x69; - else - dev->ide_regs[0x44] = val & 0x7d; - break; + case 0x44: + if (dev->local <= VIA_PIPC_586A) + dev->ide_regs[0x44] = val & 0x78; + else if (dev->local <= VIA_PIPC_586B) + dev->ide_regs[0x44] = val & 0x7b; + else if (dev->local <= VIA_PIPC_596B) + dev->ide_regs[0x44] = val & 0x7f; + else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) + dev->ide_regs[0x44] = val & 0x69; + else + dev->ide_regs[0x44] = val & 0x7d; + break; - case 0x45: - if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[0x45] = val & 0x40; - else if ((dev->local <= VIA_PIPC_596B) || (dev->local == VIA_PIPC_8231)) - dev->ide_regs[0x45] = val & 0x4f; - else if (dev->local <= VIA_PIPC_686A) - dev->ide_regs[0x45] = val & 0x5f; - else - dev->ide_regs[0x45] = (val & 0x5c) | 0x20; - break; + case 0x45: + if (dev->local <= VIA_PIPC_586B) + dev->ide_regs[0x45] = val & 0x40; + else if ((dev->local <= VIA_PIPC_596B) || (dev->local == VIA_PIPC_8231)) + dev->ide_regs[0x45] = val & 0x4f; + else if (dev->local <= VIA_PIPC_686A) + dev->ide_regs[0x45] = val & 0x5f; + else + dev->ide_regs[0x45] = (val & 0x5c) | 0x20; + break; - case 0x46: - if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) - dev->ide_regs[0x46] = val & 0xf3; - else - dev->ide_regs[0x46] = val & 0xc0; - break; + case 0x46: + if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) + dev->ide_regs[0x46] = val & 0xf3; + else + dev->ide_regs[0x46] = val & 0xc0; + break; - case 0x50: case 0x51: case 0x52: case 0x53: - if (dev->local <= VIA_PIPC_586B) - dev->ide_regs[addr] = val & 0xc3; - else if (dev->local <= VIA_PIPC_596B) - dev->ide_regs[addr] = val & ((addr & 1) ? 0xc3 : 0xcb); - else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) - dev->ide_regs[addr] = val & ((addr & 1) ? 0xc7 : 0xcf); - else - dev->ide_regs[addr] = val & 0xd7; - break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + if (dev->local <= VIA_PIPC_586B) + dev->ide_regs[addr] = val & 0xc3; + else if (dev->local <= VIA_PIPC_596B) + dev->ide_regs[addr] = val & ((addr & 1) ? 0xc3 : 0xcb); + else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231)) + dev->ide_regs[addr] = val & ((addr & 1) ? 0xc7 : 0xcf); + else + dev->ide_regs[addr] = val & 0xd7; + break; - case 0x61: case 0x69: - dev->ide_regs[addr] = val & 0x0f; - break; + case 0x61: + case 0x69: + dev->ide_regs[addr] = val & 0x0f; + break; - default: - dev->ide_regs[addr] = val; - break; - } + default: + dev->ide_regs[addr] = val; + break; + } } else if (func < pm_func) { /* USB */ - /* Read-only addresses. */ - if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0xd)) || - ((addr >= 0xe) && (addr < 0x20)) || ((addr >= 0x22) && (addr < 0x3c)) || - ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x42) && (addr < 0x44)) || - ((addr >= 0x46) && (addr < 0x84)) || ((addr >= 0x85) && (addr < 0xc0)) || (addr >= 0xc2)) - return; + /* Read-only addresses. */ + if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x20)) || ((addr >= 0x22) && (addr < 0x3c)) || ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x42) && (addr < 0x44)) || ((addr >= 0x46) && (addr < 0x84)) || ((addr >= 0x85) && (addr < 0xc0)) || (addr >= 0xc2)) + return; - if ((dev->local <= VIA_PIPC_596B) && (addr == 0x84)) - return; + if ((dev->local <= VIA_PIPC_596B) && (addr == 0x84)) + return; - /* Check disable bits for both controllers. */ - if ((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10)) - return; + /* Check disable bits for both controllers. */ + if ((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10)) + return; - switch (addr) { - case 0x04: - dev->usb_regs[func - 2][0x04] = val & 0x97; - usb_update_io_mapping(dev, func); - break; - case 0x07: - dev->usb_regs[func - 2][0x07] &= ~(val & 0x78); - break; + switch (addr) { + case 0x04: + dev->usb_regs[func - 2][0x04] = val & 0x97; + usb_update_io_mapping(dev, func); + break; + case 0x07: + dev->usb_regs[func - 2][0x07] &= ~(val & 0x78); + break; - case 0x20: - dev->usb_regs[func - 2][0x20] = (val & ~0x1f) | 1; - usb_update_io_mapping(dev, func); - break; - case 0x21: - dev->usb_regs[func - 2][0x21] = val; - usb_update_io_mapping(dev, func); - break; + case 0x20: + dev->usb_regs[func - 2][0x20] = (val & ~0x1f) | 1; + usb_update_io_mapping(dev, func); + break; + case 0x21: + dev->usb_regs[func - 2][0x21] = val; + usb_update_io_mapping(dev, func); + break; - default: - dev->usb_regs[func - 2][addr] = val; - break; - } + default: + dev->usb_regs[func - 2][addr] = val; + break; + } } else if (func == pm_func) { /* Power */ - /* Read-only addresses */ - if ((addr < 0xd) || ((addr >= 0xe) && (addr < 0x40)) || (addr == 0x43) || (addr == 0x4a) || (addr == 0x4b) || - (addr == 0x4e) || (addr == 0x4f) || (addr == 0x56) || (addr == 0x57) || ((addr >= 0x5c) && (addr < 0x61)) || - ((addr >= 0x64) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || ((addr >= 0x75) && (addr < 0x80)) || - (addr == 0x83) || ((addr >= 0x85) && (addr < 0x90)) || ((addr >= 0x92) && (addr < 0xd2)) || (addr >= 0xd7)) - return; + /* Read-only addresses */ + if ((addr < 0xd) || ((addr >= 0xe) && (addr < 0x40)) || (addr == 0x43) || (addr == 0x4a) || (addr == 0x4b) || (addr == 0x4e) || (addr == 0x4f) || (addr == 0x56) || (addr == 0x57) || ((addr >= 0x5c) && (addr < 0x61)) || ((addr >= 0x64) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || ((addr >= 0x75) && (addr < 0x80)) || (addr == 0x83) || ((addr >= 0x85) && (addr < 0x90)) || ((addr >= 0x92) && (addr < 0xd2)) || (addr >= 0xd7)) + return; - if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x48) || (addr == 0x4c) || (addr == 0x4d) || (addr >= 0x54))) - return; + if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x48) || (addr == 0x4c) || (addr == 0x4d) || (addr >= 0x54))) + return; - if ((dev->local <= VIA_PIPC_596B) && ((addr >= 0x64) && (addr < (dev->local == VIA_PIPC_596A ? 0x80 : 0x85)))) - return; + if ((dev->local <= VIA_PIPC_596B) && ((addr >= 0x64) && (addr < (dev->local == VIA_PIPC_596A ? 0x80 : 0x85)))) + return; - switch (addr) { - case 0x41: case 0x48: case 0x49: - if (addr == 0x48) { - if (dev->local >= VIA_PIPC_596A) - val = (val & 0x80) | 0x01; - else - val = 0x01; - } + switch (addr) { + case 0x41: + case 0x48: + case 0x49: + if (addr == 0x48) { + if (dev->local >= VIA_PIPC_596A) + val = (val & 0x80) | 0x01; + else + val = 0x01; + } - dev->power_regs[addr] = val; - c = (dev->power_regs[0x49] << 8); - if (dev->local >= VIA_PIPC_596A) - c |= (dev->power_regs[0x48] & 0x80); - /* Workaround for P3V133 BIOS in 596B mode mapping ACPI to E800 (same as SMBus) instead of E400. */ - if ((dev->local == VIA_PIPC_596B) && (c == ((dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0))) && (dev->power_regs[0xd2] & 0x01)) - c -= 0x400; - acpi_set_timer32(dev->acpi, dev->power_regs[0x41] & 0x08); - acpi_update_io_mapping(dev->acpi, c, dev->power_regs[0x41] & 0x80); - break; + dev->power_regs[addr] = val; + c = (dev->power_regs[0x49] << 8); + if (dev->local >= VIA_PIPC_596A) + c |= (dev->power_regs[0x48] & 0x80); + /* Workaround for P3V133 BIOS in 596B mode mapping ACPI to E800 (same as SMBus) instead of E400. */ + if ((dev->local == VIA_PIPC_596B) && (c == ((dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0))) && (dev->power_regs[0xd2] & 0x01)) + c -= 0x400; + acpi_set_timer32(dev->acpi, dev->power_regs[0x41] & 0x08); + acpi_update_io_mapping(dev->acpi, c, dev->power_regs[0x41] & 0x80); + break; - case 0x42: - dev->power_regs[addr] = (dev->power_regs[addr] & 0xf0) | (val & 0x0f); - acpi_set_irq_line(dev->acpi, dev->power_regs[addr] & 0x0f); - break; + case 0x42: + dev->power_regs[addr] = (dev->power_regs[addr] & 0xf0) | (val & 0x0f); + acpi_set_irq_line(dev->acpi, dev->power_regs[addr] & 0x0f); + break; - case 0x54: - if (dev->local <= VIA_PIPC_596B) - dev->power_regs[addr] = val; /* write-only on 686A+ */ - else - smbus_piix4_setclock(dev->smbus, (val & 0x80) ? 65536 : 16384); /* final clock undocumented on 686A, assume RTC*2 like 686B */ - break; + case 0x54: + if (dev->local <= VIA_PIPC_596B) + dev->power_regs[addr] = val; /* write-only on 686A+ */ + else + smbus_piix4_setclock(dev->smbus, (val & 0x80) ? 65536 : 16384); /* final clock undocumented on 686A, assume RTC*2 like 686B */ + break; - case 0x61: case 0x62: case 0x63: - dev->power_regs[(addr - 0x58)] = val; - break; + case 0x61: + case 0x62: + case 0x63: + dev->power_regs[(addr - 0x58)] = val; + break; - case 0x70: case 0x71: case 0x74: - dev->power_regs[addr] = val; - /* Forward hardware monitor-related registers to hwm_vt82c686.c */ - if (dev->hwm) - vt82c686_hwm_write(addr, val, dev->hwm); - break; + case 0x70: + case 0x71: + case 0x74: + dev->power_regs[addr] = val; + /* Forward hardware monitor-related registers to hwm_vt82c686.c */ + if (dev->hwm) + vt82c686_hwm_write(addr, val, dev->hwm); + break; - case 0x80: case 0x81: case 0x84: /* 596A has the SMBus I/O base and enable bit here instead. */ - dev->power_regs[addr] = val; - smbus_piix4_remap(dev->smbus, (dev->power_regs[0x81] << 8) | (dev->power_regs[0x80] & 0xf0), dev->power_regs[0x84] & 0x01); - break; + case 0x80: + case 0x81: + case 0x84: /* 596A has the SMBus I/O base and enable bit here instead. */ + dev->power_regs[addr] = val; + smbus_piix4_remap(dev->smbus, (dev->power_regs[0x81] << 8) | (dev->power_regs[0x80] & 0xf0), dev->power_regs[0x84] & 0x01); + break; - case 0xd2: - if (dev->local == VIA_PIPC_686B) - smbus_piix4_setclock(dev->smbus, (val & 0x04) ? 65536 : 16384); - /* fall-through */ + case 0xd2: + if (dev->local == VIA_PIPC_686B) + smbus_piix4_setclock(dev->smbus, (val & 0x04) ? 65536 : 16384); + /* fall-through */ - case 0x90: case 0x91: - dev->power_regs[addr] = val; - smbus_piix4_remap(dev->smbus, (dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0), dev->power_regs[0xd2] & 0x01); - break; + case 0x90: + case 0x91: + dev->power_regs[addr] = val; + smbus_piix4_remap(dev->smbus, (dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0), dev->power_regs[0xd2] & 0x01); + break; - default: - dev->power_regs[addr] = val; - break; - } + default: + dev->power_regs[addr] = val; + break; + } } else if (func <= pm_func + 2) { /* AC97 / MC97 */ - /* Read-only addresses. */ - if ((addr < 0x4) || ((addr >= 0x6) && (addr < 0x9)) || ((addr >= 0xc) && (addr < 0x11)) || (addr == 0x16) || - (addr == 0x17) || (addr == 0x1a) || (addr == 0x1b) || ((addr >= 0x1e) && (addr < 0x2c)) || - ((addr >= 0x30) && (addr < 0x34)) || ((addr >= 0x35) && (addr < 0x3c)) || ((addr >= 0x3d) && (addr < 0x41)) || - ((addr >= 0x45) && (addr < 0x4a)) || (addr >= 0x4c)) - return; + /* Read-only addresses. */ + if ((addr < 0x4) || ((addr >= 0x6) && (addr < 0x9)) || ((addr >= 0xc) && (addr < 0x11)) || (addr == 0x16) || (addr == 0x17) || (addr == 0x1a) || (addr == 0x1b) || ((addr >= 0x1e) && (addr < 0x2c)) || ((addr >= 0x30) && (addr < 0x34)) || ((addr >= 0x35) && (addr < 0x3c)) || ((addr >= 0x3d) && (addr < 0x41)) || ((addr >= 0x45) && (addr < 0x4a)) || (addr >= 0x4c)) + return; - /* Small shortcut. */ - func = func - pm_func - 1; + /* Small shortcut. */ + func = func - pm_func - 1; - /* Check disable bits and specific read-only addresses for both controllers. */ - if ((func == 0) && (((addr >= 0x09) && (addr < 0xc)) || (addr == 0x44) || (dev->pci_isa_regs[0x85] & 0x04))) - return; + /* Check disable bits and specific read-only addresses for both controllers. */ + if ((func == 0) && (((addr >= 0x09) && (addr < 0xc)) || (addr == 0x44) || (dev->pci_isa_regs[0x85] & 0x04))) + return; - if ((func == 1) && ((addr == 0x14) || (addr == 0x15) || (addr == 0x18) || (addr == 0x19) || (addr == 0x42) || - (addr == 0x43) || (addr == 0x48) || (addr == 0x4a) || (addr == 0x4b) || (dev->pci_isa_regs[0x85] & 0x08))) - return; + if ((func == 1) && ((addr == 0x14) || (addr == 0x15) || (addr == 0x18) || (addr == 0x19) || (addr == 0x42) || (addr == 0x43) || (addr == 0x48) || (addr == 0x4a) || (addr == 0x4b) || (dev->pci_isa_regs[0x85] & 0x08))) + return; - switch (addr) { - case 0x04: - dev->ac97_regs[func][addr] = val; - pipc_sgd_handlers(dev, func); - pipc_codec_handlers(dev, func); - pipc_fmnmi_handlers(dev, func); - break; + switch (addr) { + case 0x04: + dev->ac97_regs[func][addr] = val; + pipc_sgd_handlers(dev, func); + pipc_codec_handlers(dev, func); + pipc_fmnmi_handlers(dev, func); + break; - case 0x09: case 0x0a: case 0x0b: - if (dev->ac97_regs[func][0x44] & 0x20) - dev->ac97_regs[func][addr] = val; - break; + case 0x09: + case 0x0a: + case 0x0b: + if (dev->ac97_regs[func][0x44] & 0x20) + dev->ac97_regs[func][addr] = val; + break; - case 0x10: case 0x11: - dev->ac97_regs[func][addr] = val; - pipc_sgd_handlers(dev, func); - break; + case 0x10: + case 0x11: + dev->ac97_regs[func][addr] = val; + pipc_sgd_handlers(dev, func); + break; - case 0x14: case 0x15: - if (addr == 0x14) - val = (val & 0xfc) | 1; - dev->ac97_regs[func][addr] = val; - pipc_fmnmi_handlers(dev, func); - break; + case 0x14: + case 0x15: + if (addr == 0x14) + val = (val & 0xfc) | 1; + dev->ac97_regs[func][addr] = val; + pipc_fmnmi_handlers(dev, func); + break; - case 0x18: case 0x19: - if (addr == 0x18) - val = (val & 0xfc) | 1; - dev->ac97_regs[func][addr] = val; - pipc_sb_handlers(dev, func); - break; + case 0x18: + case 0x19: + if (addr == 0x18) + val = (val & 0xfc) | 1; + dev->ac97_regs[func][addr] = val; + pipc_sb_handlers(dev, func); + break; - case 0x1c: case 0x1d: - dev->ac97_regs[func][addr] = val; - pipc_codec_handlers(dev, func); - break; + case 0x1c: + case 0x1d: + dev->ac97_regs[func][addr] = val; + pipc_codec_handlers(dev, func); + break; - case 0x2c: case 0x2d: case 0x2e: case 0x2f: - if ((func == 0) && (dev->ac97_regs[func][0x42] & 0x20)) - dev->ac97_regs[func][addr] = val; - break; + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + if ((func == 0) && (dev->ac97_regs[func][0x42] & 0x20)) + dev->ac97_regs[func][addr] = val; + break; - case 0x41: - dev->ac97_regs[func][addr] = val; - ac97_via_write_control(dev->ac97, func, val); - break; + case 0x41: + dev->ac97_regs[func][addr] = val; + ac97_via_write_control(dev->ac97, func, val); + break; - case 0x42: case 0x4a: case 0x4b: - dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val; - gameport_remap(dev->gameport, (dev->ac97_regs[0][0x42] & 0x08) ? ((dev->ac97_regs[0][0x4b] << 8) | (dev->ac97_regs[0][0x4a] & 0xf8)) : 0); - if (addr == 0x42) - pipc_sb_handlers(dev, func); - break; + case 0x42: + case 0x4a: + case 0x4b: + dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val; + gameport_remap(dev->gameport, (dev->ac97_regs[0][0x42] & 0x08) ? ((dev->ac97_regs[0][0x4b] << 8) | (dev->ac97_regs[0][0x4a] & 0xf8)) : 0); + if (addr == 0x42) + pipc_sb_handlers(dev, func); + break; - case 0x43: - dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val; - break; + case 0x43: + dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val; + break; - case 0x44: - dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0xf0; - break; + case 0x44: + dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0xf0; + break; - case 0x45: case 0x48: - dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0x0f; - break; + case 0x45: + case 0x48: + dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0x0f; + break; - default: - dev->ac97_regs[func][addr] = val; - break; - } + default: + dev->ac97_regs[func][addr] = val; + break; + } } } - static void pipc_reset(void *p) { - pipc_t *dev = (pipc_t *) p; + pipc_t *dev = (pipc_t *) p; uint8_t pm_func = dev->usb[1] ? 4 : 3; pipc_write(pm_func, 0x41, 0x00, p); @@ -1524,14 +1545,13 @@ pipc_reset(void *p) pipc_write(1, 0x20, 0x01, p); pipc_write(1, 0x21, 0xcc, p); if (dev->local <= VIA_PIPC_586B) - pipc_write(1, 0x40, 0x04, p); + pipc_write(1, 0x40, 0x04, p); else - pipc_write(1, 0x40, 0x00, p); + pipc_write(1, 0x40, 0x00, p); pipc_write(0, 0x77, 0x00, p); } - static void * pipc_init(const device_t *info) { @@ -1541,7 +1561,7 @@ pipc_init(const device_t *info) pipc_log("PIPC: init()\n"); dev->local = info->local; - dev->slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pipc_read, pipc_write, dev); + dev->slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pipc_read, pipc_write, dev); dev->bm[0] = device_add_inst(&sff8038i_device, 1); sff_set_slot(dev->bm[0], dev->slot); @@ -1558,35 +1578,35 @@ pipc_init(const device_t *info) dev->nvr = device_add(&via_nvr_device); if (dev->local == VIA_PIPC_686B) - dev->smbus = device_add(&via_smbus_device); + dev->smbus = device_add(&via_smbus_device); else if (dev->local >= VIA_PIPC_596A) - dev->smbus = device_add(&piix4_smbus_device); + dev->smbus = device_add(&piix4_smbus_device); if (dev->local >= VIA_PIPC_596A) { - dev->acpi = device_add(&acpi_via_596b_device); - acpi_set_trap_update(dev->acpi, pipc_trap_update_596, dev); + dev->acpi = device_add(&acpi_via_596b_device); + acpi_set_trap_update(dev->acpi, pipc_trap_update_596, dev); } else if (dev->local >= VIA_PIPC_586B) { - dev->acpi = device_add(&acpi_via_device); - acpi_set_trap_update(dev->acpi, pipc_trap_update_586, dev); + dev->acpi = device_add(&acpi_via_device); + acpi_set_trap_update(dev->acpi, pipc_trap_update_586, dev); } dev->usb[0] = device_add_inst(&usb_device, 1); if (dev->local >= VIA_PIPC_686A) { - dev->usb[1] = device_add_inst(&usb_device, 2); + dev->usb[1] = device_add_inst(&usb_device, 2); - dev->ac97 = device_add(&ac97_via_device); - ac97_via_set_slot(dev->ac97, dev->slot, PCI_INTC); + dev->ac97 = device_add(&ac97_via_device); + ac97_via_set_slot(dev->ac97, dev->slot, PCI_INTC); - dev->sb = device_add_inst(&sb_pro_compat_device, 2); + dev->sb = device_add_inst(&sb_pro_compat_device, 2); #ifndef VIA_PIPC_FM_EMULATION - dev->sb->opl_enabled = 1; + dev->sb->opl_enabled = 1; #endif - sound_add_handler(sb_get_buffer_sbpro, dev->sb); + sound_add_handler(sb_get_buffer_sbpro, dev->sb); - dev->gameport = gameport_add(&gameport_sio_device); + dev->gameport = gameport_add(&gameport_sio_device); - dev->sio = device_add(&via_vt82c686_sio_device); - dev->hwm = device_add(&via_vt82c686_hwm_device); + dev->sio = device_add(&via_vt82c686_sio_device); + dev->hwm = device_add(&via_vt82c686_hwm_device); } pipc_reset_hard(dev); @@ -1598,26 +1618,25 @@ pipc_init(const device_t *info) dma_alias_set(); if (dev->local <= VIA_PIPC_586B) { - pci_enable_mirq(0); - pci_enable_mirq(1); - if (dev->local == VIA_PIPC_586B) - pci_enable_mirq(2); + pci_enable_mirq(0); + pci_enable_mirq(1); + if (dev->local == VIA_PIPC_586B) + pci_enable_mirq(2); } if (dev->local < VIA_PIPC_8231) - dev->ddma = device_add(&ddma_device); + dev->ddma = device_add(&ddma_device); if (dev->acpi) { - acpi_set_slot(dev->acpi, dev->slot); - acpi_set_nvr(dev->acpi, dev->nvr); + acpi_set_slot(dev->acpi, dev->slot); + acpi_set_nvr(dev->acpi, dev->nvr); - acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f); + acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f); } return dev; } - static void pipc_close(void *p) { @@ -1626,91 +1645,91 @@ pipc_close(void *p) pipc_log("PIPC: close()\n"); for (int i = 0; i < TRAP_MAX; i++) - io_trap_remove(dev->io_traps[i].trap); + io_trap_remove(dev->io_traps[i].trap); free(dev); } const device_t via_vt82c586b_device = { - .name = "VIA VT82C586B", + .name = "VIA VT82C586B", .internal_name = "via_vt82c586b", - .flags = DEVICE_PCI, - .local = VIA_PIPC_586B, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_586B, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c596a_device = { - .name = "VIA VT82C596A", + .name = "VIA VT82C596A", .internal_name = "via_vt82c596a", - .flags = DEVICE_PCI, - .local = VIA_PIPC_596A, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_596A, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c596b_device = { - .name = "VIA VT82C596B", + .name = "VIA VT82C596B", .internal_name = "via_vt82c596b", - .flags = DEVICE_PCI, - .local = VIA_PIPC_596B, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_596B, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c686a_device = { - .name = "VIA VT82C686A", + .name = "VIA VT82C686A", .internal_name = "via_vt82c686a", - .flags = DEVICE_PCI, - .local = VIA_PIPC_686A, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_686A, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c686b_device = { - .name = "VIA VT82C686B", + .name = "VIA VT82C686B", .internal_name = "via_vt82c686b", - .flags = DEVICE_PCI, - .local = VIA_PIPC_686B, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_686B, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt8231_device = { - .name = "VIA VT8231", + .name = "VIA VT8231", .internal_name = "via_vt8231", - .flags = DEVICE_PCI, - .local = VIA_PIPC_8231, - .init = pipc_init, - .close = pipc_close, - .reset = pipc_reset, + .flags = DEVICE_PCI, + .local = VIA_PIPC_8231, + .init = pipc_init, + .close = pipc_close, + .reset = pipc_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/via_vt82c49x.c b/src/chipset/via_vt82c49x.c index f951741e7..2555a688c 100644 --- a/src/chipset/via_vt82c49x.c +++ b/src/chipset/via_vt82c49x.c @@ -37,14 +37,13 @@ typedef struct { - uint8_t has_ide, index, - regs[256]; + uint8_t has_ide, index, + regs[256]; - smram_t *smram_smm, *smram_low, - *smram_high; + smram_t *smram_smm, *smram_low, + *smram_high; } vt82c49x_t; - #ifdef ENABLE_VT82C49X_LOG int vt82c49x_do_log = ENABLE_VT82C49X_LOG; static void @@ -53,124 +52,124 @@ vt82c49x_log(const char *fmt, ...) va_list ap; if (vt82c49x_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -#define vt82c49x_log(fmt, ...) +# define vt82c49x_log(fmt, ...) #endif - static void vt82c49x_recalc(vt82c49x_t *dev) { - int i, relocate; - uint8_t reg, bit; + int i, relocate; + uint8_t reg, bit; uint32_t base, state; uint32_t shadow_bitmap = 0x00000000; relocate = (dev->regs[0x33] >> 2) & 0x03; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; for (i = 0; i < 8; i++) { - base = 0xc0000 + (i << 14); - reg = 0x30 + (i >> 2); - bit = (i & 3) << 1; + base = 0xc0000 + (i << 14); + reg = 0x30 + (i >> 2); + bit = (i & 3) << 1; - if ((base >= 0xc0000) && (base <= 0xc7fff)) { - if (dev->regs[0x40] & 0x80) - state = MEM_WRITE_DISABLED; - else if ((dev->regs[reg]) & (1 << bit)) - state = MEM_WRITE_INTERNAL; - else - state = (dev->regs[0x33] & 0x40) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; + if ((base >= 0xc0000) && (base <= 0xc7fff)) { + if (dev->regs[0x40] & 0x80) + state = MEM_WRITE_DISABLED; + else if ((dev->regs[reg]) & (1 << bit)) + state = MEM_WRITE_INTERNAL; + else + state = (dev->regs[0x33] & 0x40) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; - if ((dev->regs[reg]) & (1 << (bit + 1))) - state |= MEM_READ_INTERNAL; - else - state |= (dev->regs[0x33] & 0x40) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; - } if ((base >= 0xc8000) && (base <= 0xcffff)) { - if ((dev->regs[reg]) & (1 << bit)) - state = MEM_WRITE_INTERNAL; - else - state = (dev->regs[0x33] & 0x80) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; + if ((dev->regs[reg]) & (1 << (bit + 1))) + state |= MEM_READ_INTERNAL; + else + state |= (dev->regs[0x33] & 0x40) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; + } + if ((base >= 0xc8000) && (base <= 0xcffff)) { + if ((dev->regs[reg]) & (1 << bit)) + state = MEM_WRITE_INTERNAL; + else + state = (dev->regs[0x33] & 0x80) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; - if ((dev->regs[reg]) & (1 << (bit + 1))) - state |= MEM_READ_INTERNAL; - else - state |= (dev->regs[0x33] & 0x80) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; - } else { - state = ((dev->regs[reg]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - state |= ((dev->regs[reg]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - } + if ((dev->regs[reg]) & (1 << (bit + 1))) + state |= MEM_READ_INTERNAL; + else + state |= (dev->regs[0x33] & 0x80) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; + } else { + state = ((dev->regs[reg]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + state |= ((dev->regs[reg]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + } - vt82c49x_log("(%02X=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n", - reg, dev->regs[reg], bit, base, base + 0x3fff, - ((dev->regs[reg]) & (1 << bit)) ? "en" : "dis", ((dev->regs[reg]) & (1 << (bit + 1))) ? "en" : "dis"); + vt82c49x_log("(%02X=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n", + reg, dev->regs[reg], bit, base, base + 0x3fff, + ((dev->regs[reg]) & (1 << bit)) ? "en" : "dis", ((dev->regs[reg]) & (1 << (bit + 1))) ? "en" : "dis"); - if ((dev->regs[reg]) & (1 << bit)) - shadow_bitmap |= (1 << i); - if ((dev->regs[reg]) & (1 << (bit + 1))) - shadow_bitmap |= (1 << (i + 16)); + if ((dev->regs[reg]) & (1 << bit)) + shadow_bitmap |= (1 << i); + if ((dev->regs[reg]) & (1 << (bit + 1))) + shadow_bitmap |= (1 << (i + 16)); - mem_set_mem_state_both(base, 0x4000, state); + mem_set_mem_state_both(base, 0x4000, state); } for (i = 0; i < 4; i++) { - base = 0xe0000 + (i << 15); - bit = 6 - (i & 2); + base = 0xe0000 + (i << 15); + bit = 6 - (i & 2); - if ((base >= 0xe0000) && (base <= 0xe7fff)) { - if (dev->regs[0x40] & 0x20) - state = MEM_WRITE_DISABLED; - else if ((dev->regs[0x32]) & (1 << bit)) - state = MEM_WRITE_INTERNAL; - else - state = (dev->regs[0x33] & 0x10) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; + if ((base >= 0xe0000) && (base <= 0xe7fff)) { + if (dev->regs[0x40] & 0x20) + state = MEM_WRITE_DISABLED; + else if ((dev->regs[0x32]) & (1 << bit)) + state = MEM_WRITE_INTERNAL; + else + state = (dev->regs[0x33] & 0x10) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; - if ((dev->regs[0x32]) & (1 << (bit + 1))) - state |= MEM_READ_INTERNAL; - else - state |= (dev->regs[0x33] & 0x10) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; - } else if ((base >= 0xe8000) && (base <= 0xeffff)) { - if (dev->regs[0x40] & 0x20) - state = MEM_WRITE_DISABLED; - else if ((dev->regs[0x32]) & (1 << bit)) - state = MEM_WRITE_INTERNAL; - else - state = (dev->regs[0x33] & 0x20) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; + if ((dev->regs[0x32]) & (1 << (bit + 1))) + state |= MEM_READ_INTERNAL; + else + state |= (dev->regs[0x33] & 0x10) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; + } else if ((base >= 0xe8000) && (base <= 0xeffff)) { + if (dev->regs[0x40] & 0x20) + state = MEM_WRITE_DISABLED; + else if ((dev->regs[0x32]) & (1 << bit)) + state = MEM_WRITE_INTERNAL; + else + state = (dev->regs[0x33] & 0x20) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL; - if ((dev->regs[0x32]) & (1 << (bit + 1))) - state |= MEM_READ_INTERNAL; - else - state |= (dev->regs[0x33] & 0x20) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; - } else { - if (dev->regs[0x40] & 0x40) - state = MEM_WRITE_DISABLED; - else if ((dev->regs[0x32]) & (1 << bit)) - state = ((dev->regs[0x32]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + if ((dev->regs[0x32]) & (1 << (bit + 1))) + state |= MEM_READ_INTERNAL; + else + state |= (dev->regs[0x33] & 0x20) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL; + } else { + if (dev->regs[0x40] & 0x40) + state = MEM_WRITE_DISABLED; + else if ((dev->regs[0x32]) & (1 << bit)) + state = ((dev->regs[0x32]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - state |= ((dev->regs[0x32]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - } + state |= ((dev->regs[0x32]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + } - vt82c49x_log("(32=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n", - dev->regs[0x32], bit, base, base + 0x7fff, - ((dev->regs[0x32]) & (1 << bit)) ? "en" : "dis", ((dev->regs[0x32]) & (1 << (bit + 1))) ? "en" : "dis"); + vt82c49x_log("(32=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n", + dev->regs[0x32], bit, base, base + 0x7fff, + ((dev->regs[0x32]) & (1 << bit)) ? "en" : "dis", ((dev->regs[0x32]) & (1 << (bit + 1))) ? "en" : "dis"); - if ((dev->regs[0x32]) & (1 << bit)) { - shadow_bitmap |= (0xf << ((i << 2) + 8)); - shadowbios_write |= 1; - } - if ((dev->regs[0x32]) & (1 << (bit + 1))) { - shadow_bitmap |= (0xf << ((i << 2) + 24)); - shadowbios |= 1; - } + if ((dev->regs[0x32]) & (1 << bit)) { + shadow_bitmap |= (0xf << ((i << 2) + 8)); + shadowbios_write |= 1; + } + if ((dev->regs[0x32]) & (1 << (bit + 1))) { + shadow_bitmap |= (0xf << ((i << 2) + 24)); + shadowbios |= 1; + } - mem_set_mem_state_both(base, 0x8000, state); + mem_set_mem_state_both(base, 0x8000, state); } vt82c49x_log("Shadow bitmap: %08X\n", shadow_bitmap); @@ -178,145 +177,142 @@ vt82c49x_recalc(vt82c49x_t *dev) mem_remap_top(0); switch (relocate) { - case 0x02: - if (!(shadow_bitmap & 0xfff0fff0)) - mem_remap_top(256); - break; - case 0x03: - if (!shadow_bitmap) - mem_remap_top(384); - break; + case 0x02: + if (!(shadow_bitmap & 0xfff0fff0)) + mem_remap_top(256); + break; + case 0x03: + if (!shadow_bitmap) + mem_remap_top(384); + break; } } - static void vt82c49x_write(uint16_t addr, uint8_t val, void *priv) { vt82c49x_t *dev = (vt82c49x_t *) priv; - uint8_t valxor; + uint8_t valxor; switch (addr) { - case 0xa8: - dev->index = val; - break; + case 0xa8: + dev->index = val; + break; - case 0xa9: - valxor = (val ^ dev->regs[dev->index]); - if (dev->index == 0x55) - dev->regs[dev->index] &= ~val; - else - dev->regs[dev->index] = val; + case 0xa9: + valxor = (val ^ dev->regs[dev->index]); + if (dev->index == 0x55) + dev->regs[dev->index] &= ~val; + else + dev->regs[dev->index] = val; - vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val); + vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val); - switch(dev->index) { - /* Wait States */ - case 0x03: - cpu_update_waitstates(); - break; + switch (dev->index) { + /* Wait States */ + case 0x03: + cpu_update_waitstates(); + break; - /* Shadow RAM and top of RAM relocation */ - case 0x30: - case 0x31: - case 0x32: - case 0x33: - case 0x40: - vt82c49x_recalc(dev); - break; + /* Shadow RAM and top of RAM relocation */ + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x40: + vt82c49x_recalc(dev); + break; - /* External Cache Enable(Based on the 486-VC-HD BIOS) */ - case 0x50: - cpu_cache_ext_enabled = (val & 0x84); - break; + /* External Cache Enable(Based on the 486-VC-HD BIOS) */ + case 0x50: + cpu_cache_ext_enabled = (val & 0x84); + break; - /* Software SMI */ - case 0x54: - if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) { - if (dev->regs[0x5b] & 0x20) - smi_raise(); - else - picint(1 << 15); - dev->regs[0x55] = 0x01; - } - break; + /* Software SMI */ + case 0x54: + if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) { + if (dev->regs[0x5b] & 0x20) + smi_raise(); + else + picint(1 << 15); + dev->regs[0x55] = 0x01; + } + break; - /* SMRAM */ - case 0x5b: - smram_disable_all(); + /* SMRAM */ + case 0x5b: + smram_disable_all(); - if (val & 0x80) { - smram_enable(dev->smram_smm, (val & 0x40) ? 0x00060000 : 0x00030000, 0x000a0000, 0x00020000, - 0, (val & 0x10)); - smram_enable(dev->smram_high, 0x000a0000, 0x000a0000, 0x00020000, - (val & 0x08), (val & 0x08)); - smram_enable(dev->smram_low, 0x00030000, 0x000a0000, 0x00020000, - (val & 0x02), 0); - } - break; + if (val & 0x80) { + smram_enable(dev->smram_smm, (val & 0x40) ? 0x00060000 : 0x00030000, 0x000a0000, 0x00020000, + 0, (val & 0x10)); + smram_enable(dev->smram_high, 0x000a0000, 0x000a0000, 0x00020000, + (val & 0x08), (val & 0x08)); + smram_enable(dev->smram_low, 0x00030000, 0x000a0000, 0x00020000, + (val & 0x02), 0); + } + break; - /* Edge/Level IRQ Control */ - case 0x62: case 0x63: - if (dev->index == 0x63) - pic_elcr_write(dev->index, val & 0xde, &pic2); - else { - pic_elcr_write(dev->index, val & 0xf8, &pic); - pic_elcr_set_enabled(val & 0x01); - } - break; + /* Edge/Level IRQ Control */ + case 0x62: + case 0x63: + if (dev->index == 0x63) + pic_elcr_write(dev->index, val & 0xde, &pic2); + else { + pic_elcr_write(dev->index, val & 0xf8, &pic); + pic_elcr_set_enabled(val & 0x01); + } + break; - /* Local Bus IDE Controller */ - case 0x71: - if (dev->has_ide) { - ide_pri_disable(); - ide_set_base(0, (val & 0x40) ? 0x170 : 0x1f0); - ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6); - if (val & 0x01) - ide_pri_enable(); - vt82c49x_log("VT82C496 IDE now %sabled as %sary\n", (val & 0x01) ? "en": "dis", - (val & 0x40) ? "second" : "prim"); - } - break; - } - break; + /* Local Bus IDE Controller */ + case 0x71: + if (dev->has_ide) { + ide_pri_disable(); + ide_set_base(0, (val & 0x40) ? 0x170 : 0x1f0); + ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6); + if (val & 0x01) + ide_pri_enable(); + vt82c49x_log("VT82C496 IDE now %sabled as %sary\n", (val & 0x01) ? "en" : "dis", + (val & 0x40) ? "second" : "prim"); + } + break; + } + break; } } - static uint8_t vt82c49x_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; + uint8_t ret = 0xff; vt82c49x_t *dev = (vt82c49x_t *) priv; switch (addr) { - case 0xa9: - /* Register 64h is jumper readout. */ - if (dev->index == 0x64) - ret = 0xff; - else if (dev->index == 0x63) - ret = pic_elcr_read(dev->index, &pic2) | (dev->regs[dev->index] & 0x01); - else if (dev->index == 0x62) - ret = pic_elcr_read(dev->index, &pic) | (dev->regs[dev->index] & 0x07); - else if (dev->index < 0x80) - ret = dev->regs[dev->index]; - break; + case 0xa9: + /* Register 64h is jumper readout. */ + if (dev->index == 0x64) + ret = 0xff; + else if (dev->index == 0x63) + ret = pic_elcr_read(dev->index, &pic2) | (dev->regs[dev->index] & 0x01); + else if (dev->index == 0x62) + ret = pic_elcr_read(dev->index, &pic) | (dev->regs[dev->index] & 0x07); + else if (dev->index < 0x80) + ret = dev->regs[dev->index]; + break; } return ret; } - static void vt82c49x_reset(void *priv) { uint16_t i; for (i = 0; i < 256; i++) - vt82c49x_write(i, 0x00, priv); + vt82c49x_write(i, 0x00, priv); } - static void vt82c49x_close(void *priv) { @@ -329,21 +325,20 @@ vt82c49x_close(void *priv) free(dev); } - static void * vt82c49x_init(const device_t *info) { vt82c49x_t *dev = (vt82c49x_t *) malloc(sizeof(vt82c49x_t)); memset(dev, 0x00, sizeof(vt82c49x_t)); - dev->smram_smm = smram_add(); - dev->smram_low = smram_add(); + dev->smram_smm = smram_add(); + dev->smram_low = smram_add(); dev->smram_high = smram_add(); dev->has_ide = info->local & 1; if (dev->has_ide) { - device_add(&ide_vlb_2ch_device); - ide_sec_disable(); + device_add(&ide_vlb_2ch_device); + ide_sec_disable(); } device_add(&port_92_device); @@ -359,57 +354,57 @@ vt82c49x_init(const device_t *info) } const device_t via_vt82c49x_device = { - .name = "VIA VT82C49X", + .name = "VIA VT82C49X", .internal_name = "via_vt82c49x", - .flags = 0, - .local = 0, - .init = vt82c49x_init, - .close = vt82c49x_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = vt82c49x_init, + .close = vt82c49x_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c49x_pci_device = { - .name = "VIA VT82C49X PCI", + .name = "VIA VT82C49X PCI", .internal_name = "via_vt82c49x_pci", - .flags = DEVICE_PCI, - .local = 0, - .init = vt82c49x_init, - .close = vt82c49x_close, - .reset = vt82c49x_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = vt82c49x_init, + .close = vt82c49x_close, + .reset = vt82c49x_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c49x_ide_device = { - .name = "VIA VT82C49X (With IDE)", + .name = "VIA VT82C49X (With IDE)", .internal_name = "via_vt82c49x_ide", - .flags = 0, - .local = 1, - .init = vt82c49x_init, - .close = vt82c49x_close, - .reset = NULL, + .flags = 0, + .local = 1, + .init = vt82c49x_init, + .close = vt82c49x_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t via_vt82c49x_pci_ide_device = { - .name = "VIA VT82C49X PCI (With IDE)", + .name = "VIA VT82C49X PCI (With IDE)", .internal_name = "via_vt82c49x_pci_ide", - .flags = DEVICE_PCI, - .local = 1, - .init = vt82c49x_init, - .close = vt82c49x_close, - .reset = vt82c49x_reset, + .flags = DEVICE_PCI, + .local = 1, + .init = vt82c49x_init, + .close = vt82c49x_close, + .reset = vt82c49x_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/via_vt82c505.c b/src/chipset/via_vt82c505.c index 5ce799ab6..c6fed0144 100644 --- a/src/chipset/via_vt82c505.c +++ b/src/chipset/via_vt82c505.c @@ -29,161 +29,163 @@ #include <86box/device.h> #include <86box/chipset.h> - -typedef struct vt82c505_t -{ - uint8_t index; - uint8_t pci_conf[256]; +typedef struct vt82c505_t { + uint8_t index; + uint8_t pci_conf[256]; } vt82c505_t; - static void vt82c505_write(int func, int addr, uint8_t val, void *priv) { - vt82c505_t *dev = (vt82c505_t *) priv; - uint8_t irq; + vt82c505_t *dev = (vt82c505_t *) priv; + uint8_t irq; const uint8_t irq_array[8] = { 0, 5, 9, 10, 11, 14, 15, 0 }; if (func != 0) - return; + return; - switch(addr) { - /* RX00-07h: Mandatory header field */ - case 0x04: - dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xbf) | (val & 0x40); - break; - case 0x07: - dev->pci_conf[addr] &= ~(val & 0x90); - break; + switch (addr) { + /* RX00-07h: Mandatory header field */ + case 0x04: + dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xbf) | (val & 0x40); + break; + case 0x07: + dev->pci_conf[addr] &= ~(val & 0x90); + break; - /* RX80-9F: VT82C505 internal configuration registers */ - case 0x80: - dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x0f) | (val & 0xf0); - break; - case 0x81: case 0x84: case 0x85: case 0x87: - case 0x88: case 0x89: case 0x8a: case 0x8b: - case 0x8c: case 0x8d: case 0x8e: case 0x8f: - case 0x92: case 0x94: - dev->pci_conf[addr] = val; - break; - case 0x82: - dev->pci_conf[addr] = val & 0xdb; - break; - case 0x83: - dev->pci_conf[addr] = val & 0xf9; - break; - case 0x86: - dev->pci_conf[addr] = val & 0xef; - /* Bit 7 switches between the two PCI configuration mechanisms: - 0 = configuration mechanism 1, 1 = configuration mechanism 2 */ - pci_set_pmc(!(val & 0x80)); - break; - case 0x90: - dev->pci_conf[addr] = val; - irq = irq_array[val & 0x07]; - if ((val & 0x08) && (irq != 0)) - pci_set_irq_routing(PCI_INTC, irq); - else - pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); + /* RX80-9F: VT82C505 internal configuration registers */ + case 0x80: + dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x0f) | (val & 0xf0); + break; + case 0x81: + case 0x84: + case 0x85: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0x8f: + case 0x92: + case 0x94: + dev->pci_conf[addr] = val; + break; + case 0x82: + dev->pci_conf[addr] = val & 0xdb; + break; + case 0x83: + dev->pci_conf[addr] = val & 0xf9; + break; + case 0x86: + dev->pci_conf[addr] = val & 0xef; + /* Bit 7 switches between the two PCI configuration mechanisms: + 0 = configuration mechanism 1, 1 = configuration mechanism 2 */ + pci_set_pmc(!(val & 0x80)); + break; + case 0x90: + dev->pci_conf[addr] = val; + irq = irq_array[val & 0x07]; + if ((val & 0x08) && (irq != 0)) + pci_set_irq_routing(PCI_INTC, irq); + else + pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); - irq = irq_array[(val & 0x70) >> 4]; - if ((val & 0x80) && (irq != 0)) - pci_set_irq_routing(PCI_INTD, irq); - else - pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); - break; - case 0x91: - dev->pci_conf[addr] = val; - irq = irq_array[val & 0x07]; - if ((val & 0x08) && (irq != 0)) - pci_set_irq_routing(PCI_INTA, irq); - else - pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); + irq = irq_array[(val & 0x70) >> 4]; + if ((val & 0x80) && (irq != 0)) + pci_set_irq_routing(PCI_INTD, irq); + else + pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); + break; + case 0x91: + dev->pci_conf[addr] = val; + irq = irq_array[val & 0x07]; + if ((val & 0x08) && (irq != 0)) + pci_set_irq_routing(PCI_INTA, irq); + else + pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); - irq = irq_array[(val & 0x70) >> 4]; - if ((val & 0x80) && (irq != 0)) - pci_set_irq_routing(PCI_INTB, irq); - else - pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); - break; - case 0x93: - dev->pci_conf[addr] = val & 0xe0; - break; + irq = irq_array[(val & 0x70) >> 4]; + if ((val & 0x80) && (irq != 0)) + pci_set_irq_routing(PCI_INTB, irq); + else + pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); + break; + case 0x93: + dev->pci_conf[addr] = val & 0xe0; + break; } } - static uint8_t vt82c505_read(int func, int addr, void *priv) { vt82c505_t *dev = (vt82c505_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if (func != 0) - return ret; + return ret; ret = dev->pci_conf[addr]; return ret; } - static void vt82c505_out(uint16_t addr, uint8_t val, void *priv) { vt82c505_t *dev = (vt82c505_t *) priv; if (addr == 0xa8) - dev->index = val; + dev->index = val; else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f)) - vt82c505_write(0, dev->index, val, priv); + vt82c505_write(0, dev->index, val, priv); } - static uint8_t vt82c505_in(uint16_t addr, void *priv) { vt82c505_t *dev = (vt82c505_t *) priv; - uint8_t ret = 0xff; + uint8_t ret = 0xff; if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f)) - ret = vt82c505_read(0, dev->index, priv); + ret = vt82c505_read(0, dev->index, priv); return ret; } - static void vt82c505_reset(void *priv) { vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t)); - int i; + int i; dev->pci_conf[0x04] = 0x07; dev->pci_conf[0x07] = 0x00; for (i = 0x80; i <= 0x9f; i++) { - switch (i) { - case 0x81: - vt82c505_write(0, i, 0x01, priv); - break; - case 0x84: - vt82c505_write(0, i, 0x03, priv); - break; - case 0x93: - vt82c505_write(0, i, 0x40, priv); - break; - default: - vt82c505_write(0, i, 0x00, priv); - break; - } + switch (i) { + case 0x81: + vt82c505_write(0, i, 0x01, priv); + break; + case 0x84: + vt82c505_write(0, i, 0x03, priv); + break; + case 0x93: + vt82c505_write(0, i, 0x40, priv); + break; + default: + vt82c505_write(0, i, 0x00, priv); + break; + } } pic_reset(); pic_set_pci_flag(1); } - static void vt82c505_close(void *priv) { @@ -192,7 +194,6 @@ vt82c505_close(void *priv) free(dev); } - static void * vt82c505_init(const device_t *info) { @@ -217,15 +218,15 @@ vt82c505_init(const device_t *info) } const device_t via_vt82c505_device = { - .name = "VIA VT82C505", + .name = "VIA VT82C505", .internal_name = "via_vt82c505", - .flags = DEVICE_PCI, - .local = 0, - .init = vt82c505_init, - .close = vt82c505_close, - .reset = vt82c505_reset, + .flags = DEVICE_PCI, + .local = 0, + .init = vt82c505_init, + .close = vt82c505_close, + .reset = vt82c505_reset, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/vl82c480.c b/src/chipset/vl82c480.c index ec4703399..fa5bdce7e 100644 --- a/src/chipset/vl82c480.c +++ b/src/chipset/vl82c480.c @@ -28,148 +28,146 @@ #include <86box/chipset.h> typedef struct { - uint8_t idx, - regs[256]; + uint8_t idx, + regs[256]; } vl82c480_t; - static int vl82c480_shflags(uint8_t access) { int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY; switch (access) { - case 0x00: - default: - ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY; - break; - case 0x01: - ret = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; - break; - case 0x02: - ret = MEM_READ_INTERNAL | MEM_WRITE_EXTANY; - break; - case 0x03: - ret = MEM_READ_INTERNAL | MEM_WRITE_INTERNAL; - break; + case 0x00: + default: + ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY; + break; + case 0x01: + ret = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; + break; + case 0x02: + ret = MEM_READ_INTERNAL | MEM_WRITE_EXTANY; + break; + case 0x03: + ret = MEM_READ_INTERNAL | MEM_WRITE_INTERNAL; + break; } return ret; } - static void vl82c480_recalc(vl82c480_t *dev) { - int i, j; + int i, j; uint32_t base; - uint8_t access; + uint8_t access; - shadowbios = 0; + shadowbios = 0; shadowbios_write = 0; for (i = 0; i < 6; i++) { for (j = 0; j < 8; j += 2) { - base = 0x000a0000 + (i << 16) + (j << 13); - access = (dev->regs[0x0d + i] >> j) & 3; - mem_set_mem_state(base, 0x4000, vl82c480_shflags(access)); - shadowbios |= ((base >= 0xe0000) && (access & 0x02)); - shadowbios_write |= ((base >= 0xe0000) && (access & 0x01)); - } + base = 0x000a0000 + (i << 16) + (j << 13); + access = (dev->regs[0x0d + i] >> j) & 3; + mem_set_mem_state(base, 0x4000, vl82c480_shflags(access)); + shadowbios |= ((base >= 0xe0000) && (access & 0x02)); + shadowbios_write |= ((base >= 0xe0000) && (access & 0x01)); + } } flushmmucache(); } - static void vl82c480_write(uint16_t addr, uint8_t val, void *p) { - vl82c480_t *dev = (vl82c480_t *)p; + vl82c480_t *dev = (vl82c480_t *) p; switch (addr) { - case 0xec: - dev->idx = val; - break; + case 0xec: + dev->idx = val; + break; - case 0xed: - if (dev->idx >= 0x01 && dev->idx <= 0x24) { - switch (dev->idx) { - default: - dev->regs[dev->idx] = val; - break; - case 0x04: - if (dev->regs[0x00] == 0x98) - dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7); - else - dev->regs[dev->idx] = val; - break; - case 0x05: - dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x10) | (val & 0xef); - break; - case 0x07: - dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf); - break; - case 0x0d: case 0x0e: case 0x0f: case 0x10: - case 0x11: case 0x12: - dev->regs[dev->idx] = val; - vl82c480_recalc(dev); - break; - } - } - break; + case 0xed: + if (dev->idx >= 0x01 && dev->idx <= 0x24) { + switch (dev->idx) { + default: + dev->regs[dev->idx] = val; + break; + case 0x04: + if (dev->regs[0x00] == 0x98) + dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7); + else + dev->regs[dev->idx] = val; + break; + case 0x05: + dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x10) | (val & 0xef); + break; + case 0x07: + dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf); + break; + case 0x0d: + case 0x0e: + case 0x0f: + case 0x10: + case 0x11: + case 0x12: + dev->regs[dev->idx] = val; + vl82c480_recalc(dev); + break; + } + } + break; - case 0xee: - if (mem_a20_alt) - outb(0x92, inb(0x92) & ~2); - break; + case 0xee: + if (mem_a20_alt) + outb(0x92, inb(0x92) & ~2); + break; } } - static uint8_t vl82c480_read(uint16_t addr, void *p) { - vl82c480_t *dev = (vl82c480_t *)p; - uint8_t ret = 0xff; + vl82c480_t *dev = (vl82c480_t *) p; + uint8_t ret = 0xff; switch (addr) { - case 0xec: - ret = dev->idx; - break; + case 0xec: + ret = dev->idx; + break; - case 0xed: - ret = dev->regs[dev->idx]; - break; + case 0xed: + ret = dev->regs[dev->idx]; + break; - case 0xee: - if (!mem_a20_alt) - outb(0x92, inb(0x92) | 2); - break; + case 0xee: + if (!mem_a20_alt) + outb(0x92, inb(0x92) | 2); + break; - case 0xef: - softresetx86(); - cpu_set_edx(); - break; + case 0xef: + softresetx86(); + cpu_set_edx(); + break; } return ret; } - static void vl82c480_close(void *p) { - vl82c480_t *dev = (vl82c480_t *)p; + vl82c480_t *dev = (vl82c480_t *) p; free(dev); } - static void * vl82c480_init(const device_t *info) { - vl82c480_t *dev = (vl82c480_t *)malloc(sizeof(vl82c480_t)); + vl82c480_t *dev = (vl82c480_t *) malloc(sizeof(vl82c480_t)); memset(dev, 0, sizeof(vl82c480_t)); dev->regs[0x00] = info->local; @@ -178,10 +176,10 @@ vl82c480_init(const device_t *info) dev->regs[0x03] = 0x88; dev->regs[0x06] = 0x1b; if (info->local == 0x98) - dev->regs[0x07] = 0x21; + dev->regs[0x07] = 0x21; dev->regs[0x08] = 0x38; - io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev); + io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev); device_add(&port_92_device); @@ -189,29 +187,29 @@ vl82c480_init(const device_t *info) } const device_t vl82c480_device = { - .name = "VLSI VL82c480", + .name = "VLSI VL82c480", .internal_name = "vl82c480", - .flags = 0, - .local = 0x90, - .init = vl82c480_init, - .close = vl82c480_close, - .reset = NULL, + .flags = 0, + .local = 0x90, + .init = vl82c480_init, + .close = vl82c480_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; const device_t vl82c486_device = { - .name = "VLSI VL82c486", + .name = "VLSI VL82c486", .internal_name = "vl82c486", - .flags = 0, - .local = 0x98, - .init = vl82c480_init, - .close = vl82c480_close, - .reset = NULL, + .flags = 0, + .local = 0x98, + .init = vl82c480_init, + .close = vl82c480_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL }; diff --git a/src/chipset/wd76c10.c b/src/chipset/wd76c10.c index 12b7e19a0..c4716e1d8 100644 --- a/src/chipset/wd76c10.c +++ b/src/chipset/wd76c10.c @@ -42,7 +42,7 @@ #include <86box/chipset.h> /* Lock/Unlock Procedures */ -#define LOCK dev->lock +#define LOCK dev->lock #define UNLOCKED !dev->lock #ifdef ENABLE_WD76C10_LOG @@ -52,15 +52,14 @@ wd76c10_log(const char *fmt, ...) { va_list ap; - if (wd76c10_do_log) - { + if (wd76c10_do_log) { va_start(ap, fmt); pclog_ex(fmt, ap); va_end(ap); } } #else -#define wd76c10_log(fmt, ...) +# define wd76c10_log(fmt, ...) #endif typedef struct @@ -77,92 +76,90 @@ typedef struct int lock; - fdc_t *fdc_controller; + fdc_t *fdc_controller; mem_mapping_t *mem_mapping; - serial_t *uart[2]; + serial_t *uart[2]; } wd76c10_t; -static void wd76c10_refresh_control(wd76c10_t *dev) +static void +wd76c10_refresh_control(wd76c10_t *dev) { serial_remove(dev->uart[1]); /* Serial B */ - switch ((dev->refresh_control >> 1) & 7) - { - case 1: - serial_setup(dev->uart[1], 0x3f8, 3); - break; - case 2: - serial_setup(dev->uart[1], 0x2f8, 3); - break; - case 3: - serial_setup(dev->uart[1], 0x3e8, 3); - break; - case 4: - serial_setup(dev->uart[1], 0x2e8, 3); - break; + switch ((dev->refresh_control >> 1) & 7) { + case 1: + serial_setup(dev->uart[1], 0x3f8, 3); + break; + case 2: + serial_setup(dev->uart[1], 0x2f8, 3); + break; + case 3: + serial_setup(dev->uart[1], 0x3e8, 3); + break; + case 4: + serial_setup(dev->uart[1], 0x2e8, 3); + break; } serial_remove(dev->uart[0]); /* Serial A */ - switch ((dev->refresh_control >> 5) & 7) - { - case 1: - serial_setup(dev->uart[0], 0x3f8, 4); - break; - case 2: - serial_setup(dev->uart[0], 0x2f8, 4); - break; - case 3: - serial_setup(dev->uart[0], 0x3e8, 4); - break; - case 4: - serial_setup(dev->uart[0], 0x2e8, 4); - break; + switch ((dev->refresh_control >> 5) & 7) { + case 1: + serial_setup(dev->uart[0], 0x3f8, 4); + break; + case 2: + serial_setup(dev->uart[0], 0x2f8, 4); + break; + case 3: + serial_setup(dev->uart[0], 0x3e8, 4); + break; + case 4: + serial_setup(dev->uart[0], 0x2e8, 4); + break; } lpt1_remove(); /* LPT */ - switch ((dev->refresh_control >> 9) & 3) - { - case 1: - lpt1_init(0x3bc); - lpt1_irq(7); - break; - case 2: - lpt1_init(0x378); - lpt1_irq(7); - break; - case 3: - lpt1_init(0x278); - lpt1_irq(7); - break; + switch ((dev->refresh_control >> 9) & 3) { + case 1: + lpt1_init(0x3bc); + lpt1_irq(7); + break; + case 2: + lpt1_init(0x378); + lpt1_irq(7); + break; + case 3: + lpt1_init(0x278); + lpt1_irq(7); + break; } } -static void wd76c10_split_addr(wd76c10_t *dev) +static void +wd76c10_split_addr(wd76c10_t *dev) { - switch ((dev->split_addr >> 8) & 3) - { - case 1: - if (((dev->shadow_ram >> 8) & 3) == 2) - mem_remap_top(256); - break; - case 2: - if (((dev->shadow_ram >> 8) & 3) == 1) - mem_remap_top(320); - break; - case 3: - if (((dev->shadow_ram >> 8) & 3) == 3) - mem_remap_top(384); - break; + switch ((dev->split_addr >> 8) & 3) { + case 1: + if (((dev->shadow_ram >> 8) & 3) == 2) + mem_remap_top(256); + break; + case 2: + if (((dev->shadow_ram >> 8) & 3) == 1) + mem_remap_top(320); + break; + case 3: + if (((dev->shadow_ram >> 8) & 3) == 3) + mem_remap_top(384); + break; } } -static void wd76c10_disk_chip_select(wd76c10_t *dev) +static void +wd76c10_disk_chip_select(wd76c10_t *dev) { ide_pri_disable(); - if (!(dev->disk_chip_select & 1)) - { + if (!(dev->disk_chip_select & 1)) { ide_set_base(0, !(dev->disk_chip_select & 0x0010) ? 0x1f0 : 0x170); ide_set_side(0, !(dev->disk_chip_select & 0x0010) ? 0x3f6 : 0x376); } @@ -173,259 +170,254 @@ static void wd76c10_disk_chip_select(wd76c10_t *dev) fdc_set_base(dev->fdc_controller, !(dev->disk_chip_select & 0x0010) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR); } -static void wd76c10_shadow_recalc(wd76c10_t *dev) +static void +wd76c10_shadow_recalc(wd76c10_t *dev) { - switch ((dev->shadow_ram >> 14) & 3) - { - case 0: - mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - case 1: - mem_set_mem_state_both(0x80000, 0x20000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); - break; - case 2: - mem_set_mem_state_both(0x40000, 0x60000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); - break; - case 3: - mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); - break; + switch ((dev->shadow_ram >> 14) & 3) { + case 0: + mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + case 1: + mem_set_mem_state_both(0x80000, 0x20000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); + break; + case 2: + mem_set_mem_state_both(0x40000, 0x60000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); + break; + case 3: + mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED); + break; } - switch ((dev->shadow_ram >> 8) & 3) - { - case 0: - mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); - break; - case 2: - mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); - break; - case 3: - mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); - break; + switch ((dev->shadow_ram >> 8) & 3) { + case 0: + mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + case 1: + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); + break; + case 2: + mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); + break; + case 3: + mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)); + break; } } static void wd76c10_write(uint16_t addr, uint16_t val, void *priv) { - wd76c10_t *dev = (wd76c10_t *)priv; + wd76c10_t *dev = (wd76c10_t *) priv; - if (UNLOCKED) - { - switch (addr) - { - case 0x1072: - dev->clk_control = val; - break; + if (UNLOCKED) { + switch (addr) { + case 0x1072: + dev->clk_control = val; + break; - case 0x1872: - dev->bus_timing_power_down_ctl = val; - break; + case 0x1872: + dev->bus_timing_power_down_ctl = val; + break; - case 0x2072: - dev->refresh_control = val; - wd76c10_refresh_control(dev); - break; + case 0x2072: + dev->refresh_control = val; + wd76c10_refresh_control(dev); + break; - case 0x2872: - dev->disk_chip_select = val; - wd76c10_disk_chip_select(dev); - break; + case 0x2872: + dev->disk_chip_select = val; + wd76c10_disk_chip_select(dev); + break; - case 0x3072: - dev->prog_chip_sel_addr = val; - break; + case 0x3072: + dev->prog_chip_sel_addr = val; + break; - case 0x3872: - dev->non_page_mode_dram_timing = val; - break; + case 0x3872: + dev->non_page_mode_dram_timing = val; + break; - case 0x4072: - dev->mem_control = val; - break; + case 0x4072: + dev->mem_control = val; + break; - case 0x4872: - dev->bank10staddr = val; - break; + case 0x4872: + dev->bank10staddr = val; + break; - case 0x5072: - dev->bank32staddr = val; - break; + case 0x5072: + dev->bank32staddr = val; + break; - case 0x5872: - dev->split_addr = val; - wd76c10_split_addr(dev); - break; + case 0x5872: + dev->split_addr = val; + wd76c10_split_addr(dev); + break; - case 0x6072: - dev->shadow_ram = val & 0xffbf; - wd76c10_shadow_recalc(dev); - break; + case 0x6072: + dev->shadow_ram = val & 0xffbf; + wd76c10_shadow_recalc(dev); + break; - case 0x6872: - dev->ems_control_low_address_boundry = val & 0xecff; - break; + case 0x6872: + dev->ems_control_low_address_boundry = val & 0xecff; + break; - case 0x7072: - dev->pmc_output = (val >> 8) & 0x00ff; - break; + case 0x7072: + dev->pmc_output = (val >> 8) & 0x00ff; + break; - case 0x7872: - dev->pmc_output = val & 0xff00; - break; + case 0x7872: + dev->pmc_output = val & 0xff00; + break; - case 0x8072: - dev->pmc_timer = val; - break; + case 0x8072: + dev->pmc_timer = val; + break; - case 0x8872: - dev->pmc_input = val; - break; + case 0x8872: + dev->pmc_input = val; + break; - case 0x9072: - dev->nmi_status = val & 0x00fc; - break; + case 0x9072: + dev->nmi_status = val & 0x00fc; + break; - case 0x9872: - dev->diagnostic = val & 0xfdff; - break; + case 0x9872: + dev->diagnostic = val & 0xfdff; + break; - case 0xa072: - dev->delay_line = val; - break; + case 0xa072: + dev->delay_line = val; + break; - case 0xc872: - dev->pmc_interrupt = val & 0xfcfc; - break; + case 0xc872: + dev->pmc_interrupt = val & 0xfcfc; + break; - case 0xf072: - dev->oscillator_40mhz = 0; - break; + case 0xf072: + dev->oscillator_40mhz = 0; + break; - case 0xf472: - dev->oscillator_40mhz = 1; - break; + case 0xf472: + dev->oscillator_40mhz = 1; + break; - case 0xf872: - dev->cache_flush = val; - flushmmucache(); - break; + case 0xf872: + dev->cache_flush = val; + flushmmucache(); + break; } wd76c10_log("WD76C10: dev->regs[%04x] = %04x\n", addr, val); } - switch (addr) - { - case 0xe072: - dev->ems_page_reg_pointer = val & 0x003f; - break; + switch (addr) { + case 0xe072: + dev->ems_page_reg_pointer = val & 0x003f; + break; - case 0xe872: - dev->ems_page_reg = val & 0x8fff; - break; + case 0xe872: + dev->ems_page_reg = val & 0x8fff; + break; - case 0xf073: - dev->lock_reg = val & 0x00ff; - LOCK = !(val & 0x00da); - break; + case 0xf073: + dev->lock_reg = val & 0x00ff; + LOCK = !(val & 0x00da); + break; } } static uint16_t wd76c10_read(uint16_t addr, void *priv) { - wd76c10_t *dev = (wd76c10_t *)priv; + wd76c10_t *dev = (wd76c10_t *) priv; wd76c10_log("WD76C10: R dev->regs[%04x]\n", addr); - switch (addr) - { - case 0x1072: - return dev->clk_control; + switch (addr) { + case 0x1072: + return dev->clk_control; - case 0x1872: - return dev->bus_timing_power_down_ctl; + case 0x1872: + return dev->bus_timing_power_down_ctl; - case 0x2072: - return dev->refresh_control; + case 0x2072: + return dev->refresh_control; - case 0x2872: - return dev->disk_chip_select; + case 0x2872: + return dev->disk_chip_select; - case 0x3072: - return dev->prog_chip_sel_addr; + case 0x3072: + return dev->prog_chip_sel_addr; - case 0x3872: - return dev->non_page_mode_dram_timing; + case 0x3872: + return dev->non_page_mode_dram_timing; - case 0x4072: - return dev->mem_control; + case 0x4072: + return dev->mem_control; - case 0x4872: - return dev->bank10staddr; + case 0x4872: + return dev->bank10staddr; - case 0x5072: - return dev->bank32staddr; + case 0x5072: + return dev->bank32staddr; - case 0x5872: - return dev->split_addr; + case 0x5872: + return dev->split_addr; - case 0x6072: - return dev->shadow_ram; + case 0x6072: + return dev->shadow_ram; - case 0x6872: - return dev->ems_control_low_address_boundry; + case 0x6872: + return dev->ems_control_low_address_boundry; - case 0x7072: - return (dev->pmc_output << 8) & 0xff00; + case 0x7072: + return (dev->pmc_output << 8) & 0xff00; - case 0x7872: - return (dev->pmc_output) & 0xff00; + case 0x7872: + return (dev->pmc_output) & 0xff00; - case 0x8072: - return dev->pmc_timer; + case 0x8072: + return dev->pmc_timer; - case 0x8872: - return dev->pmc_input; + case 0x8872: + return dev->pmc_input; - case 0x9072: - return dev->nmi_status; + case 0x9072: + return dev->nmi_status; - case 0x9872: - return dev->diagnostic; + case 0x9872: + return dev->diagnostic; - case 0xa072: - return dev->delay_line; + case 0xa072: + return dev->delay_line; - case 0xb872: - return (inb(0x040b) << 8) | inb(0x04d6); + case 0xb872: + return (inb(0x040b) << 8) | inb(0x04d6); - case 0xc872: - return dev->pmc_interrupt; + case 0xc872: + return dev->pmc_interrupt; - case 0xd072: - return dev->port_shadow; + case 0xd072: + return dev->port_shadow; - case 0xe072: - return dev->ems_page_reg_pointer; + case 0xe072: + return dev->ems_page_reg_pointer; - case 0xe872: - return dev->ems_page_reg; + case 0xe872: + return dev->ems_page_reg; - case 0xfc72: - return 0x0ff0; + case 0xfc72: + return 0x0ff0; - default: - return 0xffff; + default: + return 0xffff; } } static void wd76c10_close(void *priv) { - wd76c10_t *dev = (wd76c10_t *)priv; + wd76c10_t *dev = (wd76c10_t *) priv; free(dev); } @@ -433,12 +425,12 @@ wd76c10_close(void *priv) static void * wd76c10_init(const device_t *info) { - wd76c10_t *dev = (wd76c10_t *)malloc(sizeof(wd76c10_t)); + wd76c10_t *dev = (wd76c10_t *) malloc(sizeof(wd76c10_t)); memset(dev, 0, sizeof(wd76c10_t)); device_add(&port_92_inv_device); - dev->uart[0] = device_add_inst(&ns16450_device, 1); - dev->uart[1] = device_add_inst(&ns16450_device, 2); + dev->uart[0] = device_add_inst(&ns16450_device, 1); + dev->uart[1] = device_add_inst(&ns16450_device, 2); dev->fdc_controller = device_add(&fdc_at_device); device_add(&ide_isa_device); @@ -536,15 +528,15 @@ wd76c10_init(const device_t *info) } const device_t wd76c10_device = { - .name = "Western Digital WD76C10", + .name = "Western Digital WD76C10", .internal_name = "wd76c10", - .flags = 0, - .local = 0, - .init = wd76c10_init, - .close = wd76c10_close, - .reset = NULL, + .flags = 0, + .local = 0, + .init = wd76c10_init, + .close = wd76c10_close, + .reset = NULL, { .available = NULL }, .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL + .force_redraw = NULL, + .config = NULL };