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More Cyrix fixes.

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This commit is contained in:
OBattler
2025-03-19 03:12:36 +01:00
parent 67f0e95740
commit 395f23cf57
4 changed files with 383 additions and 128 deletions
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208
src/cpu/x86_ops_cyrix.h
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@@ -35,7 +35,13 @@ opSVDC_common(uint32_t fetchdat)
static int
opSVDC_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
@@ -47,7 +53,13 @@ opSVDC_a16(uint32_t fetchdat)
static int
opSVDC_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
@@ -88,7 +100,13 @@ opRSDC_common(uint32_t fetchdat)
static int
opRSDC_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
@@ -100,7 +118,13 @@ opRSDC_a16(uint32_t fetchdat)
static int
opRSDC_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
@@ -113,7 +137,13 @@ opRSDC_a32(uint32_t fetchdat)
static int
opSVLDT_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -126,7 +156,13 @@ opSVLDT_a16(uint32_t fetchdat)
static int
opSVLDT_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -140,7 +176,13 @@ opSVLDT_a32(uint32_t fetchdat)
static int
opRSLDT_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -152,7 +194,13 @@ opRSLDT_a16(uint32_t fetchdat)
static int
opRSLDT_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -165,7 +213,13 @@ opRSLDT_a32(uint32_t fetchdat)
static int
opSVTS_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -178,7 +232,13 @@ opSVTS_a16(uint32_t fetchdat)
static int
opSVTS_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -192,7 +252,13 @@ opSVTS_a32(uint32_t fetchdat)
static int
opRSTS_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -205,7 +271,13 @@ opRSTS_a16(uint32_t fetchdat)
static int
opRSTS_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -219,9 +291,13 @@ opRSTS_a32(uint32_t fetchdat)
static int
opSMINT(UNUSED(uint32_t fetchdat))
{
uint8_t ccr1_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) &&
(cyrix.arr[3].size > 0);
if (in_smm)
fatal("opSMINT\n");
else {
else if (ccr1_check) {
is_smint = 1;
enter_smm(0);
}
@@ -232,9 +308,26 @@ opSMINT(UNUSED(uint32_t fetchdat))
static int
opRDSHR_a16(UNUSED(uint32_t fetchdat))
{
if (in_smm)
fatal("opRDSHR_a16\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
if (cpu_mod == 3) {
cpu_state.regs[cpu_rm].l = cyrix.smhr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
} else {
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(cyrix.smhr);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 0);
}
return cpu_state.abrt;
} else
x86illegal();
return 1;
@@ -242,30 +335,91 @@ opRDSHR_a16(UNUSED(uint32_t fetchdat))
static int
opRDSHR_a32(UNUSED(uint32_t fetchdat))
{
if (in_smm)
fatal("opRDSHR_a32\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
if (cpu_mod == 3) {
cpu_state.regs[cpu_rm].l = cyrix.smhr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
} else {
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(cyrix.smhr);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 1);
}
return cpu_state.abrt;
} else
x86illegal();
return 1;
}
static int
opWRSHR_a16(UNUSED(uint32_t fetchdat))
opWRSHR_a16(uint32_t fetchdat)
{
if (in_smm)
fatal("opWRSHR_a16\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
if (cpu_mod == 3) {
cyrix.smhr = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
} else {
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
temp = geteal();
if (cpu_state.abrt)
return 1;
cyrix.smhr = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 0);
}
return 0;
} else
x86illegal();
return 1;
}
static int
opWRSHR_a32(UNUSED(uint32_t fetchdat))
opWRSHR_a32(uint32_t fetchdat)
{
if (in_smm)
fatal("opWRSHR_a32\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
if (cpu_mod == 3) {
cyrix.smhr = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
} else {
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
temp = geteal();
if (cpu_state.abrt)
return 1;
cyrix.smhr = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 1);
}
return 0;
} else
x86illegal();
return 1;