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More Cyrix fixes.

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This commit is contained in:
OBattler
2025-03-19 03:12:36 +01:00
parent 67f0e95740
commit 395f23cf57
4 changed files with 383 additions and 128 deletions
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34
src/cpu/386_common.c
View File

@@ -1449,26 +1449,44 @@ enter_smm(int in_hlt)
void
enter_smm_check(int in_hlt)
{
if ((in_smm == 0) && smi_line) {
uint8_t ccr1_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) && (cyrix.arr[3].size > 0);
if (smi_line) {
if (!is_cxsmm || ccr1_check) switch (in_smm) {
default:
#ifdef ENABLE_386_COMMON_LOG
fatal("SMI while in_smm = %i\n", in_smm);
break;
#endif
case 0:
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SMI while not in SMM\n");
#endif
enter_smm(in_hlt);
} else if ((in_smm == 1) && smi_line) {
break;
case 1:
/* Mark this so that we don't latch more than one SMI. */
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SMI while in unlatched SMM\n");
#endif
smi_latched = 1;
} else if ((in_smm == 2) && smi_line) {
/* Mark this so that we don't latch more than one SMI. */
break;
case 2:
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SMI while in latched SMM\n");
#endif
break;
}
#ifdef ENABLE_386_COMMON_LOG
else {
x386_common_log("SMI while in Cyrix disabled mode\n");
x386_common_log("lol\n");
}
#endif
if (smi_line)
smi_line = 0;
}
}
void
@@ -2186,6 +2204,12 @@ cpu_fast_off_reset(void)
void
smi_raise(void)
{
uint8_t ccr1_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) && (cyrix.arr[3].size > 0);
if (is_cxsmm && !ccr1_check)
return;
if (is486 && (cpu_fast_off_flags & 0x80000000))
cpu_fast_off_advance();

120
src/cpu/cpu.c
View File

@@ -40,6 +40,7 @@
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/smram.h>
#include <86box/timer.h>
#include <86box/gdbstub.h>
#include <86box/plat_fallthrough.h>
@@ -50,13 +51,6 @@
#endif /* USE_DYNAREC */
#include "x87_timings.h"
#define CCR1_USE_SMI (1 << 1)
#define CCR1_SMAC (1 << 2)
#define CCR1_SM3 (1 << 7)
#define CCR3_SMI_LOCK (1 << 0)
#define CCR3_NMI_EN (1 << 1)
enum {
CPUID_FPU = (1 << 0), /* On-chip Floating Point Unit */
CPUID_VME = (1 << 1), /* Virtual 8086 mode extensions */
@@ -289,6 +283,10 @@ uint8_t ccr5;
uint8_t ccr6;
uint8_t ccr7;
uint8_t reg_30 = 0x00;
uint8_t arr[24] = { 0 };
uint8_t rcr[8] = { 0 };
static int cyrix_addr;
static void cpu_write(uint16_t addr, uint8_t val, void *priv);
@@ -2627,6 +2625,23 @@ cpu_ven_reset(void)
msr.amd_efer = (cpu_s->cpu_type >= CPU_K6_2C) ? 2ULL : 0ULL;
break;
case CPU_Cx6x86MX:
ccr0 = 0x00;
ccr1 = 0x00;
ccr2 = 0x00;
ccr3 = 0x00;
ccr4 = 0x80;
ccr5 = 0x00;
ccr6 = 0x00;
memset(arr, 0x00, 24);
memset(rcr, 0x00, 3);
cyrix.arr[3].base = 0x00;
cyrix.arr[3].size = 0; /* Disabled */
cyrix.smhr &= ~SMHR_VALID;
CPUID = cpu_s->cpuid_model;
reg_30 = 0xff;
break;
case CPU_PENTIUMPRO:
case CPU_PENTIUM2:
case CPU_PENTIUM2D:
@@ -4237,23 +4252,33 @@ cpu_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
picintc(1 << 13);
else
nmi = 0;
return;
} else if (addr >= 0xf1)
return; /* FPU stuff */
if (!(addr & 1))
} else if ((addr < 0xf1) && !(addr & 1))
cyrix_addr = val;
else
switch (cyrix_addr) {
else if (addr < 0xf1) switch (cyrix_addr) {
default:
if (cyrix_addr >= 0xc0)
fatal("Writing unimplemented Cyrix register %02X\n", cyrix_addr);
break;
case 0x30: /* ???? */
reg_30 = val;
break;
case 0xc0: /* CCR0 */
ccr0 = val;
break;
case 0xc1: /* CCR1 */
case 0xc1: { /* CCR1 */
uint8_t old = ccr1;
if ((ccr3 & CCR3_SMI_LOCK) && !in_smm)
val = (val & ~(CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) | (ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3));
ccr1 = val;
if ((old ^ ccr1) & (CCR1_SMAC)) {
if (ccr1 & CCR1_SMAC)
smram_backup_all();
smram_recalc_all(!(ccr1 & CCR1_SMAC));
}
break;
case 0xc2: /* CCR2 */
} case 0xc2: /* CCR2 */
ccr2 = val;
break;
case 0xc3: /* CCR3 */
@@ -4261,20 +4286,28 @@ cpu_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
val = (val & ~(CCR3_NMI_EN)) | (ccr3 & CCR3_NMI_EN) | CCR3_SMI_LOCK;
ccr3 = val;
break;
case 0xc4 ... 0xcc:
if (ccr5 & 0x20)
arr[cyrix_addr - 0xc4] = val;
break;
case 0xcd:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
if ((ccr5 & 0x20) || (!(ccr3 & CCR3_SMI_LOCK) || in_smm)) {
arr[cyrix_addr - 0xc4] = val;
cyrix.arr[3].base = (cyrix.arr[3].base & ~0xff000000) | (val << 24);
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xce:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
if ((ccr5 & 0x20) || (!(ccr3 & CCR3_SMI_LOCK) || in_smm)) {
arr[cyrix_addr - 0xc4] = val;
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x00ff0000) | (val << 16);
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xcf:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
if ((ccr5 & 0x20) || (!(ccr3 & CCR3_SMI_LOCK) || in_smm)) {
arr[cyrix_addr - 0xc4] = val;
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
if ((val & 0xf) == 0xf)
cyrix.arr[3].size = 1ULL << 32; /* 4 GB */
@@ -4285,6 +4318,15 @@ cpu_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xd0 ... 0xdb:
if (((ccr3 & 0xf0) == 0x10) && (ccr5 & 0x20))
arr[cyrix_addr - 0xc4] = val;
break;
case 0xdc ... 0xe3:
if ((ccr3 & 0xf0) == 0x10)
rcr[cyrix_addr - 0xdc] = val;
break;
case 0xe8: /* CCR4 */
if ((ccr3 & 0xf0) == 0x10) {
@@ -4319,6 +4361,15 @@ cpu_read(uint16_t addr, UNUSED(void *priv))
if (addr == 0xf007)
ret = 0x7f;
else if ((addr < 0xf0) && (addr & 1)) switch (cyrix_addr) {
default:
if (cyrix_addr >= 0xc0)
fatal("Reading unimplemented Cyrix register %02X\n", cyrix_addr);
break;
case 0x30: /* ???? */
ret = reg_30;
break;
case 0xc0:
ret = ccr0;
break;
@@ -4331,14 +4382,36 @@ cpu_read(uint16_t addr, UNUSED(void *priv))
case 0xc3:
ret = ccr3;
break;
case 0xc4 ... 0xcc:
if (ccr5 & 0x20)
ret = arr[cyrix_addr - 0xc4];
break;
case 0xcd ... 0xcf:
if ((ccr5 & 0x20) || (!(ccr3 & CCR3_SMI_LOCK) || in_smm))
ret = arr[cyrix_addr - 0xc4];
break;
case 0xd0 ... 0xdb:
if (((ccr3 & 0xf0) == 0x10) && (ccr5 & 0x20))
ret = arr[cyrix_addr - 0xc4];
break;
case 0xdc ... 0xe3:
if ((ccr3 & 0xf0) == 0x10)
ret = rcr[cyrix_addr - 0xdc];
break;
case 0xe8:
ret = ((ccr3 & 0xf0) == 0x10) ? ccr4 : 0xff;
if ((ccr3 & 0xf0) == 0x10)
ret = ccr4;
break;
case 0xe9:
ret = ((ccr3 & 0xf0) == 0x10) ? ccr5 : 0xff;
if ((ccr3 & 0xf0) == 0x10)
ret = ccr5;
break;
case 0xea:
ret = ((ccr3 & 0xf0) == 0x10) ? ccr6 : 0xff;
if ((ccr3 & 0xf0) == 0x10)
ret = ccr6;
break;
case 0xeb:
ret = ccr7;
@@ -4349,9 +4422,6 @@ cpu_read(uint16_t addr, UNUSED(void *priv))
case 0xff:
ret = cpu_s->cyrix_id >> 8;
break;
default:
break;
}
return ret;

7
src/cpu/cpu.h
View File

@@ -120,6 +120,13 @@ enum {
#define CPU_ALTERNATE_XTAL 4
#define CPU_FIXED_MULTIPLIER 8
#define CCR1_USE_SMI (1 << 1)
#define CCR1_SMAC (1 << 2)
#define CCR1_SM3 (1 << 7)
#define CCR3_SMI_LOCK (1 << 0)
#define CCR3_NMI_EN (1 << 1)
#if (defined __amd64__ || defined _M_X64)
# define LOOKUP_INV -1LL
#else

208
src/cpu/x86_ops_cyrix.h
View File

@@ -35,7 +35,13 @@ opSVDC_common(uint32_t fetchdat)
static int
opSVDC_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
@@ -47,7 +53,13 @@ opSVDC_a16(uint32_t fetchdat)
static int
opSVDC_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
@@ -88,7 +100,13 @@ opRSDC_common(uint32_t fetchdat)
static int
opRSDC_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
@@ -100,7 +118,13 @@ opRSDC_a16(uint32_t fetchdat)
static int
opRSDC_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
@@ -113,7 +137,13 @@ opRSDC_a32(uint32_t fetchdat)
static int
opSVLDT_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -126,7 +156,13 @@ opSVLDT_a16(uint32_t fetchdat)
static int
opSVLDT_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -140,7 +176,13 @@ opSVLDT_a32(uint32_t fetchdat)
static int
opRSLDT_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -152,7 +194,13 @@ opRSLDT_a16(uint32_t fetchdat)
static int
opRSLDT_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg + cpu_state.eaaddr, &ldt);
@@ -165,7 +213,13 @@ opRSLDT_a32(uint32_t fetchdat)
static int
opSVTS_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -178,7 +232,13 @@ opSVTS_a16(uint32_t fetchdat)
static int
opSVTS_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -192,7 +252,13 @@ opSVTS_a32(uint32_t fetchdat)
static int
opRSTS_a16(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -205,7 +271,13 @@ opRSTS_a16(uint32_t fetchdat)
static int
opRSTS_a32(uint32_t fetchdat)
{
if (in_smm) {
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &tr);
@@ -219,9 +291,13 @@ opRSTS_a32(uint32_t fetchdat)
static int
opSMINT(UNUSED(uint32_t fetchdat))
{
uint8_t ccr1_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) &&
(cyrix.arr[3].size > 0);
if (in_smm)
fatal("opSMINT\n");
else {
else if (ccr1_check) {
is_smint = 1;
enter_smm(0);
}
@@ -232,9 +308,26 @@ opSMINT(UNUSED(uint32_t fetchdat))
static int
opRDSHR_a16(UNUSED(uint32_t fetchdat))
{
if (in_smm)
fatal("opRDSHR_a16\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
if (cpu_mod == 3) {
cpu_state.regs[cpu_rm].l = cyrix.smhr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
} else {
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(cyrix.smhr);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 0);
}
return cpu_state.abrt;
} else
x86illegal();
return 1;
@@ -242,30 +335,91 @@ opRDSHR_a16(UNUSED(uint32_t fetchdat))
static int
opRDSHR_a32(UNUSED(uint32_t fetchdat))
{
if (in_smm)
fatal("opRDSHR_a32\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
if (cpu_mod == 3) {
cpu_state.regs[cpu_rm].l = cyrix.smhr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
} else {
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(cyrix.smhr);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 1);
}
return cpu_state.abrt;
} else
x86illegal();
return 1;
}
static int
opWRSHR_a16(UNUSED(uint32_t fetchdat))
opWRSHR_a16(uint32_t fetchdat)
{
if (in_smm)
fatal("opWRSHR_a16\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_16(fetchdat);
if (cpu_mod == 3) {
cyrix.smhr = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
} else {
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
temp = geteal();
if (cpu_state.abrt)
return 1;
cyrix.smhr = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 0);
}
return 0;
} else
x86illegal();
return 1;
}
static int
opWRSHR_a32(UNUSED(uint32_t fetchdat))
opWRSHR_a32(uint32_t fetchdat)
{
if (in_smm)
fatal("opWRSHR_a32\n");
else
uint8_t ins_check = ((ccr1 & (CCR1_USE_SMI | CCR1_SM3)) ==
(CCR1_USE_SMI | CCR1_SM3)) &&
((ccr1 & CCR1_SMAC) || in_smm) &&
(cyrix.arr[3].size > 0) &&
(CPL == 0);
if (ins_check) {
fetch_ea_32(fetchdat);
if (cpu_mod == 3) {
cyrix.smhr = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
} else {
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
temp = geteal();
if (cpu_state.abrt)
return 1;
cyrix.smhr = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 1);
}
return 0;
} else
x86illegal();
return 1;