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Machine code restructure, models are now machines instead and the init functions are in the machine files rather than in machine.c (former model.c), also moved the machine stuff into the machine/ subdirectory.

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OBattler
2017-09-02 20:39:57 +02:00
parent be16ee33ba
commit 3e10570bbd
90 changed files with 2390 additions and 2388 deletions
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267
src/machine/machine.c Normal file
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@@ -0,0 +1,267 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of the emulated machines.
*
* Version: @(#)machine.c 1.0.9 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
*/
#include <stdint.h>
#include <stdio.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../disc.h"
#include "../fdc.h"
#include "../fdd.h"
#include "../io.h"
#include "machine.h"
#include "machine_common.h"
#include "machine_amstrad.h"
#include "machine_europc.h"
#include "machine_olivetti_m24.h"
#include "machine_pcjr.h"
#include "machine_tandy.h"
#include "machine_xt.h"
#include "machine_xt_laserxt.h"
#include "machine_at.h"
#include "machine_at_ali1429.h"
#include "machine_at_commodore.h"
#include "machine_at_headland.h"
#include "machine_at_neat.h"
#include "machine_at_opti495.h"
#include "machine_at_scat.h"
#include "machine_at_wd76c10.h"
#include "machine_ps1.h"
#include "machine_ps2_isa.h"
#include "machine_ps2_mca.h"
#include "machine_at_sis_85c471.h"
#include "machine_at_sis_85c496.h"
#include "machine_at_430lx_nx.h"
#include "machine_at_430fx.h"
#include "machine_at_430hx.h"
#include "machine_at_430vx.h"
#include "machine_at_440fx.h"
#include "../video/vid_pcjr.h"
#include "../video/vid_tandy.h"
#include "../video/vid_tandysl.h"
int machine;
int AMSTRAD, AT, PCI, TANDY;
int serial_enabled[SERIAL_MAX] = { 0, 0 };
int lpt_enabled = 0, bugger_enabled = 0;
int romset;
machine_t machines[] =
{
{"[8088] AMI XT clone", ROM_AMIXT, "amixt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] Compaq Portable", ROM_PORTABLE, "portable", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 128, 640, 128, 0, machine_xt_init, NULL },
{"[8088] DTK XT clone", ROM_DTKXT, "dtk", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] IBM PC", ROM_IBMPC, "ibmpc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 32, 0, machine_xt_init, NULL },
{"[8088] IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{"[8088] IBM XT", ROM_IBMXT, "ibmxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] Generic XT clone", ROM_GENXT, "genxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] Juko XT clone", ROM_JUKOPC, "jukopc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] Phoenix XT clone", ROM_PXXT, "pxxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, machine_xt_init, NULL },
{"[8088] Schneider EuroPC", ROM_EUROPC, "europc", {{"", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 512, 640, 128, 0, machine_europc_init, NULL },
{"[8088] Tandy 1000", ROM_TANDY, "tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, machine_tandy1k_init, tandy1000_get_device },
{"[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 256, 640, 128, 0, machine_tandy1k_init, tandy1000hx_get_device },
{"[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, machine_xt_laserxt_init, NULL },
{"[8088] VTech Laser XT3", ROM_LXT3, "lxt3", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, machine_xt_laserxt_init, NULL },
{"[8086] Amstrad PC1512", ROM_PC1512, "pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AMSTRAD, 512, 640, 128, 63, machine_amstrad_init, NULL },
{"[8086] Amstrad PC1640", ROM_PC1640, "pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AMSTRAD, 640, 640, 0, 63, machine_amstrad_init, NULL },
{"[8086] Amstrad PC2086", ROM_PC2086, "pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AMSTRAD, 640, 640, 0, 63, machine_amstrad_init, NULL },
{"[8086] Amstrad PC3086", ROM_PC3086, "pc3086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AMSTRAD, 640, 640, 0, 63, machine_amstrad_init, NULL },
{"[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_OLIM24, 128, 640, 128, 0, machine_olim24_init, NULL },
{"[8086] Sinclair PC200", ROM_PC200, "pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AMSTRAD, 512, 640, 128, 63, machine_amstrad_init, NULL },
{"[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 512, 768, 128, 0, machine_tandy1ksl2_init, NULL },
{"[286 ISA] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_neat_init, NULL },
{"[286 ISA] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_scat_init, NULL },
{"[286 ISA] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{"[286 ISA] Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_scat_init, NULL },
{"[286 ISA] IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT, 256,15872, 128, 63, machine_at_top_remap_init, NULL },
{"[286 ISA] IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD, 512,16384, 512, 127, machine_ps1_m2011_init, NULL },
{"[286 ISA] IBM PS/2 model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{"[286 ISA] Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_scat_init, NULL },
{"[286 MCA] IBM PS/2 model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD | MACHINE_MCA, 1, 16, 1, 63, machine_ps2_model_50_init, NULL },
{"[386SX ISA] AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_headland_init, NULL },
{"[386SX ISA] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 1, 16, 1, 127, machine_at_wd76c10_init, NULL },
{"[386SX ISA] Award 386SX clone", ROM_AWARD386SX_OPTI495, "award386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{"[386SX ISA] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 512,16384, 128, 127, machine_at_neat_init, NULL },
{"[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 1, 16, 1, 127, machine_ps1_m2121_init, NULL },
{"[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 1, 16, 1, 127, machine_ps1_m2121_init, NULL },
{"[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD | MACHINE_MCA, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
{"[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{"[386DX ISA] Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 1, 16, 1, 127, machine_at_wd76c10_init, NULL },
{"[386DX ISA] Award 386DX clone", ROM_AWARD386DX_OPTI495, "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{"[386DX ISA] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{"[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD | MACHINE_MCA, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
{"[486 ISA] AMI 486 clone", ROM_AMI486, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{"[486 ISA] AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{"[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{"[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_at_dtk486_init, NULL },
{"[486 ISA] IBM PS/1 machine 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE, 1, 64, 1, 127, machine_ps1_m2133_init, NULL },
{"[486 MCA] IBM PS/2 model 80-486", ROM_IBMPS2_M80, "ibmps2_m80-486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_AT | MACHINE_PS2 | MACHINE_PS2_HDD | MACHINE_MCA, 1, 32, 1, 63, machine_ps2_model_80_486_init, NULL },
{"[486 PCI] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE | MACHINE_PCI, 1, 64, 1, 127, machine_at_r418_init, NULL },
{"[Socket 4 LX] Intel Premiere/PCI", ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_batman_init, NULL },
{"[Socket 5 NX] Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_plato_init, NULL },
{"[Socket 5 FX] ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_p54tp4xe_init, NULL },
{"[Socket 5 FX] Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_endeavor_init, NULL },
{"[Socket 5 FX] Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_zappa_init, NULL },
{"[Socket 5 FX] PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_mb500n_init, NULL },
{"[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT, "president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_HAS_IDE | MACHINE_PCI, 1, 128, 1, 127, machine_at_president_init, NULL },
{"[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_thor_init, NULL },
{"[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_thor_init, NULL },
{"[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_acerm3a_init, NULL },
{"[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_acerv35n_init, NULL },
{"[Socket 7 HX] AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_ap53_init, NULL },
{"[Socket 7 HX] ASUS P/I-P55T2P4", ROM_P55T2P4, "p55t2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_p55t2p4_init, NULL },
{"[Socket 7 HX] ASUS P/I-P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_p55t2s_init, NULL },
{"[Socket 7 VX] ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_p55tvp4_init, NULL },
{"[Socket 7 VX] Award 430VX PCI", ROM_430VX, "430vx", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_i430vx_init, NULL },
{"[Socket 7 VX] Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_p55va_init, NULL },
{"[Socket 8 FX] Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_i440fx_init, NULL },
{"[Socket 8 FX] Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_AT | MACHINE_PS2 | MACHINE_HAS_IDE | MACHINE_PCI, 1, 256, 1, 127, machine_at_s1668_init, NULL },
{"", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0,0, 0 }
};
int machine_count(void)
{
return (sizeof(machines) / sizeof(machine)) - 1;
}
int machine_getromset(void)
{
return machines[machine].id;
}
int machine_getromset_ex(int m)
{
return machines[m].id;
}
int machine_getmachine(int romset)
{
int c = 0;
while (machines[c].id != -1)
{
if (machines[c].id == romset)
return c;
c++;
}
return 0;
}
char *machine_getname(void)
{
return machines[machine].name;
}
device_t *machine_getdevice(int machine)
{
if (machines[machine].get_device)
{
return machines[machine].get_device();
}
else
{
return NULL;
}
}
char *machine_get_internal_name(void)
{
return machines[machine].internal_name;
}
char *machine_get_internal_name_ex(int m)
{
return machines[m].internal_name;
}
int machine_get_nvrmask(int m)
{
return machines[m].nvrmask;
}
int machine_get_machine_from_internal_name(char *s)
{
int c = 0;
while (machines[c].id != -1)
{
if (!strcmp(machines[c].internal_name, s))
return c;
c++;
}
return 0;
}
void machine_init(void)
{
pclog("Initializing as %s\n", machine_getname());
AMSTRAD = AT = PCI = TANDY = 0;
io_init();
fdc_update_is_nsc(0);
machines[machine].init();
if (machines[machine].get_device)
device_add(machines[machine].get_device());
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of the emulated machines.
*
* Version: @(#)machine.h 1.0.3 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#ifndef EMU_MACHINE_H
# define EMU_MACHINE_H
#define MACHINE_AT 1
#define MACHINE_PS2 2
#define MACHINE_AMSTRAD 4
#define MACHINE_OLIM24 8
#define MACHINE_HAS_IDE 16
#define MACHINE_MCA 32
#define MACHINE_PCI 64
#define MACHINE_PS2_HDD 128
#define MACHINE_NEC 256
#define MACHINE_FUJITSU 512
#define MACHINE_RM 1024
typedef struct {
char name[64];
int id;
char internal_name[24];
struct {
char name[16];
CPU *cpus;
} cpu[5];
int fixed_gfxcard;
int flags;
int min_ram, max_ram;
int ram_granularity;
int nvrmask;
void (*init)(void);
device_t *(*get_device)(void);
} machine_t;
/* Global variables. */
extern machine_t machines[];
extern int machine;
/* Core functions. */
extern int machine_count(void);
extern int machine_getromset(void);
extern int machine_getmachine(int romset);
extern char *machine_getname(void);
extern char *machine_get_internal_name(void);
extern int machine_get_machine_from_internal_name(char *s);
extern void machine_init(void);
extern device_t *machine_getdevice(int machine);
extern int machine_getromset_ex(int m);
extern char *machine_get_internal_name_ex(int m);
extern int machine_get_nvrmask(int m);
/* Global variables for boards and systems. */
#ifdef EMU_MOUSE_H
extern mouse_t mouse_amstrad;
extern mouse_t mouse_olim24;
#endif
#endif /*EMU_MACHINE_H*/

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#include <stdlib.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../disc.h"
#include "../fdd.h"
#include "../fdc.h"
#include "../gameport.h"
#include "../io.h"
#include "../keyboard.h"
#include "../keyboard_amstrad.h"
#include "../lpt.h"
#include "../mem.h"
#include "../mouse.h"
#include "../nmi.h"
#include "../nvr.h"
#include "machine_common.h"
static uint8_t amstrad_dead;
static uint8_t amstrad_read(uint16_t port, void *priv)
{
pclog("amstrad_read : %04X\n",port);
switch (port)
{
case 0x379:
return 7;
case 0x37a:
if (romset == ROM_PC1512) return 0x20;
if (romset == ROM_PC200) return 0x80;
return 0;
case 0xdead:
return amstrad_dead;
}
return 0xff;
}
static void amstrad_write(uint16_t port, uint8_t val, void *priv)
{
switch (port)
{
case 0xdead:
amstrad_dead = val;
break;
}
}
static uint8_t mousex, mousey;
static void amstrad_mouse_write(uint16_t addr, uint8_t val, void *p)
{
if (addr == 0x78)
mousex = 0;
else
mousey = 0;
}
static uint8_t amstrad_mouse_read(uint16_t addr, void *p)
{
if (addr == 0x78)
return mousex;
return mousey;
}
typedef struct mouse_amstrad_t
{
int oldb;
} mouse_amstrad_t;
static uint8_t mouse_amstrad_poll(int x, int y, int z, int b, void *p)
{
mouse_amstrad_t *mouse = (mouse_amstrad_t *)p;
mousex += x;
mousey -= y;
if ((b & 1) && !(mouse->oldb & 1))
keyboard_send(0x7e);
if ((b & 2) && !(mouse->oldb & 2))
keyboard_send(0x7d);
if (!(b & 1) && (mouse->oldb & 1))
keyboard_send(0xfe);
if (!(b & 2) && (mouse->oldb & 2))
keyboard_send(0xfd);
mouse->oldb = b;
return(0);
}
static void *mouse_amstrad_init(void)
{
mouse_amstrad_t *mouse = (mouse_amstrad_t *)malloc(sizeof(mouse_amstrad_t));
memset(mouse, 0, sizeof(mouse_amstrad_t));
return mouse;
}
static void mouse_amstrad_close(void *p)
{
mouse_amstrad_t *mouse = (mouse_amstrad_t *)p;
free(mouse);
}
mouse_t mouse_amstrad =
{
"Amstrad mouse",
"amstrad",
MOUSE_TYPE_AMSTRAD,
mouse_amstrad_init,
mouse_amstrad_close,
mouse_amstrad_poll
};
static void amstrad_init(void)
{
lpt2_remove_ams();
io_sethandler(0x0078, 0x0001, amstrad_mouse_read, NULL, NULL, amstrad_mouse_write, NULL, NULL, NULL);
io_sethandler(0x007a, 0x0001, amstrad_mouse_read, NULL, NULL, amstrad_mouse_write, NULL, NULL, NULL);
io_sethandler(0x0379, 0x0002, amstrad_read, NULL, NULL, NULL, NULL, NULL, NULL);
io_sethandler(0xdead, 0x0001, amstrad_read, NULL, NULL, amstrad_write, NULL, NULL, NULL);
}
void machine_amstrad_init(void)
{
AMSTRAD = 1;
machine_common_init();
mem_add_bios();
amstrad_init();
keyboard_amstrad_init();
nvr_init();
nmi_init();
fdc_set_dskchg_activelow();
if (joystick_type != 7)
device_add(&gameport_device);
}

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void machine_amstrad_init(void);

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#include "../ibm.h"
#include "../bugger.h"
#include "../device.h"
#include "../dma.h"
#include "../gameport.h"
#include "../hdd/hdd_ide_at.h"
#include "../keyboard_at.h"
#include "../lpt.h"
#include "../mem.h"
#include "../nvr.h"
#include "../pic.h"
#include "../pit.h"
#include "machine_common.h"
#include "machine_at.h"
void machine_at_init(void)
{
AT = 1;
machine_common_init();
if (lpt_enabled)
lpt2_remove();
mem_add_bios();
pit_set_out_func(&pit, 1, pit_refresh_timer_at);
dma16_init();
keyboard_at_init();
nvr_init();
pic2_init();
if (joystick_type != 7)
device_add(&gameport_device);
if (bugger_enabled)
bugger_init();
}
void machine_at_ide_init(void)
{
machine_at_init();
ide_init();
}
void machine_at_top_remap_init(void)
{
machine_at_init();
mem_remap_top_384k();
}
void machine_at_ide_top_remap_init(void)
{
machine_at_ide_init();
mem_remap_top_384k();
}

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void machine_at_init(void);
void machine_at_ide_init(void);
void machine_at_top_remap_init(void);
void machine_at_ide_top_remap_init(void);

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 430FX PCISet chip.
*
* Version: @(#)machine_at_430fx.c 1.0.3 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../fdc37c665.h"
#include "../intel_flash.h"
#include "../mem.h"
#include "../memregs.h"
#include "../pc87306.h"
#include "../pci.h"
#include "../piix.h"
#include "../w83877f.h"
#include "machine_at.h"
#include "machine_at_430fx.h"
static uint8_t card_i430fx[256];
static void i430fx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void i430fx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
return;
if (addr >= 0x10 && addr < 0x4f)
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x02;
val |= 0x04;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x59: /*PAM0*/
if ((card_i430fx[0x59] ^ val) & 0xf0)
{
i430fx_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
pclog("i430fx_write : PAM0 write %02X\n", val);
break;
case 0x5a: /*PAM1*/
if ((card_i430fx[0x5a] ^ val) & 0x0f)
i430fx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i430fx[0x5a] ^ val) & 0xf0)
i430fx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((card_i430fx[0x5b] ^ val) & 0x0f)
i430fx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i430fx[0x5b] ^ val) & 0xf0)
i430fx_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((card_i430fx[0x5c] ^ val) & 0x0f)
i430fx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i430fx[0x5c] ^ val) & 0xf0)
i430fx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i430fx[0x5d] ^ val) & 0x0f)
i430fx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i430fx[0x5d] ^ val) & 0xf0)
i430fx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i430fx[0x5e] ^ val) & 0x0f)
i430fx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i430fx[0x5e] ^ val) & 0xf0)
i430fx_map(0xe4000, 0x04000, val >> 4);
pclog("i430fx_write : PAM5 write %02X\n", val);
break;
case 0x5f: /*PAM6*/
if ((card_i430fx[0x5f] ^ val) & 0x0f)
i430fx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i430fx[0x5f] ^ val) & 0xf0)
i430fx_map(0xec000, 0x04000, val >> 4);
pclog("i430fx_write : PAM6 write %02X\n", val);
break;
}
card_i430fx[addr] = val;
}
static uint8_t i430fx_read(int func, int addr, void *priv)
{
if (func)
return 0xff;
return card_i430fx[addr];
}
static void i430fx_reset(void)
{
memset(card_i430fx, 0, 256);
card_i430fx[0x00] = 0x86; card_i430fx[0x01] = 0x80; /*Intel*/
card_i430fx[0x02] = 0x22; card_i430fx[0x03] = 0x01; /*SB82437FX-66*/
card_i430fx[0x04] = 0x06; card_i430fx[0x05] = 0x00;
card_i430fx[0x06] = 0x00; card_i430fx[0x07] = 0x82;
if (romset == ROM_MB500N) card_i430fx[0x07] = 0x02;
card_i430fx[0x08] = 0x00; /*A0 stepping*/
card_i430fx[0x09] = 0x00; card_i430fx[0x0a] = 0x00; card_i430fx[0x0b] = 0x06;
card_i430fx[0x52] = 0x40; /*256kb PLB cache*/
if (romset == ROM_MB500N)
{
card_i430fx[0x52] = 0x42;
card_i430fx[0x53] = 0x14;
card_i430fx[0x56] = 0x52; /*DRAM control*/
}
card_i430fx[0x57] = 0x01;
card_i430fx[0x60] = card_i430fx[0x61] = card_i430fx[0x62] = card_i430fx[0x63] = card_i430fx[0x64] = 0x02;
if (romset == ROM_MB500N)
{
card_i430fx[0x67] = 0x11;
card_i430fx[0x69] = 0x03;
card_i430fx[0x70] = 0x20;
}
card_i430fx[0x72] = 0x02;
if (romset == ROM_MB500N)
{
card_i430fx[0x74] = 0x0e;
card_i430fx[0x78] = 0x23;
}
}
static void i430fx_pci_reset(void)
{
i430fx_write(0, 0x59, 0x00, NULL);
}
static void i430fx_init(void)
{
pci_add_card(0, i430fx_read, i430fx_write, NULL);
i430fx_reset();
pci_reset_handler.pci_master_reset = i430fx_pci_reset;
}
void machine_at_p54tp4xe_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
fdc37c665_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_endeavor_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
pc87306_init();
device_add(&intel_flash_bxt_ami_device);
}
void machine_at_zappa_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
pc87306_init();
device_add(&intel_flash_bxt_ami_device);
}
void machine_at_mb500n_init(void)
{
machine_at_ide_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
fdc37c665_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_president_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
w83877f_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_thor_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
pc87306_init();
device_add(&intel_flash_bxt_ami_device);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel 430FX PCISet chip.
*
* Version: @(#)machine_at_430fx.h 1.0.0 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
void machine_at_p54tp4xe_init(void);
void machine_at_endeavor_init(void);
void machine_at_zappa_init(void);
void machine_at_mb500n_init(void);
void machine_at_president_init(void);
void machine_at_thor_init(void);

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 430HX PCISet chip.
*
* Version: @(#)machine_at_430hx.c 1.0.3 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../fdc37c669.h"
#include "../fdc37c932fr.h"
#include "../io.h"
#include "../intel_flash.h"
#include "../mem.h"
#include "../memregs.h"
#include "../pc87306.h"
#include "../pci.h"
#include "../piix.h"
#include "../w83877f.h"
#include "machine_at.h"
#include "machine_at_430hx.h"
static uint8_t card_i430hx[256];
static void i430hx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void i430hx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x02;
val |= 0x04;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val &= 0x80;
val |= 0x02;
break;
case 0x59: /*PAM0*/
if ((card_i430hx[0x59] ^ val) & 0xf0)
{
i430hx_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
break;
case 0x5a: /*PAM1*/
if ((card_i430hx[0x5a] ^ val) & 0x0f)
i430hx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i430hx[0x5a] ^ val) & 0xf0)
i430hx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((card_i430hx[0x5b] ^ val) & 0x0f)
i430hx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i430hx[0x5b] ^ val) & 0xf0)
i430hx_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((card_i430hx[0x5c] ^ val) & 0x0f)
i430hx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i430hx[0x5c] ^ val) & 0xf0)
i430hx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i430hx[0x5d] ^ val) & 0x0f)
i430hx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i430hx[0x5d] ^ val) & 0xf0)
i430hx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i430hx[0x5e] ^ val) & 0x0f)
i430hx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i430hx[0x5e] ^ val) & 0xf0)
i430hx_map(0xe4000, 0x04000, val >> 4);
break;
case 0x5f: /*PAM6*/
if ((card_i430hx[0x5f] ^ val) & 0x0f)
i430hx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i430hx[0x5f] ^ val) & 0xf0)
i430hx_map(0xec000, 0x04000, val >> 4);
break;
}
card_i430hx[addr] = val;
}
static uint8_t i430hx_read(int func, int addr, void *priv)
{
if (func)
return 0xff;
return card_i430hx[addr];
}
static void i430hx_reset(void)
{
memset(card_i430hx, 0, 256);
card_i430hx[0x00] = 0x86; card_i430hx[0x01] = 0x80; /*Intel*/
card_i430hx[0x02] = 0x50; card_i430hx[0x03] = 0x12; /*82439HX*/
card_i430hx[0x04] = 0x06; card_i430hx[0x05] = 0x00;
card_i430hx[0x06] = 0x00; card_i430hx[0x07] = 0x02;
card_i430hx[0x08] = 0x00; /*A0 stepping*/
card_i430hx[0x09] = 0x00; card_i430hx[0x0a] = 0x00; card_i430hx[0x0b] = 0x06;
card_i430hx[0x51] = 0x20;
card_i430hx[0x52] = 0xB5; /*512kb cache*/
card_i430hx[0x59] = 0x40;
card_i430hx[0x5A] = card_i430hx[0x5B] = card_i430hx[0x5C] = card_i430hx[0x5D] = card_i430hx[0x5E] = card_i430hx[0x5F] = 0x44;
card_i430hx[0x56] = 0x52; /*DRAM control*/
card_i430hx[0x57] = 0x01;
card_i430hx[0x60] = card_i430hx[0x61] = card_i430hx[0x62] = card_i430hx[0x63] = card_i430hx[0x64] = card_i430hx[0x65] = card_i430hx[0x66] = card_i430hx[0x67] = 0x02;
card_i430hx[0x68] = 0x11;
card_i430hx[0x72] = 0x02;
}
static void i430hx_pci_reset(void)
{
i430hx_write(0, 0x59, 0x00, NULL);
}
static void i430hx_init(void)
{
pci_add_card(0, i430hx_read, i430hx_write, NULL);
i430hx_reset();
pci_reset_handler.pci_master_reset = i430hx_pci_reset;
}
void machine_at_acerm3a_init(void)
{
machine_at_ide_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x10, PCI_CARD_ONBOARD, 4, 0, 0, 0);
i430hx_init();
piix3_init(7);
fdc37c932fr_init();
device_add(&intel_flash_bxb_device);
}
void machine_at_acerv35n_init(void)
{
machine_at_ide_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
i430hx_init();
piix3_init(7);
fdc37c932fr_init();
device_add(&intel_flash_bxb_device);
}
void machine_at_ap53_init(void)
{
machine_at_ide_init();
memregs_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_ONBOARD, 1, 2, 3, 4);
i430hx_init();
piix3_init(7);
fdc37c669_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_p55t2p4_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430hx_init();
piix3_init(7);
w83877f_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_p55t2s_init(void)
{
machine_at_ide_init();
memregs_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430hx_init();
piix3_init(7);
pc87306_init();
device_add(&intel_flash_bxt_device);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel 430HX PCISet chip.
*
* Version: @(#)machine_at_430hx.h 1.0.0 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
void machine_at_acerm3a_init(void);
void machine_at_acerv35n_init(void);
void machine_at_ap53_init(void);
void machine_at_p55t2p4_init(void);
void machine_at_p55t2s_init(void);

241
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 430LX and 430NX PCISet chips.
*
* Version: @(#)machine_at_430lx_nx.c 1.0.3 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../fdc37c665.h"
#include "../intel.h"
#include "../intel_flash.h"
#include "../mem.h"
#include "../memregs.h"
#include "../pci.h"
#include "../sio.h"
#include "machine_at.h"
#include "machine_at_430lx_nx.h"
static uint8_t card_i430_lx_nx[256];
static void i430lx_nx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void i430lx_nx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
break;
case 0x05:
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x59: /*PAM0*/
if ((card_i430_lx_nx[0x59] ^ val) & 0xf0)
{
i430lx_nx_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
pclog("i430lx_write : PAM0 write %02X\n", val);
break;
case 0x5a: /*PAM1*/
if ((card_i430_lx_nx[0x5a] ^ val) & 0x0f)
i430lx_nx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5a] ^ val) & 0xf0)
i430lx_nx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if (romset == ROM_REVENGE)
{
if ((card_i430_lx_nx[0x5b] ^ val) & 0x0f)
i430lx_nx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5b] ^ val) & 0xf0)
i430lx_nx_map(0xcc000, 0x04000, val >> 4);
}
break;
case 0x5c: /*PAM3*/
if ((card_i430_lx_nx[0x5c] ^ val) & 0x0f)
i430lx_nx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5c] ^ val) & 0xf0)
i430lx_nx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i430_lx_nx[0x5d] ^ val) & 0x0f)
i430lx_nx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5d] ^ val) & 0xf0)
i430lx_nx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i430_lx_nx[0x5e] ^ val) & 0x0f)
i430lx_nx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5e] ^ val) & 0xf0)
i430lx_nx_map(0xe4000, 0x04000, val >> 4);
pclog("i430lx_write : PAM5 write %02X\n", val);
break;
case 0x5f: /*PAM6*/
if ((card_i430_lx_nx[0x5f] ^ val) & 0x0f)
i430lx_nx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i430_lx_nx[0x5f] ^ val) & 0xf0)
i430lx_nx_map(0xec000, 0x04000, val >> 4);
pclog("i430lx_write : PAM6 write %02X\n", val);
break;
}
card_i430_lx_nx[addr] = val;
}
static uint8_t i430lx_nx_read(int func, int addr, void *priv)
{
if (func)
return 0xff;
return card_i430_lx_nx[addr];
}
static void i430lx_nx_reset_common(void)
{
memset(card_i430_lx_nx, 0, 256);
card_i430_lx_nx[0x00] = 0x86; card_i430_lx_nx[0x01] = 0x80; /*Intel*/
card_i430_lx_nx[0x02] = 0xa3; card_i430_lx_nx[0x03] = 0x04; /*82434LX/NX*/
card_i430_lx_nx[0x04] = 0x06; card_i430_lx_nx[0x05] = 0x00;
card_i430_lx_nx[0x06] = 0x00; card_i430_lx_nx[0x07] = 0x02;
card_i430_lx_nx[0x09] = 0x00; card_i430_lx_nx[0x0a] = 0x00; card_i430_lx_nx[0x0b] = 0x06;
card_i430_lx_nx[0x57] = 0x31;
card_i430_lx_nx[0x60] = card_i430_lx_nx[0x61] = card_i430_lx_nx[0x62] = card_i430_lx_nx[0x63] = card_i430_lx_nx[0x64] = 0x02;
}
static void i430lx_reset(void)
{
i430lx_nx_reset_common();
card_i430_lx_nx[0x08] = 0x03; /*A3 stepping*/
card_i430_lx_nx[0x50] = 0x80;
card_i430_lx_nx[0x52] = 0x40; /*256kb PLB cache*/
}
static void i430nx_reset(void)
{
i430lx_nx_reset_common();
card_i430_lx_nx[0x08] = 0x10; /*A0 stepping*/
card_i430_lx_nx[0x50] = 0xA0;
card_i430_lx_nx[0x52] = 0x44; /*256kb PLB cache*/
card_i430_lx_nx[0x66] = card_i430_lx_nx[0x67] = 0x02;
}
static void i430lx_nx_pci_reset(void)
{
i430lx_nx_write(0, 0x59, 0x00, NULL);
}
static void i430lx_init(void)
{
pci_add_card(0, i430lx_nx_read, i430lx_nx_write, NULL);
i430lx_reset();
pci_reset_handler.pci_master_reset = i430lx_nx_pci_reset;
}
static void i430nx_init(void)
{
pci_add_card(0, i430lx_nx_read, i430lx_nx_write, NULL);
i430nx_reset();
pci_reset_handler.pci_master_reset = i430lx_nx_pci_reset;
}
static void machine_at_premiere_common_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
sio_init(2);
fdc37c665_init();
intel_batman_init();
device_add(&intel_flash_bxt_ami_device);
}
void machine_at_batman_init(void)
{
machine_at_premiere_common_init();
i430lx_init();
}
void machine_at_plato_init(void)
{
machine_at_premiere_common_init();
i430nx_init();
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel 430LX and 430NX
* PCISet chips.
*
* Version: @(#)machine_at_430lx_nx.h 1.0.0 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
void machine_at_batman_init(void);
void machine_at_plato_init(void);

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 430VX PCISet chip.
*
* Version: @(#)machine_at_430vx.c 1.0.4 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../fdc37c932fr.h"
#include "../io.h"
#include "../mem.h"
#include "../memregs.h"
#include "../intel_flash.h"
#include "../pci.h"
#include "../piix.h"
#include "../um8669f.h"
#include "../w83877f.h"
#include "machine_at.h"
#include "machine_at_430vx.h"
static uint8_t card_i430vx[256];
static void i430vx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void i430vx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x02;
val |= 0x04;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val &= 0x80;
val |= 0x02;
break;
case 0x59: /*PAM0*/
if ((card_i430vx[0x59] ^ val) & 0xf0)
{
i430vx_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
/* pclog("i430vx_write : PAM0 write %02X\n", val); */
break;
case 0x5a: /*PAM1*/
if ((card_i430vx[0x5a] ^ val) & 0x0f)
i430vx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5a] ^ val) & 0xf0)
i430vx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((card_i430vx[0x5b] ^ val) & 0x0f)
i430vx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5b] ^ val) & 0xf0)
i430vx_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((card_i430vx[0x5c] ^ val) & 0x0f)
i430vx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5c] ^ val) & 0xf0)
i430vx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i430vx[0x5d] ^ val) & 0x0f)
i430vx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5d] ^ val) & 0xf0)
i430vx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i430vx[0x5e] ^ val) & 0x0f)
i430vx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i430vx[0x5e] ^ val) & 0xf0)
i430vx_map(0xe4000, 0x04000, val >> 4);
/* pclog("i430vx_write : PAM5 write %02X\n", val); */
break;
case 0x5f: /*PAM6*/
if ((card_i430vx[0x5f] ^ val) & 0x0f)
i430vx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i430vx[0x5f] ^ val) & 0xf0)
i430vx_map(0xec000, 0x04000, val >> 4);
/* pclog("i430vx_write : PAM6 write %02X\n", val); */
break;
}
card_i430vx[addr] = val;
}
static uint8_t i430vx_read(int func, int addr, void *priv)
{
if (func)
return 0xff;
return card_i430vx[addr];
}
static void i430vx_reset(void)
{
memset(card_i430vx, 0, 256);
card_i430vx[0x00] = 0x86; card_i430vx[0x01] = 0x80; /*Intel*/
card_i430vx[0x02] = 0x30; card_i430vx[0x03] = 0x70; /*82437VX*/
card_i430vx[0x04] = 0x06; card_i430vx[0x05] = 0x00;
card_i430vx[0x06] = 0x00; card_i430vx[0x07] = 0x02;
card_i430vx[0x08] = 0x00; /*A0 stepping*/
card_i430vx[0x09] = 0x00; card_i430vx[0x0a] = 0x00; card_i430vx[0x0b] = 0x06;
card_i430vx[0x52] = 0x42; /*256kb PLB cache*/
card_i430vx[0x53] = 0x14;
card_i430vx[0x56] = 0x52; /*DRAM control*/
card_i430vx[0x57] = 0x01;
card_i430vx[0x60] = card_i430vx[0x61] = card_i430vx[0x62] = card_i430vx[0x63] = card_i430vx[0x64] = 0x02;
card_i430vx[0x67] = 0x11;
card_i430vx[0x69] = 0x03;
card_i430vx[0x70] = 0x20;
card_i430vx[0x72] = 0x02;
card_i430vx[0x74] = 0x0e;
card_i430vx[0x78] = 0x23;
}
static void i430vx_pci_reset(void)
{
i430vx_write(0, 0x59, 0x00, NULL);
}
void i430vx_init(void)
{
pci_add_card(0, i430vx_read, i430vx_write, NULL);
i430vx_reset();
pci_reset_handler.pci_master_reset = i430vx_pci_reset;
}
void machine_at_p55tvp4_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430vx_init();
piix3_init(7);
w83877f_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_i430vx_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430vx_init();
piix3_init(7);
um8669f_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_p55va_init(void)
{
machine_at_ide_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430vx_init();
piix3_init(7);
fdc37c932fr_init();
device_add(&intel_flash_bxt_device);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel 430VX PCISet chip.
*
* Version: @(#)machine_at_430vx.h 1.0.0 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
void machine_at_p55tvp4_init(void);
void machine_at_i430vx_init(void);
void machine_at_p55va_init(void);

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 440FX PCISet chip.
*
* Version: @(#)machine_at_440fx.c 1.0.3 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../fdc37c665.h"
#include "../intel_flash.h"
#include "../io.h"
#include "../mem.h"
#include "../memregs.h"
#include "../pci.h"
#include "../piix.h"
#include "machine_at.h"
#include "machine_at_440fx.h"
static uint8_t card_i440fx[256];
static void i440fx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3)
{
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void i440fx_write(int func, int addr, uint8_t val, void *priv)
{
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x02;
val |= 0x04;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val &= 0x80;
val |= 0x02;
break;
case 0x59: /*PAM0*/
if ((card_i440fx[0x59] ^ val) & 0xf0)
{
i440fx_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
break;
case 0x5a: /*PAM1*/
if ((card_i440fx[0x5a] ^ val) & 0x0f)
i440fx_map(0xc0000, 0x04000, val & 0xf);
if ((card_i440fx[0x5a] ^ val) & 0xf0)
i440fx_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((card_i440fx[0x5b] ^ val) & 0x0f)
i440fx_map(0xc8000, 0x04000, val & 0xf);
if ((card_i440fx[0x5b] ^ val) & 0xf0)
i440fx_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((card_i440fx[0x5c] ^ val) & 0x0f)
i440fx_map(0xd0000, 0x04000, val & 0xf);
if ((card_i440fx[0x5c] ^ val) & 0xf0)
i440fx_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((card_i440fx[0x5d] ^ val) & 0x0f)
i440fx_map(0xd8000, 0x04000, val & 0xf);
if ((card_i440fx[0x5d] ^ val) & 0xf0)
i440fx_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((card_i440fx[0x5e] ^ val) & 0x0f)
i440fx_map(0xe0000, 0x04000, val & 0xf);
if ((card_i440fx[0x5e] ^ val) & 0xf0)
i440fx_map(0xe4000, 0x04000, val >> 4);
break;
case 0x5f: /*PAM6*/
if ((card_i440fx[0x5f] ^ val) & 0x0f)
i440fx_map(0xe8000, 0x04000, val & 0xf);
if ((card_i440fx[0x5f] ^ val) & 0xf0)
i440fx_map(0xec000, 0x04000, val >> 4);
break;
}
card_i440fx[addr] = val;
}
static uint8_t i440fx_read(int func, int addr, void *priv)
{
if (func)
return 0xff;
return card_i440fx[addr];
}
static void i440fx_reset(void)
{
memset(card_i440fx, 0, 256);
card_i440fx[0x00] = 0x86; card_i440fx[0x01] = 0x80; /*Intel*/
card_i440fx[0x02] = 0x37; card_i440fx[0x03] = 0x12; /*82441FX*/
card_i440fx[0x04] = 0x03; card_i440fx[0x05] = 0x01;
card_i440fx[0x06] = 0x80; card_i440fx[0x07] = 0x00;
card_i440fx[0x08] = 0x02; /*A0 stepping*/
card_i440fx[0x09] = 0x00; card_i440fx[0x0a] = 0x00; card_i440fx[0x0b] = 0x06;
card_i440fx[0x0d] = 0x00;
card_i440fx[0x0f] = 0x00;
card_i440fx[0x2c] = 0xf4;
card_i440fx[0x2d] = 0x1a;
card_i440fx[0x2e] = 0x00;
card_i440fx[0x2f] = 0x11;
card_i440fx[0x50] = 0x00;
card_i440fx[0x51] = 0x01;
card_i440fx[0x52] = card_i440fx[0x54] = card_i440fx[0x55] = card_i440fx[0x56] = 0x00;
card_i440fx[0x53] = 0x80;
card_i440fx[0x57] = 0x01;
card_i440fx[0x58] = 0x10;
card_i440fx[0x5a] = card_i440fx[0x5b] = card_i440fx[0x5c] = card_i440fx[0x5d] = card_i440fx[0x5e] = 0x11;
card_i440fx[0x5f] = 0x31;
card_i440fx[0x72] = 0x02;
}
static void i440fx_pci_reset(void)
{
i440fx_write(0, 0x59, 0x00, NULL);
}
static void i440fx_init(void)
{
pci_add_card(0, i440fx_read, i440fx_write, NULL);
i440fx_reset();
pci_reset_handler.pci_master_reset = i440fx_pci_reset;
}
void machine_at_i440fx_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i440fx_init();
piix3_init(7);
fdc37c665_init();
device_add(&intel_flash_bxt_device);
}
void machine_at_s1668_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
i440fx_init();
piix3_init(7);
fdc37c665_init();
device_add(&intel_flash_bxt_device);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the implementation of the Intel 440FX PCISet chip.
*
* Version: @(#)machine_at_440fx.h 1.0.0 2017/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
void machine_at_i440fx_init(void);
void machine_at_s1668_init(void);

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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../hdd/hdd_ide_at.h"
#include "../io.h"
#include "../mem.h"
#include "machine_at.h"
#include "machine_at_ali1429.h"
static int ali1429_index;
static uint8_t ali1429_regs[256];
static void ali1429_recalc(void)
{
int c;
for (c = 0; c < 8; c++)
{
uint32_t base = 0xc0000 + (c << 15);
if (ali1429_regs[0x13] & (1 << c))
{
switch (ali1429_regs[0x14] & 3)
{
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
flushmmucache();
}
void ali1429_write(uint16_t port, uint8_t val, void *priv)
{
if (!(port & 1))
ali1429_index = val;
else
{
ali1429_regs[ali1429_index] = val;
switch (ali1429_index)
{
case 0x13:
ali1429_recalc();
break;
case 0x14:
shadowbios = val & 1;
shadowbios_write = val & 2;
ali1429_recalc();
break;
}
}
}
uint8_t ali1429_read(uint16_t port, void *priv)
{
if (!(port & 1))
return ali1429_index;
if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && cpu_iscyrix)
return 0xff; /*Don't conflict with Cyrix config registers*/
return ali1429_regs[ali1429_index];
}
static void ali1429_reset(void)
{
memset(ali1429_regs, 0xff, 256);
}
static void ali1429_init(void)
{
io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, NULL);
}
void machine_at_ali1429_init(void)
{
ali1429_reset();
machine_at_ide_init();
ali1429_init();
secondary_ide_check();
}

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void machine_at_ali1429_init(void);

46
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#include "../ibm.h"
#include "../io.h"
#include "../lpt.h"
#include "../serial.h"
#include "machine_at.h"
#include "machine_at_commodore.h"
static void cbm_io_write(uint16_t port, uint8_t val, void *p)
{
lpt1_remove();
lpt2_remove();
switch (val & 3)
{
case 1:
lpt1_init(0x3bc);
break;
case 2:
lpt1_init(0x378);
break;
case 3:
lpt1_init(0x278);
break;
}
switch (val & 0xc)
{
case 0x4:
serial_setup(1, 0x2f8, 3);
break;
case 0x8:
serial_setup(1, 0x3f8, 4);
break;
}
}
static void cbm_io_init()
{
io_sethandler(0x0230, 0x0001, NULL,NULL,NULL, cbm_io_write,NULL,NULL, NULL);
}
void machine_at_cmdpc_init(void)
{
machine_at_ide_top_remap_init();
cbm_io_init();
}

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void machine_at_cmdpc_init(void);

71
src/machine/machine_at_compaq.c Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../mem.h"
#include "machine_at.h"
#include "machine_at_compaq.h"
/* Compaq Deskpro 386 remaps RAM from 0xA0000-0xFFFFF to 0xFA0000-0xFFFFFF */
static mem_mapping_t compaq_ram_mapping;
static uint8_t compaq_read_ram(uint32_t addr, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
static uint16_t compaq_read_ramw(uint32_t addr, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
}
static uint32_t compaq_read_raml(uint32_t addr, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
}
static void compaq_write_ram(uint32_t addr, uint8_t val, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
}
static void compaq_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
}
static void compaq_write_raml(uint32_t addr, uint32_t val, void *priv)
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
}
static void compaq_init(void)
{
mem_mapping_add(&compaq_ram_mapping, 0xfa0000, 0x60000,
compaq_read_ram, compaq_read_ramw, compaq_read_raml,
compaq_write_ram, compaq_write_ramw, compaq_write_raml,
ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the Compaq chips.
*
* Version: @(#)machine_at_compaq.h 1.0.0 2017/09/02
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2017 Miran Grca.
*/

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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../mem.h"
#include "machine_at.h"
#include "machine_at_headland.h"
static int headland_index;
static uint8_t headland_regs[256];
static void headland_write(uint16_t addr, uint8_t val, void *priv)
{
if (addr & 1)
{
if (headland_index == 0xc1 && !is486) val = 0;
headland_regs[headland_index] = val;
if (headland_index == 0x82)
{
shadowbios = val & 0x10;
shadowbios_write = !(val & 0x10);
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
}
}
else
headland_index = val;
}
static uint8_t headland_read(uint16_t addr, void *priv)
{
if (addr & 1)
{
if ((headland_index >= 0xc0 || headland_index == 0x20) && cpu_iscyrix)
return 0xff; /*Don't conflict with Cyrix config registers*/
return headland_regs[headland_index];
}
return headland_index;
}
static void headland_init(void)
{
io_sethandler(0x0022, 0x0002, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
}
void machine_at_headland_init(void)
{
machine_at_ide_init();
headland_init();
}

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void machine_at_headland_init(void);

90
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
/*This is the chipset used in the AMI 286 clone model*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "machine_at.h"
#include "machine_at_neat.h"
static uint8_t neat_regs[256];
static int neat_index;
static int neat_emspage[4];
static void neat_write(uint16_t port, uint8_t val, void *priv)
{
switch (port)
{
case 0x22:
neat_index = val;
break;
case 0x23:
neat_regs[neat_index] = val;
switch (neat_index)
{
case 0x6E: /*EMS page extension*/
neat_emspage[3] = (neat_emspage[3] & 0x7F) | (( val & 3) << 7);
neat_emspage[2] = (neat_emspage[2] & 0x7F) | (((val >> 2) & 3) << 7);
neat_emspage[1] = (neat_emspage[1] & 0x7F) | (((val >> 4) & 3) << 7);
neat_emspage[0] = (neat_emspage[0] & 0x7F) | (((val >> 6) & 3) << 7);
break;
}
break;
case 0x0208: case 0x0209: case 0x4208: case 0x4209:
case 0x8208: case 0x8209: case 0xC208: case 0xC209:
neat_emspage[port >> 14] = (neat_emspage[port >> 14] & 0x180) | (val & 0x7F);
break;
}
}
static uint8_t neat_read(uint16_t port, void *priv)
{
switch (port)
{
case 0x22:
return neat_index;
case 0x23:
return neat_regs[neat_index];
}
return 0xff;
}
#if NOT_USED
static void neat_writeems(uint32_t addr, uint8_t val)
{
ram[(neat_emspage[(addr >> 14) & 3] << 14) + (addr & 0x3FFF)] = val;
}
static uint8_t neat_readems(uint32_t addr)
{
return ram[(neat_emspage[(addr >> 14) & 3] << 14) + (addr & 0x3FFF)];
}
#endif
static void neat_init(void)
{
io_sethandler(0x0022, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x0208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x4208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x8208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0xc208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
}
void machine_at_neat_init(void)
{
machine_at_ide_init();
neat_init();
}

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void machine_at_neat_init(void);

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src/machine/machine_at_opti495.c Normal file
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/*OPTi 82C495 emulation
This is the chipset used in the AMI386 model
Details for the chipset from Ralph Brown's interrupt list
This describes the OPTi 82C493, the 82C495 seems similar except there is one
more register (2C)
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
Desc: The OPTi 486SXWB contains three chips and is designed for systems
running at 20, 25 and 33MHz. The chipset includes an 82C493 System
Controller (SYSC), the 82C392 Data Buffer Controller, and the
82C206 Integrated peripheral Controller (IPC).
Note: every access to PORT 0024h must be preceded by a write to PORT 0022h,
even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"
0022 ?W configuration register index (see #P0178)
0024 RW configuration register data
(Table P0178)
Values for OPTi 82C493 System Controller configuration register index:
20h Control Register 1 (see #P0179)
21h Control Register 2 (see #P0180)
22h Shadow RAM Control Register 1 (see #P0181)
23h Shadow RAM Control Register 2 (see #P0182)
24h DRAM Control Register 1 (see #P0183)
25h DRAM Control Register 2 (see #P0184)
26h Shadow RAM Control Register 3 (see #P0185)
27h Control Register 3 (see #P0186)
28h Non-cachable Block 1 Register 1 (see #P0187)
29h Non-cachable Block 1 Register 2 (see #P0188)
2Ah Non-cachable Block 2 Register 1 (see #P0187)
2Bh Non-cachable Block 2 Register 2 (see #P0188)
Bitfields for OPTi-82C493 Control Register 1:
Bit(s) Description (Table P0179)
7-6 Revision of 82C493 (readonly) (default=01)
5 Burst wait state control
1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
(if bit 5 is set to 1, bit 4 must be set to 0)
4 Cache memory data buffer output enable control
0 = disable (default)
1 = enable
(must be disabled for frequency <= 33Mhz)
3 Single Address Latch Enable (ALE)
0 = disable (default)
1 = enable
(if enabled, SYSC will activate single ALE rather than multiples
during bus conversion cycles)
2 enable Extra AT Cycle Wait State (default is 0 = disabled)
1 Emulation keyboard Reset Control
0 = disable (default)
1 = enable
Note: This bit must be enabled in BIOS default value; enabling this
bit requires HALT instruction to be executed before SYSC
generates processor reset (CPURST)
0 enable Alternative Fast Reset (default is 0 = disabled)
SeeAlso: #P0180,#P0186
Bitfields for OPTi-82C493 Control Register 2:
Bit(s) Description (Table P0180)
7 Master Mode Byte Swap Enable
0 = disable (default)
1 = enable
6 Emulation Keyboard Reset Delay Control
0 = Generate reset pulse 2us later (default)
1 = Generate reset pulse immediately
5 disable Parity Check (default is 0 = enabled)
4 Cache Enable
0 = Cache disabled and DRAM burst mode enabled (default)
1 = Cache enabled and DRAM burst mode disabled
3-2 Cache Size
00 64KB (default)
01 128KB
10 256KB
11 512KB
1 Secondary Cache Read Burst Cycles Control
0 = 3-1-1-1 cycle (default)
1 = 2-1-1-1 cycle
0 Cache Write Wait State Control
0 = 1 wait state (default)
1 = 0 wait state
SeeAlso: #P0179,#P0186
Bitfields for OPTi-82C493 Shadow RAM Control Register 1:
Bit(s) Description (Table P0181)
7 ROM(F0000h - FFFFFh) Enable
0 = read/write on write-protected DRAM
1 = read from ROM, write to DRAM (default)
6 Shadow RAM at D0000h - EFFFFh Area
0 = disable (default)
1 = enable
5 Shadow RAM at E0000h - EFFFFh Area
0 = disable shadow RAM (default)
E0000h - EFFFFh ROM is defaulted to reside on XD bus
1 = enable shadow RAM
4 enable write-protect for Shadow RAM at D0000h - DFFFFh Area
0 = disable (default)
1 = enable
3 enable write-protect for Shadow RAM at E0000h - EFFFFh Area
0 = disable (default)
1 = enable
2 Hidden refresh enable (with holding CPU)
(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used)
1 = disable (default)
0 = enable
1 unused
0 enable Slow Refresh (four times slower than normal refresh)
(default is 0 = disable)
SeeAlso: #P0182
Bitfields for OPTi-82C493 Shadow RAM Control Register 2:
Bit(s) Description (Table P0182)
7 enable Shadow RAM at EC000h - EFFFFh area
6 enable Shadow RAM at E8000h - EBFFFh area
5 enable Shadow RAM at E4000h - E7FFFh area
4 enable Shadow RAM at E0000h - E3FFFh area
3 enable Shadow RAM at DC000h - DFFFFh area
2 enable Shadow RAM at D8000h - DBFFFh area
1 enable Shadow RAM at D4000h - D7FFFh area
0 enable Shadow RAM at D0000h - D3FFFh area
Note: the default is disabled (0) for all areas
Bitfields for OPTi-82C493 DRAM Control Register 1:
Bit(s) Description (Table P0183)
7 DRAM size
0 = 256K DRAM mode
1 = 1M and 4M DRAM mode
6-4 DRAM types used for bank0 and bank1
bits 7-4 Bank0 Bank1
0000 256K x
0001 256K 256K
0010 256K 1M
0011 x x
01xx x x
1000 1M x (default)
1001 1M 1M
1010 1M 4M
1011 4M 1M
1100 4M x
1101 4M 4M
111x x x
3 unused
2-0 DRAM types used for bank2 and bank3
bits 7,2-0 Bank2 Bank3
x000 1M x
x001 1M 1M
x010 x x
x011 4M 1M
x100 4M x
x101 4M 4M
x11x x x (default)
SeeAlso: #P0184
Bitfields for OPTi-82C493 DRAM Control Register 2:
Bit(s) Description (Table P0184)
7-6 Read cycle additional wait states
00 not used
01 = 0
10 = 1
11 = 2 (default)
5-4 Write cycle additional wait states
00 = 0
01 = 1
10 = 2
11 = 3 (default)
3 Fast decode enable
0 = disable fast decode. DRAM base wait states not changed (default)
1 = enable fast decode. DRAM base wait state is decreased by 1
Note: This function may be enabled in 20/25Mhz operation to speed up
DRAM access. If bit 4 of index register 21h (cache enable
bit) is enabled, this bit is automatically disabled--even if
set to 1
2 unused
1-0 ATCLK selection
00 ATCLK = CLKI/6 (default)
01 ATCLK = CLKI/4 (default)
10 ATCLK = CLKI/3
11 ATCLK = CLK2I/5 (CLKI * 2 /5)
Note: bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
set to 0 when 82C493 is reset.
SeeAlso: #P0183,#P0185
Bitfields for OPTi-82C493 Shadow RAM Control Register 3:
Bit(s) Description (Table P0185)
7 unused
6 Shadow RAM copy enable for address C0000h - CFFFFh
0 = Read/write at AT bus (default)
1 = Read from AT bus and write into shadow RAM
5 Shadow write protect at address C0000h - CFFFFh
0 = Write protect disable (default)
1 = Write protect enable
4 enable Shadow RAM at C0000h - CFFFFh
3 enable Shadow RAM at CC000h - CFFFFh
2 enable Shadow RAM at C8000h - CBFFFh
1 enable Shadow RAM at C4000h - C7FFFh
0 enable Shadow RAM at C0000h - C3FFFh
Note: the default is disabled (0) for bits 4-0
SeeAlso: #P0183,#P0184
Bitfields for OPTi-82C493 Control Register 3:
Bit(s) Description (Table P0186)
7 enable NCA# pin to low state (default is 1 = enabled)
6-5 unused
4 Video BIOS at C0000h - C8000h non-cacheable
0 = cacheable
1 = non-cacheable (default)
3-0 Cacheable address range for local memory
0000 0 - 64MB
0001 0 - 4MB (default)
0010 0 - 8MB
0011 0 - 12MB
0100 0 - 16MB
0101 0 - 20MB
0110 0 - 24MB
0111 0 - 28MB
1000 0 - 32MB
1001 0 - 36MB
1010 0 - 40MB
1011 0 - 44MB
1100 0 - 48MB
1101 0 - 52MB
1110 0 - 56MB
1111 0 - 60MB
Note: If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
0-2 MB and independent of the value of bits 3-0
SeeAlso: #P0179,#P0180
Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
Bit(s) Description (Table P0187)
7-5 Size of non-cachable memory block
000 64K
001 128K
010 256K
011 512K
1xx disabled (default)
4-2 unused
1-0 Address bits 25 and 24 of non-cachable memory block (default = 00)
Note: this register is used together with configuration register 29h
(non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
define a non-cacheable block. The starting address must be a
multiple of the block size
SeeAlso: #P0178,#P0188
Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
Bit(s) Description (Table P0188)
7-0 Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
Note: the block address is forced to be a multiple of the block size by
ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187
*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../mem.h"
#include "machine_at.h"
#include "machine_at_opti495.h"
static uint8_t optiregs[0x10];
static int optireg;
static void opti495_write(uint16_t addr, uint8_t val, void *p)
{
switch (addr)
{
case 0x22:
optireg=val;
break;
case 0x24:
printf("Writing OPTI reg %02X %02X\n",optireg,val);
if (optireg>=0x20 && optireg<=0x2C)
{
optiregs[optireg-0x20]=val;
if (optireg == 0x21)
{
cpu_cache_ext_enabled = val & 0x10;
cpu_update_waitstates();
}
if (optireg == 0x22)
{
shadowbios = !(val & 0x80);
shadowbios_write = val & 0x80;
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
}
}
break;
}
}
static uint8_t opti495_read(uint16_t addr, void *p)
{
switch (addr)
{
case 0x24:
if (optireg>=0x20 && optireg<=0x2C) return optiregs[optireg-0x20];
break;
}
return 0xFF;
}
static void opti495_init(void)
{
io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
optiregs[0x22-0x20] = 0x80;
}
void machine_at_opti495_init(void)
{
machine_at_ide_init();
opti495_init();
}

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void machine_at_opti495_init(void);

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src/machine/machine_at_scat.c Normal file
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/*This is the chipset used in the Award 286 clone model*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../mem.h"
#include "../cpu/x86.h"
#include "machine_at.h"
#include "machine_at_scat.h"
#define SCAT_DMA_WAIT_STATE_CONTROL 0x01
#define SCAT_VERSION 0x40
#define SCAT_CLOCK_CONTROL 0x41
#define SCAT_PERIPHERAL_CONTROL 0x44
#define SCAT_MISCELLANEOUS_STATUS 0x45
#define SCAT_POWER_MANAGEMENT 0x46
#define SCAT_ROM_ENABLE 0x48
#define SCAT_RAM_WRITE_PROTECT 0x49
#define SCAT_SHADOW_RAM_ENABLE_1 0x4A
#define SCAT_SHADOW_RAM_ENABLE_2 0x4B
#define SCAT_SHADOW_RAM_ENABLE_3 0x4C
#define SCAT_DRAM_CONFIGURATION 0x4D
#define SCAT_EXTENDED_BOUNDARY 0x4E
#define SCAT_EMS_CONTROL 0x4F
typedef struct scat_t
{
uint8_t regs_2x8;
uint8_t regs_2x9;
} scat_t;
static uint8_t scat_regs[256];
static int scat_index;
static uint8_t scat_port_92 = 0;
static uint8_t scat_ems_reg_2xA = 0;
static mem_mapping_t scat_mapping[32];
static mem_mapping_t scat_high_mapping[16];
static scat_t scat_stat[32];
static uint32_t scat_xms_bound;
static mem_mapping_t scat_shadowram_mapping[6];
static mem_mapping_t scat_4000_9FFF_mapping[24];
static mem_mapping_t scat_A000_BFFF_mapping;
uint8_t scat_read(uint16_t port, void *priv);
void scat_write(uint16_t port, uint8_t val, void *priv);
void scat_shadow_state_update(void)
{
int i, val;
/* TODO - ROMCS enable features should be implemented later. */
for (i = 0; i < 24; i++)
{
val = ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
if (i < 8)
{
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
}
else
{
if ((scat_regs[SCAT_RAM_WRITE_PROTECT] >> ((i - 8) >> 1)) & 1)
{
val |= MEM_WRITE_DISABLED;
}
else
{
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
}
}
mem_set_mem_state((i + 40) << 14, 0x4000, val);
}
flushmmucache();
}
void scat_set_xms_bound(uint8_t val)
{
uint32_t max_xms_size = (mem_size >= 16384) ? 0xFC0000 : mem_size << 10;
int i;
switch (val & 0x0F)
{
case 1:
scat_xms_bound = 0x100000;
break;
case 2:
scat_xms_bound = 0x140000;
break;
case 3:
scat_xms_bound = 0x180000;
break;
case 4:
scat_xms_bound = 0x200000;
break;
case 5:
scat_xms_bound = 0x300000;
break;
case 6:
scat_xms_bound = 0x400000;
break;
case 7:
scat_xms_bound = 0x600000;
break;
case 8:
scat_xms_bound = 0x800000;
break;
case 9:
scat_xms_bound = 0xA00000;
break;
case 10:
scat_xms_bound = 0xC00000;
break;
case 11:
scat_xms_bound = 0xE00000;
break;
default:
scat_xms_bound = (mem_size >= 16384 ? 0xFC0000 : mem_size << 10);
break;
}
if ((val & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3)
{
if (val != 1)
{
if(mem_size > 1024) mem_mapping_disable(&ram_high_mapping);
for(i=0;i<6;i++)
mem_mapping_enable(&scat_shadowram_mapping[i]);
if ((val & 0x0F) == 0)
scat_xms_bound = 0x160000;
}
else
{
for(i=0;i<6;i++)
mem_mapping_disable(&scat_shadowram_mapping[i]);
if(mem_size > 1024) mem_mapping_enable(&ram_high_mapping);
}
pclog("Set XMS bound(%02X) = %06X(%dKbytes for EMS access)\n", val, scat_xms_bound, (0x160000 - scat_xms_bound) >> 10);
if (scat_xms_bound > 0x100000)
mem_set_mem_state(0x100000, scat_xms_bound - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if (scat_xms_bound < 0x160000)
mem_set_mem_state(scat_xms_bound, 0x160000 - scat_xms_bound, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
else
{
for(i=0;i<6;i++)
mem_mapping_disable(&scat_shadowram_mapping[i]);
if(mem_size > 1024) mem_mapping_enable(&ram_high_mapping);
if (scat_xms_bound > max_xms_size)
scat_xms_bound = max_xms_size;
pclog("Set XMS bound(%02X) = %06X(%dKbytes for EMS access)\n", val, scat_xms_bound, ((mem_size << 10) - scat_xms_bound) >> 10);
if (scat_xms_bound > 0x100000)
mem_set_mem_state(0x100000, scat_xms_bound - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if (scat_xms_bound < (mem_size << 10))
mem_set_mem_state(scat_xms_bound, (mem_size << 10) - scat_xms_bound, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
uint32_t get_scat_addr(uint32_t addr, scat_t *p)
{
if (p && (scat_regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
{
addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14;
}
if (mem_size < 2048 && ((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) > 7 || (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) != 0))
addr = (addr & ~0x780000) | ((addr & 0x600000) >> 2);
else if((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) < 8 && (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0)
{
addr &= ~0x600000;
if(mem_size > 2048 || (mem_size == 2048 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) < 6))
addr |= (addr & 0x180000) << 2;
}
if ((scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3 && (addr & ~0x600000) >= 0x100000 && (addr & ~0x600000) < 0x160000)
addr ^= mem_size < 2048 ? 0x1F0000 : 0x670000;
return addr;
}
void scat_memmap_state_update(void)
{
int i;
uint32_t addr;
for(i=16;i<24;i++)
{
addr = get_scat_addr(0x40000 + (i << 14), NULL);
mem_mapping_set_exec(&scat_4000_9FFF_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
}
addr = get_scat_addr(0xA0000, NULL);
mem_mapping_set_exec(&scat_A000_BFFF_mapping, addr < (mem_size << 10) ? ram + addr : NULL);
for(i=0;i<6;i++)
{
addr = get_scat_addr(0x100000 + (i << 16), NULL);
mem_mapping_set_exec(&scat_shadowram_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
}
flushmmucache();
}
void scat_set_global_EMS_state(int state)
{
int i;
uint32_t base_addr, virt_addr;
for(i=0; i<32; i++)
{
base_addr = (i + 16) << 14;
if(i >= 24)
base_addr += 0x30000;
if(state && (scat_stat[i].regs_2x9 & 0x80))
{
virt_addr = get_scat_addr(base_addr, &scat_stat[i]);
if(i < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[i]);
mem_mapping_enable(&scat_mapping[i]);
if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&scat_mapping[i], ram + virt_addr);
else mem_mapping_set_exec(&scat_mapping[i], NULL);
}
else
{
mem_mapping_set_exec(&scat_mapping[i], ram + base_addr);
mem_mapping_disable(&scat_mapping[i]);
if(i < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
}
}
void scat_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t scat_reg_valid = 0, scat_shadow_update = 0, scat_map_update = 0, index;
uint32_t base_addr, virt_addr;
switch (port)
{
case 0x22:
scat_index = val;
break;
case 0x23:
switch (scat_index)
{
case SCAT_CLOCK_CONTROL:
case SCAT_PERIPHERAL_CONTROL:
scat_reg_valid = 1;
break;
case SCAT_EMS_CONTROL:
if(val & 0x40)
{
if(val & 1)
{
io_sethandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
else
{
io_sethandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
}
else
{
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
scat_set_global_EMS_state(val & 0x80);
scat_reg_valid = 1;
break;
case SCAT_POWER_MANAGEMENT:
val &= 0x40;
scat_reg_valid = 1;
break;
case SCAT_DRAM_CONFIGURATION:
if((scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0)
{
if((val & 0x0F) == 3)
{
if(mem_size > 1024) mem_mapping_disable(&ram_high_mapping);
for(index=0;index<6;index++)
mem_mapping_enable(&scat_shadowram_mapping[index]);
}
else
{
for(index=0;index<6;index++)
mem_mapping_disable(&scat_shadowram_mapping[index]);
if(mem_size > 1024) mem_mapping_enable(&ram_high_mapping);
}
}
else
{
for(index=0;index<6;index++)
mem_mapping_disable(&scat_shadowram_mapping[index]);
if(mem_size > 1024) mem_mapping_enable(&ram_high_mapping);
}
scat_map_update = 1;
cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
cpu_update_waitstates();
scat_reg_valid = 1;
break;
case SCAT_EXTENDED_BOUNDARY:
scat_set_xms_bound(val & 0x4f);
mem_set_mem_state(0x40000, 0x60000, (val & 0x20) ? MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL : MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if((val ^ scat_regs[SCAT_EXTENDED_BOUNDARY]) & 0x40) scat_map_update = 1;
scat_reg_valid = 1;
break;
case SCAT_ROM_ENABLE:
case SCAT_RAM_WRITE_PROTECT:
case SCAT_SHADOW_RAM_ENABLE_1:
case SCAT_SHADOW_RAM_ENABLE_2:
case SCAT_SHADOW_RAM_ENABLE_3:
scat_reg_valid = 1;
scat_shadow_update = 1;
break;
default:
break;
}
if (scat_reg_valid)
scat_regs[scat_index] = val;
#ifndef RELEASE_BUILD
else pclog("Attemped to write unimplemented SCAT register %02X at %04X:%04X\n", scat_index, val, CS, cpu_state.pc);
#endif
if (scat_shadow_update)
scat_shadow_state_update();
if (scat_map_update)
scat_memmap_state_update();
break;
case 0x92:
if ((mem_a20_alt ^ val) & 2)
{
mem_a20_alt = val & 2;
mem_a20_recalc();
}
if ((~scat_port_92 & val) & 1)
{
softresetx86();
cpu_set_edx();
}
scat_port_92 = val;
break;
case 0x208:
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if((scat_regs[SCAT_EMS_CONTROL] & 0x80) && (scat_stat[index].regs_2x9 & 0x80))
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
else mem_mapping_set_exec(&scat_mapping[index], NULL);
flushmmucache();
}
}
break;
case 0x209:
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if (scat_regs[SCAT_EMS_CONTROL] & 0x80)
{
if (val & 0x80)
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(index < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[index]);
if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
else mem_mapping_set_exec(&scat_mapping[index], NULL);
mem_mapping_enable(&scat_mapping[index]);
}
else
{
mem_mapping_set_exec(&scat_mapping[index], ram + base_addr);
mem_mapping_disable(&scat_mapping[index]);
if(index < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[index]);
}
flushmmucache();
}
if (scat_ems_reg_2xA & 0x80)
{
scat_ems_reg_2xA = (scat_ems_reg_2xA & 0xe0) | ((scat_ems_reg_2xA + 1) & 0x1f);
}
}
break;
case 0x20A:
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
scat_ems_reg_2xA = val;
}
break;
}
}
uint8_t scat_read(uint16_t port, void *priv)
{
uint8_t val = 0xff, index;
switch (port)
{
case 0x23:
switch (scat_index)
{
case SCAT_MISCELLANEOUS_STATUS:
val = (scat_regs[scat_index] & 0xbf) | ((mem_a20_key & 2) << 5);
break;
case SCAT_DRAM_CONFIGURATION:
val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
break;
default:
val = scat_regs[scat_index];
break;
}
break;
case 0x92:
val = scat_port_92;
break;
case 0x208:
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
break;
case 0x209:
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
break;
case 0x20A:
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
{
val = scat_ems_reg_2xA;
}
break;
}
return val;
}
uint8_t mem_read_scatems(uint32_t addr, void *priv)
{
uint8_t val = 0xff;
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
val = mem_read_ram(addr, priv);
return val;
}
void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
mem_write_ram(addr, val, priv);
}
static void scat_init(void)
{
int i;
io_sethandler(0x0022, 0x0002, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
for (i = 0; i < 256; i++)
{
scat_regs[i] = 0xff;
}
scat_regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
scat_regs[SCAT_VERSION] = 10;
scat_regs[SCAT_CLOCK_CONTROL] = 2;
scat_regs[SCAT_PERIPHERAL_CONTROL] = 0x80;
scat_regs[SCAT_MISCELLANEOUS_STATUS] = 0x37;
scat_regs[SCAT_POWER_MANAGEMENT] = 0;
scat_regs[SCAT_ROM_ENABLE] = 0xC0;
scat_regs[SCAT_RAM_WRITE_PROTECT] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_1] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_2] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_3] = 0;
scat_regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12;
scat_regs[SCAT_EXTENDED_BOUNDARY] = 0;
scat_regs[SCAT_EMS_CONTROL] = 0;
scat_port_92 = 0;
mem_mapping_set_addr(&ram_low_mapping, 0, 0x40000);
for (i = 0; i < 24; i++)
{
mem_mapping_add(&scat_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, mem_size > 256 + (i << 4) ? ram + 0x40000 + (i << 14) : NULL, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
mem_mapping_add(&scat_A000_BFFF_mapping, 0xA0000, 0x20000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_A000_BFFF_mapping);
for (i = 0; i < 32; i++)
{
scat_stat[i].regs_2x8 = 0xff;
scat_stat[i].regs_2x9 = 0x03;
mem_mapping_add(&scat_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + ((i + (i >= 24 ? 28 : 16)) << 14), 0, &scat_stat[i]);
mem_mapping_disable(&scat_mapping[i]);
}
for(i=4;i<10;i++) isram[i] = 0;
for (i = 12; i < 16; i++)
{
mem_mapping_add(&scat_high_mapping[i], (i << 14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (i << 14), 0, NULL);
}
for(i=0;i<6;i++)
mem_mapping_add(&scat_shadowram_mapping[i], 0x100000 + (i << 16), 0x10000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, mem_size >= 1024 ? ram + get_scat_addr(0x100000 + (i << 16), NULL) : NULL, MEM_MAPPING_INTERNAL, NULL);
scat_set_xms_bound(0);
scat_shadow_state_update();
}
void machine_at_scat_init(void)
{
machine_at_ide_init();
scat_init();
}

1
src/machine/machine_at_scat.h Normal file
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extern void machine_at_scat_init(void);

248
src/machine/machine_at_sis_85c471.c Normal file
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 85c471 chip.
*
* SiS sis85c471 Super I/O Chip
* Used by DTK PKM-0038S E-2
*
* Version: @(#)sis85c471.c 1.0.3 2017/09/02
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2017 Miran Grca.
*/
#include "../ibm.h"
#include "../disc.h"
#include "../fdc.h"
#include "../fdd.h"
#include "../hdd/hdd_ide_at.h"
#include "../io.h"
#include "../lpt.h"
#include "../memregs.h"
#include "../serial.h"
#include "machine_at.h"
#include "machine_at_sis_85c471.h"
static int sis_85c471_curreg;
static uint8_t sis_85c471_regs[39];
static void sis_85c471_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t x;
if (index)
{
if ((val >= 0x50) && (val <= 0x76)) sis_85c471_curreg = val;
return;
}
else
{
if ((sis_85c471_curreg < 0x50) || (sis_85c471_curreg > 0x76)) return;
x = val ^ sis_85c471_regs[sis_85c471_curreg - 0x50];
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (sis_85c471_curreg != 0x52) sis_85c471_regs[sis_85c471_curreg - 0x50] = val;
goto process_value;
}
return;
process_value:
switch(sis_85c471_curreg)
{
case 0x73:
#if 0
if (x & 0x40)
{
if (val & 0x40)
ide_pri_enable();
else
ide_pri_disable();
}
#endif
if (x & 0x20)
{
if (val & 0x20)
{
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
{
serial_remove(1);
serial_remove(2);
}
}
if (x & 0x10)
{
if (val & 0x10)
lpt1_init(0x378);
else
lpt1_remove();
}
break;
}
sis_85c471_curreg = 0;
}
static uint8_t sis_85c471_read(uint16_t port, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t temp;
if (index)
return sis_85c471_curreg;
else
if ((sis_85c471_curreg >= 0x50) && (sis_85c471_curreg <= 0x76))
{
temp = sis_85c471_regs[sis_85c471_curreg - 0x50];
sis_85c471_curreg = 0;
return temp;
}
else
return 0xFF;
}
static void sis_85c471_init(void)
{
int i = 0;
lpt2_remove();
sis_85c471_curreg = 0;
for (i = 0; i < 0x27; i++)
{
sis_85c471_regs[i] = 0;
}
sis_85c471_regs[9] = 0x40;
switch (mem_size)
{
case 0:
case 1:
sis_85c471_regs[9] |= 0;
break;
case 2:
case 3:
sis_85c471_regs[9] |= 1;
break;
case 4:
sis_85c471_regs[9] |= 2;
break;
case 5:
sis_85c471_regs[9] |= 0x20;
break;
case 6:
case 7:
sis_85c471_regs[9] |= 9;
break;
case 8:
case 9:
sis_85c471_regs[9] |= 4;
break;
case 10:
case 11:
sis_85c471_regs[9] |= 5;
break;
case 12:
case 13:
case 14:
case 15:
sis_85c471_regs[9] |= 0xB;
break;
case 16:
sis_85c471_regs[9] |= 0x13;
break;
case 17:
sis_85c471_regs[9] |= 0x21;
break;
case 18:
case 19:
sis_85c471_regs[9] |= 6;
break;
case 20:
case 21:
case 22:
case 23:
sis_85c471_regs[9] |= 0xD;
break;
case 24:
case 25:
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
sis_85c471_regs[9] |= 0xE;
break;
case 32:
case 33:
case 34:
case 35:
sis_85c471_regs[9] |= 0x1B;
break;
case 36:
case 37:
case 38:
case 39:
sis_85c471_regs[9] |= 0xF;
break;
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
sis_85c471_regs[9] |= 0x17;
break;
case 48:
sis_85c471_regs[9] |= 0x1E;
break;
default:
if (mem_size < 64)
{
sis_85c471_regs[9] |= 0x1E;
}
else if ((mem_size >= 65) && (mem_size < 68))
{
sis_85c471_regs[9] |= 0x22;
}
else
{
sis_85c471_regs[9] |= 0x24;
}
break;
}
sis_85c471_regs[0x11] = 9;
sis_85c471_regs[0x12] = 0xFF;
sis_85c471_regs[0x23] = 0xF0;
sis_85c471_regs[0x26] = 1;
fdc_update_densel_polarity(1);
fdc_update_densel_force(0);
fdd_swap = 0;
io_sethandler(0x0022, 0x0002, sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, NULL);
}
void machine_at_dtk486_init(void)
{
machine_at_ide_init();
memregs_init();
sis_85c471_init();
secondary_ide_check();
}

15
src/machine/machine_at_sis_85c471.h Normal file
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 85c471 chip.
*
* Version: @(#)machine_at_sis_85c471.h 1.0.2 2017/09/02
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2017 Miran Grca.
*/
extern void machine_at_dtk486_init(void);

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src/machine/machine_at_sis_85c496.c Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <stdlib.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../fdc37c665.h"
#include "../io.h"
#include "../mem.h"
#include "../memregs.h"
#include "../pci.h"
#include "machine_at.h"
#include "machine_at_sis_85c496.h"
typedef struct sis_85c496_t
{
uint8_t pci_conf[256];
} sis_85c496_t;
sis_85c496_t sis496;
static void sis_85c496_recalcmapping(void)
{
int c;
for (c = 0; c < 8; c++)
{
uint32_t base = 0xc0000 + (c << 15);
if (sis496.pci_conf[0x44] & (1 << c))
{
switch (sis496.pci_conf[0x45] & 3)
{
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
flushmmucache();
shadowbios = (sis496.pci_conf[0x44] & 0xf0);
}
static void sis_85c496_write(int func, int addr, uint8_t val, void *p)
{
switch (addr)
{
case 0x44: /*Shadow configure*/
if ((sis496.pci_conf[0x44] & val) ^ 0xf0)
{
sis496.pci_conf[0x44] = val;
sis_85c496_recalcmapping();
}
break;
case 0x45: /*Shadow configure*/
if ((sis496.pci_conf[0x45] & val) ^ 0x01)
{
sis496.pci_conf[0x45] = val;
sis_85c496_recalcmapping();
}
break;
case 0xc0:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, val & 0xf);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
break;
case 0xc1:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, val & 0xf);
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
case 0xc2:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, val & 0xf);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
break;
case 0xc3:// pclog("IRQ routing %02x %02x\n", addr, val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, val & 0xf);
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
}
if ((addr >= 4 && addr < 8) || addr >= 0x40)
sis496.pci_conf[addr] = val;
}
static uint8_t sis_85c496_read(int func, int addr, void *p)
{
return sis496.pci_conf[addr];
}
static void sis_85c496_reset(void)
{
memset(&sis496, 0, sizeof(sis_85c496_t));
sis496.pci_conf[0x00] = 0x39; /*SiS*/
sis496.pci_conf[0x01] = 0x10;
sis496.pci_conf[0x02] = 0x96; /*496/497*/
sis496.pci_conf[0x03] = 0x04;
sis496.pci_conf[0x04] = 7;
sis496.pci_conf[0x05] = 0;
sis496.pci_conf[0x06] = 0x80;
sis496.pci_conf[0x07] = 0x02;
sis496.pci_conf[0x08] = 2; /*Device revision*/
sis496.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis496.pci_conf[0x0a] = 0x00;
sis496.pci_conf[0x0b] = 0x06;
sis496.pci_conf[0x0e] = 0x00; /*Single function device*/
}
static void sis_85c496_pci_reset(void)
{
uint8_t val = 0;
val = sis_85c496_read(0, 0x44, NULL); /* Read current value of 0x44. */
sis_85c496_write(0, 0x44, val & 0xf, NULL); /* Turn off shadow BIOS but keep the lower 4 bits. */
}
static void sis_85c496_init(void)
{
pci_add_card(5, sis_85c496_read, sis_85c496_write, NULL);
sis_85c496_reset();
pci_reset_handler.pci_master_reset = sis_85c496_pci_reset;
}
static void machine_at_sis_85c496_common_init(void)
{
machine_at_ide_init();
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
sis_85c496_init();
}
void machine_at_r418_init(void)
{
machine_at_sis_85c496_common_init();
fdc37c665_init();
}

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src/machine/machine_at_sis_85c496.h Normal file
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extern void machine_at_r418_init(void);

329
src/machine/machine_at_sis_85c50x.c Normal file
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 50x PCI chips.
*
* Version: @(#)machine_at_sis_85c50x.c 1.0.2 2017/09/02
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2017 Miran Grca.
*/
#include <stdlib.h>
#include "../ibm.h"
#include "../io.h"
#include "../mem.h"
#include "../pci.h"
#include "machine_at.h"
#include "machine_at_sis_85c50x.h"
typedef struct sis_85c501_t
{
uint8_t pci_conf[256];
uint8_t turbo_reg;
} sis_85c501_t;
sis_85c501_t sis_85c501;
typedef struct sis_85c503_t
{
uint8_t pci_conf[256];
} sis_85c503_t;
sis_85c503_t sis_85c503;
typedef struct sis_85c50x_t
{
uint8_t isa_conf[12];
uint8_t reg;
} sis_85c50x_isa_t;
sis_85c50x_isa_t sis_85c50x_isa;
static void sis_85c501_recalcmapping(void)
{
int c, d;
for (c = 0; c < 1; c++)
{
for (d = 0; d < 4; d++)
{
uint32_t base = 0xe0000 + (d << 14);
if (sis_85c501.pci_conf[0x54 + c] & (1 << (d + 4)))
{
switch (sis_85c501.pci_conf[0x53] & 0x60)
{
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
flushmmucache();
shadowbios = 1;
}
static void sis_85c501_write(int func, int addr, uint8_t val, void *p)
{
/* pclog("sis_85c501_write : addr=%02x val=%02x\n", addr, val); */
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
break;
case 0x05:
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((sis_85c501.pci_conf[0x54] & val) ^ 0xf0)
{
sis_85c501.pci_conf[0x54] = val;
sis_85c501_recalcmapping();
}
break;
}
sis_85c501.pci_conf[addr] = val;
}
static void sis_85c503_write(int func, int addr, uint8_t val, void *p)
{
/* pclog("sis_85c503_write : addr=%02x val=%02x\n", addr, val); */
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x41)
return;
switch(addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
pclog("Set IRQ routing: INT A -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
pclog("Set IRQ routing: INT B -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
pclog("Set IRQ routing: INT C -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
pclog("Set IRQ routing: INT D -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
}
sis_85c503.pci_conf[addr] = val;
}
static void sis_85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB) sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg] = val;
}
else
{
sis_85c50x_isa.reg = val;
}
}
static uint8_t sis_85c501_read(int func, int addr, void *p)
{
if (func)
return 0xff;
return sis_85c501.pci_conf[addr];
}
static uint8_t sis_85c503_read(int func, int addr, void *p)
{
if (func > 0)
return 0xff;
return sis_85c503.pci_conf[addr];
}
static uint8_t sis_85c50x_isa_read(uint16_t port, void *priv)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB)
return sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg];
else
return 0xff;
}
else
{
return sis_85c50x_isa.reg;
}
}
static void sis_85c501_reset(void)
{
memset(&sis_85c501, 0, sizeof(sis_85c501_t));
sis_85c501.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c501.pci_conf[0x01] = 0x10;
sis_85c501.pci_conf[0x02] = 0x06; /*501/502*/
sis_85c501.pci_conf[0x03] = 0x04;
sis_85c501.pci_conf[0x04] = 7;
sis_85c501.pci_conf[0x05] = 0;
sis_85c501.pci_conf[0x06] = 0x80;
sis_85c501.pci_conf[0x07] = 0x02;
sis_85c501.pci_conf[0x08] = 0; /*Device revision*/
sis_85c501.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c501.pci_conf[0x0a] = 0x00;
sis_85c501.pci_conf[0x0b] = 0x06;
sis_85c501.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c501.pci_conf[0x50] = 0xbc;
sis_85c501.pci_conf[0x51] = 0xfb;
sis_85c501.pci_conf[0x52] = 0xad;
sis_85c501.pci_conf[0x53] = 0xfe;
shadowbios = 1;
}
static void sis_85c501_init(void)
{
pci_add_card(0, sis_85c501_read, sis_85c501_write, NULL);
sis_85c501_reset();
pci_reset_handler.pci_master_reset = NULL;
}
static void sis_85c503_reset(void)
{
memset(&sis_85c503, 0, sizeof(sis_85c503_t));
sis_85c503.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c503.pci_conf[0x01] = 0x10;
sis_85c503.pci_conf[0x02] = 0x08; /*503*/
sis_85c503.pci_conf[0x03] = 0x00;
sis_85c503.pci_conf[0x04] = 7;
sis_85c503.pci_conf[0x05] = 0;
sis_85c503.pci_conf[0x06] = 0x80;
sis_85c503.pci_conf[0x07] = 0x02;
sis_85c503.pci_conf[0x08] = 0; /*Device revision*/
sis_85c503.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c503.pci_conf[0x0a] = 0x01;
sis_85c503.pci_conf[0x0b] = 0x06;
sis_85c503.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c503.pci_conf[0x41] = sis_85c503.pci_conf[0x42] = sis_85c503.pci_conf[0x43] = sis_85c503.pci_conf[0x44] = 0x80;
}
static void sis_85c503_init(int card)
{
pci_add_card(card, sis_85c503_read, sis_85c503_write, NULL);
sis_85c503_reset();
trc_init();
port_92_reset();
port_92_add();
pci_reset_handler.pci_set_reset = sis_85c503_reset;
}
static void sis_85c50x_isa_init(void)
{
memset(&sis_85c50x_isa, 0, sizeof(sis_85c50x_isa_t));
io_sethandler(0x22, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, NULL);
}

13
src/machine/machine_at_sis_85c50x.h Normal file
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 50x PCI chips.
*
* Version: @(#)machine_at_sis_85c50x.h 1.0.2 2017/09/02
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2017 Miran Grca.
*/

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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include "../ibm.h"
#include "../disc.h"
#include "../fdc.h"
#include "../io.h"
#include "../mem.h"
#include "../serial.h"
#include "machine_at.h"
#include "machine_at_wd76c10.h"
static uint16_t wd76c10_0092;
static uint16_t wd76c10_2072;
static uint16_t wd76c10_2872;
static uint16_t wd76c10_5872;
static uint16_t
wd76c10_read(uint16_t port, void *priv)
{
switch (port)
{
case 0x0092:
return wd76c10_0092;
case 0x2072:
return wd76c10_2072;
case 0x2872:
return wd76c10_2872;
case 0x5872:
return wd76c10_5872;
}
return 0;
}
static void
wd76c10_write(uint16_t port, uint16_t val, void *priv)
{
pclog("WD76C10 write %04X %04X\n", port, val);
switch (port)
{
case 0x0092:
wd76c10_0092 = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x2072:
wd76c10_2072 = val;
serial_remove(1);
if (!(val & 0x10))
{
switch ((val >> 5) & 7)
{
case 1: serial_setup(1, 0x3f8, 4); break;
case 2: serial_setup(1, 0x2f8, 4); break;
case 3: serial_setup(1, 0x3e8, 4); break;
case 4: serial_setup(1, 0x2e8, 4); break;
default: serial_remove(1); break;
}
}
serial_remove(2);
if (!(val & 0x01))
{
switch ((val >> 1) & 7)
{
case 1: serial_setup(2, 0x3f8, 3); break;
case 2: serial_setup(2, 0x2f8, 3); break;
case 3: serial_setup(2, 0x3e8, 3); break;
case 4: serial_setup(2, 0x2e8, 3); break;
default: serial_remove(1); break;
}
}
break;
case 0x2872:
wd76c10_2872 = val;
fdc_remove();
if (!(val & 1))
fdc_add();
break;
case 0x5872:
wd76c10_5872 = val;
break;
}
}
static uint8_t
wd76c10_readb(uint16_t port, void *priv)
{
if (port & 1)
return wd76c10_read(port & ~1, priv) >> 8;
return wd76c10_read(port, priv) & 0xff;
}
static void
wd76c10_writeb(uint16_t port, uint8_t val, void *priv)
{
uint16_t temp = wd76c10_read(port, priv);
if (port & 1)
wd76c10_write(port & ~1, (temp & 0x00ff) | (val << 8), priv);
else
wd76c10_write(port , (temp & 0xff00) | val, priv);
}
static void wd76c10_init(void)
{
io_sethandler(0x0092, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x2072, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x2872, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x5872, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
}
void machine_at_wd76c10_init(void)
{
machine_at_ide_init();
wd76c10_init();
}

4
src/machine/machine_at_wd76c10.h Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
extern void machine_at_wd76c10_init(void);

37
src/machine/machine_common.c Normal file
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#include "../ibm.h"
#include "../dma.h"
#include "../disc.h"
#include "../fdd.h"
#include "../fdc.h"
#include "../lpt.h"
#include "../pic.h"
#include "../pit.h"
#include "../serial.h"
#include "machine_common.h"
void machine_common_init(void)
{
/* System devices first. */
dma_init();
pic_init();
pit_init();
fdc_add();
if (lpt_enabled)
{
lpt_init();
}
if (serial_enabled[0])
{
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
}
if (serial_enabled[1])
{
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
}
}

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src/machine/machine_common.h Normal file
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extern void machine_common_init(void);

144
src/machine/machine_europc.c Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <stdio.h>
#include <string.h>
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../device.h"
#include "../gameport.h"
#include "../keyboard_xt.h"
#include "../lpt.h"
#include "../mem.h"
#include "../nmi.h"
#include "../rom.h"
#include "machine_common.h"
#include "machine_europc.h"
uint8_t europcdat[16];
struct
{
uint8_t dat[16];
uint8_t stat;
uint8_t addr;
} europc_rtc;
static uint8_t jim_load_nvr(void)
{
FILE *f;
f = nvrfopen(L"europc_jim.nvr", L"rb");
if (f)
{
fread(europcdat, 1, 16, f);
fread(europc_rtc.dat, 1, 16, f);
fclose(f);
f = NULL;
return 1;
}
return 0;
}
void jim_save_nvr(void)
{
FILE *f;
f = nvrfopen(L"europc_jim.nvr", L"wb");
if (f)
{
fwrite(europcdat, 1, 16, f);
fwrite(europc_rtc.dat, 1, 16, f);
fclose(f);
f = NULL;
}
}
static void writejim(uint16_t addr, uint8_t val, void *p)
{
if ((addr&0xFF0)==0x250) europcdat[addr&0xF]=val;
switch (addr)
{
case 0x25A:
switch (europc_rtc.stat)
{
case 0:
europc_rtc.addr=val&0xF;
europc_rtc.stat++;
break;
case 1:
europc_rtc.dat[europc_rtc.addr]=(europc_rtc.dat[europc_rtc.addr]&0xF)|(val<<4);
europc_rtc.stat++;
break;
case 2:
europc_rtc.dat[europc_rtc.addr]=(europc_rtc.dat[europc_rtc.addr]&0xF0)|(val&0xF);
europc_rtc.stat=0;
break;
}
break;
}
}
static uint8_t readjim(uint16_t addr, void *p)
{
switch (addr)
{
case 0x250: case 0x251: case 0x252: case 0x253: return 0;
case 0x254: case 0x255: case 0x256: case 0x257: return europcdat[addr&0xF];
case 0x25A:
if (europc_rtc.stat==1)
{
europc_rtc.stat=2;
return europc_rtc.dat[europc_rtc.addr]>>4;
}
if (europc_rtc.stat==2)
{
europc_rtc.stat=0;
return europc_rtc.dat[europc_rtc.addr]&0xF;
}
return 0;
}
return 0;
}
static void jim_init(void)
{
uint8_t viddat;
memset(europc_rtc.dat,0,16);
if (!jim_load_nvr())
{
europc_rtc.dat[0xF]=1;
europc_rtc.dat[3]=1;
europc_rtc.dat[4]=1;
europc_rtc.dat[5]=0x88;
}
if (gfxcard==GFX_CGA || gfxcard == GFX_COLORPLUS) viddat=0x12;
else if (gfxcard==GFX_MDA || gfxcard==GFX_HERCULES || gfxcard==GFX_INCOLOR) viddat=3;
else viddat=0x10;
europc_rtc.dat[0xB]=viddat;
europc_rtc.dat[0xD]=viddat; /*Checksum*/
io_sethandler(0x250, 0x10, readjim, NULL, NULL, writejim, NULL, NULL, NULL);
}
void machine_europc_init(void)
{
machine_common_init();
mem_add_bios();
lpt3_init(0x3bc);
jim_init();
keyboard_xt_init();
nmi_init();
if (joystick_type != 7)
device_add(&gameport_device);
}

3
src/machine/machine_europc.h Normal file
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void jim_save_nvr(void);
void machine_europc_init(void);

47
src/machine/machine_olivetti_m24.c Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../gameport.h"
#include "../keyboard_olim24.h"
#include "../mem.h"
#include "../nmi.h"
#include "../nvr.h"
#include "../io.h"
#include "machine_common.h"
#include "machine_olivetti_m24.h"
static uint8_t olivetti_m24_read(uint16_t port, void *priv)
{
switch (port)
{
case 0x66:
return 0x00;
case 0x67:
return 0x20 | 0x40 | 0x0C;
}
return 0xff;
}
static void olivetti_m24_init(void)
{
io_sethandler(0x0066, 0x0002, olivetti_m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
}
void machine_olim24_init(void)
{
machine_common_init();
mem_add_bios();
keyboard_olim24_init();
nvr_init();
olivetti_m24_init();
nmi_init();
if (joystick_type != 7) device_add(&gameport_device);
}

1
src/machine/machine_olivetti_m24.h Normal file
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void machine_olim24_init(void);

29
src/machine/machine_pcjr.c Normal file
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#include "../ibm.h"
#include "../device.h"
#include "../disc.h"
#include "../fdc.h"
#include "../fdd.h"
#include "../keyboard_pcjr.h"
#include "../mem.h"
#include "../nmi.h"
#include "../pic.h"
#include "../pit.h"
#include "../serial.h"
#include "../sound/snd_sn76489.h"
#include "machine_pcjr.h"
void machine_pcjr_init(void)
{
mem_add_bios();
fdc_add_pcjr();
pic_init();
pit_init();
pit_set_out_func(&pit, 0, pit_irq0_timer_pcjr);
if (serial_enabled[0])
serial_setup(1, 0x2f8, 3);
keyboard_pcjr_init();
device_add(&sn76489_device);
nmi_mask = 0x80;
}

1
src/machine/machine_pcjr.h Normal file
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void machine_pcjr_init(void);

385
src/machine/machine_ps1.c Normal file
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../disc.h"
#include "../dma.h"
#include "../gameport.h"
#include "../hdd/hdd_ide_at.h"
#include "../fdd.h"
#include "../fdc.h"
#include "../io.h"
#include "../keyboard_at.h"
#include "../lpt.h"
#include "../mem.h"
#include "../nvr.h"
#include "../pic.h"
#include "../pit.h"
#include "../rom.h"
#include "../serial.h"
#include "../sound/snd_ps1.h"
#include "machine_common.h"
#include "machine_ps1.h"
static rom_t ps1_high_rom;
static uint8_t ps1_92, ps1_94, ps1_102, ps1_103, ps1_104, ps1_105, ps1_190;
static int ps1_e0_addr;
static uint8_t ps1_e0_regs[256];
static struct
{
uint8_t status, int_status;
uint8_t attention, ctrl;
} ps1_hd;
static uint8_t ps1_read(uint16_t port, void *p)
{
uint8_t temp;
switch (port)
{
case 0x91:
return 0;
case 0x92:
return ps1_92;
case 0x94:
return ps1_94;
case 0x102:
return ps1_102 | 8;
case 0x103:
return ps1_103;
case 0x104:
return ps1_104;
case 0x105:
return ps1_105;
case 0x190:
return ps1_190;
case 0x322:
temp = ps1_hd.status;
break;
case 0x324:
temp = ps1_hd.int_status;
ps1_hd.int_status &= ~0x02;
break;
default:
temp = 0xff;
break;
}
return temp;
}
static void ps1_write(uint16_t port, uint8_t val, void *p)
{
switch (port)
{
case 0x0092:
ps1_92 = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x94:
ps1_94 = val;
break;
case 0x102:
lpt1_remove();
if (val & 0x04)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps1_102 = val;
break;
case 0x103:
ps1_103 = val;
break;
case 0x104:
ps1_104 = val;
break;
case 0x105:
ps1_105 = val;
break;
case 0x190:
ps1_190 = val;
break;
case 0x322:
ps1_hd.ctrl = val;
if (val & 0x80)
ps1_hd.status |= 0x02;
break;
case 0x324:
ps1_hd.attention = val & 0xf0;
if (ps1_hd.attention)
ps1_hd.status = 0x14;
break;
}
}
void ps1mb_init(void)
{
io_sethandler(0x0091, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0320, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0322, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
if (!enable_xtide)
{
rom_init(&ps1_high_rom,
L"roms/machines/ibmps1es/f80000_shell.bin",
0xf80000,
0x80000,
0x7ffff,
0,
MEM_MAPPING_EXTERNAL);
}
/* rom_init_interleaved(&ps1_high_rom,
L"roms/machines/ibmps1es/ibm_1057757_24-05-90.bin",
L"roms/machines/ibmps1es/ibm_1057757_29-15-90.bin",
0xfc0000,
0x40000,
0x3ffff,
0,
MEM_MAPPING_EXTERNAL);*/
ps1_190 = 0;
lpt1_remove();
lpt2_remove();
lpt1_init(0x3bc);
serial_remove(1);
serial_remove(2);
memset(&ps1_hd, 0, sizeof(ps1_hd));
}
/*PS/1 Model 2121.
This is similar to the model 2011 but some of the functionality has moved to a
chip at ports 0xe0 (index)/0xe1 (data). The only functions I have identified
are enables for the first 512kb and next 128kb of RAM, in bits 0 of registers
0 and 1 respectively.
Port 0x105 has bit 7 forced high. Without this 128kb of memory will be missed
by the BIOS on cold boots.
The reserved 384kb is remapped to the top of extended memory. If this is not
done then you get an error on startup.
*/
static uint8_t ps1_m2121_read(uint16_t port, void *p)
{
uint8_t temp;
switch (port)
{
case 0x91:
return 0;
case 0x92:
return ps1_92;
case 0x94:
return ps1_94;
case 0xe1:
return ps1_e0_regs[ps1_e0_addr];
case 0x102:
return ps1_102;
case 0x103:
return ps1_103;
case 0x104:
return ps1_104;
case 0x105:
return ps1_105 | 0x80;
case 0x190:
return ps1_190;
default:
temp = 0xff;
break;
}
return temp;
}
static void ps1_m2121_recalc_memory(void)
{
/*Enable first 512kb*/
mem_set_mem_state(0x00000, 0x80000, (ps1_e0_regs[0] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
/*Enable 512-640kb*/
mem_set_mem_state(0x80000, 0x20000, (ps1_e0_regs[1] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
}
void ps1_m2121_write(uint16_t port, uint8_t val, void *p)
{
switch (port)
{
case 0x0092:
if (val & 1)
{
softresetx86();
cpu_set_edx();
}
ps1_92 = val & ~1;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x94:
ps1_94 = val;
break;
case 0xe0:
ps1_e0_addr = val;
break;
case 0xe1:
ps1_e0_regs[ps1_e0_addr] = val;
ps1_m2121_recalc_memory();
break;
case 0x102:
lpt1_remove();
if (val & 0x04)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps1_102 = val;
break;
case 0x103:
ps1_103 = val;
break;
case 0x104:
ps1_104 = val;
break;
case 0x105:
ps1_105 = val;
break;
case 0x190:
ps1_190 = val;
break;
}
}
static void ps1mb_m2121_init(void)
{
io_sethandler(0x0091, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x00e0, 0x0002, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
rom_init(&ps1_high_rom,
L"roms/machines/ibmps1_2121/fc0000_shell.bin",
0xfc0000,
0x40000,
0x3ffff,
0,
MEM_MAPPING_EXTERNAL);
ps1_92 = 0;
ps1_190 = 0;
lpt1_init(0x3bc);
mem_remap_top_384k();
}
static void ps1mb_m2133_init(void)
{
io_sethandler(0x0091, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
ps1_92 = 0;
ps1_190 = 0;
lpt1_init(0x3bc);
mem_remap_top_384k();
}
static void machine_ps1_common_init(void)
{
AT = 1;
machine_common_init();
mem_add_bios();
pit_set_out_func(&pit, 1, pit_refresh_timer_at);
dma16_init();
if (romset != ROM_IBMPS1_2011)
{
ide_init();
}
keyboard_at_init();
nvr_init();
pic2_init();
if (romset != ROM_IBMPS1_2133)
{
fdc_set_dskchg_activelow();
device_add(&ps1_audio_device);
}
/*PS/1 audio uses ports 200h and 202-207h, so only initialise gameport on 201h*/
if (joystick_type != 7)
device_add(&gameport_201_device);
}
void machine_ps1_m2011_init(void)
{
machine_ps1_common_init();
ps1mb_init();
mem_remap_top_384k();
}
void machine_ps1_m2121_init(void)
{
machine_ps1_common_init();
ps1mb_m2121_init();
fdc_set_ps1();
}
void machine_ps1_m2133_init(void)
{
machine_ps1_common_init();
ps1mb_m2133_init();
}

3
src/machine/machine_ps1.h Normal file
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void machine_ps1_m2011_init(void);
void machine_ps1_m2121_init(void);
void machine_ps1_m2133_init(void);

169
src/machine/machine_ps2_isa.c Normal file
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#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../device.h"
#include "../disc.h"
#include "../dma.h"
#include "../fdd.h"
#include "../fdc.h"
#include "../io.h"
#include "../keyboard.h"
#include "../keyboard_at.h"
#include "../lpt.h"
#include "../mem.h"
#include "../nvr.h"
#include "../pic.h"
#include "../pit.h"
#include "../rom.h"
#include "../serial.h"
#include "machine_common.h"
#include "machine_ps2_isa.h"
static uint8_t ps2_92, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190;
static struct
{
uint8_t status, int_status;
uint8_t attention, ctrl;
} ps2_hd;
static uint8_t ps2_read(uint16_t port, void *p)
{
uint8_t temp;
switch (port)
{
case 0x91:
return 0;
case 0x92:
return ps2_92;
case 0x94:
return ps2_94;
case 0x102:
return ps2_102 | 8;
case 0x103:
return ps2_103;
case 0x104:
return ps2_104;
case 0x105:
return ps2_105;
case 0x190:
return ps2_190;
case 0x322:
temp = ps2_hd.status;
break;
case 0x324:
temp = ps2_hd.int_status;
ps2_hd.int_status &= ~0x02;
break;
default:
temp = 0xff;
break;
}
return temp;
}
static void ps2_write(uint16_t port, uint8_t val, void *p)
{
switch (port)
{
case 0x0092:
ps2_92 = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x94:
ps2_94 = val;
break;
case 0x102:
lpt1_remove();
if (val & 0x04)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps2_102 = val;
break;
case 0x103:
ps2_103 = val;
break;
case 0x104:
ps2_104 = val;
break;
case 0x105:
ps2_105 = val;
break;
case 0x190:
ps2_190 = val;
break;
case 0x322:
ps2_hd.ctrl = val;
if (val & 0x80)
ps2_hd.status |= 0x02;
break;
case 0x324:
ps2_hd.attention = val & 0xf0;
if (ps2_hd.attention)
ps2_hd.status = 0x14;
break;
}
}
static void ps2board_init(void)
{
io_sethandler(0x0091, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0320, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0322, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
ps2_92 = 0;
ps2_190 = 0;
lpt1_init(0x3bc);
memset(&ps2_hd, 0, sizeof(ps2_hd));
}
void machine_ps2_m30_286_init(void)
{
AT = 1;
machine_common_init();
mem_add_bios();
pit_set_out_func(&pit, 1, pit_refresh_timer_at);
dma16_init();
keyboard_at_init();
nvr_init();
pic2_init();
ps2board_init();
fdc_set_dskchg_activelow();
fdc_set_ps1();
}

1
src/machine/machine_ps2_isa.h Normal file
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void machine_ps2_m30_286_init(void);

846
src/machine/machine_ps2_mca.c Normal file
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#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../cpu/x86.h"
#include "../device.h"
#include "../dma.h"
#include "../io.h"
#include "../keyboard_at.h"
#include "../lpt.h"
#include "../mca.h"
#include "../mem.h"
#include "../mouse.h"
#include "../nvr.h"
#include "../pic.h"
#include "../pit.h"
#include "../rom.h"
#include "../ps2_nvr.h"
#include "../serial.h"
#include "machine_common.h"
#include "machine_ps2_mca.h"
static struct
{
uint8_t adapter_setup;
uint8_t option[4];
uint8_t pos_vga;
uint8_t setup;
uint8_t sys_ctrl_port_a;
uint8_t subaddr_lo, subaddr_hi;
uint8_t memory_bank[8];
uint8_t io_id;
mem_mapping_t shadow_mapping;
mem_mapping_t split_mapping;
mem_mapping_t expansion_mapping;
uint8_t (*planar_read)(uint16_t port);
void (*planar_write)(uint16_t port, uint8_t val);
uint8_t mem_regs[3];
uint32_t split_addr;
uint8_t mem_pos_regs[8];
} ps2;
static uint8_t ps2_read_shadow_ram(uint32_t addr, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
return mem_read_ram(addr, priv);
}
static uint16_t ps2_read_shadow_ramw(uint32_t addr, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
return mem_read_ramw(addr, priv);
}
static uint32_t ps2_read_shadow_raml(uint32_t addr, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
return mem_read_raml(addr, priv);
}
static void ps2_write_shadow_ram(uint32_t addr, uint8_t val, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
mem_write_ram(addr, val, priv);
}
static void ps2_write_shadow_ramw(uint32_t addr, uint16_t val, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
mem_write_ramw(addr, val, priv);
}
static void ps2_write_shadow_raml(uint32_t addr, uint32_t val, void *priv)
{
addr = (addr & 0x1ffff) + 0xe0000;
mem_write_raml(addr, val, priv);
}
static uint8_t ps2_read_split_ram(uint32_t addr, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
return mem_read_ram(addr, priv);
}
static uint16_t ps2_read_split_ramw(uint32_t addr, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
return mem_read_ramw(addr, priv);
}
static uint32_t ps2_read_split_raml(uint32_t addr, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
return mem_read_raml(addr, priv);
}
static void ps2_write_split_ram(uint32_t addr, uint8_t val, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
mem_write_ram(addr, val, priv);
}
static void ps2_write_split_ramw(uint32_t addr, uint16_t val, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
mem_write_ramw(addr, val, priv);
}
static void ps2_write_split_raml(uint32_t addr, uint32_t val, void *priv)
{
addr = (addr & 0x3ffff) + 0xa0000;
mem_write_raml(addr, val, priv);
}
#define PS2_SETUP_IO 0x80
#define PS2_SETUP_VGA 0x20
#define PS2_ADAPTER_SETUP 0x08
static uint8_t model_50_read(uint16_t port)
{
switch (port)
{
case 0x100:
return 0xff;
case 0x101:
return 0xfb;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
}
return 0xff;
}
static uint8_t model_55sx_read(uint16_t port)
{
switch (port)
{
case 0x100:
return 0xff;
case 0x101:
return 0xfb;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.memory_bank[ps2.option[3] & 7];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
}
return 0xff;
}
static uint8_t model_80_read(uint16_t port)
{
switch (port)
{
case 0x100:
return 0xff;
case 0x101:
return 0xfd;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
}
return 0xff;
}
static void model_50_write(uint16_t port, uint8_t val)
{
switch (port)
{
case 0x100:
ps2.io_id = val;
break;
case 0x101:
break;
case 0x102:
lpt1_remove();
serial_remove(1);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2.option[1] = val;
break;
case 0x104:
ps2.option[2] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
}
}
static void model_55sx_write(uint16_t port, uint8_t val)
{
switch (port)
{
case 0x100:
ps2.io_id = val;
break;
case 0x101:
break;
case 0x102:
lpt1_remove();
serial_remove(1);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2.option[1] = val;
break;
case 0x104:
ps2.memory_bank[ps2.option[3] & 7] &= ~0xf;
ps2.memory_bank[ps2.option[3] & 7] |= (val & 0xf);
pclog("Write memory bank %i %02x\n", ps2.option[3] & 7, val);
break;
case 0x105:
pclog("Write POS3 %02x\n", val);
ps2.option[3] = val;
shadowbios = !(val & 0x10);
shadowbios_write = val & 0x10;
if (shadowbios)
{
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_mapping_disable(&ps2.shadow_mapping);
}
else
{
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_enable(&ps2.shadow_mapping);
}
if ((ps2.option[1] & 1) && !(ps2.option[3] & 0x20))
mem_set_mem_state(mem_size * 1024, 256 * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state(mem_size * 1024, 256 * 1024, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
}
}
static void model_80_write(uint16_t port, uint8_t val)
{
switch (port)
{
case 0x100:
break;
case 0x101:
break;
case 0x102:
lpt1_remove();
serial_remove(1);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2.option[1] = (ps2.option[1] & 0x0f) | (val & 0xf0);
break;
case 0x104:
ps2.option[2] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
}
}
uint8_t ps2_mca_read(uint16_t port, void *p)
{
uint8_t temp;
switch (port)
{
case 0x91:
fatal("Read 91 setup=%02x adapter=%02x\n", ps2.setup, ps2.adapter_setup);
case 0x92:
temp = ps2.sys_ctrl_port_a;
break;
case 0x94:
temp = ps2.setup;
break;
case 0x96:
temp = ps2.adapter_setup | 0x70;
break;
case 0x100:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0xfd;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x101:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0xef;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x102:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = ps2.pos_vga;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x103:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x104:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x105:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x106:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x107:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
default:
temp = 0xff;
break;
}
pclog("ps2_read: port=%04x temp=%02x\n", port, temp);
return temp;
}
static void ps2_mca_write(uint16_t port, uint8_t val, void *p)
{
pclog("ps2_write: port=%04x val=%02x %04x:%04x\n", port, val, CS,cpu_state.pc);
switch (port)
{
case 0x0092:
if ((val & 1) && !(ps2.sys_ctrl_port_a & 1))
{
softresetx86();
cpu_set_edx();
}
ps2.sys_ctrl_port_a = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x94:
ps2.setup = val;
break;
case 0x96:
ps2.adapter_setup = val;
mca_set_index(val & 7);
break;
case 0x100:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
mca_write(port, val);
break;
case 0x101:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
mca_write(port, val);
break;
case 0x102:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (!(ps2.setup & PS2_SETUP_VGA))
ps2.pos_vga = val;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x103:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x104:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x105:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x106:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x107:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
}
}
static void ps2_mca_board_common_init()
{
io_sethandler(0x0091, 0x0002, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
ps2.setup = 0xff;
lpt1_init(0x3bc);
}
static void ps2_mca_board_model_50_init()
{
ps2_mca_board_common_init();
mem_remap_top_384k();
mca_init(4);
ps2.planar_read = model_50_read;
ps2.planar_write = model_50_write;
}
static void ps2_mca_board_model_55sx_init()
{
ps2_mca_board_common_init();
mem_mapping_add(&ps2.shadow_mapping,
(mem_size+256) * 1024,
128*1024,
ps2_read_shadow_ram,
ps2_read_shadow_ramw,
ps2_read_shadow_raml,
ps2_write_shadow_ram,
ps2_write_shadow_ramw,
ps2_write_shadow_raml,
&ram[0xe0000],
MEM_MAPPING_INTERNAL,
NULL);
mem_remap_top_256k();
ps2.option[3] = 0x10;
memset(ps2.memory_bank, 0xf0, 8);
switch (mem_size/1024)
{
case 1:
ps2.memory_bank[0] = 0x61;
break;
case 2:
ps2.memory_bank[0] = 0x51;
break;
case 3:
ps2.memory_bank[0] = 0x51;
ps2.memory_bank[1] = 0x61;
break;
case 4:
ps2.memory_bank[0] = 0x51;
ps2.memory_bank[1] = 0x51;
break;
case 5:
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x61;
break;
case 6:
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x51;
break;
case 7: /*Not supported*/
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x51;
break;
case 8:
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x01;
break;
}
mca_init(4);
ps2.planar_read = model_55sx_read;
ps2.planar_write = model_55sx_write;
}
static void mem_encoding_update()
{
if (ps2.split_addr >= mem_size*1024)
mem_mapping_disable(&ps2.split_mapping);
ps2.split_addr = (ps2.mem_regs[0] & 0xf) << 20;
if (ps2.mem_regs[1] & 2)
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
if (!(ps2.mem_regs[1] & 8))
{
if (ps2.split_addr >= mem_size*1024)
mem_mapping_set_addr(&ps2.split_mapping, ps2.split_addr, 256*1024);
}
}
static uint8_t mem_encoding_read(uint16_t addr, void *p)
{
switch (addr)
{
case 0xe0:
return ps2.mem_regs[0];
case 0xe1:
return ps2.mem_regs[1];
}
return 0xff;
}
static void mem_encoding_write(uint16_t addr, uint8_t val, void *p)
{
switch (addr)
{
case 0xe0:
ps2.mem_regs[0] = val;
break;
case 0xe1:
ps2.mem_regs[1] = val;
break;
}
mem_encoding_update();
}
static uint8_t ps2_mem_expansion_read(int port, void *p)
{
return ps2.mem_pos_regs[port & 7];
}
static void ps2_mem_expansion_write(int port, uint8_t val, void *p)
{
if (port < 0x102 || port == 0x104)
return;
ps2.mem_pos_regs[port & 7] = val;
if (ps2.mem_pos_regs[2] & 1)
mem_mapping_enable(&ps2.expansion_mapping);
else
mem_mapping_disable(&ps2.expansion_mapping);
}
static void ps2_mca_board_model_80_type2_init()
{
ps2_mca_board_common_init();
mem_remap_top_256k();
ps2.split_addr = mem_size * 1024;
mca_init(24);
ps2.planar_read = model_80_read;
ps2.planar_write = model_80_write;
device_add(&ps2_nvr_device);
io_sethandler(0x00e0, 0x0002, mem_encoding_read, NULL, NULL, mem_encoding_write, NULL, NULL, NULL);
ps2.mem_regs[1] = 2;
switch (mem_size/1024)
{
case 1:
ps2.option[1] = 0x0c;
break;
case 2:
ps2.option[1] = 0x0e;
break;
case 3:
ps2.option[1] = 0x02;
break;
case 4:
default:
ps2.option[1] = 0x0a;
break;
}
mem_mapping_add(&ps2.split_mapping,
(mem_size+256) * 1024,
256*1024,
ps2_read_split_ram,
ps2_read_split_ramw,
ps2_read_split_raml,
ps2_write_split_ram,
ps2_write_split_ramw,
ps2_write_split_raml,
&ram[0xa0000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.split_mapping);
if (mem_size > 4096)
{
/* Only 4 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x800000);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 5:
ps2.mem_pos_regs[4] = 0xfc;
break;
case 6:
ps2.mem_pos_regs[4] = 0xfe;
break;
case 7:
ps2.mem_pos_regs[4] = 0xf2;
break;
case 8:
ps2.mem_pos_regs[4] = 0xfa;
break;
case 9:
ps2.mem_pos_regs[4] = 0xca;
break;
case 10:
ps2.mem_pos_regs[4] = 0xea;
break;
case 11:
ps2.mem_pos_regs[4] = 0x2a;
break;
case 12:
ps2.mem_pos_regs[4] = 0xaa;
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x400000,
(mem_size - 4096)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x400000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
}
static void machine_ps2_common_init(void)
{
AT = 1;
machine_common_init();
mem_add_bios();
dma16_init();
ps2_dma_init();
keyboard_at_init();
keyboard_at_init_ps2();
mouse_ps2_init();
nvr_init();
pic2_init();
pit_ps2_init();
}
void machine_ps2_model_50_init(void)
{
machine_ps2_common_init();
ps2_mca_board_model_50_init();
}
void machine_ps2_model_55sx_init(void)
{
machine_ps2_common_init();
ps2_mca_board_model_55sx_init();
}
void machine_ps2_model_80_init(void)
{
machine_ps2_common_init();
ps2_mca_board_model_80_type2_init();
}
void machine_ps2_model_80_486_init(void)
{
machine_ps2_common_init();
ps2_mca_board_model_80_type2_init();
}

4
src/machine/machine_ps2_mca.h Normal file
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extern void machine_ps2_model_50_init(void);
extern void machine_ps2_model_55sx_init(void);
extern void machine_ps2_model_80_init(void);
extern void machine_ps2_model_80_486_init(void);

44
src/machine/machine_tandy.c Normal file
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@@ -0,0 +1,44 @@
#include "../ibm.h"
#include "../device.h"
#include "../gameport.h"
#include "../keyboard_xt.h"
#include "../mem.h"
#include "../nmi.h"
#include "../tandy_eeprom.h"
#include "../tandy_rom.h"
#include "../sound/snd_pssj.h"
#include "../sound/snd_sn76489.h"
#include "machine_common.h"
void machine_tandy1k_init(void)
{
TANDY = 1;
machine_common_init();
mem_add_bios();
keyboard_tandy_init();
if (romset == ROM_TANDY)
device_add(&sn76489_device);
else
device_add(&ncr8496_device);
nmi_init();
if (romset != ROM_TANDY)
device_add(&tandy_eeprom_device);
if (joystick_type != 7)
device_add(&gameport_device);
}
void machine_tandy1ksl2_init(void)
{
machine_common_init();
mem_add_bios();
keyboard_tandy_init();
device_add(&pssj_device);
nmi_init();
device_add(&tandy_rom_device);
device_add(&tandy_eeprom_device);
if (joystick_type != 7) device_add(&gameport_device);
}

2
src/machine/machine_tandy.h Normal file
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@@ -0,0 +1,2 @@
void machine_tandy1k_init(void);
void machine_tandy1ksl2_init(void);

29
src/machine/machine_xt.c Normal file
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@@ -0,0 +1,29 @@
#include "../ibm.h"
#include "../bugger.h"
#include "../device.h"
#include "../gameport.h"
#include "../keyboard_xt.h"
#include "../mem.h"
#include "../nmi.h"
#include "../pit.h"
#include "machine_common.h"
#include "machine_xt.h"
void machine_xt_init(void)
{
machine_common_init();
mem_add_bios();
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
keyboard_xt_init();
nmi_init();
if (joystick_type != 7)
device_add(&gameport_device);
if (bugger_enabled)
bugger_init();
}

1
src/machine/machine_xt.h Normal file
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void machine_xt_init(void);

134
src/machine/machine_xt_laserxt.c Normal file
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@@ -0,0 +1,134 @@
/*This is the chipset used in the LaserXT series model*/
#include "../ibm.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../mem.h"
#include "machine_xt.h"
#include "machine_xt_laserxt.h"
static int laserxt_emspage[4];
static int laserxt_emscontrol[4];
static mem_mapping_t laserxt_ems_mapping[4];
static int laserxt_ems_baseaddr_index = 0;
static uint32_t get_laserxt_ems_addr(uint32_t addr)
{
if(laserxt_emspage[(addr >> 14) & 3] & 0x80)
{
addr = 0xA0000 + ((laserxt_emspage[(addr >> 14) & 3] & 0x0F) << 14) + ((laserxt_emspage[(addr >> 14) & 3] & 0x40) << 12) + (addr & 0x3FFF);
}
return addr;
}
static void laserxt_write(uint16_t port, uint8_t val, void *priv)
{
int i;
uint32_t paddr, vaddr;
switch (port)
{
case 0x0208: case 0x4208: case 0x8208: case 0xC208:
laserxt_emspage[port >> 14] = val;
paddr = 0xC0000 + (port & 0xC000) + (((laserxt_ems_baseaddr_index + (4 - (port >> 14))) & 0x0C) << 14);
if(val & 0x80)
{
mem_mapping_enable(&laserxt_ems_mapping[port >> 14]);
vaddr = get_laserxt_ems_addr(paddr);
mem_mapping_set_exec(&laserxt_ems_mapping[port >> 14], ram + vaddr);
}
else
{
mem_mapping_disable(&laserxt_ems_mapping[port >> 14]);
}
flushmmucache();
break;
case 0x0209: case 0x4209: case 0x8209: case 0xC209:
laserxt_emscontrol[port >> 14] = val;
laserxt_ems_baseaddr_index = 0;
for(i=0; i<4; i++)
{
laserxt_ems_baseaddr_index |= (laserxt_emscontrol[i] & 0x80) >> (7 - i);
}
if(laserxt_ems_baseaddr_index < 3)
{
mem_mapping_disable(&romext_mapping);
}
else
{
mem_mapping_enable(&romext_mapping);
}
mem_mapping_set_addr(&laserxt_ems_mapping[0], 0xC0000 + (((laserxt_ems_baseaddr_index + 4) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[1], 0xC4000 + (((laserxt_ems_baseaddr_index + 3) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[2], 0xC8000 + (((laserxt_ems_baseaddr_index + 2) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[3], 0xCC000 + (((laserxt_ems_baseaddr_index + 1) & 0x0C) << 14), 0x4000);
flushmmucache();
break;
}
}
static uint8_t laserxt_read(uint16_t port, void *priv)
{
switch (port)
{
case 0x0208: case 0x4208: case 0x8208: case 0xC208:
return laserxt_emspage[port >> 14];
case 0x0209: case 0x4209: case 0x8209: case 0xC209:
return laserxt_emscontrol[port >> 14];
break;
}
return 0xff;
}
static void mem_write_laserxtems(uint32_t addr, uint8_t val, void *priv)
{
addr = get_laserxt_ems_addr(addr);
if (addr < (mem_size << 10))
ram[addr] = val;
}
static uint8_t mem_read_laserxtems(uint32_t addr, void *priv)
{
uint8_t val = 0xFF;
addr = get_laserxt_ems_addr(addr);
if (addr < (mem_size << 10))
val = ram[addr];
return val;
}
static void laserxt_init(void)
{
int i;
if(mem_size > 640)
{
io_sethandler(0x0208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0x4208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0x8208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0xc208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
}
for (i = 0; i < 4; i++)
{
laserxt_emspage[i] = 0x7F;
laserxt_emscontrol[i] = (i == 3) ? 0x00 : 0x80;
mem_mapping_add(&laserxt_ems_mapping[i], 0xE0000 + (i << 14), 0x4000, mem_read_laserxtems, NULL, NULL, mem_write_laserxtems, NULL, NULL, ram + 0xA0000 + (i << 14), 0, NULL);
mem_mapping_disable(&laserxt_ems_mapping[i]);
}
mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
void machine_xt_laserxt_init(void)
{
machine_xt_init();
laserxt_init();
}

1
src/machine/machine_xt_laserxt.h Normal file
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@@ -0,0 +1 @@
void machine_xt_laserxt_init(void);