Machine code restructure, models are now machines instead and the init functions are in the machine files rather than in machine.c (former model.c), also moved the machine stuff into the machine/ subdirectory.
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OBattler
227
src/machine/machine_at_440fx.c
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227
src/machine/machine_at_440fx.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel 440FX PCISet chip.
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*
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* Version: @(#)machine_at_440fx.c 1.0.3 2017/09/02
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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* Copyright 2008-2017 Sarah Walker.
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* Copyright 2016-2017 Miran Grca.
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*/
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#include <string.h>
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#include "../ibm.h"
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#include "../cpu/cpu.h"
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#include "../device.h"
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#include "../fdc37c665.h"
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#include "../intel_flash.h"
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#include "../io.h"
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#include "../mem.h"
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#include "../memregs.h"
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#include "../pci.h"
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#include "../piix.h"
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#include "machine_at.h"
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#include "machine_at_440fx.h"
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static uint8_t card_i440fx[256];
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static void i440fx_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3)
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{
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void i440fx_write(int func, int addr, uint8_t val, void *priv)
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{
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if (func)
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return;
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if ((addr >= 0x10) && (addr < 0x4f))
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0c: case 0x0e:
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return;
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case 0x04: /*Command register*/
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val &= 0x02;
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val |= 0x04;
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break;
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case 0x05:
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val = 0;
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break;
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case 0x06: /*Status*/
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val = 0;
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break;
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case 0x07:
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val &= 0x80;
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val |= 0x02;
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break;
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case 0x59: /*PAM0*/
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if ((card_i440fx[0x59] ^ val) & 0xf0)
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{
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i440fx_map(0xf0000, 0x10000, val >> 4);
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shadowbios = (val & 0x10);
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}
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break;
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case 0x5a: /*PAM1*/
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if ((card_i440fx[0x5a] ^ val) & 0x0f)
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i440fx_map(0xc0000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5a] ^ val) & 0xf0)
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i440fx_map(0xc4000, 0x04000, val >> 4);
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break;
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case 0x5b: /*PAM2*/
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if ((card_i440fx[0x5b] ^ val) & 0x0f)
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i440fx_map(0xc8000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5b] ^ val) & 0xf0)
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i440fx_map(0xcc000, 0x04000, val >> 4);
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break;
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case 0x5c: /*PAM3*/
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if ((card_i440fx[0x5c] ^ val) & 0x0f)
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i440fx_map(0xd0000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5c] ^ val) & 0xf0)
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i440fx_map(0xd4000, 0x04000, val >> 4);
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break;
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case 0x5d: /*PAM4*/
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if ((card_i440fx[0x5d] ^ val) & 0x0f)
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i440fx_map(0xd8000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5d] ^ val) & 0xf0)
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i440fx_map(0xdc000, 0x04000, val >> 4);
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break;
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case 0x5e: /*PAM5*/
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if ((card_i440fx[0x5e] ^ val) & 0x0f)
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i440fx_map(0xe0000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5e] ^ val) & 0xf0)
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i440fx_map(0xe4000, 0x04000, val >> 4);
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break;
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case 0x5f: /*PAM6*/
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if ((card_i440fx[0x5f] ^ val) & 0x0f)
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i440fx_map(0xe8000, 0x04000, val & 0xf);
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if ((card_i440fx[0x5f] ^ val) & 0xf0)
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i440fx_map(0xec000, 0x04000, val >> 4);
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break;
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}
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card_i440fx[addr] = val;
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}
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static uint8_t i440fx_read(int func, int addr, void *priv)
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{
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if (func)
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return 0xff;
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return card_i440fx[addr];
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}
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static void i440fx_reset(void)
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{
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memset(card_i440fx, 0, 256);
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card_i440fx[0x00] = 0x86; card_i440fx[0x01] = 0x80; /*Intel*/
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card_i440fx[0x02] = 0x37; card_i440fx[0x03] = 0x12; /*82441FX*/
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card_i440fx[0x04] = 0x03; card_i440fx[0x05] = 0x01;
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card_i440fx[0x06] = 0x80; card_i440fx[0x07] = 0x00;
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card_i440fx[0x08] = 0x02; /*A0 stepping*/
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card_i440fx[0x09] = 0x00; card_i440fx[0x0a] = 0x00; card_i440fx[0x0b] = 0x06;
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card_i440fx[0x0d] = 0x00;
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card_i440fx[0x0f] = 0x00;
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card_i440fx[0x2c] = 0xf4;
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card_i440fx[0x2d] = 0x1a;
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card_i440fx[0x2e] = 0x00;
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card_i440fx[0x2f] = 0x11;
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card_i440fx[0x50] = 0x00;
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card_i440fx[0x51] = 0x01;
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card_i440fx[0x52] = card_i440fx[0x54] = card_i440fx[0x55] = card_i440fx[0x56] = 0x00;
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card_i440fx[0x53] = 0x80;
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card_i440fx[0x57] = 0x01;
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card_i440fx[0x58] = 0x10;
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card_i440fx[0x5a] = card_i440fx[0x5b] = card_i440fx[0x5c] = card_i440fx[0x5d] = card_i440fx[0x5e] = 0x11;
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card_i440fx[0x5f] = 0x31;
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card_i440fx[0x72] = 0x02;
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}
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static void i440fx_pci_reset(void)
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{
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i440fx_write(0, 0x59, 0x00, NULL);
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}
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static void i440fx_init(void)
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{
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pci_add_card(0, i440fx_read, i440fx_write, NULL);
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i440fx_reset();
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pci_reset_handler.pci_master_reset = i440fx_pci_reset;
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}
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void machine_at_i440fx_init(void)
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{
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machine_at_ide_init();
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memregs_init();
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pci_init(PCI_CONFIG_TYPE_1);
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pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
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pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
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pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
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pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
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i440fx_init();
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piix3_init(7);
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fdc37c665_init();
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device_add(&intel_flash_bxt_device);
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}
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void machine_at_s1668_init(void)
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{
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machine_at_ide_init();
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memregs_init();
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pci_init(PCI_CONFIG_TYPE_1);
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pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
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pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
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pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
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pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
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pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
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i440fx_init();
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piix3_init(7);
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fdc37c665_init();
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device_add(&intel_flash_bxt_device);
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}
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