Added the DTK PKM-0031Y.
This commit is contained in:
OBattler
@@ -72,6 +72,7 @@ add_library(chipset OBJECT
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sis_5572_usb.c
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sis_5595_pmu.c
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sis_55xx.c
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sl82c461.c
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via_vt82c49x.c
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via_vt82c505.c
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gc100.c
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362
src/chipset/sl82c461.c
Normal file
362
src/chipset/sl82c461.c
Normal file
@@ -0,0 +1,362 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Symphony SL82C461 (Haydn II) chipset.
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*
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* Symphony SL82C461 Configuration Registers (WARNING: May be inaccurate!):
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*
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* - Register 00h:
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* - Bit 6: External cache present (if clear, AMI BIOS'es will not
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* allow enabling external cache).
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*
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* - Register 01h:
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* - Bit 0: Fast Gate A20 Enable (Handler mostly).
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* Is it? Enabling/disabling fast gate A20 doesn't appear
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* to do much to any register at all.
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*
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* - Register 02h:
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* - Bit 0: Optional Chipset Turbo Pin;
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* - Bits 4-2:
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* - 000 = CLK2/3;
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* - 001 = CLK2/4;
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* - 010 = CLK2/5;
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* - 011 = 7.159 MHz (ATCLK2);
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* - 100 = CLK2/6;
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* - 110 = CLK2/2.5;
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* - 111 = CLK2/2.
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*
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* - Register 06h:
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* - Bit 2: Decoupled Refresh Option.
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*
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* - Register 08h:
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* - Bits 3, 2: I/O Recovery Time (SYSCLK):
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* - 0, 0 = 0;
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* - 1, 1 = 12.
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* - Bit 1: Extended ALE.
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*
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* - Register 25h:
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* Bit 7 here causes AMI 111192 CMOS Setup to return 7168 KB RAM
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* instead of 6912 KB. This is 256 KB off. Relocation?
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* Also, returning bit 5 clear instead of set, causes the AMI BIOS
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* to set bits 0,1 of register 45h to 1,0 instead of 0,1.
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*
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* - Register 2Dh:
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* - Bit 7: Enable 256KB Memory Relocation;
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* - Bit 6: Enable 384KB Memory Relocation, bit 7 must also be set.
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*
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* - Register 2Eh:
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* - Bit 7: CC000-CFFFF Shadow Read Enable;
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* - Bit 6: CC000-CFFFF Shadow Write Enable;
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* - Bit 5: C8000-CBFFF Shadow Read Enable;
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* - Bit 4: C8000-CBFFF Shadow Write Enable;
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* - Bit 3: C4000-C7FFF Shadow Read Enable;
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* - Bit 2: C4000-C7FFF Shadow Write Enable;
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* - Bit 1: C0000-C3FFF Shadow Read Enable;
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* - Bit 0: C0000-C3FFF Shadow Write Enable.
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*
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* - Register 2Fh:
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* - Bit 7: DC000-DFFFF Shadow Read Enable;
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* - Bit 6: DC000-DFFFF Shadow Write Enable;
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* - Bit 5: D8000-DBFFF Shadow Read Enable;
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* - Bit 4: D8000-DBFFF Shadow Write Enable;
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* - Bit 3: D4000-D7FFF Shadow Read Enable;
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* - Bit 2: D4000-D7FFF Shadow Write Enable;
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* - Bit 1: D0000-D3FFF Shadow Read Enable;
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* - Bit 0: D0000-D3FFF Shadow Write Enable.
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*
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* - Register 30h:
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* - Bit 7: E0000-EFFFF Shadow Read Enable;
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* - Bit 6: E0000-EFFFF Shadow Write Enable.
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*
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* - Register 31h:
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* - Bit 7: F0000-FFFFF Shadow Read Enable;
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* - Bit 6: F0000-FFFFF Shadow Write Enable.
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*
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* - Register 33h (NOTE: Waitstates also affect register 32h):
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* - Bits 3, 0:
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* - 0,0 = 0 W/S;
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* - 1,0 = 1 W/S;
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* - 1,1 = 2 W/S.
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*
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* - Register 40h:
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* - Bit 3: External Cache Enabled (0 = yes, 1 = no);
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* I also see bits 5, 4, 3 of register 44h affected:
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* - 38h (so all 3 set) when cache is disabled;
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* - 00h (all 3 clear) when it's enabled.
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*
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* - Register 45h:
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* - Bit 3: Video Shadow RAM Cacheable;
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* - Bit 4: Adapter Shadow RAM Cacheable;
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* - Bit 5: BIOS Shadow RAM Cacheable.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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* Tiseno100,
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*
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* Copyright 2025 Miran Grca.
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* Copyright 2021-2025 Tiseno100.
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*/
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#include <math.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/chipset.h>
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typedef struct {
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uint8_t index;
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uint8_t regs[256];
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uint8_t shadow[4];
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} sl82c461_t;
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#ifdef ENABLE_SL82C461_LOG
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int sl82c461_do_log = ENABLE_SL82C461_LOG;
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static void
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sl82c461_log(const char *fmt, ...)
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{
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va_list ap;
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if (sl82c461_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define sl82c461_log(fmt, ...)
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#endif
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static void
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sl82c461_recalcmapping(sl82c461_t *dev)
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{
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int do_shadow = 0;
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for (uint32_t i = 0; i < 8; i += 2) {
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if ((dev->regs[0x2e] ^ dev->shadow[0x00]) & (3 << i)) {
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uint32_t base = 0x000c0000 + ((i >> 1) << 14);
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uint32_t read = ((dev->regs[0x2e] >> i) & 0x02) ? MEM_READ_INTERNAL :
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MEM_READ_EXTANY;
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uint32_t write = ((dev->regs[0x2e] >> i) & 0x01) ? MEM_WRITE_INTERNAL :
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MEM_WRITE_EXTANY;
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mem_set_mem_state_both(base, 0x00004000, read | write);
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do_shadow++;
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}
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if ((dev->regs[0x2f] ^ dev->shadow[0x01]) & (3 << i)) {
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uint32_t base = 0x000d0000 + ((i >> 1) << 14);
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uint32_t read = ((dev->regs[0x2f] >> i) & 0x02) ? MEM_READ_INTERNAL :
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MEM_READ_EXTANY;
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uint32_t write = ((dev->regs[0x2f] >> i) & 0x01) ? MEM_WRITE_INTERNAL :
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MEM_WRITE_EXTANY;
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mem_set_mem_state_both(base, 0x00004000, read | write);
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do_shadow++;
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}
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}
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if ((dev->regs[0x30] ^ dev->shadow[0x02]) & 0xc0) {
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uint32_t base = 0x000e0000;
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uint32_t read = ((dev->regs[0x30] >> 6) & 0x02) ? MEM_READ_INTERNAL :
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MEM_READ_EXTANY;
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uint32_t write = ((dev->regs[0x30] >> 6) & 0x01) ? MEM_WRITE_INTERNAL :
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MEM_WRITE_EXTANY;
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mem_set_mem_state_both(base, 0x00010000, read | write);
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do_shadow++;
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}
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if ((dev->regs[0x31] ^ dev->shadow[0x03]) & 0xc0) {
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uint32_t base = 0x000f0000;
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uint32_t read = ((dev->regs[0x31] >> 6) & 0x02) ? MEM_READ_INTERNAL :
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MEM_READ_EXTANY;
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uint32_t write = ((dev->regs[0x31] >> 6) & 0x01) ? MEM_WRITE_INTERNAL :
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MEM_WRITE_EXTANY;
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shadowbios = !!((dev->regs[0x31] >> 6) & 0x02);
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shadowbios_write = !!((dev->regs[0x31] >> 6) & 0x01);
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mem_set_mem_state_both(base, 0x00010000, read | write);
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do_shadow++;
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}
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if (do_shadow) {
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memcpy(dev->shadow, &(dev->regs[0x2e]), 4 * sizeof(uint8_t));
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flushmmucache_nopc();
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}
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}
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static void
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sl82c461_write(uint16_t addr, uint8_t val, void *priv)
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{
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sl82c461_t *dev = (sl82c461_t *) priv;
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sl82c461_log("[%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, addr, val);
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if (addr & 0x0001) {
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dev->regs[dev->index] = val;
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switch (dev->index) {
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case 0x01:
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/* NOTE: This is to be verified. */
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mem_a20_alt = val & 1;
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mem_a20_recalc();
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break;
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case 0x02: {
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double bus_clk;
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switch (val & 0x1c) {
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case 0x00:
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bus_clk = cpu_busspeed / 3.0;
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break;
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case 0x04:
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bus_clk = cpu_busspeed / 4.0;
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break;
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case 0x08:
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bus_clk = cpu_busspeed / 5.0;
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break;
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default:
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case 0x0c:
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bus_clk = 7159091.0;
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break;
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case 0x10:
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bus_clk = cpu_busspeed / 6.0;
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break;
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case 0x18:
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bus_clk = cpu_busspeed / 2.5;
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break;
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case 0x1c:
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bus_clk = cpu_busspeed / 2.0;
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break;
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}
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cpu_set_isa_speed((int) round(bus_clk));
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break;
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} case 0x2d:
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switch (val & 0xc0) {
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case 0xc0:
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mem_remap_top(384);
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break;
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case 0x80:
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mem_remap_top(256);
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break;
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default:
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case 0x00:
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mem_remap_top(0);
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break;
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}
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break;
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case 0x2e ... 0x31:
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sl82c461_recalcmapping(dev);
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break;
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case 0x33:
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switch (val & 0x09) {
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default:
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case 0x00:
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cpu_waitstates = 0;
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break;
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case 0x08:
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cpu_waitstates = 1;
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break;
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case 0x09:
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cpu_waitstates = 2;
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break;
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}
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cpu_update_waitstates();
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break;
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case 0x40:
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cpu_cache_ext_enabled = !(val & 0x08);
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cpu_update_waitstates();
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break;
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}
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} else
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dev->index = val;
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}
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static uint8_t
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sl82c461_read(uint16_t addr, void *priv)
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{
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sl82c461_t *dev = (sl82c461_t *) priv;
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uint8_t ret = 0x00;
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if (addr & 0x0001)
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if (dev->index == 0x00)
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ret = dev->regs[dev->index] | 0x40;
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else
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ret = dev->regs[dev->index];
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else
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ret = dev->index;
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sl82c461_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
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return ret;
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}
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static void
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sl82c461_close(void *priv)
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{
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sl82c461_t *dev = (sl82c461_t *) priv;
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free(dev);
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}
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static void *
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sl82c461_init(const device_t *info)
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{
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sl82c461_t *dev = (sl82c461_t *) calloc(1, sizeof(sl82c461_t));
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dev->regs[0x00] = 0x40;
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dev->regs[0x02] = 0x0c;
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dev->regs[0x40] = 0x08;
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memset(dev->shadow, 0xff, 4 * sizeof(uint8_t));
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mem_a20_alt = 0x00;
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mem_a20_recalc();
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cpu_set_isa_speed(7159091.0);
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sl82c461_recalcmapping(dev);
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cpu_waitstates = 0;
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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io_sethandler(0x00a8, 2,
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sl82c461_read, NULL, NULL,
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sl82c461_write, NULL, NULL, dev);
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return dev;
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}
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const device_t sl82c461_device = {
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.name = "Symphony SL82C461 (Haydn II)",
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.internal_name = "sis_85c471",
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.flags = 0,
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.local = 0,
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.init = sl82c461_init,
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.close = sl82c461_close,
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.reset = NULL,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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@@ -159,6 +159,9 @@ extern const device_t stpc_atlas_device;
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extern const device_t stpc_serial_device;
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extern const device_t stpc_lpt_device;
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/* Symphony */
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extern const device_t sl82c461_device;
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/* UMC */
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extern const device_t umc_8886f_device;
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extern const device_t umc_8886af_device;
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@@ -555,6 +555,7 @@ extern int machine_at_aptiva510_init(const machine_t *);
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extern int machine_at_pc330_6573_init(const machine_t *);
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extern int machine_at_mvi486_init(const machine_t *);
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extern int machine_at_dtk461_init(const machine_t *);
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extern int machine_at_sis401_init(const machine_t *);
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extern int machine_at_isa486_init(const machine_t *);
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extern int machine_at_av4_init(const machine_t *);
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@@ -134,6 +134,27 @@ machine_at_tandy4000_init(const machine_t *model)
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return ret;
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}
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int
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machine_at_dtk461_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear("roms/machines/dtk461/DTK.BIO",
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0x000f0000, 65536, 0);
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if (bios_only || !ret)
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return ret;
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machine_at_common_init(model);
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device_add(&sl82c461_device);
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device_add(&keyboard_at_ami_device);
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if (fdc_current[0] == FDC_INTERNAL)
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device_add(&fdc_at_device);
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return ret;
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}
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static void
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machine_at_sis401_common_init(const machine_t *model)
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{
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@@ -6403,6 +6403,46 @@ const machine_t machines[] = {
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.snd_device = NULL,
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.net_device = NULL
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},
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/* Has AMIKey F KBC firmware. */
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{
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.name = "[Symphony SL42C460] DTK PKM-0031Y",
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.internal_name = "dtk461",
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.type = MACHINE_TYPE_486,
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.chipset = MACHINE_CHIPSET_SYMPHONY_SL82C460,
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.init = machine_at_dtk461_init,
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.p1_handler = NULL,
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.gpio_handler = NULL,
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.available_flag = MACHINE_AVAILABLE,
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.gpio_acpi_handler = NULL,
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.cpu = {
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.package = CPU_PKG_SOCKET1,
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.block = CPU_BLOCK_NONE,
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.min_bus = 0,
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.max_bus = 0,
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.min_voltage = 0,
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.max_voltage = 0,
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.min_multi = 0,
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.max_multi = 0
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},
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.bus_flags = MACHINE_AT,
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.flags = MACHINE_APM,
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.ram = {
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.min = 1024,
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.max = 65536,
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.step = 1024
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},
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.nvrmask = 127,
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.kbc_device = NULL,
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.kbc_p1 = 0xff,
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.gpio = 0xffffffff,
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.gpio_acpi = 0xffffffff,
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.device = NULL,
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.fdc_device = NULL,
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.sio_device = NULL,
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.vid_device = NULL,
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.snd_device = NULL,
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.net_device = NULL
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},
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/* The chip is a Lance LT38C41, a clone of the Intel 8041, and the BIOS sends
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commands BC, BD, and C9 which exist on both AMIKey and Phoenix MultiKey/42,
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but it does not write a byte after C9, which is consistent with AMIKey, so
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Reference in New Issue
Block a user