Intel SIO overhaul, slight DMA clean-ups and SIO-related additions, made the PIIX/SMSC series of southbridges aware of CPU speed changes, and fixed a bug in the 86F loading code.
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@@ -3811,7 +3811,7 @@ d86f_load(int drive, wchar_t *fn)
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if (dev->extra_bit_cells[1] > 32768) dev->extra_bit_cells[1] = 32768;
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}
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} else {
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dev->extra_bit_cells[0] = 0;
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dev->extra_bit_cells[1] = 0;
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}
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} else {
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switch ((dev->disk_flags >> 1) >> 3) {
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