Intel SIO overhaul, slight DMA clean-ups and SIO-related additions, made the PIIX/SMSC series of southbridges aware of CPU speed changes, and fixed a bug in the 86F loading code.

This commit is contained in:
OBattler
2020-06-11 12:52:50 +02:00
parent de1cae40f7
commit 464a6da62f
6 changed files with 1050 additions and 225 deletions

View File

@@ -3811,7 +3811,7 @@ d86f_load(int drive, wchar_t *fn)
if (dev->extra_bit_cells[1] > 32768) dev->extra_bit_cells[1] = 32768;
}
} else {
dev->extra_bit_cells[0] = 0;
dev->extra_bit_cells[1] = 0;
}
} else {
switch ((dev->disk_flags >> 1) >> 3) {