Intel SIO overhaul, slight DMA clean-ups and SIO-related additions, made the PIIX/SMSC series of southbridges aware of CPU speed changes, and fixed a bug in the 86F loading code.

2020-06-11 12:52:50 +02:00
parent de1cae40f7
commit 464a6da62f
6 changed files with 1050 additions and 225 deletions
--- a/src/pci.c
+++ b/src/pci.c
@@ -677,6 +677,7 @@ static void
 trc_reset(uint8_t val)
 {
    if (val & 2) {
+	dma_reset();
 	device_reset_all_pci();

 	cpu_alt_reset = 0;