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This commit is contained in:
Jasmine Iwanek
2022-02-20 02:26:27 -05:00
parent a66e392b26
commit 4674756664
401 changed files with 6985 additions and 6985 deletions
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2
src/scsi/scsi.c
View File

@@ -166,7 +166,7 @@ scsi_card_get_from_internal_name(char *s)
return(c);
c++;
}
return(0);
}

12
src/scsi/scsi_aha154x.c
View File

@@ -301,7 +301,7 @@ aha_param_len(void *p)
case CMD_SHADOW_RAM:
return 1;
break;
break;
case CMD_WRITE_EEPROM:
return 35;
@@ -407,7 +407,7 @@ aha_cmds(void *p)
dev->DataBuf[1] = dev->Lock;
dev->DataReplyLeft = 2;
break;
case CMD_MBENABLE: /* Mailbox interface enable Command */
dev->DataReplyLeft = 0;
if (dev->CmdBuf[1] == dev->Lock) {
@@ -549,7 +549,7 @@ aha_mca_write(int port, uint8_t val, void *priv)
/* Save the new IRQ and DMA channel values. */
dev->Irq = (dev->pos_regs[4] & 0x07) + 8;
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
/* Extract the BIOS ROM address info. */
if (! (dev->pos_regs[2] & 0x80)) switch(dev->pos_regs[3] & 0x38) {
@@ -1013,7 +1013,7 @@ aha_init(const device_t *info)
dev->rom_shramsz = 128; /* size of shadow RAM */
dev->ha_bps = 5000000.0; /* normal SCSI */
break;
case AHA_154xB:
strcpy(dev->name, "AHA-154xB");
switch(dev->Base) {
@@ -1107,11 +1107,11 @@ aha_init(const device_t *info)
/* Enable MCA. */
dev->pos_regs[0] = 0x1F; /* MCA board ID */
dev->pos_regs[1] = 0x0F;
dev->pos_regs[1] = 0x0F;
mca_add(aha_mca_read, aha_mca_write, aha_mca_feedb, NULL, dev);
dev->ha_bps = 5000000.0; /* normal SCSI */
break;
}
}
/* Initialize ROM BIOS if needed. */
aha_setbios(dev);

58
src/scsi/scsi_buslogic.c
View File

@@ -268,7 +268,7 @@ BuslogicGetNVRFileName(buslogic_data_t *bl)
switch(bl->chip)
{
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
return "bt542b.nvr";
return "bt542b.nvr";
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
return "bt545s.nvr";
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
@@ -483,7 +483,7 @@ buslogic_get_host_id(void *p)
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
@@ -503,8 +503,8 @@ buslogic_get_irq(void *p)
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) ||
(bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
@@ -526,8 +526,8 @@ buslogic_get_dma(void *p)
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30)
return (dev->Base ? 7 : 0);
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
return dev->DmaChannel;
@@ -557,7 +557,7 @@ buslogic_param_len(void *p)
return sizeof(MailboxInitExtended_t);
case 0x83:
return 12;
case 0x90:
case 0x90:
case 0x91:
return 2;
case 0x94:
@@ -615,7 +615,7 @@ BuslogicSCSIBIOSDMATransfer(x54x_t *dev, ESCMD *ESCSICmd, uint8_t TargetID, int
static void
BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, uint8_t DataReply)
{
{
ESCMD *ESCSICmd = (ESCMD *)CmdBuf;
uint32_t i;
uint8_t temp_cdb[12];
@@ -633,8 +633,8 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
DataInBuf[3] = SCSI_STATUS_OK;
return;
}
buslogic_log("Scanning SCSI Target ID %i\n", ESCSICmd->TargetId);
buslogic_log("Scanning SCSI Target ID %i\n", ESCSICmd->TargetId);
sd->status = SCSI_STATUS_OK;
@@ -648,7 +648,7 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
scsi_device_identify(sd, ESCSICmd->LogicalUnit);
buslogic_log("Transfer Control %02X\n", ESCSICmd->DataDirection);
buslogic_log("CDB Length %i\n", ESCSICmd->CDBLength);
buslogic_log("CDB Length %i\n", ESCSICmd->CDBLength);
}
target_cdb_len = 12;
@@ -687,7 +687,7 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
DataInBuf[3] = SCSI_STATUS_OK;
} else if (scsi_devices[dev->bus][ESCSICmd->TargetId].status == SCSI_STATUS_CHECK_CONDITION) {
DataInBuf[2] = CCB_COMPLETE;
DataInBuf[3] = SCSI_STATUS_CHECK_CONDITION;
DataInBuf[3] = SCSI_STATUS_CHECK_CONDITION;
}
dev->DataReplyLeft = DataReply;
@@ -732,7 +732,7 @@ buslogic_cmds(void *p)
}
dev->DataReplyLeft = 8;
break;
case 0x24:
case 0x24:
for (i = 0; i < 15; i++) {
if (scsi_device_present(&scsi_devices[dev->bus][i]) && (i != buslogic_get_host_id(dev)))
TargetsPresentMask |= (1 << i);
@@ -771,7 +771,7 @@ buslogic_cmds(void *p)
buslogic_log("Execute SCSI BIOS Command: %u more bytes follow\n", dev->CmdParamLeft);
} else {
buslogic_log("Execute SCSI BIOS Command: received %u bytes\n", dev->CmdBuf[0]);
BuslogicSCSIBIOSRequestSetup(dev, dev->CmdBuf, dev->DataBuf, 4);
BuslogicSCSIBIOSRequestSetup(dev, dev->CmdBuf, dev->DataBuf, 4);
}
break;
case 0x84:
@@ -817,7 +817,7 @@ buslogic_cmds(void *p)
dev->DataReplyLeft = sizeof(BuslogicPCIInformation_t);
} else {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
dev->Status |= STAT_INVCMD;
}
break;
case 0x8B:
@@ -862,7 +862,7 @@ buslogic_cmds(void *p)
ReplyIESI->cMailbox = dev->MailboxCount;
ReplyIESI->uMailboxAddressBase = dev->MailboxOutAddr;
ReplyIESI->fHostWideSCSI = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) &&
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) &&
(bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23) &&
(bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16))
ReplyIESI->fLevelSensitiveInterrupt = bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt;
@@ -876,12 +876,12 @@ buslogic_cmds(void *p)
buslogic_log("Aggressive Round Robin Mode = %d\n", bl->fAggressiveRoundRobinMode);
dev->DataReplyLeft = 0;
break;
case 0x90:
case 0x90:
buslogic_log("Store Local RAM\n");
Offset = dev->CmdBuf[0];
dev->DataReplyLeft = 0;
memcpy(&(bl->LocalRAM.u8View[Offset]), &(dev->CmdBuf[2]), dev->CmdBuf[1]);
dev->DataReply = 0;
break;
case 0x91:
@@ -899,9 +899,9 @@ buslogic_cmds(void *p)
break;
}
case 0x92:
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
@@ -980,7 +980,7 @@ buslogic_cmds(void *p)
return 1;
} else {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
dev->Status |= STAT_INVCMD;
}
break;
case 0x96:
@@ -988,7 +988,7 @@ buslogic_cmds(void *p)
bl->ExtendedLUNCCBFormat = 0;
else if (dev->CmdBuf[0] == 1)
bl->ExtendedLUNCCBFormat = 1;
dev->DataReplyLeft = 0;
break;
case 0x97:
@@ -1309,7 +1309,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
x54x_mem_set_addr(dev, bl->MMIOBase);
}
}
return;
return;
case 0x30: /* PCI_ROMBAR */
case 0x31: /* PCI_ROMBAR */
@@ -1390,7 +1390,7 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
/* Save the new IRQ and DMA channel values. */
dev->Irq = ((dev->pos_regs[2] >> 1) & 0x07) + 8;
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
/* Extract the BIOS ROM address info. */
if (dev->pos_regs[2] & 0xe0) switch(dev->pos_regs[2] & 0xe0) {
@@ -1401,7 +1401,7 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
case 0x00: /* [0]=000x xxxx */
bl->bios_addr = 0;
break;
case 0xc0: /* [0]=110x xxxx */
bl->bios_addr = 0xD8000;
break;
@@ -1679,7 +1679,7 @@ buslogic_init(const device_t *info)
dev->fw_rev = "BA335";
dev->flags |= X54X_32BIT;
dev->pos_regs[0] = 0x08; /* MCA board ID */
dev->pos_regs[1] = 0x07;
dev->pos_regs[1] = 0x07;
mca_add(buslogic_mca_read, buslogic_mca_write, buslogic_mca_feedb, NULL, dev);
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
@@ -1788,9 +1788,9 @@ buslogic_init(const device_t *info)
if ((bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
mem_mapping_disable(&bl->bios.mapping);
buslogic_log("Buslogic on port 0x%04X\n", dev->Base);
x54x_device_reset(dev);
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) && (bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) &&

36
src/scsi/scsi_cdrom.c
View File

@@ -140,7 +140,7 @@ const uint8_t scsi_cdrom_command_flags[0x100] =
IMPLEMENTED | CHECK_READY, /* 0xBE */
IMPLEMENTED | CHECK_READY, /* 0xBF */
IMPLEMENTED | CHECK_READY | SCSI_ONLY, /* 0xC0 */
IMPLEMENTED | CHECK_READY | SCSI_ONLY, /* 0xC1 */
IMPLEMENTED | CHECK_READY | SCSI_ONLY, /* 0xC1 */
IMPLEMENTED | CHECK_READY | SCSI_ONLY, /* 0xC2 */
0, /* 0xC3 */
IMPLEMENTED | CHECK_READY | SCSI_ONLY, /* 0xC4 */
@@ -1127,7 +1127,7 @@ scsi_cdrom_read_dvd_structure(scsi_cdrom_t *dev, int format, const uint8_t *pack
/* Size of buffer, not including 2 byte size field */
buf[0] = ((4 + 2) >> 8) & 0xff;
buf[1] = (4 + 2) & 0xff;
buf[1] = (4 + 2) & 0xff;
/* 4 byte header + 4 byte data */
return (4 + 4);
@@ -1564,16 +1564,16 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_set_phase(dev, SCSI_PHASE_DATA_IN);
scsi_cdrom_buf_alloc(dev, 65536);
if ((!dev->drv->ops) && ((cdb[1] & 3) == 2)) {
scsi_cdrom_not_ready(dev);
return;
}
}
memset(dev->buffer, 0, 4);
cdrom_read_disc_info_toc(dev->drv, dev->buffer, cdb[2], cdb[1] & 3);
len = 4;
scsi_cdrom_set_buf_len(dev, BufLen, &len);
@@ -1979,7 +1979,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
case GPCMD_READ_DISC_INFORMATION:
scsi_cdrom_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[7];
max_len <<= 8;
max_len |= cdb[8];
@@ -2064,7 +2064,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_illegal_mode(dev);
break;
case GPCMD_TOSHIBA_PLAY_AUDIO:
case GPCMD_TOSHIBA_PLAY_AUDIO:
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
if ((dev->drv->host_drive < 1) || (dev->drv->cd_status <= CD_STATUS_DATA_ONLY)) {
scsi_cdrom_illegal_mode(dev);
@@ -2072,7 +2072,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
}
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
ret = cdrom_toshiba_audio_play(dev->drv, pos, cdb[9]);
if (ret)
scsi_cdrom_command_complete(dev);
else
@@ -2207,7 +2207,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
dev->buffer[1] = 0x13;
break;
}
scsi_cdrom_log("Audio Status = %02x\n", dev->buffer[1]);
}
@@ -2246,7 +2246,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_set_buf_len(dev, BufLen, &alloc_length);
scsi_cdrom_data_command_finish(dev, len, len, len, 0);
break;
break;
case GPCMD_READ_DVD_STRUCTURE:
scsi_cdrom_set_phase(dev, SCSI_PHASE_DATA_IN);
@@ -2306,7 +2306,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_command_complete(dev);
break;
case GPCMD_CADDY_EJECT:
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
scsi_cdrom_stop(sc);
@@ -2384,22 +2384,22 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
memset(dev->buffer, 0, 8);
dev->buffer[0] = 5; /*CD-ROM*/
dev->buffer[1] = 0x80; /*Removable*/
if (dev->drv->bus_type == CDROM_BUS_SCSI) {
dev->buffer[2] = 0x02;
dev->buffer[3] = 0x02;
}
else {
dev->buffer[2] = 0x00;
dev->buffer[3] = 0x21;
dev->buffer[3] = 0x21;
}
dev->buffer[4] = 31;
if (dev->drv->bus_type == CDROM_BUS_SCSI) {
dev->buffer[6] = 1; /* 16-bit transfers supported */
dev->buffer[7] = 0x20; /* Wide bus supported */
}
if (dev->drv->bus_type == CDROM_BUS_SCSI) {
ide_padstr8(dev->buffer + 8, 8, "TOSHIBA"); /* Vendor */
ide_padstr8(dev->buffer + 16, 16, "XM6201TASUN32XCD"); /* Product */
@@ -2487,7 +2487,7 @@ atapi_out:
case GPCMD_STOP_PLAY_SCAN:
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
if (dev->drv->cd_status <= CD_STATUS_DATA_ONLY) {
if (dev->drv->cd_status <= CD_STATUS_DATA_ONLY) {
scsi_cdrom_illegal_mode(dev);
break;
}

4
src/scsi/scsi_disk.c
View File

@@ -495,7 +495,7 @@ scsi_disk_reset(scsi_common_t *sc)
void
scsi_disk_request_sense(scsi_disk_t *dev, uint8_t *buffer, uint8_t alloc_length, int desc)
{
{
/*Will return 18 bytes of 0*/
if (alloc_length != 0) {
memset(buffer, 0, alloc_length);
@@ -922,7 +922,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * SCSI_TIME;
break;
}
}
scsi_disk_buf_alloc(dev, 65536);

148
src/scsi/scsi_ncr5380.c
View File

@@ -94,7 +94,7 @@
#define STATUS_BUFFER_NOT_READY 0x04
#define STATUS_53C80_ACCESSIBLE 0x80
typedef struct {
typedef struct {
uint8_t icr, mode, tcr, data_wait;
uint8_t isr, output_data, target_id, tx_data;
uint8_t msglun;
@@ -115,10 +115,10 @@ typedef struct {
uint8_t buffer[512];
uint8_t ext_ram[0x80];
uint8_t block_count;
int block_loaded;
int pos, host_pos;
int bios_enabled;
} t128_t;
@@ -154,7 +154,7 @@ typedef struct {
pc_timer_t timer;
double period;
int ncr_busy;
int ncr_busy;
} ncr5380_t;
#define STATE_IDLE 0
@@ -229,7 +229,7 @@ get_dev_id(uint8_t data)
return(-1);
}
static int
static int
getmsglen(uint8_t *msgp, int len)
{
uint8_t msg = msgp[0];
@@ -247,9 +247,9 @@ ncr_reset(ncr5380_t *ncr_dev, ncr_t *ncr)
{
memset(ncr, 0x00, sizeof(ncr_t));
ncr_log("NCR reset\n");
timer_stop(&ncr_dev->timer);
for (int i = 0; i < 8; i++)
scsi_device_reset(&scsi_devices[ncr_dev->bus][i]);
@@ -260,10 +260,10 @@ static void
ncr_timer_on(ncr5380_t *ncr_dev, ncr_t *ncr, int callback)
{
double p = ncr_dev->period;
if (ncr->data_wait & 2)
ncr->data_wait &= ~2;
if (callback) {
if (ncr_dev->type == 3)
p *= 512.0;
@@ -272,7 +272,7 @@ ncr_timer_on(ncr5380_t *ncr_dev, ncr_t *ncr, int callback)
}
p += 1.0;
ncr_log("P = %lf, command = %02x, callback = %i, period = %lf, t128 pos = %i\n", p, ncr->command[0], callback, ncr_dev->period, ncr_dev->t128.host_pos);
timer_on_auto(&ncr_dev->timer, p);
}
@@ -338,7 +338,7 @@ ncr_bus_read(ncr5380_t *ncr_dev)
ncr->wait_data--;
if (!ncr->wait_data) {
dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
SET_BUS_STATE(ncr, ncr->new_phase);
SET_BUS_STATE(ncr, ncr->new_phase);
phase = (ncr->cur_bus & SCSI_PHASE_MESSAGE_IN);
if (phase == SCSI_PHASE_DATA_IN) {
@@ -538,7 +538,7 @@ ncr_bus_update(void *priv, int bus)
ncr->cur_bus &= ~BUS_REQ;
ncr->new_phase = SCSI_PHASE_MESSAGE_IN;
ncr->wait_data = 4;
ncr->wait_complete = 8;
ncr->wait_complete = 8;
}
break;
case STATE_MESSAGEIN:
@@ -578,7 +578,7 @@ ncr_bus_update(void *priv, int bus)
}
static void
static void
ncr_write(uint16_t port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -611,7 +611,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
}
ncr->mode = val;
if (ncr_dev->type == 3) {
/*Don't stop the timer until it finishes the transfer*/
if (ncr_dev->t128.block_loaded && (ncr->mode & MODE_DMA)) {
@@ -632,7 +632,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr_log("Continuing DMA mode\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
if (!ncr_dev->block_count_loaded && !(ncr->mode & MODE_DMA)) {
ncr_log("No DMA mode\n");
@@ -651,15 +651,15 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
case 4: /* Select Enable Register */
ncr_log("Write: Select Enable register\n");
break;
case 5: /* start DMA Send */
ncr_log("Write: start DMA send register\n");
/*a Write 6/10 has occurred, start the timer when the block count is loaded*/
ncr->dma_mode = DMA_SEND;
if (ncr_dev->type == 3) {
memset(ncr_dev->t128.buffer, 0, MIN(512, dev->buffer_length));
ncr_log("DMA send timer start, enabled? = %i\n", timer_is_enabled(&ncr_dev->timer));
memset(ncr_dev->t128.buffer, 0, MIN(512, dev->buffer_length));
ncr_log("DMA send timer start, enabled? = %i\n", timer_is_enabled(&ncr_dev->timer));
ncr_dev->t128.block_count = dev->buffer_length >> 9;
ncr_dev->t128.block_loaded = 1;
@@ -668,7 +668,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
} else {
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
memset(ncr_dev->buffer, 0, MIN(128, dev->buffer_length));
ncr_log("DMA send timer on\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
@@ -682,12 +682,12 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
if (ncr_dev->type == 3) {
ncr_log("DMA receive timer start, enabled? = %i, cdb[0] = %02x\n", timer_is_enabled(&ncr_dev->timer), ncr->command[0]);
memset(ncr_dev->t128.buffer, 0, MIN(512, dev->buffer_length));
ncr_dev->t128.block_count = dev->buffer_length >> 9;
if (dev->buffer_length < 512)
ncr_dev->t128.block_count = 1;
ncr_dev->t128.block_loaded = 1;
ncr_dev->t128.host_pos = MIN(512, dev->buffer_length);
@@ -696,7 +696,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
} else {
if ((ncr->mode & MODE_DMA) && !timer_is_enabled(&ncr_dev->timer)) {
memset(ncr_dev->buffer, 0, MIN(128, dev->buffer_length));
ncr_log("DMA receive timer start\n");
ncr_timer_on(ncr_dev, ncr, 0);
}
@@ -707,7 +707,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
ncr_log("NCR5380: bad write %04x %02x\n", port, val);
break;
}
if (ncr->dma_mode == DMA_IDLE || ncr_dev->type == 0 || ncr_dev->type == 3) {
bus_host = get_bus_host(ncr);
ncr_bus_update(priv, bus_host);
@@ -715,7 +715,7 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
}
static uint8_t
static uint8_t
ncr_read(uint16_t port, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -763,11 +763,11 @@ ncr_read(uint16_t port, void *priv)
case 5: /* Bus and Status register */
ncr_log("Read: Bus and Status register\n");
ret = 0;
ret = 0;
bus = get_bus_host(ncr);
ncr_log("Get host from Interrupt\n");
/*Check if the phase in process matches with TCR's*/
if ((bus & SCSI_PHASE_MESSAGE_IN) == (ncr->cur_bus & SCSI_PHASE_MESSAGE_IN)) {
ncr_log("Phase match\n");
@@ -781,13 +781,13 @@ ncr_read(uint16_t port, void *priv)
ret |= STATUS_ACK;
if (bus & BUS_ATN)
ret |= 0x02;
if ((bus & BUS_REQ) && (ncr->mode & MODE_DMA)) {
ncr_log("Entering DMA mode\n");
ret |= STATUS_DRQ;
bus_state = 0;
if (bus & BUS_IO)
bus_state |= TCR_IO;
if (bus & BUS_CD)
@@ -828,14 +828,14 @@ ncr_read(uint16_t port, void *priv)
/* Memory-mapped I/O READ handler. */
static uint8_t
static uint8_t
memio_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
uint8_t ret = 0xff;
addr &= 0x3fff;
if (addr < 0x2000)
@@ -858,14 +858,14 @@ memio_read(uint32_t addr, void *priv)
#endif
ret = ncr_read(addr, ncr_dev);
break;
case 0x3900:
if (ncr_dev->buffer_host_pos >= MIN(128, dev->buffer_length) || !(ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
ret = 0xff;
} else {
ret = ncr_dev->buffer[ncr_dev->buffer_host_pos++];
if (ncr_dev->buffer_host_pos == MIN(128, dev->buffer_length)) {
if (ncr_dev->buffer_host_pos == MIN(128, dev->buffer_length)) {
ncr_dev->status_ctrl |= STATUS_BUFFER_NOT_READY;
ncr_log("Transfer busy read, status = %02x\n", ncr_dev->status_ctrl);
}
@@ -893,7 +893,7 @@ memio_read(uint32_t addr, void *priv)
ret = 0xff;
break;
}
break;
break;
}
#if ENABLE_NCR5380_LOG
@@ -906,13 +906,13 @@ memio_read(uint32_t addr, void *priv)
/* Memory-mapped I/O WRITE handler. */
static void
static void
memio_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
addr &= 0x3fff;
ncr_log("memio_write(%08x,%02x) %i %02x\n", addr, val, ncr_dev->buffer_host_pos, ncr_dev->status_ctrl);
@@ -927,7 +927,7 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
case 0x3880:
ncr_write(addr, val, ncr_dev);
break;
case 0x3900:
if (!(ncr_dev->status_ctrl & CTRL_DATA_DIR) && ncr_dev->buffer_host_pos < MIN(128, dev->buffer_length)) {
ncr_dev->buffer[ncr_dev->buffer_host_pos++] = val;
@@ -962,7 +962,7 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
if (ncr->mode & MODE_DMA)
ncr_timer_on(ncr_dev, ncr, 0);
if (ncr_dev->status_ctrl & CTRL_DATA_DIR) {
ncr_dev->buffer_host_pos = MIN(128, dev->buffer_length);
ncr_dev->status_ctrl |= STATUS_BUFFER_NOT_READY;
@@ -972,13 +972,13 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
}
break;
}
break;
break;
}
}
/* Memory-mapped I/O READ handler for the Trantor T130B. */
static uint8_t
static uint8_t
t130b_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -996,7 +996,7 @@ t130b_read(uint32_t addr, void *priv)
/* Memory-mapped I/O WRITE handler for the Trantor T130B. */
static void
static void
t130b_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -1008,7 +1008,7 @@ t130b_write(uint32_t addr, uint8_t val, void *priv)
}
static uint8_t
static uint8_t
t130b_in(uint16_t port, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -1021,8 +1021,8 @@ t130b_in(uint16_t port, void *priv)
case 0x04: case 0x05:
ret = memio_read(0x3900, ncr_dev);
break;
break;
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
ret = ncr_read(port, ncr_dev);
@@ -1034,7 +1034,7 @@ t130b_in(uint16_t port, void *priv)
}
static void
static void
t130b_out(uint16_t port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -1048,8 +1048,8 @@ t130b_out(uint16_t port, uint8_t val, void *priv)
case 0x04: case 0x05:
memio_write(0x3900, val, ncr_dev);
break;
break;
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
ncr_write(port, val, ncr_dev);
@@ -1062,7 +1062,7 @@ ncr_dma_send(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
{
int bus, c = 0;
uint8_t data;
if (scsi_device_get_callback(dev) > 0.0)
ncr_timer_on(ncr_dev, ncr, 1);
else
@@ -1147,7 +1147,7 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
} else {
ncr_timer_on(ncr_dev, ncr, 0);
}
for (c = 0; c < 10; c++) {
ncr_bus_read(ncr_dev);
if (ncr->cur_bus & BUS_REQ)
@@ -1162,9 +1162,9 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
ncr_bus_update(ncr_dev, bus | BUS_ACK);
ncr_bus_update(ncr_dev, bus & ~BUS_ACK);
if (ncr_dev->type == 3) {
ncr_dev->t128.buffer[ncr_dev->t128.pos++] = temp;
ncr_dev->t128.buffer[ncr_dev->t128.pos++] = temp;
ncr_log("Buffer pos for reading = %d, temp = %02x\n", ncr_dev->t128.pos, temp);
if (ncr_dev->t128.pos == MIN(512, dev->buffer_length)) {
@@ -1186,10 +1186,10 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
return;
}
} else {
ncr_dev->buffer[ncr_dev->buffer_pos++] = temp;
ncr_dev->buffer[ncr_dev->buffer_pos++] = temp;
ncr_log("Buffer pos for reading = %d\n", ncr_dev->buffer_pos);
if (ncr_dev->buffer_pos == MIN(128, dev->buffer_length)) {
if (ncr_dev->buffer_pos == MIN(128, dev->buffer_length)) {
ncr_dev->buffer_pos = 0;
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
@@ -1249,7 +1249,7 @@ ncr_callback(void *priv)
ncr_log("DMA_SEND with DMA direction set wrong\n");
break;
}
if (!(ncr_dev->status_ctrl & STATUS_BUFFER_NOT_READY)) {
ncr_log("Write buffer status ready\n");
break;
@@ -1262,7 +1262,7 @@ ncr_callback(void *priv)
ncr_log("Write status busy\n");
break;
}
if (!ncr_dev->t128.block_loaded) {
ncr_log("Write block not loaded\n");
break;
@@ -1293,12 +1293,12 @@ ncr_callback(void *priv)
ncr_log("Read status busy, block count = %i, host pos = %i\n", ncr_dev->t128.block_count, ncr_dev->t128.host_pos);
break;
}
if (!ncr_dev->t128.block_loaded) {
ncr_log("Read block not loaded\n");
break;
}
if (ncr_dev->t128.host_pos < MIN(512, dev->buffer_length))
break;
}
@@ -1316,7 +1316,7 @@ ncr_callback(void *priv)
}
}
static uint8_t
static uint8_t
t128_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
@@ -1329,7 +1329,7 @@ t128_read(uint32_t addr, void *priv)
ret = ncr_dev->bios_rom.rom[addr & 0x1fff];
else if (addr >= 0x1800 && addr < 0x1880)
ret = ncr_dev->t128.ext_ram[addr & 0x7f];
else if (addr >= 0x1c00 && addr < 0x1c20) {
else if (addr >= 0x1c00 && addr < 0x1c20) {
ret = ncr_dev->t128.ctrl;
} else if (addr >= 0x1c20 && addr < 0x1c40) {
ret = ncr_dev->t128.status;
@@ -1358,7 +1358,7 @@ t128_read(uint32_t addr, void *priv)
ret = ncr_dev->t128.buffer[ncr_dev->t128.host_pos++];
ncr_log("Read transfer, addr = %i, pos = %i\n", addr & 0x1ff, ncr_dev->t128.host_pos);
if (ncr_dev->t128.host_pos == MIN(512, dev->buffer_length)) {
ncr_dev->t128.status &= ~0x04;
ncr_log("Transfer busy read, status = %02x, period = %lf\n", ncr_dev->t128.status, ncr_dev->period);
@@ -1368,17 +1368,17 @@ t128_read(uint32_t addr, void *priv)
cycles += 100; /*Needed to avoid timer de-syncing with transfers.*/
}
}
return(ret);
}
static void
static void
t128_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
addr &= 0x3fff;
if (addr >= 0x1800 && addr < 0x1880)
ncr_dev->t128.ext_ram[addr & 0x7f] = val;
@@ -1444,7 +1444,7 @@ ncr_init(const device_t *info)
rom_init(&ncr_dev->bios_rom, LCS6821N_ROM,
ncr_dev->rom_addr, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
memio_read, NULL, NULL,
memio_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
@@ -1454,16 +1454,16 @@ ncr_init(const device_t *info)
ncr_dev->rom_addr = device_get_config_hex20("bios_addr");
ncr_dev->irq = device_get_config_int("irq");
ncr_dev->bios_ver = device_get_config_int("bios_ver");
if (ncr_dev->bios_ver == 1)
fn = RT1000B_820R_ROM;
else
fn = RT1000B_810R_ROM;
rom_init(&ncr_dev->bios_rom, fn,
ncr_dev->rom_addr, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
memio_read, NULL, NULL,
memio_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
@@ -1478,7 +1478,7 @@ ncr_init(const device_t *info)
rom_init(&ncr_dev->bios_rom, T130B_ROM,
ncr_dev->rom_addr, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
t130b_read, NULL, NULL,
t130b_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
@@ -1492,12 +1492,12 @@ ncr_init(const device_t *info)
ncr_dev->rom_addr = device_get_config_hex20("bios_addr");
ncr_dev->irq = device_get_config_int("irq");
ncr_dev->t128.bios_enabled = device_get_config_int("boot");
if (ncr_dev->t128.bios_enabled)
rom_init(&ncr_dev->bios_rom, T128_ROM,
ncr_dev->rom_addr, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
mem_mapping_add(&ncr_dev->mapping, ncr_dev->rom_addr, 0x4000,
t128_read, NULL, NULL,
t128_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
@@ -1518,7 +1518,7 @@ ncr_init(const device_t *info)
} else {
ncr_dev->t128.status = 0x04;
ncr_dev->t128.host_pos = 512;
if (!ncr_dev->t128.bios_enabled)
ncr_dev->t128.status |= 0x80;
}
@@ -1528,7 +1528,7 @@ ncr_init(const device_t *info)
}
static void
static void
ncr_close(void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;

38
src/scsi/scsi_ncr53c8xx.c
View File

@@ -286,7 +286,7 @@ typedef struct {
ncr53c8xx_request *current;
int irq;
uint32_t dsa;
uint32_t temp;
uint32_t dnad;
@@ -640,11 +640,11 @@ ncr53c8xx_command_complete(void *priv, uint32_t status)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)priv;
int out;
out = (dev->sstat1 & PHASE_MASK) == PHASE_DO;
ncr53c8xx_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: Command complete status=%d\n", dev->current->tag, dev->current_lun, dev->last_command, (int)status);
dev->status = status;
dev->command_complete = 2;
dev->command_complete = 2;
if (dev->waiting && dev->dbc != 0) {
/* Raise phase mismatch for short transfers. */
ncr53c8xx_bad_phase(dev, out, PHASE_ST);
@@ -667,7 +667,7 @@ ncr53c8xx_do_dma(ncr53c8xx_t *dev, int out, uint8_t id)
ncr53c8xx_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: Device not present when attempting to do DMA\n", id, dev->current_lun, dev->last_command);
return;
}
if (!dev->current->dma_len) {
/* Wait until data is available. */
ncr53c8xx_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: DMA no data available\n", id, dev->current_lun, dev->last_command);
@@ -758,7 +758,7 @@ ncr53c8xx_do_command(ncr53c8xx_t *dev, uint8_t id)
ncr53c8xx_bad_selection(dev, id);
return 0;
}
dev->current = (ncr53c8xx_request*)malloc(sizeof(ncr53c8xx_request));
dev->current->tag = id;
@@ -1068,7 +1068,7 @@ again:
dev->dsps = addr;
dev->dcmd = insn >> 24;
dev->dsp += 8;
switch (insn >> 30) {
case 0: /* Block move. */
ncr53c8xx_log("00: Block move\n");
@@ -2002,7 +2002,7 @@ ncr53c8xx_io_readw(uint16_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
uint16_t val;
addr &= 0xff;
val = ncr53c8xx_reg_readb(dev, addr);
val |= ncr53c8xx_reg_readb(dev, addr + 1) << 8;
@@ -2015,7 +2015,7 @@ ncr53c8xx_io_readl(uint16_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
uint32_t val;
addr &= 0xff;
val = ncr53c8xx_reg_readb(dev, addr);
val |= ncr53c8xx_reg_readb(dev, addr + 1) << 8;
@@ -2036,7 +2036,7 @@ ncr53c8xx_io_writeb(uint16_t addr, uint8_t val, void *p)
static void
ncr53c8xx_io_writew(uint16_t addr, uint16_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
@@ -2120,7 +2120,7 @@ ncr53c8xx_mmio_readl(uint32_t addr, void *p)
val = ncr53c8xx_reg_readb(dev, addr);
val |= ncr53c8xx_reg_readb(dev, addr + 1) << 8;
val |= ncr53c8xx_reg_readb(dev, addr + 2) << 16;
val |= ncr53c8xx_reg_readb(dev, addr + 3) << 24;
val |= ncr53c8xx_reg_readb(dev, addr + 3) << 24;
return val;
}
@@ -2182,7 +2182,7 @@ ncr53c8xx_ram_readl(uint32_t addr, void *p)
val = ncr53c8xx_ram_readb(addr, p);
val |= ncr53c8xx_ram_readb(addr + 1, p) << 8;
val |= ncr53c8xx_ram_readb(addr + 2, p) << 16;
val |= ncr53c8xx_ram_readb(addr + 3, p) << 24;
val |= ncr53c8xx_ram_readb(addr + 3, p) << 24;
return val;
}
@@ -2392,7 +2392,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
return;
}
switch (addr)
switch (addr)
{
case 0x04:
valxor = (val & 0x57) ^ ncr53c8xx_pci_regs[addr];
@@ -2458,7 +2458,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
if (dev->MMIOBase != 0)
ncr53c8xx_mem_set_addr(dev, dev->MMIOBase);
}
return;
return;
case 0x19: case 0x1A: case 0x1B:
if (!dev->wide)
@@ -2478,7 +2478,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
if (dev->RAMBase != 0)
ncr53c8xx_ram_set_addr(dev, dev->RAMBase);
}
return;
return;
case 0x30: case 0x31: case 0x32: case 0x33:
if (dev->has_bios == 0)
@@ -2567,13 +2567,13 @@ ncr53c8xx_init(const device_t *info)
dev->wide = 0;
} else if (dev->chip == CHIP_815) {
dev->chip_rev = 0x04;
dev->nvr_path = "ncr53c815.nvr";
dev->nvr_path = "ncr53c815.nvr";
dev->wide = 0;
}
ncr53c8xx_pci_bar[0].addr_regs[0] = 1;
ncr53c8xx_pci_bar[1].addr_regs[0] = 0;
ncr53c8xx_pci_regs[0x04] = 3;
ncr53c8xx_pci_bar[1].addr_regs[0] = 0;
ncr53c8xx_pci_regs[0x04] = 3;
if (dev->has_bios == 2) {
ncr53c8xx_pci_bar[3].addr = 0xffff0000;
@@ -2595,7 +2595,7 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_ram_init(dev, 0x0ffff000);
ncr53c8xx_ram_disable(dev);
}
if (dev->has_bios)
ncr53c8xx_bios_disable(dev);
@@ -2613,7 +2613,7 @@ ncr53c8xx_init(const device_t *info)
}
static void
static void
ncr53c8xx_close(void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)priv;

168
src/scsi/scsi_pcscsi.c
View File

@@ -178,7 +178,7 @@ typedef struct {
int32_t xfer_counter;
int dma_enabled;
uint32_t buffer_pos;
uint32_t dma_regs[8];
uint32_t sbac;
@@ -186,18 +186,18 @@ typedef struct {
double period;
pc_timer_t timer;
int mca;
uint16_t Base;
uint8_t HostID, DmaChannel;
struct
{
uint8_t mode;
uint8_t status;
int pos;
} dma_86c01;
uint8_t pos_regs[8];
} esp_t;
@@ -364,7 +364,7 @@ esp_get_cmd(esp_t *dev, uint32_t maxlen)
{
uint8_t buf[ESP_CMDFIFO_SZ];
uint32_t dmalen, n;
dev->id = dev->wregs[ESP_WBUSID] & BUSID_DID;
if (dev->dma) {
dmalen = MIN(esp_get_tc(dev), maxlen);
@@ -410,20 +410,20 @@ esp_do_command_phase(esp_t *dev)
scsi_device_t *sd;
sd = &scsi_devices[dev->bus][dev->id];
sd->buffer_length = -1;
cmdlen = fifo8_num_used(&dev->cmdfifo);
if (!cmdlen)
return;
esp_fifo_pop_buf(&dev->cmdfifo, buf, cmdlen);
for (int i = 0; i < cmdlen; i++)
esp_log("CDB[%i] = %02x\n", i, buf[i]);
scsi_device_command_phase0(sd, buf);
dev->buffer_pos = 0;
dev->ti_size = sd->buffer_length;
dev->xfer_counter = sd->buffer_length;
@@ -445,7 +445,7 @@ esp_do_command_phase(esp_t *dev)
dev->rregs[ESP_RSTAT] |= STAT_DO;
esp_log("ESP Data Out\n");
dev->ti_size = -sd->buffer_length;
esp_timer_on(dev, sd, scsi_device_get_callback(sd));
esp_timer_on(dev, sd, scsi_device_get_callback(sd));
}
esp_log("ESP SCSI Start reading/writing\n");
esp_do_dma(dev, sd);
@@ -461,9 +461,9 @@ esp_do_command_phase(esp_t *dev)
} else
esp_pci_command_complete(dev, sd->status);
}
scsi_device_identify(sd, SCSI_LUN_USE_CDB);
dev->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
esp_raise_irq(dev);
}
@@ -473,13 +473,13 @@ esp_do_message_phase(esp_t *dev)
{
int len;
uint8_t message;
if (dev->cmdfifo_cdb_offset) {
message = esp_fifo_pop(&dev->cmdfifo);
dev->lun = message & 7;
dev->cmdfifo_cdb_offset--;
if (scsi_device_present(&scsi_devices[dev->bus][dev->id]) && (dev->lun > 0)) {
/* We only support LUN 0 */
esp_log("LUN = %i\n", dev->lun);
@@ -490,10 +490,10 @@ esp_do_message_phase(esp_t *dev)
fifo8_reset(&dev->cmdfifo);
return;
}
scsi_device_identify(&scsi_devices[dev->bus][dev->id], dev->lun);
}
}
esp_log("CDB offset = %i\n", dev->cmdfifo_cdb_offset);
if (dev->cmdfifo_cdb_offset) {
@@ -557,13 +557,13 @@ esp_do_nodma(esp_t *dev, scsi_device_t *sd)
if (dev->do_cmd) {
esp_log("ESP Command on FIFO\n");
dev->ti_size = 0;
if ((dev->rregs[ESP_RSTAT] & 7) == STAT_CD) {
if (dev->cmdfifo_cdb_offset == fifo8_num_used(&dev->cmdfifo)) {
esp_log("CDB offset = %i used return\n", dev->cmdfifo_cdb_offset);
return;
}
dev->do_cmd = 0;
esp_do_cmd(dev);
} else {
@@ -600,13 +600,13 @@ esp_do_nodma(esp_t *dev, scsi_device_t *sd)
dev->ti_size += count;
dev->xfer_counter -= count;
}
esp_log("ESP FIFO Transfer bytes = %d\n", dev->xfer_counter);
if (dev->xfer_counter <= 0) {
if (sd->phase == SCSI_PHASE_DATA_OUT) {
if (dev->ti_size < 0) {
esp_log("ESP FIFO Keep writing\n");
esp_do_nodma(dev, sd);
esp_do_nodma(dev, sd);
} else {
esp_log("ESP FIFO Write finished\n");
scsi_device_command_phase1(sd);
@@ -661,9 +661,9 @@ esp_do_dma(esp_t *dev, scsi_device_t *sd)
} else {
esp_log("ESP SCSI device found on ID %d, LUN %d\n", dev->id, dev->lun);
}
count = tdbc = esp_get_tc(dev);
if (dev->mca) { /*See the comment in the esp_do_busid_cmd() function.*/
if (sd->buffer_length < 0) {
if (dev->dma_enabled)
@@ -686,11 +686,11 @@ esp_do_dma(esp_t *dev, scsi_device_t *sd)
esp_pci_dma_memory_rw(dev, buf, count, READ_FROM_DEVICE);
fifo8_push_all(&dev->cmdfifo, buf, count);
dev->ti_size = 0;
if ((dev->rregs[ESP_RSTAT] & 7) == STAT_CD) {
if (dev->cmdfifo_cdb_offset == fifo8_num_used(&dev->cmdfifo))
return;
dev->do_cmd = 0;
esp_do_cmd(dev);
} else {
@@ -711,7 +711,7 @@ esp_do_dma(esp_t *dev, scsi_device_t *sd)
}
esp_log("ESP SCSI dmaleft = %d, async_len = %i, buffer length = %d\n", esp_get_tc(dev), sd->buffer_length);
/* Make sure count is never bigger than buffer_length. */
if (count > dev->xfer_counter)
count = dev->xfer_counter;
@@ -739,7 +739,7 @@ esp_do_dma(esp_t *dev, scsi_device_t *sd)
}
dev->dma_86c01.pos = 0;
} else
esp_pci_dma_memory_rw(dev, sd->sc->temp_buffer + dev->buffer_pos, count, WRITE_TO_DEVICE);
esp_pci_dma_memory_rw(dev, sd->sc->temp_buffer + dev->buffer_pos, count, WRITE_TO_DEVICE);
}
esp_set_tc(dev, esp_get_tc(dev) - count);
dev->buffer_pos += count;
@@ -749,13 +749,13 @@ esp_do_dma(esp_t *dev, scsi_device_t *sd)
} else if (sd->phase == SCSI_PHASE_DATA_OUT) {
dev->ti_size += count;
}
esp_log("ESP SCSI Transfer bytes = %d\n", dev->xfer_counter);
if (dev->xfer_counter <= 0) {
if (sd->phase == SCSI_PHASE_DATA_OUT) {
if (dev->ti_size < 0) {
esp_log("ESP SCSI Keep writing\n");
esp_do_dma(dev, sd);
esp_do_dma(dev, sd);
} else {
esp_log("ESP SCSI Write finished\n");
scsi_device_command_phase1(sd);
@@ -783,7 +783,7 @@ done:
}
} else {
/* Partially filled a scsi buffer. Complete immediately. */
partial:
partial:
esp_log("ESP SCSI Partially filled the SCSI buffer\n");
esp_dma_done(dev);
}
@@ -794,7 +794,7 @@ static void
esp_report_command_complete(esp_t *dev, uint32_t status)
{
esp_log("ESP Command complete\n");
dev->ti_size = 0;
dev->status = status;
dev->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
@@ -814,7 +814,7 @@ static void
esp_pci_command_complete(void *priv, uint32_t status)
{
esp_t *dev = (esp_t *)priv;
esp_command_complete(dev, status);
dev->dma_regs[DMA_WBC] = 0;
dev->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
@@ -916,7 +916,7 @@ static void
esp_write_response(esp_t *dev)
{
uint8_t buf[2];
buf[0] = dev->status;
buf[1] = 0;
@@ -927,7 +927,7 @@ esp_write_response(esp_t *dev)
buf[dev->dma_86c01.pos++] = val & 0xff;
}
dev->dma_86c01.pos = 0;
} else
} else
esp_pci_dma_memory_rw(dev, buf, 2, WRITE_TO_DEVICE);
dev->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
dev->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
@@ -952,7 +952,7 @@ esp_callback(void *p)
handle_ti(dev);
}
}
esp_log("ESP DMA activated = %d, CMD activated = %d\n", dev->dma_enabled, dev->do_cmd);
}
@@ -975,7 +975,7 @@ esp_reg_read(esp_t *dev, uint32_t saddr)
dev->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
}
}
dev->rregs[ESP_FIFO] = esp_fifo_pop(&dev->fifo);
ret = dev->rregs[ESP_FIFO];
break;
@@ -1003,7 +1003,7 @@ esp_reg_read(esp_t *dev, uint32_t saddr)
default:
ret = dev->rregs[saddr];
break;
}
esp_log("Read reg %02x = %02x\n", saddr, ret);
return ret;
@@ -1073,7 +1073,7 @@ esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
break;
case CMD_BUSRESET:
if (!(dev->wregs[ESP_CFG1] & CFG1_RESREPT)) {
dev->rregs[ESP_RINTR] |= INTR_RST;
dev->rregs[ESP_RINTR] |= INTR_RST;
esp_log("ESP Bus Reset with IRQ\n");
esp_raise_irq(dev);
}
@@ -1175,15 +1175,15 @@ esp_pci_dma_memory_rw(esp_t *dev, uint8_t *buf, uint32_t len, int dir)
dev->dma_regs[DMA_WAC] += len;
if (dev->dma_regs[DMA_WBC] == 0)
dev->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
}
}
static uint32_t
esp_pci_dma_read(esp_t *dev, uint16_t saddr)
esp_pci_dma_read(esp_t *dev, uint16_t saddr)
{
uint32_t ret;
ret = dev->dma_regs[saddr];
if (saddr == DMA_STAT) {
if (dev->rregs[ESP_RSTAT] & STAT_INT) {
ret |= DMA_STAT_SCSIINT;
@@ -1195,7 +1195,7 @@ esp_pci_dma_read(esp_t *dev, uint16_t saddr)
esp_log("ESP PCI DMA Read done cleared\n");
}
}
esp_log("ESP PCI DMA Read regs addr = %04x, temp = %06x\n", saddr, ret);
return ret;
}
@@ -1203,8 +1203,8 @@ esp_pci_dma_read(esp_t *dev, uint16_t saddr)
static void
esp_pci_dma_write(esp_t *dev, uint16_t saddr, uint32_t val)
{
uint32_t mask;
uint32_t mask;
switch (saddr) {
case DMA_CMD:
dev->dma_regs[saddr] = val;
@@ -1268,12 +1268,12 @@ esp_pci_hard_reset(esp_t *dev)
}
static uint32_t
esp_io_pci_read(esp_t *dev, uint32_t addr, unsigned int size)
esp_io_pci_read(esp_t *dev, uint32_t addr, unsigned int size)
{
uint32_t ret;
addr &= 0x7f;
if (addr < 0x40) {
/* SCSI core reg */
ret = esp_reg_read(dev, addr >> 2);
@@ -1289,18 +1289,18 @@ esp_io_pci_read(esp_t *dev, uint32_t addr, unsigned int size)
/* Invalid region */
ret = 0;
}
/* give only requested data */
ret >>= (addr & 3) * 8;
ret &= ~(~(uint64_t)0 << (8 * size));
ret &= ~(~(uint64_t)0 << (8 * size));
esp_log("ESP PCI I/O read: addr = %02x, val = %02x\n", addr, ret);
return ret;
}
static void
esp_io_pci_write(esp_t *dev, uint32_t addr, uint32_t val, unsigned int size)
{
esp_io_pci_write(esp_t *dev, uint32_t addr, uint32_t val, unsigned int size)
{
uint32_t current, mask;
int shift;
@@ -1450,10 +1450,10 @@ dc390_write_eeprom(esp_t *dev, int ena, int clk, int dat)
uint8_t eedo = eeprom->out;
uint16_t address = eeprom->address;
uint8_t command = eeprom->opcode;
esp_log("EEPROM CS=%02x,SK=%02x,DI=%02x,DO=%02x,tick=%d\n",
ena, clk, dat, eedo, tick);
if (!eeprom->oldena && ena) {
esp_log("EEPROM Start chip select cycle\n");
tick = 0;
@@ -1466,7 +1466,7 @@ dc390_write_eeprom(esp_t *dev, int ena, int clk, int dat)
esp_log("EEPROM Erase All\n");
for (address = 0; address < 64; address++)
eeprom->data[address] = 0xffff;
dc390_save_eeprom(dev);
dc390_save_eeprom(dev);
} else if (command == 3) {
esp_log("EEPROM Erase Word\n");
eeprom->data[address] = 0xffff;
@@ -1480,7 +1480,7 @@ dc390_write_eeprom(esp_t *dev, int ena, int clk, int dat)
esp_log("EEPROM Write All\n");
for (address = 0; address < 64; address++)
eeprom->data[address] &= eeprom->dat;
dc390_save_eeprom(dev);
dc390_save_eeprom(dev);
}
}
}
@@ -1550,7 +1550,7 @@ dc390_write_eeprom(esp_t *dev, int ena, int clk, int dat)
esp_log("EEPROM Additional unneeded tick, not processed\n");
}
}
eeprom->count = tick;
eeprom->oldena = ena;
eeprom->oldclk = clk;
@@ -1582,9 +1582,9 @@ dc390_load_eeprom(esp_t *dev)
nvr[i * 2] = 0x57;
nvr[i * 2 + 1] = 0x00;
}
esp_log("EEPROM Defaults\n");
nvr[EE_ADAPT_SCSI_ID] = 7;
nvr[EE_MODE2] = 0x0f;
nvr[EE_TAG_CMD_NUM] = 0x04;
@@ -1595,12 +1595,12 @@ dc390_load_eeprom(esp_t *dev)
checksum += ((nvr[i] & 0xff) | (nvr[i + 1] << 8));
esp_log("Checksum calc = %04x, nvr = %02x\n", checksum, nvr[i]);
}
checksum = 0x1234 - checksum;
nvr[EE_CHKSUM1] = checksum & 0xff;
nvr[EE_CHKSUM2] = checksum >> 8;
esp_log("EEPROM Checksum = %04x\n", checksum);
}
}
}
uint8_t esp_pci_regs[256];
@@ -1759,7 +1759,7 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
dev->irq = val;
esp_log("ESP IRQ now: %i\n", val);
return;
case 0x40 ... 0x4f:
esp_pci_regs[addr] = val;
return;
@@ -1775,12 +1775,12 @@ dc390_init(const device_t *info)
memset(dev, 0x00, sizeof(esp_t));
dev->bus = scsi_get_bus();
dev->mca = 0;
fifo8_create(&dev->fifo, ESP_FIFO_SZ);
fifo8_create(&dev->cmdfifo, ESP_CMDFIFO_SZ);
fifo8_create(&dev->cmdfifo, ESP_CMDFIFO_SZ);
dev->PCIBase = 0;
dev->MMIOBase = 0;
@@ -1820,9 +1820,9 @@ ncr53c90_in(uint16_t port, void *priv)
{
esp_t *dev = (esp_t *)priv;
uint16_t ret = 0;
port &= 0x1f;
if (port >= 0x10)
ret = esp_reg_read(dev, port - 0x10);
else {
@@ -1830,15 +1830,15 @@ ncr53c90_in(uint16_t port, void *priv)
case 0x02:
ret = dev->dma_86c01.mode;
break;
case 0x0c:
ret = dev->dma_86c01.status;
break;
}
}
esp_log("[%04X:%08X]: NCR53c90 DMA read port = %02x, ret = %02x\n", CS, cpu_state.pc, port, ret);
esp_log("[%04X:%08X]: NCR53c90 DMA read port = %02x, ret = %02x\n", CS, cpu_state.pc, port, ret);
return ret;
}
@@ -1861,7 +1861,7 @@ ncr53c90_out(uint16_t port, uint16_t val, void *priv)
port &= 0x1f;
esp_log("[%04X:%08X]: NCR53c90 DMA write port = %02x, val = %02x\n", CS, cpu_state.pc, port, val);
esp_log("[%04X:%08X]: NCR53c90 DMA write port = %02x, val = %02x\n", CS, cpu_state.pc, port, val);
if (port >= 0x10)
esp_reg_write(dev, port - 0x10, val);
@@ -1909,7 +1909,7 @@ ncr53c90_mca_write(int port, uint8_t val, void *priv)
dev->pos_regs[port & 7] = val;
/* This is always necessary so that the old handler doesn't remain. */
if (dev->Base != 0) {
if (dev->Base != 0) {
io_removehandler(dev->Base, 0x20,
ncr53c90_inb, ncr53c90_inw, NULL,
ncr53c90_outb, ncr53c90_outw, NULL, dev);
@@ -1922,8 +1922,8 @@ ncr53c90_mca_write(int port, uint8_t val, void *priv)
dev->irq = 3 + (2 * ((dev->pos_regs[2] & 0x30) >> 4));
if (dev->irq == 9)
dev->irq = 2;
dev->DmaChannel = dev->pos_regs[3] & 0x0f;
dev->DmaChannel = dev->pos_regs[3] & 0x0f;
/*
* Get misc SCSI config stuff. For now, we are only
@@ -1967,14 +1967,14 @@ ncr53c90_mca_init(const device_t *info)
memset(dev, 0x00, sizeof(esp_t));
dev->bus = scsi_get_bus();
dev->mca = 1;
fifo8_create(&dev->fifo, ESP_FIFO_SZ);
fifo8_create(&dev->cmdfifo, ESP_CMDFIFO_SZ);
dev->pos_regs[0] = 0x4d; /* MCA board ID */
dev->pos_regs[1] = 0x7f;
dev->pos_regs[1] = 0x7f;
mca_add(ncr53c90_mca_read, ncr53c90_mca_write, ncr53c90_mca_feedb, NULL, dev);
esp_hard_reset(dev);
@@ -1984,15 +1984,15 @@ ncr53c90_mca_init(const device_t *info)
return(dev);
}
static void
static void
esp_close(void *priv)
{
esp_t *dev = (esp_t *)priv;
if (dev) {
fifo8_destroy(&dev->fifo);
fifo8_destroy(&dev->cmdfifo);
fifo8_destroy(&dev->cmdfifo);
free(dev);
dev = NULL;
}

134
src/scsi/scsi_spock.c
View File

@@ -101,26 +101,26 @@ typedef struct {
typedef struct {
rom_t bios_rom;
int bios_ver;
int irq, irq_inactive;
uint8_t pos_regs[8];
uint8_t basic_ctrl;
uint32_t command;
uint8_t attention,
attention_pending;
int attention_wait;
uint8_t cir[4],
cir_pending[4];
uint8_t irq_status;
uint32_t scb_addr;
uint8_t status;
get_complete_stat_t get_complete_stat;
@@ -153,16 +153,16 @@ typedef struct {
int irq_requests[SCSI_ID_MAX];
pc_timer_t callback_timer;
int cmd_timer;
int scb_state;
int in_reset;
int in_invalid;
uint64_t temp_period;
double media_period;
scsi_state_t scsi_state;
} spock_t;
@@ -265,7 +265,7 @@ spock_rethink_irqs(spock_t *scsi)
}
}
static __inline void
static __inline void
spock_set_irq(spock_t *scsi, int id, int type)
{
spock_log("spock_set_irq id=%i type=%x %02x\n", id, type, scsi->irq_status);
@@ -274,7 +274,7 @@ spock_set_irq(spock_t *scsi, int id, int type)
spock_rethink_irqs(scsi);
}
static __inline void
static __inline void
spock_clear_irq(spock_t *scsi, int id)
{
spock_log("spock_clear_irq id=%i\n", id);
@@ -294,7 +294,7 @@ spock_write(uint16_t port, uint8_t val, void *p)
spock_t *scsi = (spock_t *)p;
spock_log("spock_write: port=%04x val=%02x %04x:%04x\n", port, val, CS, cpu_state.pc);
switch (port & 7) {
case 0: case 1: case 2: case 3: /*Command Interface Register*/
scsi->cir_pending[port & 3] = val;
@@ -309,7 +309,7 @@ spock_write(uint16_t port, uint8_t val, void *p)
scsi->attention_wait = 2;
scsi->status |= STATUS_BUSY;
break;
case 5: /*Basic Control Register*/
if ((scsi->basic_ctrl & CTRL_RESET) && !(val & CTRL_RESET)) {
spock_log("Spock: SCSI reset and busy\n");
@@ -350,7 +350,7 @@ spock_read(uint16_t port, void *p)
{
spock_t *scsi = (spock_t *)p;
uint8_t temp = 0xff;
switch (port & 7) {
case 0: case 1: case 2: case 3: /*Command Interface Register*/
temp = scsi->cir_pending[port & 3];
@@ -378,9 +378,9 @@ spock_read(uint16_t port, void *p)
}
break;
}
spock_log("spock_read: port=%04x val=%02x %04x(%05x):%04x %02x\n", port, temp, CS, cs, cpu_state.pc, BH);
return temp;
return temp;
}
static uint16_t
@@ -397,9 +397,9 @@ spock_readw(uint16_t port, void *p)
temp = scsi->cir_pending[2] | (scsi->cir_pending[3] << 8);
break;
}
spock_log("spock_readw: port=%04x val=%04x\n", port, temp);
return temp;
return temp;
}
static void
@@ -423,7 +423,7 @@ spock_get_len(spock_t *scsi, scb_t *scb)
if (scb->enable & ENABLE_PT) {
for (i = 0; i < scsi->data_len; i += 8) {
spock_rd_sge(scsi, scsi->data_ptr + i, &scb->sge);
DataToTransfer += scb->sge.sys_buf_byte_count;
}
return(DataToTransfer);
@@ -437,13 +437,13 @@ spock_process_imm_cmd(spock_t *scsi)
{
int i;
int adapter_id, phys_id, lun_id;
switch (scsi->command & CMD_MASK) {
case CMD_ASSIGN:
adapter_id = (scsi->command >> 16) & 15;
phys_id = (scsi->command >> 20) & 7;
lun_id = (scsi->command >> 24) & 7;
if (adapter_id == 15) {
if (phys_id == 7) /*Device 15 always adapter*/
spock_set_irq(scsi, scsi->attention & 0x0f, IRQ_TYPE_IMM_CMD_COMPLETE);
@@ -490,13 +490,13 @@ spock_process_imm_cmd(spock_t *scsi)
for (i = 0; i < 8; i++)
scsi_device_reset(&scsi_devices[scsi->bus][i]);
spock_log("Adapter Reset\n");
if (!scsi->adapter_reset && scsi->bios_ver) /*The early 1990 bios must have its boot drive
set to ID 6 according https://www.ardent-tool.com/IBM_SCSI/SCSI-A.html */
scsi->adapter_reset = 1;
else
scsi->adapter_reset = 0;
scsi->scb_state = 0;
}
spock_set_irq(scsi, scsi->attention & 0x0f, IRQ_TYPE_IMM_CMD_COMPLETE);
@@ -540,24 +540,24 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->in_reset = 0;
return;
}
if (scsi->in_invalid) {
spock_log("Invalid command\n");
spock_set_irq(scsi, scsi->attention & 0x0f, IRQ_TYPE_COMMAND_ERROR);
scsi->in_invalid = 0;
return;
}
spock_log("SCB State = %d\n", scsi->scb_state);
do
{
old_scb_state = scsi->scb_state;
switch (scsi->scb_state) {
case 0: /* Idle */
break;
case 1: /* Select */
if (scsi->dev_id[scsi->scb_id].phys_id == -1) {
uint16_t term_stat_block_addr7 = (0xe << 8) | 0;
@@ -570,7 +570,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
dma_bm_write(scb->term_status_block_addr + 0x8*2, (uint8_t *)&term_stat_block_addr8, 2, 2);
break;
}
dma_bm_read(scsi->scb_addr, (uint8_t *)&scb->command, 2, 2);
dma_bm_read(scsi->scb_addr + 2, (uint8_t *)&scb->enable, 2, 2);
dma_bm_read(scsi->scb_addr + 4, (uint8_t *)&scb->lba_addr, 4, 2);
@@ -596,13 +596,13 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scb->sge.sys_buf_addr, scb->sge.sys_buf_byte_count,
scb->term_status_block_addr, scb->scb_chain_addr,
scb->block_count, scb->block_length, scsi->scb_id);
switch (scb->command & CMD_MASK) {
case CMD_GET_COMPLETE_STATUS:
{
spock_log("Get Complete Status\n");
get_complete_stat_t *get_complete_stat = &scsi->get_complete_stat;
get_complete_stat->scb_status = 0x201;
get_complete_stat->retry_count = 0;
get_complete_stat->residual_byte_count = 0;
@@ -644,7 +644,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
{
spock_log("Get POS Info\n");
get_pos_info_t *get_pos_info = &scsi->get_pos_info;
get_pos_info->pos = 0x8eff;
get_pos_info->pos1 = scsi->pos_regs[3] | (scsi->pos_regs[2] << 8);
get_pos_info->pos2 = 0x0e | (scsi->pos_regs[4] << 8);
@@ -654,7 +654,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
get_pos_info->pos6 = (30 << 8) | 1;
get_pos_info->pos7 = 0;
get_pos_info->pos8 = 0;
dma_bm_write(scb->sge.sys_buf_addr, (uint8_t *)&get_pos_info->pos, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 2, (uint8_t *)&get_pos_info->pos1, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 4, (uint8_t *)&get_pos_info->pos2, 2, 2);
@@ -693,7 +693,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->cdb_id = scsi->scb_id;
} else {
scsi->cdb_id = scsi->dev_id[scsi->scb_id].phys_id;
}
}
spock_log("Send Other SCSI, ID=%d\n", scsi->cdb_id);
dma_bm_read(scsi->scb_addr + 0x18, scsi->cdb, 12, 2);
scsi->cdb[1] = (scsi->cdb[1] & 0x1f) | (scsi->dev_id[scsi->scb_id].lun_id << 5); /*Patch correct LUN into command*/
@@ -758,7 +758,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->scsi_state = SCSI_STATE_SELECT;
scsi->scb_state = 2;
return;
case CMD_VERIFY:
spock_log("Device Verify\n");
scsi->cdb[0] = GPCMD_VERIFY_10;
@@ -777,7 +777,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->scsi_state = SCSI_STATE_SELECT;
scsi->scb_state = 2;
return;
case CMD_REQUEST_SENSE:
if (scsi->adapter_reset)
scsi->cdb_id = scsi->scb_id;
@@ -796,7 +796,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
return;
}
break;
case 2: /* Wait */
if (scsi->scsi_state == SCSI_STATE_IDLE && scsi_device_present(&scsi_devices[scsi->bus][scsi->cdb_id])) {
if (scsi->last_status == SCSI_STATUS_OK) {
@@ -807,7 +807,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
uint16_t term_stat_block_addr8 = 0x20;
uint16_t term_stat_block_addrb = scsi->scb_addr & 0xffff;
uint16_t term_stat_block_addrc = scsi->scb_addr >> 16;
spock_set_irq(scsi, scsi->scb_id, IRQ_TYPE_COMMAND_FAIL);
scsi->scb_state = 0;
spock_log("Status Check Condition on device ID %d\n", scsi->cdb_id);
@@ -825,7 +825,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
dma_bm_write(scb->term_status_block_addr + 0x8*2, (uint8_t *)&term_stat_block_addr8, 2, 2);
}
break;
case 3: /* Complete */
if (scb->enable & 1) {
scsi->scb_state = 1;
@@ -851,7 +851,7 @@ spock_process_scsi(spock_t *scsi, scb_t *scb)
switch (scsi->scsi_state) {
case SCSI_STATE_IDLE:
break;
case SCSI_STATE_SELECT:
spock_log("Selecting ID %d\n", scsi->cdb_id);
if ((scsi->cdb_id != (uint8_t)-1) && scsi_device_present(&scsi_devices[scsi->bus][scsi->cdb_id])) {
@@ -881,38 +881,38 @@ spock_process_scsi(spock_t *scsi, scb_t *scb)
12);
spock_add_to_period(scsi, 12);
}
scsi->data_ptr = scb->sge.sys_buf_addr;
scsi->data_len = scb->sge.sys_buf_byte_count;
if (scb->enable & 0x400)
sd->buffer_length = -1;
else
sd->buffer_length = spock_get_len(scsi, scb);
scsi_device_command_phase0(sd, scsi->temp_cdb);
spock_log("SCSI ID %i: Current CDB[0] = %02x, LUN = %i, data len = %i, max len = %i, phase val = %02x\n", scsi->cdb_id, scsi->temp_cdb[0], scsi->temp_cdb[1] >> 5, sd->buffer_length, spock_get_len(scsi, scb), sd->phase);
if (sd->phase != SCSI_PHASE_STATUS && sd->buffer_length > 0) {
p = scsi_device_get_callback(sd);
if (p <= 0.0)
spock_add_to_period(scsi, sd->buffer_length);
else
scsi->media_period += p;
if (scb->enable & ENABLE_PT) {
int32_t buflen = sd->buffer_length;
int sg_pos = 0;
uint32_t DataTx = 0;
uint32_t Address;
if (scb->sge.sys_buf_byte_count > 0) {
for (c = 0; c < scsi->data_len; c += 8) {
spock_rd_sge(scsi, scsi->data_ptr + c, &scb->sge);
Address = scb->sge.sys_buf_addr;
DataTx = MIN((int) scb->sge.sys_buf_byte_count, buflen);
if ((sd->phase == SCSI_PHASE_DATA_IN) && DataTx) {
spock_log("Writing S/G segment %i: length %i, pointer %08X\n", c, DataTx, Address);
dma_bm_write(Address, &sd->sc->temp_buffer[sg_pos], DataTx, 2);
@@ -920,10 +920,10 @@ spock_process_scsi(spock_t *scsi, scb_t *scb)
spock_log("Reading S/G segment %i: length %i, pointer %08X\n", c, DataTx, Address);
dma_bm_read(Address, &sd->sc->temp_buffer[sg_pos], DataTx, 2);
}
sg_pos += scb->sge.sys_buf_byte_count;
buflen -= scb->sge.sys_buf_byte_count;
if (buflen < 0)
buflen = 0;
}
@@ -967,7 +967,7 @@ spock_callback(void *priv)
if (scsi->cmd_timer) {
scsi->cmd_timer--;
if (!scsi->cmd_timer) {
spock_execute_cmd(scsi, scb);
spock_execute_cmd(scsi, scb);
}
}
@@ -982,7 +982,7 @@ spock_callback(void *priv)
scsi->cir[2] = scsi->cir_pending[2];
scsi->cir[3] = scsi->cir_pending[3];
scsi->cir_status = 0;
switch (scsi->attention >> 4) {
case 1: /*Immediate command*/
scsi->cmd_status = 0x0a;
@@ -997,7 +997,7 @@ spock_callback(void *priv)
break;
}
break;
case 3: case 4: case 0x0f: /*Start SCB*/
scsi->cmd_status = 1;
scsi->scb_addr = scsi->cir[0] | (scsi->cir[1] << 8) | (scsi->cir[2] << 16) | (scsi->cir[3] << 24);
@@ -1006,7 +1006,7 @@ spock_callback(void *priv)
spock_log("Start SCB at ID = %d\n", scsi->scb_id);
scsi->scb_state = 1;
break;
case 5: /*Invalid*/
case 0x0a: /*Invalid*/
scsi->in_invalid = 1;
@@ -1022,13 +1022,13 @@ spock_callback(void *priv)
}
spock_process_scsi(scsi, scb);
period = 0.2 * ((double) scsi->temp_period);
timer_on(&scsi->callback_timer, (scsi->media_period + period + 10.0), 0);
spock_log("Temporary period: %lf us (%" PRIi64 " periods)\n", scsi->callback_timer.period, scsi->temp_period);
}
static void
static void
spock_mca_write(int port, uint8_t val, void *priv)
{
spock_t *scsi = (spock_t *)priv;
@@ -1038,7 +1038,7 @@ spock_mca_write(int port, uint8_t val, void *priv)
io_removehandler((((scsi->pos_regs[2] >> 1) & 7) * 8) + 0x3540, 0x0008, spock_read, spock_readw, NULL, spock_write, spock_writew, NULL, scsi);
mem_mapping_disable(&scsi->bios_rom.mapping);
scsi->pos_regs[port & 7] = val;
scsi->adapter_id = (scsi->pos_regs[3] & 0xe0) >> 5;
@@ -1053,7 +1053,7 @@ spock_mca_write(int port, uint8_t val, void *priv)
}
}
static uint8_t
static uint8_t
spock_mca_read(int port, void *priv)
{
spock_t *scsi = (spock_t *)priv;
@@ -1074,7 +1074,7 @@ spock_mca_reset(void *priv)
{
spock_t *scsi = (spock_t *)priv;
int i;
scsi->in_reset = 2;
scsi->cmd_timer = SPOCK_TIME * 50;
scsi->status = STATUS_BUSY;
@@ -1087,7 +1087,7 @@ spock_mca_reset(void *priv)
/* Reset all devices on controller reset. */
for (i = 0; i < 8; i++)
scsi_device_reset(&scsi_devices[scsi->bus][i]);
scsi->adapter_reset = 0;
}
@@ -1101,9 +1101,9 @@ spock_init(const device_t *info)
scsi->bus = scsi_get_bus();
scsi->irq = 14;
scsi->bios_ver = device_get_config_int("bios_ver");
switch (scsi->bios_ver) {
case 1:
rom_init_interleaved(&scsi->bios_rom, SPOCK_U68_1991_ROM, SPOCK_U69_1991_ROM,
@@ -1128,28 +1128,28 @@ spock_init(const device_t *info)
for (c = 0; c < (SCSI_ID_MAX-1); c++) {
scsi->dev_id[c].phys_id = -1;
}
scsi->dev_id[SCSI_ID_MAX-1].phys_id = scsi->adapter_id;
timer_add(&scsi->callback_timer, spock_callback, scsi, 1);
scsi->callback_timer.period = 10.0;
timer_set_delay_u64(&scsi->callback_timer, (uint64_t) (scsi->callback_timer.period * ((double) TIMER_USEC)));
return scsi;
}
static void
static void
spock_close(void *p)
{
spock_t *scsi = (spock_t *)p;
if (scsi) {
free(scsi);
scsi = NULL;
}
}
static int
static int
spock_available(void)
{
return rom_present(SPOCK_U68_1991_ROM) && rom_present(SPOCK_U69_1991_ROM) &&

18
src/scsi/scsi_x54x.c
View File

@@ -545,7 +545,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
break;
}
x54x_log("BIOS Request %02X complete: %02X\n", cmd->command, ret);
return(ret);
}
@@ -622,7 +622,7 @@ x54x_ccb(x54x_t *dev)
static void
x54x_mbi(x54x_t *dev)
{
{
Req_t *req = &dev->Req;
// uint32_t CCBPointer = req->CCBPointer;
addr24 CCBPointer;
@@ -1073,7 +1073,7 @@ x54x_notify(x54x_t *dev)
static void
x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
{
{
Req_t *req = &dev->Req;
uint8_t id, lun;
scsi_device_t *sd;
@@ -1112,8 +1112,8 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
scsi_device_identify(sd, lun);
x54x_log("Transfer Control %02X\n", req->CmdBlock.common.ControlByte);
x54x_log("CDB Length %i\n", req->CmdBlock.common.CdbLength);
x54x_log("CCB Opcode %x\n", req->CmdBlock.common.Opcode);
x54x_log("CDB Length %i\n", req->CmdBlock.common.CdbLength);
x54x_log("CCB Opcode %x\n", req->CmdBlock.common.Opcode);
if ((req->CmdBlock.common.Opcode > 0x04) && (req->CmdBlock.common.Opcode != 0x81)) {
x54x_log("Invalid opcode: %02X\n",
req->CmdBlock.common.ControlByte);
@@ -1152,7 +1152,7 @@ x54x_req_abort(x54x_t *dev, uint32_t CCBPointer)
static uint32_t
x54x_mbo(x54x_t *dev, Mailbox32_t *Mailbox32)
{
{
Mailbox_t MailboxOut;
uint32_t Outgoing;
uint32_t ccbp;
@@ -1569,7 +1569,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
case CMD_ECHO:
case CMD_OPTIONS:
dev->CmdParamLeft = 1;
break;
break;
case CMD_SELTIMEOUT:
dev->CmdParamLeft = 4;
@@ -1593,7 +1593,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
if (dev->ven_cmd_phase1)
dev->ven_cmd_phase1(dev);
}
if (! dev->CmdParamLeft) {
x54x_log("Running Operation Code 0x%02X\n", dev->Command);
switch (dev->Command) {
@@ -1941,7 +1941,7 @@ x54x_init(const device_t *info)
dev->card_bus = info->flags;
dev->callback_phase = 0;
timer_add(&dev->ResetCB, x54x_reset_poll, dev, 0);
timer_add(&dev->timer, x54x_cmd_callback, dev, 1);
dev->timer.period = 10.0;