From 49463607c1b5825d7805fdc5abcdec9bb1ed4027 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 17 Mar 2025 04:29:58 +0100 Subject: [PATCH] C&T 69000: Rewrite the PCI register handling and intialize the registers to sane default, fixes the card's detection by the Windows 98 driver installer. --- src/video/vid_chips_69000.c | 248 +++++++++++++++++++++--------------- 1 file changed, 144 insertions(+), 104 deletions(-) diff --git a/src/video/vid_chips_69000.c b/src/video/vid_chips_69000.c index b0e8db35a..c17fe2004 100644 --- a/src/video/vid_chips_69000.c +++ b/src/video/vid_chips_69000.c @@ -107,6 +107,7 @@ typedef struct chips_69000_t { uint8_t mm_regs[256], mm_index; uint8_t flat_panel_regs[256], flat_panel_index; uint8_t ext_regs[256], ext_index; + uint8_t pci_regs[256]; union { uint32_t mem_regs[4]; @@ -2156,57 +2157,74 @@ static uint8_t chips_69000_pci_read(UNUSED(int func), int addr, void *priv) { chips_69000_t *chips = (chips_69000_t *) priv; + uint8_t ret = 0x00; - { - switch (addr) { - case 0x00: - return 0x2C; - case 0x01: - return 0x10; - case 0x02: - return 0xC0; - case 0x03: - return 0x00; - case 0x04: - return (chips->pci_conf_status & 0b11100011) | 0x80; - case 0x06: - return 0x80; - case 0x07: - return 0x02; - case 0x08: - case 0x09: - case 0x0a: - return 0x00; - case 0x0b: - return 0x03; - case 0x13: - return chips->linear_mapping.base >> 24; - case 0x30: - return chips->pci_rom_enable & 0x1; - case 0x31: - return 0x0; - case 0x32: - return chips->rom_addr & 0xFF; - case 0x33: - return (chips->rom_addr & 0xFF00) >> 8; - case 0x3c: - return chips->pci_line_interrupt; - case 0x3d: - return 0x01; - case 0x2C: - case 0x2D: - case 0x6C: - case 0x6D: - return (chips->subsys_vid >> ((addr & 1) * 8)) & 0xFF; - case 0x2E: - case 0x2F: - case 0x6E: - case 0x6F: - return (chips->subsys_pid >> ((addr & 1) * 8)) & 0xFF; - default: - return 0x00; - } + switch (addr) { + case 0x00: + ret = 0x2c; + break; + case 0x01: + ret = 0x10; + break; + case 0x02: + ret = 0xc0; + break; + case 0x03: + ret = 0x00; + break; + + case 0x04: + ret = (chips->pci_conf_status & 0x73) | 0x80; + break; + case 0x05: + ret = chips->pci_regs[addr] & 0x01; + break; + case 0x06: + ret = 0x80; + break; + case 0x07: + ret = chips->pci_regs[addr] | 0x02; + break; + + case 0x0b: + ret = 0x03; + break; + + case 0x13: + ret = chips->linear_mapping.base >> 24; + break; + + case 0x2c ... 0x2d: + case 0x6c ... 0x6d: + ret = chips->subsys_vid_b[addr & 1]; + break; + case 0x2e ... 0x2f: + case 0x6e ... 0x6f: + ret = chips->subsys_pid_b[addr & 1]; + break; + + case 0x30: + ret = chips->pci_rom_enable & 0x1; + break; + case 0x32: + ret = chips->rom_addr & 0xff; + break; + case 0x33: + ret = (chips->rom_addr & 0xff00) >> 8; + break; + + case 0x3c: + ret = chips->pci_line_interrupt; + break; + case 0x3d: + ret = 0x01; + break; + + default: + break; } + + return ret; } static void @@ -2214,67 +2232,77 @@ chips_69000_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) { chips_69000_t *chips = (chips_69000_t *) priv; - { - switch (addr) { - case 0x04: - { - chips->pci_conf_status = val; - io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); - mem_mapping_disable(&chips->linear_mapping); - mem_mapping_disable(&chips->svga.mapping); - if (chips->pci_conf_status & PCI_COMMAND_IO) { - io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); - } - if (chips->pci_conf_status & PCI_COMMAND_MEM) { - mem_mapping_enable(&chips->svga.mapping); - if (chips->linear_mapping.base) - mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); - } - break; - } - case 0x13: - { - chips->linear_mapping.base = val << 24; - if (chips->linear_mapping.base) - mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); - break; - } - case 0x3c: - chips->pci_line_interrupt = val; - break; - case 0x30: - if (chips->on_board) break; + switch (addr) { + case 0x04: + chips->pci_conf_status = val; + io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); + mem_mapping_disable(&chips->linear_mapping); + mem_mapping_disable(&chips->svga.mapping); + if (!chips->on_board) + mem_mapping_disable(&chips->bios_rom.mapping); + if (val & PCI_COMMAND_IO) + io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); + if (val & PCI_COMMAND_MEM) { + if (!chips->on_board && (chips->pci_rom_enable & 1)) + mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); + mem_mapping_enable(&chips->svga.mapping); + if (chips->linear_mapping.base > 0x00000000) + mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); + } + break; + case 0x05: + chips->pci_regs[addr] = val & 0x01; + break; + case 0x07: + chips->pci_regs[addr] &= ~(val & 0xc8); + break; + + case 0x13: + chips->linear_mapping.base = val << 24; + mem_mapping_disable(&chips->linear_mapping); + if ((chips->pci_conf_status & PCI_COMMAND_MEM) && + (chips->linear_mapping.base > 0x00000000)) + mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); + break; + + case 0x30: + if (!chips->on_board) { chips->pci_rom_enable = val & 0x1; mem_mapping_disable(&chips->bios_rom.mapping); - if (chips->pci_rom_enable & 1) { + if ((chips->pci_conf_status & PCI_COMMAND_MEM) && + (chips->pci_rom_enable & 1)) mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); - } - break; - case 0x32: - if (chips->on_board) break; - chips->rom_addr &= ~0xFF; - chips->rom_addr |= val & 0xFC; - if (chips->pci_rom_enable & 1) { + } + break; + case 0x32: + if (!chips->on_board) { + chips->rom_addr &= ~0xff; + chips->rom_addr |= val & 0xfc; + if ((chips->pci_conf_status & PCI_COMMAND_MEM) && + (chips->pci_rom_enable & 1)) mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); - } - break; - case 0x33: - if (chips->on_board) break; - chips->rom_addr &= ~0xFF00; + } + break; + case 0x33: + if (!chips->on_board) { + chips->rom_addr &= ~0xff00; chips->rom_addr |= (val << 8); - if (chips->pci_rom_enable & 1) { + if ((chips->pci_conf_status & PCI_COMMAND_MEM) && + (chips->pci_rom_enable & 1)) mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); - } - break; - case 0x6C: - case 0x6D: - chips->subsys_vid_b[addr & 1] = val; - break; - case 0x6E: - case 0x6F: - chips->subsys_pid_b[addr & 1] = val; - break; - } + } + break; + + case 0x3c: + chips->pci_line_interrupt = val; + break; + + case 0x6c ... 0x6d: + chips->subsys_vid_b[addr & 1] = val; + break; + case 0x6e ... 0x6f: + chips->subsys_pid_b[addr & 1] = val; + break; } } @@ -2839,6 +2867,18 @@ chips_69000_init(const device_t *info) chips->flat_panel_regs[0x01] = 1; + chips->pci_conf_status = 0x00; + chips->pci_rom_enable = 0x00; + chips->rom_addr = 0x0000; + chips->subsys_vid = 0x102c; + chips->subsys_pid = 0x00c0; + + io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); + mem_mapping_disable(&chips->linear_mapping); + mem_mapping_disable(&chips->svga.mapping); + if (!chips->on_board) + mem_mapping_disable(&chips->bios_rom.mapping); + *reset_state = *chips; return chips;