diff --git a/src/cpu/808x.c b/src/cpu/808x.c index 62c8395af..2e24d3c49 100644 --- a/src/cpu/808x.c +++ b/src/cpu/808x.c @@ -90,44 +90,44 @@ static bool cpu_md_write_disable = 1; #define fetch_ea_32(val) #define PREFETCH_RUN(a, b, c, d, e, f, g, h) -#define CYCLES(val) \ - { \ - wait(val, 0); \ +#define CYCLES(val) \ + { \ + wait_cycs(val, 0); \ } #define CLOCK_CYCLES_ALWAYS(val) \ { \ - wait(val, 0); \ + wait_cycs(val, 0); \ } #if 0 # define CLOCK_CYCLES_FPU(val) \ { \ - wait(val, 0); \ + wait_cycs(val, 0); \ } -# define CLOCK_CYCLES(val) \ - { \ - if (fpu_cycles > 0) { \ - fpu_cycles -= (val); \ - if (fpu_cycles < 0) { \ - wait(val, 0); \ - } \ - } else { \ - wait(val, 0); \ - } \ +# define CLOCK_CYCLES(val) \ + { \ + if (fpu_cycles > 0) { \ + fpu_cycles -= (val); \ + if (fpu_cycles < 0) { \ + wait_cycs(val, 0); \ + } \ + } else { \ + wait_cycs(val, 0); \ + } \ } # define CONCURRENCY_CYCLES(c) fpu_cycles = (c) #else -# define CLOCK_CYCLES(val) \ - { \ - wait(val, 0); \ +# define CLOCK_CYCLES(val) \ + { \ + wait_cycs(val, 0); \ } # define CLOCK_CYCLES_FPU(val) \ { \ - wait(val, 0); \ + wait_cycs(val, 0); \ } # define CONCURRENCY_CYCLES(c) @@ -297,12 +297,8 @@ fetch_and_bus(int c, int bus) } } -#ifdef wait -#undef wait -#endif - static void -wait(int c, int bus) +wait_cycs(int c, int bus) { cycles -= c; fetch_and_bus(c, bus); @@ -344,13 +340,13 @@ cpu_io(int bits, int out, uint16_t port) int old_cycles = cycles; if (out) { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); if (bits == 16) { if (is8086 && !(port & 1)) { old_cycles = cycles; outw(port, AX); } else { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; outb(port++, AL); outb(port, AH); @@ -360,13 +356,13 @@ cpu_io(int bits, int out, uint16_t port) outb(port, AL); } } else { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); if (bits == 16) { if (is8086 && !(port & 1)) { old_cycles = cycles; AX = inw(port); } else { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; AL = inb(port++); AH = inb(port); @@ -386,7 +382,7 @@ readmemb(uint32_t a) { uint8_t ret; - wait(4, 1); + wait_cycs(4, 1); ret = read_mem_b(a); return ret; @@ -410,11 +406,11 @@ readmemw(uint32_t s, uint16_t a) { uint16_t ret; - wait(4, 1); + wait_cycs(4, 1); if (is8086 && !(a & 1)) ret = read_mem_w(s + a); else { - wait(4, 1); + wait_cycs(4, 1); ret = read_mem_b(s + a); ret |= read_mem_b(s + ((is186 && !is_nec) ? (a + 1) : (a + 1) & 0xffff)) << 8; } @@ -469,7 +465,7 @@ writememb(uint32_t s, uint32_t a, uint8_t v) { uint32_t addr = s + a; - wait(4, 1); + wait_cycs(4, 1); write_mem_b(addr, v); if ((addr >= 0xf0000) && (addr <= 0xfffff)) @@ -482,12 +478,12 @@ writememw(uint32_t s, uint32_t a, uint16_t v) { uint32_t addr = s + a; - wait(4, 1); + wait_cycs(4, 1); if (is8086 && !(a & 1)) write_mem_w(addr, v); else { write_mem_b(addr, v & 0xff); - wait(4, 1); + wait_cycs(4, 1); addr = s + ((is186 && !is_nec) ? (a + 1) : ((a + 1) & 0xffff)); write_mem_b(addr, v >> 8); } @@ -564,7 +560,7 @@ pfq_fetchb_common(void) /* Reset prefetch queue internal position. */ pfq_ip = cpu_state.pc; /* Fill the queue. */ - wait(4 - (biu_cycles & 3), 0); + wait_cycs(4 - (biu_cycles & 3), 0); } /* Fetch. */ @@ -578,7 +574,7 @@ pfq_fetchb(void) uint8_t ret; ret = pfq_fetchb_common(); - wait(1, 0); + wait_cycs(1, 0); return ret; } @@ -590,7 +586,7 @@ pfq_fetchw(void) uint16_t temp; temp = pfq_fetchb_common(); - wait(1, 0); + wait_cycs(1, 0); temp |= (pfq_fetchb_common() << 8); return temp; @@ -764,38 +760,38 @@ do_mod_rm(void) if (cpu_mod == 3) return; - wait(1, 0); + wait_cycs(1, 0); if ((rmdat & 0xc7) == 0x06) { - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = pfq_fetchw(); easeg = ovr_seg ? *ovr_seg : ds; - wait(1, 0); + wait_cycs(1, 0); return; } else switch (cpu_rm) { case 0: case 3: - wait(2, 0); + wait_cycs(2, 0); break; case 1: case 2: - wait(3, 0); + wait_cycs(3, 0); break; } cpu_state.eaaddr = (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]); easeg = ovr_seg ? *ovr_seg : *mod1seg[cpu_rm]; switch (rmdat & 0xc0) { case 0x40: - wait(3, 0); + wait_cycs(3, 0); cpu_state.eaaddr += sign_extend(pfq_fetchb()); break; case 0x80: - wait(3, 0); + wait_cycs(3, 0); cpu_state.eaaddr += pfq_fetchw(); break; } cpu_state.eaaddr &= 0xffff; - wait(2, 0); + wait_cycs(2, 0); } #undef getr8 @@ -987,7 +983,7 @@ access(int num, UNUSED(int bits)) case 62: case 66: case 68: - wait(1, 0); + wait_cycs(1, 0); break; case 3: case 11: @@ -1003,7 +999,7 @@ access(int num, UNUSED(int bits)) case 52: case 53: case 54: - wait(2, 0); + wait_cycs(2, 0); break; case 16: case 18: @@ -1012,7 +1008,7 @@ access(int num, UNUSED(int bits)) case 32: case 37: case 42: - wait(3, 0); + wait_cycs(3, 0); break; case 10: case 12: @@ -1025,59 +1021,59 @@ access(int num, UNUSED(int bits)) case 39: case 41: case 60: - wait(4, 0); + wait_cycs(4, 0); break; case 4: case 70: - wait(5, 0); + wait_cycs(5, 0); break; case 31: case 38: case 40: - wait(6, 0); + wait_cycs(6, 0); break; case 5: if (opcode == 0xcc) - wait(7, 0); + wait_cycs(7, 0); else - wait(4, 0); + wait_cycs(4, 0); break; case 36: - wait(1, 0); + wait_cycs(1, 0); pfq_clear(); - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(1, 0); - wait(3, 0); + wait_cycs(1, 0); + wait_cycs(3, 0); break; case 43: - wait(2, 0); + wait_cycs(2, 0); pfq_clear(); - wait(1, 0); + wait_cycs(1, 0); break; case 57: if (cpu_mod != 3) - wait(2, 0); - wait(4, 0); + wait_cycs(2, 0); + wait_cycs(4, 0); break; case 58: if (cpu_mod != 3) - wait(1, 0); - wait(4, 0); + wait_cycs(1, 0); + wait_cycs(4, 0); break; case 59: - wait(2, 0); + wait_cycs(2, 0); pfq_clear(); if (cpu_mod != 3) - wait(1, 0); - wait(3, 0); + wait_cycs(1, 0); + wait_cycs(3, 0); break; case 65: - wait(1, 0); + wait_cycs(1, 0); pfq_clear(); - wait(2, 0); + wait_cycs(2, 0); if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); break; } } @@ -1100,7 +1096,7 @@ interrupt(uint16_t addr) old_cs = CS; access(5, 16); new_ip = readmemw(0, cpu_state.eaaddr); - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff; access(6, 16); new_cs = readmemw(0, cpu_state.eaaddr); @@ -1136,7 +1132,7 @@ interrupt_brkem(uint16_t addr) old_cs = CS; access(5, 16); new_ip = readmemw(0, cpu_state.eaaddr); - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff; access(6, 16); new_cs = readmemw(0, cpu_state.eaaddr); @@ -1205,7 +1201,7 @@ custom_nmi(void) access(5, 16); (void) readmemw(0, cpu_state.eaaddr); new_ip = custom_nmi_vector & 0xffff; - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff; access(6, 16); (void) readmemw(0, cpu_state.eaaddr); @@ -1264,20 +1260,20 @@ check_interrupts(void) repeating = 0; completed = 1; ovr_seg = NULL; - wait(3, 0); + wait_cycs(3, 0); /* ACK to PIC */ temp = pic_irq_ack(); - wait(4, 1); - wait(1, 0); + wait_cycs(4, 1); + wait_cycs(1, 0); /* ACK to PIC */ temp = pic_irq_ack(); - wait(4, 1); - wait(1, 0); + wait_cycs(4, 1); + wait_cycs(1, 0); in_lock = 0; clear_lock = 0; - wait(1, 0); + wait_cycs(1, 0); /* Here is where temp should be filled, but we cheat. */ - wait(3, 0); + wait_cycs(3, 0); opcode = 0x00; interrupt(temp); } @@ -1291,7 +1287,7 @@ rep_action(int bits) if (in_rep == 0) return 0; - wait(2, 0); + wait_cycs(2, 0); t = CX; if (irq_pending() && (repeating != 0)) { access(71, bits); @@ -1303,16 +1299,16 @@ rep_action(int bits) t = 0; } if (t == 0) { - wait(1, 0); + wait_cycs(1, 0); completed = 1; repeating = 0; return 1; } --CX; completed = 0; - wait(2, 0); + wait_cycs(2, 0); if (!repeating) - wait(2, 0); + wait_cycs(2, 0); return 0; } @@ -1322,7 +1318,7 @@ jump(uint16_t delta) uint16_t old_ip; access(67, 8); pfq_clear(); - wait(5, 0); + wait_cycs(5, 0); old_ip = cpu_state.pc; set_ip((cpu_state.pc + delta) & 0xffff); return old_ip; @@ -1346,9 +1342,9 @@ jcc(uint8_t opcode, int cond) { /* int8_t offset; */ - wait(1, 0); + wait_cycs(1, 0); cpu_data = pfq_fetchb(); - wait(1, 0); + wait_cycs(1, 0); if ((!cond) == !!(opcode & 0x01)) jump_short(); } @@ -1538,32 +1534,32 @@ mul(uint16_t a, uint16_t b) bit_count = 16; high_bit = 0x8000; } else - wait(8, 0); + wait_cycs(8, 0); size_mask = (1 << bit_count) - 1; if ((rmdat & 0x38) == 0x28) { if (!top_bit(a, bit_count)) { if (top_bit(b, bit_count)) { - wait(1, 0); + wait_cycs(1, 0); if ((b & size_mask) != ((opcode & 1) ? 0x8000 : 0x80)) - wait(1, 0); + wait_cycs(1, 0); b = ~b + 1; negate = 1; } } else { - wait(1, 0); + wait_cycs(1, 0); a = ~a + 1; negate = 1; if (top_bit(b, bit_count)) { b = ~b + 1; negate = 0; } else - wait(4, 0); + wait_cycs(4, 0); } - wait(10, 0); + wait_cycs(10, 0); } - wait(3, 0); + wait_cycs(3, 0); } c = 0; @@ -1571,13 +1567,13 @@ mul(uint16_t a, uint16_t b) carry = (a & 1) != 0; a >>= 1; for (i = 0; i < bit_count; ++i) { - wait(7, 0); + wait_cycs(7, 0); if (carry) { cpu_src = c; cpu_dest = b; add(bit_count); c = cpu_data & size_mask; - wait(1, 0); + wait_cycs(1, 0); carry = !!(cpu_state.flags & C_FLAG); } r = (c >> 1) + (carry ? high_bit : 0); @@ -1592,7 +1588,7 @@ mul(uint16_t a, uint16_t b) a = (~a + 1) & size_mask; if (a == 0) ++c; - wait(9, 0); + wait_cycs(9, 0); } cpu_data = a; cpu_dest = c; @@ -1637,7 +1633,7 @@ set_co_mul(UNUSED(int bits), int carry) set_of(carry); set_zf_ex(!carry); if (!carry) - wait(1, 0); + wait_cycs(1, 0); } /* Was div(), renamed to avoid conflicts with stdlib div(). */ @@ -1668,28 +1664,28 @@ x86_div(uint16_t l, uint16_t h) h &= size_mask; negative = 1; dividend_negative = 1; - wait(4, 0); + wait_cycs(4, 0); } if (top_bit(cpu_src, bit_count)) { cpu_src = ~cpu_src + 1; negative = !negative; } else - wait(1, 0); - wait(9, 0); + wait_cycs(1, 0); + wait_cycs(9, 0); } - wait(3, 0); + wait_cycs(3, 0); } - wait(8, 0); + wait_cycs(8, 0); cpu_src &= size_mask; if (h >= cpu_src) { if (opcode != 0xd4) - wait(1, 0); + wait_cycs(1, 0); interrupt(0); return 0; } if (opcode != 0xd4) - wait(1, 0); - wait(2, 0); + wait_cycs(1, 0); + wait_cycs(2, 0); carry = 1; for (b = 0; b < bit_count; ++b) { r = (l << 1) + (carry ? 1 : 0); @@ -1698,32 +1694,32 @@ x86_div(uint16_t l, uint16_t h) r = (h << 1) + (carry ? 1 : 0); carry = top_bit(h, bit_count); h = r; - wait(8, 0); + wait_cycs(8, 0); if (carry) { carry = 0; h -= cpu_src; if (b == bit_count - 1) - wait(2, 0); + wait_cycs(2, 0); } else { carry = cpu_src > h; if (!carry) { h -= cpu_src; - wait(1, 0); + wait_cycs(1, 0); if (b == bit_count - 1) - wait(2, 0); + wait_cycs(2, 0); } } } l = ~((l << 1) + (carry ? 1 : 0)); if (opcode != 0xd4 && (rmdat & 0x38) == 0x38) { - wait(4, 0); + wait_cycs(4, 0); if (top_bit(l, bit_count)) { if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); interrupt(0); return 0; } - wait(7, 0); + wait_cycs(7, 0); if (negative) l = ~l + 1; if (dividend_negative) @@ -1782,7 +1778,7 @@ aa(void) { set_pzs(8); AL = cpu_data & 0x0f; - wait(6, 0); + wait_cycs(6, 0); } static void @@ -1852,7 +1848,7 @@ cpu_inb(uint16_t port) int old_cycles = cycles; uint8_t ret; - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; ret = inb(port); @@ -1868,12 +1864,12 @@ cpu_inw(uint16_t port) int old_cycles = cycles; uint16_t ret; - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); if (is8086 && !(port & 1)) { old_cycles = cycles; ret = inw(port); } else { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; ret = inb(port++); ret |= (inb(port) << 8); @@ -1889,7 +1885,7 @@ cpu_outb(uint16_t port, uint16_t val) { int old_cycles = cycles; - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; outb(port, val); @@ -1902,13 +1898,13 @@ cpu_outw(uint16_t port, uint16_t val) { int old_cycles = cycles; - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); if (is8086 && !(port & 1)) { old_cycles = cycles; outw(port, val); } else { - wait(is_mazovia ? 5 : 4, 1); + wait_cycs(is_mazovia ? 5 : 4, 1); old_cycles = cycles; outb(port++, val); outb(port, val >> 8); @@ -1958,7 +1954,7 @@ execx86(int cycs) in_lock = 0; clear_lock = 0; } - wait(1, 0); + wait_cycs(1, 0); } completed = 1; @@ -1967,7 +1963,7 @@ execx86(int cycs) switch (opcode) { case 0x60: /*PUSHA/PUSH R*/ orig_sp = SP; - wait(1, 0); + wait_cycs(1, 0); push(&AX); push(&CX); push(&DX); @@ -1979,7 +1975,7 @@ execx86(int cycs) handled = 1; break; case 0x61: /*POPA/POP R*/ - wait(9, 0); + wait_cycs(9, 0); DI = pop(); SI = pop(); BP = pop(); @@ -2011,7 +2007,7 @@ execx86(int cycs) case 0x65: if (is_nec) { /* REPC/REPNC */ - wait(1, 0); + wait_cycs(1, 0); in_rep = (opcode == 0x64 ? 1 : 2); rep_c_flag = 1; completed = 0; @@ -2021,7 +2017,7 @@ execx86(int cycs) case 0x68: wordtopush = pfq_fetchw(); - wait(1, 0); + wait_cycs(1, 0); push(&wordtopush); handled = 1; break; @@ -2061,12 +2057,12 @@ execx86(int cycs) bits = 8 << (opcode & 1); handled = 1; if (!repeating) - wait(2, 0); + wait_cycs(2, 0); if (rep_action(bits)) break; else if (!repeating) - wait(7, 0); + wait_cycs(7, 0); if (bits == 16) { writememw(es, DI, cpu_inw(DX)); @@ -2089,12 +2085,12 @@ execx86(int cycs) bits = 8 << (opcode & 1); handled = 1; if (!repeating) - wait(2, 0); + wait_cycs(2, 0); if (rep_action(bits)) break; else if (!repeating) - wait(7, 0); + wait_cycs(7, 0); if (bits == 16) { cpu_outw(DX, readmemw(dest_seg, SI)); @@ -2137,12 +2133,12 @@ execx86(int cycs) bits = 8 << (opcode & 1); do_mod_rm(); if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); access(53, bits); cpu_data = get_ea(); cpu_src = pfq_fetchb(); - wait((cpu_mod != 3) ? 9 : 6, 0); + wait_cycs((cpu_mod != 3) ? 9 : 6, 0); if (!is_nec) cpu_src &= 0x1F; @@ -2214,7 +2210,7 @@ execx86(int cycs) break; } if ((opcode & 2) != 0) - wait(4, 0); + wait_cycs(4, 0); --cpu_src; } access(17, bits); @@ -2248,7 +2244,7 @@ execx86(int cycs) switch (opcode) { case 0x28: /* ROL4 r/m */ do_mod_rm(); - wait(21, 0); + wait_cycs(21, 0); temp_val = geteab(); temp_al = AL; @@ -2266,7 +2262,7 @@ execx86(int cycs) case 0x2a: /* ROR4 r/m */ do_mod_rm(); - wait(21, 0); + wait_cycs(21, 0); temp_val = geteab(); temp_al = AL; @@ -2285,7 +2281,7 @@ execx86(int cycs) case 0x19: /* TEST1 r16/m16, imm4 */ bits = 8 << (opcode & 0x1); do_mod_rm(); - wait(3, 0); + wait_cycs(3, 0); bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL); bit &= ((1 << (3 + (opcode & 0x1))) - 1); @@ -2303,7 +2299,7 @@ execx86(int cycs) case 0x1f: /* NOT1 r16/m16, imm4 */ bits = 8 << (opcode & 0x1); do_mod_rm(); - wait(3, 0); + wait_cycs(3, 0); bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL); bit &= ((1 << (3 + (opcode & 0x1))) - 1); @@ -2323,7 +2319,7 @@ execx86(int cycs) case 0x1d: /* SET1 r16/m16, imm4 */ bits = 8 << (opcode & 0x1); do_mod_rm(); - wait(3, 0); + wait_cycs(3, 0); bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL); bit &= ((1 << (3 + (opcode & 0x1))) - 1); @@ -2343,7 +2339,7 @@ execx86(int cycs) case 0x1b: /* CLR1 r16/m16, imm4 */ bits = 8 << (opcode & 0x1); do_mod_rm(); - wait(3, 0); + wait_cycs(3, 0); bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL); bit &= ((1 << (3 + (opcode & 0x1))) - 1); @@ -2366,9 +2362,9 @@ execx86(int cycs) nibble = 0; srcseg = ovr_seg ? *ovr_seg : ds; - wait(5, 0); + wait_cycs(5, 0); for (i = 0; i < ((nibbles_count / 2) + odd); i++) { - wait(19, 0); + wait_cycs(19, 0); destcmp = read_mem_b((es) + DI + i); for (nibble = 0; nibble < 2; nibble++) { destbyte = destcmp >> (nibble ? 4 : 0); @@ -2401,9 +2397,9 @@ execx86(int cycs) nibble = 0; srcseg = ovr_seg ? *ovr_seg : ds; - wait(5, 0); + wait_cycs(5, 0); for (i = 0; i < ((nibbles_count / 2) + odd); i++) { - wait(19, 0); + wait_cycs(19, 0); destcmp = read_mem_b((es) + DI + i); for (nibble = 0; nibble < 2; nibble++) { destbyte = destcmp >> (nibble ? 4 : 0); @@ -2436,9 +2432,9 @@ execx86(int cycs) nibble = 0; srcseg = ovr_seg ? *ovr_seg : ds; - wait(5, 0); + wait_cycs(5, 0); for (i = 0; i < ((nibbles_count / 2) + odd); i++) { - wait(19, 0); + wait_cycs(19, 0); destcmp = read_mem_b((es) + DI + i); for (nibble = 0; nibble < 2; nibble++) { destbyte = destcmp >> (nibble ? 4 : 0); @@ -2464,7 +2460,7 @@ execx86(int cycs) case 0x31: /* INS reg1, reg2 */ case 0x39: /* INS reg8, imm4 */ do_mod_rm(); - wait(1, 0); + wait_cycs(1, 0); bit_length = ((opcode & 0x8) ? (pfq_fetchb() & 0xF) : (getr8(cpu_reg) & 0xF)) + 1; bit_offset = getr8(cpu_rm) & 0xF; @@ -2493,7 +2489,7 @@ execx86(int cycs) case 0x33: /* EXT reg1, reg2 */ case 0x3b: /* EXT reg8, imm4 */ do_mod_rm(); - wait(1, 0); + wait_cycs(1, 0); bit_length = ((opcode & 0x8) ? (pfq_fetchb() & 0xF) : (getr8(cpu_reg) & 0xF)) + 1; bit_offset = getr8(cpu_rm) & 0xF; @@ -2541,7 +2537,7 @@ execx86(int cycs) pfq_pos = 0; } else load_seg(pop(), _opseg[(opcode >> 3) & 0x03]); - wait(1, 0); + wait_cycs(1, 0); /* All POP segment instructions suppress interrupts for one instruction. */ noint = 1; break; @@ -2550,7 +2546,7 @@ execx86(int cycs) case 0x2E: /*CS:*/ case 0x36: /*SS:*/ case 0x3E: /*DS:*/ - wait(1, 0); + wait_cycs(1, 0); ovr_seg = opseg[(opcode >> 3) & 0x03]; completed = 0; break; @@ -2601,21 +2597,21 @@ execx86(int cycs) cpu_src = tempw; } if (cpu_mod != 3) - wait(2, 0); - wait(1, 0); + wait_cycs(2, 0); + wait_cycs(1, 0); alu_op(bits); if (cpu_alu_op != 7) { if ((opcode & 2) == 0) { access(10, bits); set_ea(cpu_data); if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); } else { set_reg(cpu_reg, cpu_data); - wait(1, 0); + wait_cycs(1, 0); } } else - wait(1, 0); + wait_cycs(1, 0); break; case 0x04: @@ -2636,7 +2632,7 @@ execx86(int cycs) case 0x3d: /* alu A, imm */ bits = 8 << (opcode & 1); - wait(1, 0); + wait_cycs(1, 0); cpu_data = pfq_fetch(); cpu_dest = get_accum(bits); /* AX/AL */ cpu_src = cpu_data; @@ -2644,7 +2640,7 @@ execx86(int cycs) alu_op(bits); if (cpu_alu_op != 7) set_accum(bits, cpu_data); - wait(1, 0); + wait_cycs(1, 0); break; case 0x27: /*DAA*/ @@ -2667,7 +2663,7 @@ execx86(int cycs) } AL = cpu_dest; set_pzs(8); - wait(3, 0); + wait_cycs(3, 0); break; case 0x2F: /*DAS*/ cpu_dest = AL; @@ -2689,10 +2685,10 @@ execx86(int cycs) } AL = cpu_dest; set_pzs(8); - wait(3, 0); + wait_cycs(3, 0); break; case 0x37: /*AAA*/ - wait(1, 0); + wait_cycs(1, 0); if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9)) { cpu_src = 6; ++AH; @@ -2700,7 +2696,7 @@ execx86(int cycs) } else { cpu_src = 0; clear_ca(); - wait(1, 0); + wait_cycs(1, 0); } cpu_dest = AL; cpu_data = cpu_dest + cpu_src; @@ -2708,7 +2704,7 @@ execx86(int cycs) aa(); break; case 0x3F: /*AAS*/ - wait(1, 0); + wait_cycs(1, 0); if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9)) { cpu_src = 6; --AH; @@ -2716,7 +2712,7 @@ execx86(int cycs) } else { cpu_src = 0; clear_ca(); - wait(1, 0); + wait_cycs(1, 0); } cpu_dest = AL; cpu_data = cpu_dest - cpu_src; @@ -2741,7 +2737,7 @@ execx86(int cycs) case 0x4E: case 0x4F: /* INCDEC rw */ - wait(1, 0); + wait_cycs(1, 0); cpu_dest = cpu_state.regs[opcode & 7].w; cpu_src = 1; bits = 16; @@ -2778,7 +2774,7 @@ execx86(int cycs) case 0x5F: access(23, 16); cpu_state.regs[opcode & 0x07].w = pop(); - wait(1, 0); + wait_cycs(1, 0); break; case 0x60: /*JO alias*/ @@ -2845,20 +2841,20 @@ execx86(int cycs) cpu_data = get_ea(); cpu_dest = cpu_data; if (cpu_mod != 3) - wait(3, 0); + wait_cycs(3, 0); if (opcode == 0x81) { if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); cpu_src = pfq_fetchw(); } else { if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); if (opcode == 0x83) cpu_src = sign_extend(pfq_fetchb()); else cpu_src = pfq_fetchb() | 0xff00; } - wait(1, 0); + wait_cycs(1, 0); cpu_alu_op = (rmdat & 0x38) >> 3; alu_op(bits); if (cpu_alu_op != 7) { @@ -2866,7 +2862,7 @@ execx86(int cycs) set_ea(cpu_data); } else { if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); } break; @@ -2879,8 +2875,8 @@ execx86(int cycs) cpu_data = get_ea(); test(bits, cpu_data, get_reg(cpu_reg)); if (cpu_mod == 3) - wait(2, 0); - wait(2, 0); + wait_cycs(2, 0); + wait_cycs(2, 0); break; case 0x86: case 0x87: @@ -2891,7 +2887,7 @@ execx86(int cycs) cpu_data = get_ea(); cpu_src = get_reg(cpu_reg); set_reg(cpu_reg, cpu_data); - wait(3, 0); + wait_cycs(3, 0); access(12, bits); set_ea(cpu_src); break; @@ -2901,7 +2897,7 @@ execx86(int cycs) /* MOV rm, reg */ bits = 8 << (opcode & 1); do_mod_rm(); - wait(1, 0); + wait_cycs(1, 0); access(13, bits); set_ea(get_reg(cpu_reg)); break; @@ -2912,15 +2908,15 @@ execx86(int cycs) do_mod_rm(); access(50, bits); set_reg(cpu_reg, get_ea()); - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); break; case 0x8C: /*MOV w,sreg*/ do_mod_rm(); if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); access(14, 16); seteaw(_opseg[(rmdat & 0x18) >> 3]->seg); break; @@ -2928,9 +2924,9 @@ execx86(int cycs) case 0x8D: /*LEA*/ do_mod_rm(); cpu_state.regs[cpu_reg].w = cpu_state.eaaddr; - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); break; case 0x8E: /*MOV sreg,w*/ @@ -2942,23 +2938,23 @@ execx86(int cycs) pfq_pos = 0; } else load_seg(tempw, _opseg[(rmdat & 0x18) >> 3]); - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); if (((rmdat & 0x18) >> 3) == 2) noint = 1; break; case 0x8F: /*POPW*/ do_mod_rm(); - wait(1, 0); + wait_cycs(1, 0); cpu_src = cpu_state.eaaddr; access(24, 16); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); cpu_data = pop(); cpu_state.eaaddr = cpu_src; - wait(2, 0); + wait_cycs(2, 0); access(15, 16); seteaw(cpu_data); break; @@ -2972,30 +2968,30 @@ execx86(int cycs) case 0x96: case 0x97: /* XCHG AX, rw */ - wait(1, 0); + wait_cycs(1, 0); cpu_data = cpu_state.regs[opcode & 7].w; cpu_state.regs[opcode & 7].w = AX; AX = cpu_data; - wait(1, 0); + wait_cycs(1, 0); break; case 0x98: /*CBW*/ - wait(1, 0); + wait_cycs(1, 0); AX = sign_extend(AL); break; case 0x99: /*CWD*/ - wait(4, 0); + wait_cycs(4, 0); if (!top_bit(AX, 16)) DX = 0; else { - wait(1, 0); + wait_cycs(1, 0); DX = 0xffff; } break; case 0x9A: /*CALL FAR*/ - wait(1, 0); + wait_cycs(1, 0); new_ip = pfq_fetchw(); - wait(1, 0); + wait_cycs(1, 0); new_cs = pfq_fetchw(); pfq_clear(); access(31, 16); @@ -3009,11 +3005,11 @@ execx86(int cycs) break; case 0x9B: /*WAIT*/ if (!repeating) - wait(2, 0); - wait(5, 0); + wait_cycs(2, 0); + wait_cycs(5, 0); #ifdef NO_HACK if (irq_pending()) { - wait(7, 0); + wait_cycs(7, 0); check_interrupts(); } else { repeating = 1; @@ -3021,7 +3017,7 @@ execx86(int cycs) clock_end(); } #else - wait(7, 0); + wait_cycs(7, 0); check_interrupts(); #endif break; @@ -3039,16 +3035,16 @@ execx86(int cycs) cpu_state.flags = pop() | 0x8002; else cpu_state.flags = pop() | 0x0002; - wait(1, 0); + wait_cycs(1, 0); sync_to_i8080(); break; case 0x9E: /*SAHF*/ - wait(1, 0); + wait_cycs(1, 0); cpu_state.flags = (cpu_state.flags & 0xff02) | AH; - wait(2, 0); + wait_cycs(2, 0); break; case 0x9F: /*LAHF*/ - wait(1, 0); + wait_cycs(1, 0); AH = cpu_state.flags & 0xd7; break; @@ -3056,17 +3052,17 @@ execx86(int cycs) case 0xA1: /* MOV A, [iw] */ bits = 8 << (opcode & 1); - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = pfq_fetchw(); access(1, bits); set_accum(bits, readmem((ovr_seg ? *ovr_seg : ds))); - wait(1, 0); + wait_cycs(1, 0); break; case 0xA2: case 0xA3: /* MOV [iw], A */ bits = 8 << (opcode & 1); - wait(1, 0); + wait_cycs(1, 0); cpu_state.eaaddr = pfq_fetchw(); access(7, bits); writemem((ovr_seg ? *ovr_seg : ds), get_accum(bits)); @@ -3078,18 +3074,18 @@ execx86(int cycs) case 0xAD: /* LODS */ bits = 8 << (opcode & 1); if (!repeating) { - wait(1, 0); + wait_cycs(1, 0); if ((opcode & 8) == 0 && in_rep != 0) - wait(1, 0); + wait_cycs(1, 0); } if (rep_action(bits)) { - wait(1, 0); + wait_cycs(1, 0); if ((opcode & 8) != 0) - wait(1, 0); + wait_cycs(1, 0); break; } if (in_rep != 0 && (opcode & 8) != 0) - wait(1, 0); + wait_cycs(1, 0); access(20, bits); lods(bits); if ((opcode & 8) == 0) { @@ -3098,12 +3094,12 @@ execx86(int cycs) } else { set_accum(bits, cpu_data); if (in_rep != 0) - wait(2, 0); + wait_cycs(2, 0); } if (in_rep == 0) { - wait(3, 0); + wait_cycs(3, 0); if ((opcode & 8) != 0) - wait(1, 0); + wait_cycs(1, 0); break; } repeating = 1; @@ -3116,19 +3112,19 @@ execx86(int cycs) case 0xAF: /* SCAS */ bits = 8 << (opcode & 1); if (!repeating) - wait(1, 0); + wait_cycs(1, 0); if (rep_action(bits)) { - wait(2, 0); + wait_cycs(2, 0); break; } if (in_rep != 0) - wait(1, 0); - wait(1, 0); + wait_cycs(1, 0); + wait_cycs(1, 0); cpu_dest = get_accum(bits); if ((opcode & 8) == 0) { access(21, bits); lods(bits); - wait(1, 0); + wait_cycs(1, 0); cpu_dest = cpu_data; } access(2, bits); @@ -3137,14 +3133,14 @@ execx86(int cycs) DI = string_increment(bits); cpu_src = cpu_data; sub(bits); - wait(2, 0); + wait_cycs(2, 0); if (in_rep == 0) { - wait(3, 0); + wait_cycs(3, 0); break; } if ((!!(cpu_state.flags & (rep_c_flag ? C_FLAG : Z_FLAG))) == (in_rep == 1)) { completed = 1; - wait(4, 0); + wait_cycs(4, 0); break; } repeating = 1; @@ -3155,29 +3151,29 @@ execx86(int cycs) case 0xA9: /* TEST A, imm */ bits = 8 << (opcode & 1); - wait(1, 0); + wait_cycs(1, 0); cpu_data = pfq_fetch(); test(bits, get_accum(bits), cpu_data); - wait(1, 0); + wait_cycs(1, 0); break; case 0xAA: case 0xAB: /* STOS */ bits = 8 << (opcode & 1); if (!repeating) { - wait(1, 0); + wait_cycs(1, 0); if (in_rep != 0) - wait(1, 0); + wait_cycs(1, 0); } if (rep_action(bits)) { - wait(1, 0); + wait_cycs(1, 0); break; } cpu_data = AX; access(28, bits); stos(bits); if (in_rep == 0) { - wait(3, 0); + wait_cycs(3, 0); break; } repeating = 1; @@ -3192,12 +3188,12 @@ execx86(int cycs) case 0xB5: case 0xB6: case 0xB7: - wait(1, 0); + wait_cycs(1, 0); if (opcode & 0x04) cpu_state.regs[opcode & 0x03].b.h = pfq_fetchb(); else cpu_state.regs[opcode & 0x03].b.l = pfq_fetchb(); - wait(1, 0); + wait_cycs(1, 0); break; case 0xB8: @@ -3208,9 +3204,9 @@ execx86(int cycs) case 0xBD: case 0xBE: case 0xBF: - wait(1, 0); + wait_cycs(1, 0); cpu_state.regs[opcode & 0x07].w = pfq_fetchw(); - wait(1, 0); + wait_cycs(1, 0); break; case 0xC0: @@ -3224,28 +3220,28 @@ execx86(int cycs) /* RET */ bits = 8 + (opcode & 0x08); if ((opcode & 9) != 1) - wait(1, 0); + wait_cycs(1, 0); if (!(opcode & 1)) { cpu_src = pfq_fetchw(); - wait(1, 0); + wait_cycs(1, 0); } if ((opcode & 9) == 9) - wait(1, 0); + wait_cycs(1, 0); pfq_clear(); access(26, bits); new_ip = pop(); - wait(2, 0); + wait_cycs(2, 0); if ((opcode & 8) == 0) new_cs = CS; else { access(42, bits); new_cs = pop(); if (opcode & 1) - wait(1, 0); + wait_cycs(1, 0); } if (!(opcode & 1)) { SP += cpu_src; - wait(1, 0); + wait_cycs(1, 0); } load_cs(new_cs); access(72, bits); @@ -3263,7 +3259,7 @@ execx86(int cycs) access(57, bits); read_ea2(bits); load_seg(cpu_data, (opcode & 0x01) ? &cpu_state.seg_ds : &cpu_state.seg_es); - wait(1, 0); + wait_cycs(1, 0); break; case 0xC6: @@ -3271,12 +3267,12 @@ execx86(int cycs) /* MOV rm, imm */ bits = 8 << (opcode & 1); do_mod_rm(); - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); cpu_data = pfq_fetch(); if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); access(16, bits); set_ea(cpu_data); break; @@ -3285,13 +3281,13 @@ execx86(int cycs) interrupt(3); break; case 0xCD: /*INT*/ - wait(1, 0); + wait_cycs(1, 0); interrupt(pfq_fetchb()); break; case 0xCE: /*INTO*/ - wait(3, 0); + wait_cycs(3, 0); if (cpu_state.flags & V_FLAG) { - wait(2, 0); + wait_cycs(2, 0); interrupt(4); } break; @@ -3299,7 +3295,7 @@ execx86(int cycs) case 0xCF: /*IRET*/ access(43, 8); new_ip = pop(); - wait(3, 0); + wait_cycs(3, 0); access(44, 8); new_cs = pop(); load_cs(new_cs); @@ -3310,7 +3306,7 @@ execx86(int cycs) cpu_state.flags = pop() | 0x8002; else cpu_state.flags = pop() | 0x0002; - wait(5, 0); + wait_cycs(5, 0); noint = 1; nmi_enable = 1; if (is_nec && !(cpu_state.flags & MD_FLAG)) @@ -3325,15 +3321,15 @@ execx86(int cycs) bits = 8 << (opcode & 1); do_mod_rm(); if (cpu_mod == 3) - wait(1, 0); + wait_cycs(1, 0); access(53, bits); cpu_data = get_ea(); if ((opcode & 2) == 0) { cpu_src = 1; - wait((cpu_mod != 3) ? 4 : 0, 0); + wait_cycs((cpu_mod != 3) ? 4 : 0, 0); } else { cpu_src = CL; - wait((cpu_mod != 3) ? 9 : 6, 0); + wait_cycs((cpu_mod != 3) ? 9 : 6, 0); } if (is186 && !is_nec) cpu_src &= 0x1F; @@ -3405,7 +3401,7 @@ execx86(int cycs) break; } if ((opcode & 2) != 0) - wait(4, 0); + wait_cycs(4, 0); --cpu_src; } access(17, bits); @@ -3413,7 +3409,7 @@ execx86(int cycs) break; case 0xD4: /*AAM*/ - wait(1, 0); + wait_cycs(1, 0); #ifdef NO_VARIANT_ON_NEC if (is_nec) { (void) pfq_fetchb(); @@ -3429,7 +3425,7 @@ execx86(int cycs) } break; case 0xD5: /*AAD*/ - wait(1, 0); + wait_cycs(1, 0); if (is_nec) { (void) pfq_fetchb(); mul(10, AH); @@ -3444,9 +3440,9 @@ execx86(int cycs) break; case 0xD6: /*SALC*/ if (!is_nec) { - wait(1, 0); + wait_cycs(1, 0); AL = (cpu_state.flags & C_FLAG) ? 0xff : 0x00; - wait(1, 0); + wait_cycs(1, 0); break; } fallthrough; @@ -3454,7 +3450,7 @@ execx86(int cycs) cpu_state.eaaddr = (BX + AL) & 0xffff; access(4, 8); AL = readmemb((ovr_seg ? *ovr_seg : ds) + cpu_state.eaaddr); - wait(1, 0); + wait_cycs(1, 0); break; case 0xD8: @@ -3535,9 +3531,9 @@ execx86(int cycs) } cpu_state.pc = tempw; /* Do this as the x87 code advances it, which is needed on the 286+ core, but not here. */ - wait(1, 0); + wait_cycs(1, 0); if (cpu_mod != 3) - wait(2, 0); + wait_cycs(2, 0); break; case 0xE0: @@ -3545,10 +3541,10 @@ execx86(int cycs) case 0xE2: case 0xE3: /* LOOP */ - wait(3, 0); + wait_cycs(3, 0); cpu_data = pfq_fetchb(); if (opcode != 0xe2) - wait(1, 0); + wait_cycs(1, 0); if (opcode != 0xe3) { --CX; oldc = (CX != 0); @@ -3578,7 +3574,7 @@ execx86(int cycs) case 0xEF: bits = 8 << (opcode & 1); if ((opcode & 0x0e) != 0x0c) - wait(1, 0); + wait_cycs(1, 0); if ((opcode & 8) == 0) cpu_data = pfq_fetchb(); else @@ -3590,7 +3586,7 @@ execx86(int cycs) cpu_io(16, 0, cpu_data); else cpu_io(8, 0, cpu_data); - wait(1, 0); + wait_cycs(1, 0); } else { if ((opcode & 8) == 0) access(8, bits); @@ -3604,19 +3600,19 @@ execx86(int cycs) break; case 0xE8: /*CALL rel 16*/ - wait(1, 0); + wait_cycs(1, 0); cpu_state.oldpc = jump_near(); access(34, 8); push((uint16_t *) &(cpu_state.oldpc)); break; case 0xE9: /*JMP rel 16*/ - wait(1, 0); + wait_cycs(1, 0); jump_near(); break; case 0xEA: /*JMP far*/ - wait(1, 0); + wait_cycs(1, 0); addr = pfq_fetchw(); - wait(1, 0); + wait_cycs(1, 0); tempw = pfq_fetchw(); load_cs(tempw); access(70, 8); @@ -3624,22 +3620,22 @@ execx86(int cycs) set_ip(addr); break; case 0xEB: /*JMP rel*/ - wait(1, 0); + wait_cycs(1, 0); cpu_data = (int8_t) pfq_fetchb(); jump_short(); - wait(1, 0); + wait_cycs(1, 0); break; case 0xF0: case 0xF1: /*LOCK - F1 is alias*/ in_lock = 1; - wait(1, 0); + wait_cycs(1, 0); completed = 0; break; case 0xF2: /*REPNE*/ case 0xF3: /*REPE*/ - wait(1, 0); + wait_cycs(1, 0); in_rep = (opcode == 0xf2 ? 1 : 2); completed = 0; rep_c_flag = 0; @@ -3647,12 +3643,12 @@ execx86(int cycs) case 0xF4: /*HLT*/ if (!repeating) { - wait(1, 0); + wait_cycs(1, 0); pfq_clear(); } - wait(1, 0); + wait_cycs(1, 0); if (irq_pending()) { - wait(cycles & 1, 0); + wait_cycs(cycles & 1, 0); check_interrupts(); } else { repeating = 1; @@ -3661,7 +3657,7 @@ execx86(int cycs) } break; case 0xF5: /*CMC*/ - wait(1, 0); + wait_cycs(1, 0); cpu_state.flags ^= C_FLAG; break; @@ -3675,18 +3671,18 @@ execx86(int cycs) case 0x00: case 0x08: /* TEST */ - wait(2, 0); + wait_cycs(2, 0); if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); cpu_src = pfq_fetch(); - wait(1, 0); + wait_cycs(1, 0); test(bits, cpu_data, cpu_src); if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); break; case 0x10: /* NOT */ case 0x18: /* NEG */ - wait(2, 0); + wait_cycs(2, 0); if ((rmdat & 0x38) == 0x10) cpu_data = ~cpu_data; else { @@ -3700,7 +3696,7 @@ execx86(int cycs) case 0x20: /* MUL */ case 0x28: /* IMUL */ old_flags = cpu_state.flags; - wait(1, 0); + wait_cycs(1, 0); mul(get_accum(bits), cpu_data); if (opcode & 1) { AX = cpu_data; @@ -3717,7 +3713,7 @@ execx86(int cycs) set_sf(bits); set_pf(); if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); /* NOTE: When implementing the V20, care should be taken to not change the zero flag. */ if (is_nec) @@ -3726,10 +3722,10 @@ execx86(int cycs) case 0x30: /* DIV */ case 0x38: /* IDIV */ if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); cpu_src = cpu_data; if (x86_div(AL, AH)) - wait(1, 0); + wait_cycs(1, 0); break; } break; @@ -3737,19 +3733,19 @@ execx86(int cycs) case 0xF8: case 0xF9: /* CLCSTC */ - wait(1, 0); + wait_cycs(1, 0); set_cf(opcode & 1); break; case 0xFA: case 0xFB: /* CLISTI */ - wait(1, 0); + wait_cycs(1, 0); set_if(opcode & 1); break; case 0xFC: case 0xFD: /* CLDSTD */ - wait(1, 0); + wait_cycs(1, 0); set_df(opcode & 1); break; @@ -3774,22 +3770,22 @@ execx86(int cycs) } do_af(); set_pzs(bits); - wait(2, 0); + wait_cycs(2, 0); access(19, bits); set_ea(cpu_data); break; case 0x10: /* CALL rm */ cpu_data_opff_rm(); access(63, bits); - wait(1, 0); + wait_cycs(1, 0); pfq_clear(); - wait(4, 0); + wait_cycs(4, 0); if (cpu_mod != 3) - wait(1, 0); - wait(1, 0); /* Wait. */ + wait_cycs(1, 0); + wait_cycs(1, 0); /* Wait. */ cpu_state.oldpc = cpu_state.pc; set_ip(cpu_data); - wait(2, 0); + wait_cycs(2, 0); access(35, bits); push((uint16_t *) &(cpu_state.oldpc)); break; @@ -3803,7 +3799,7 @@ execx86(int cycs) access(36, bits); push(&(CS)); access(64, bits); - wait(4, 0); + wait_cycs(4, 0); cpu_state.oldpc = cpu_state.pc; load_cs(new_cs); set_ip(new_ip); @@ -3829,7 +3825,7 @@ execx86(int cycs) case 0x30: /* PUSH rm */ case 0x38: if (cpu_mod != 3) - wait(1, 0); + wait_cycs(1, 0); access(38, bits); push((uint16_t *) &(cpu_data)); break; @@ -3839,7 +3835,7 @@ execx86(int cycs) default: x808x_log("Illegal opcode: %02X\n", opcode); pfq_fetchb(); - wait(8, 0); + wait_cycs(8, 0); break; } } diff --git a/src/cpu/x87_ops.h b/src/cpu/x87_ops.h index b134bf8fc..1e4504949 100644 --- a/src/cpu/x87_ops.h +++ b/src/cpu/x87_ops.h @@ -581,7 +581,7 @@ static int FPU_ILLEGAL_a16(UNUSED(uint32_t fetchdat)) { geteaw(); - wait(timing_rr, 0); + wait_cycs(timing_rr, 0); return 0; } #else diff --git a/src/cpu/x87_ops_misc.h b/src/cpu/x87_ops_misc.h index 9a01f7496..417beea62 100644 --- a/src/cpu/x87_ops_misc.h +++ b/src/cpu/x87_ops_misc.h @@ -7,7 +7,7 @@ opFI(uint32_t fetchdat) cpu_state.npxc &= ~0x80; if (rmdat == 0xe1) cpu_state.npxc |= 0x80; - wait(3, 0); + wait_cycs(3, 0); return 0; } #else diff --git a/src/cpu/x87_ops_sf.h b/src/cpu/x87_ops_sf.h index 0d4fee81a..adbaa2003 100644 --- a/src/cpu/x87_ops_sf.h +++ b/src/cpu/x87_ops_sf.h @@ -354,7 +354,7 @@ sf_FI(uint32_t fetchdat) fpu_state.cwd &= ~FPU_SW_Summary; if (rmdat == 0xe1) fpu_state.cwd |= FPU_SW_Summary; - wait(3, 0); + wait_cycs(3, 0); return 0; } #else