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Fixed the Riva 128 and TNT PCI handlers.

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This commit is contained in:
OBattler
2017-01-03 03:54:58 +01:00
parent 8818686ef4
commit 4a8414231b
1 changed files with 22 additions and 42 deletions
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64
src/vid_nv_riva128.c
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@@ -1776,9 +1776,17 @@ static void riva128_pci_write(int func, int addr, uint8_t val, void *p)
case PCI_REG_COMMAND: case PCI_REG_COMMAND:
riva128->pci_regs[PCI_REG_COMMAND] = val & 0x27; riva128->pci_regs[PCI_REG_COMMAND] = val & 0x27;
io_removehandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&riva128->mmio_mapping);
mem_mapping_disable(&riva128->linear_mapping);
mem_mapping_disable(&riva128->ramin_mapping);
if (val & PCI_COMMAND_IO) if (val & PCI_COMMAND_IO)
{ {
io_sethandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128); io_sethandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
}
if (val & PCI_COMMAND_MEM)
{
uint32_t mmio_addr = riva128->pci_regs[0x13] << 24; uint32_t mmio_addr = riva128->pci_regs[0x13] << 24;
uint32_t linear_addr = riva128->pci_regs[0x17] << 24; uint32_t linear_addr = riva128->pci_regs[0x17] << 24;
if (!mmio_addr && !linear_addr) if (!mmio_addr && !linear_addr)
@@ -1796,14 +1804,6 @@ static void riva128_pci_write(int func, int addr, uint8_t val, void *p)
svga->linear_base = linear_addr; svga->linear_base = linear_addr;
} }
} }
else
{
io_removehandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&riva128->mmio_mapping);
mem_mapping_disable(&riva128->linear_mapping);
mem_mapping_disable(&riva128->ramin_mapping);
}
return; return;
case 0x05: case 0x05:
@@ -1818,14 +1818,11 @@ static void riva128_pci_write(int func, int addr, uint8_t val, void *p)
{ {
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
uint32_t mmio_addr = riva128->pci_regs[0x13] << 24; uint32_t mmio_addr = riva128->pci_regs[0x13] << 24;
mem_mapping_disable(&riva128->mmio_mapping);
if (mmio_addr) if (mmio_addr)
{ {
mem_mapping_set_addr(&riva128->mmio_mapping, mmio_addr, 0x1000000); mem_mapping_set_addr(&riva128->mmio_mapping, mmio_addr, 0x1000000);
} }
else
{
mem_mapping_disable(&riva128->mmio_mapping);
}
return; return;
} }
@@ -1833,33 +1830,26 @@ static void riva128_pci_write(int func, int addr, uint8_t val, void *p)
{ {
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
uint32_t linear_addr = riva128->pci_regs[0x17] << 24; uint32_t linear_addr = riva128->pci_regs[0x17] << 24;
mem_mapping_disable(&riva128->linear_mapping);
mem_mapping_disable(&riva128->ramin_mapping);
if (linear_addr) if (linear_addr)
{ {
mem_mapping_set_addr(&riva128->linear_mapping, linear_addr, 0xc00000); mem_mapping_set_addr(&riva128->linear_mapping, linear_addr, 0xc00000);
mem_mapping_set_addr(&riva128->ramin_mapping, linear_addr + 0xc00000, 0x200000); mem_mapping_set_addr(&riva128->ramin_mapping, linear_addr + 0xc00000, 0x200000);
svga->linear_base = linear_addr; svga->linear_base = linear_addr;
} }
else
{
mem_mapping_disable(&riva128->linear_mapping);
mem_mapping_disable(&riva128->ramin_mapping);
}
return; return;
} }
case 0x30: case 0x32: case 0x33: case 0x30: case 0x32: case 0x33:
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
mem_mapping_disable(&riva128->bios_rom.mapping);
if (riva128->pci_regs[0x30] & 0x01) if (riva128->pci_regs[0x30] & 0x01)
{ {
uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24); uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24);
// pclog("RIVA 128 bios_rom enabled at %08x\n", addr); // pclog("RIVA 128 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x8000); mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x8000);
} }
else
{
// pclog("RIVA 128 bios_rom disabled\n");
mem_mapping_disable(&riva128->bios_rom.mapping);
}
return; return;
case 0x3c: case 0x3c:
@@ -1886,9 +1876,16 @@ static void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
case PCI_REG_COMMAND: case PCI_REG_COMMAND:
riva128->pci_regs[PCI_REG_COMMAND] = val & 0x27; riva128->pci_regs[PCI_REG_COMMAND] = val & 0x27;
io_removehandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&riva128->mmio_mapping);
mem_mapping_disable(&riva128->linear_mapping);
if (val & PCI_COMMAND_IO) if (val & PCI_COMMAND_IO)
{ {
io_sethandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128); io_sethandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
}
if (val & PCI_COMMAND_MEM)
{
uint32_t mmio_addr = riva128->pci_regs[0x13] << 24; uint32_t mmio_addr = riva128->pci_regs[0x13] << 24;
uint32_t linear_addr = riva128->pci_regs[0x17] << 24; uint32_t linear_addr = riva128->pci_regs[0x17] << 24;
if (!mmio_addr && !linear_addr) if (!mmio_addr && !linear_addr)
@@ -1905,13 +1902,6 @@ static void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
svga->linear_base = linear_addr; svga->linear_base = linear_addr;
} }
} }
else
{
io_removehandler(0x03c0, 0x0020, riva128_in, NULL, NULL, riva128_out, NULL, NULL, riva128);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&riva128->mmio_mapping);
mem_mapping_disable(&riva128->linear_mapping);
}
return; return;
case 0x05: case 0x05:
@@ -1926,14 +1916,11 @@ static void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
{ {
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
uint32_t mmio_addr = riva128->pci_regs[0x13] << 24; uint32_t mmio_addr = riva128->pci_regs[0x13] << 24;
mem_mapping_disable(&riva128->mmio_mapping);
if (mmio_addr) if (mmio_addr)
{ {
mem_mapping_set_addr(&riva128->mmio_mapping, mmio_addr, 0x1000000); mem_mapping_set_addr(&riva128->mmio_mapping, mmio_addr, 0x1000000);
} }
else
{
mem_mapping_disable(&riva128->mmio_mapping);
}
return; return;
} }
@@ -1941,31 +1928,24 @@ static void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
{ {
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
uint32_t linear_addr = riva128->pci_regs[0x17] << 24; uint32_t linear_addr = riva128->pci_regs[0x17] << 24;
mem_mapping_disable(&riva128->linear_mapping);
if (linear_addr) if (linear_addr)
{ {
mem_mapping_set_addr(&riva128->linear_mapping, linear_addr, 0x1000000); mem_mapping_set_addr(&riva128->linear_mapping, linear_addr, 0x1000000);
svga->linear_base = linear_addr; svga->linear_base = linear_addr;
} }
else
{
mem_mapping_disable(&riva128->linear_mapping);
}
return; return;
} }
case 0x30: case 0x32: case 0x33: case 0x30: case 0x32: case 0x33:
riva128->pci_regs[addr] = val; riva128->pci_regs[addr] = val;
mem_mapping_disable(&riva128->bios_rom.mapping);
if (riva128->pci_regs[0x30] & 0x01) if (riva128->pci_regs[0x30] & 0x01)
{ {
uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24); uint32_t addr = (riva128->pci_regs[0x32] << 16) | (riva128->pci_regs[0x33] << 24);
// pclog("RIVA TNT bios_rom enabled at %08x\n", addr); // pclog("RIVA TNT bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x10000); mem_mapping_set_addr(&riva128->bios_rom.mapping, addr, 0x10000);
} }
else
{
// pclog("RIVA TNT bios_rom disabled\n");
mem_mapping_disable(&riva128->bios_rom.mapping);
}
return; return;
case 0x3c: case 0x3c: