From 4bd374a7dfcceebac5249fb01409c7395762bb6d Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 2 Apr 2025 16:55:57 -0300
Subject: [PATCH] Don't apply the Deschutes cacheability fix to Covington

---
 src/cpu/cpu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 61bd8bf36..ffe582604 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -2651,8 +2651,9 @@ cpu_ven_reset(void)
             msr.mtrr_cap = 0x00000508ULL;
 
             /* 4 GB cacheable space on Deschutes 651h and later (including the 1632h
-               Overdrive) according to the Pentium II Processor Specification Update. */
-            if (cpu_s->cpuid_model >= 0x651)
+               Overdrive) according to the Pentium II Processor Specification Update.
+               Covington 651h (no L2 cache) reports the same 512 MB value as Klamath. */
+            if (CPUID >= (!strncmp(cpu_f->internal_name, "celeron", 7) ? 0x660 : 0x651))
                 msr.bbl_cr_ctl3 |= 0x00300000;
             break;