Added PSE emulation, based on mainline PCem commit.
This commit is contained in:
@@ -72,6 +72,7 @@ enum
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{
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CPUID_FPU = (1 << 0),
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CPUID_VME = (1 << 1),
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CPUID_PSE = (1 << 3),
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CPUID_TSC = (1 << 4),
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CPUID_MSR = (1 << 5),
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CPUID_CMPXCHG8B = (1 << 8),
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@@ -1211,7 +1212,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
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codegen_timing_set(&codegen_timing_pentium);
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break;
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@@ -1252,7 +1253,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
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codegen_timing_set(&codegen_timing_pentium);
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break;
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@@ -1452,7 +1453,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
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codegen_timing_set(&codegen_timing_pentium);
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break;
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@@ -1486,7 +1487,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
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codegen_timing_set(&codegen_timing_686);
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break;
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@@ -1521,7 +1522,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
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codegen_timing_set(&codegen_timing_686);
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break;
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#endif
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@@ -1556,7 +1557,7 @@ void cpu_set()
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cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_hasVME = 1;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
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cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
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codegen_timing_set(&codegen_timing_686);
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break;
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@@ -1681,7 +1682,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
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}
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else
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EAX = 0;
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@@ -1769,7 +1770,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
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}
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else if (EAX == 0x80000000)
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{
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@@ -1780,7 +1781,7 @@ void cpu_CPUID()
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{
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EAX = CPUID + 0x100;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP;
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}
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else if (EAX == 0x80000002)
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{
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@@ -1831,7 +1832,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX;
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}
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else
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EAX = 0;
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@@ -1926,7 +1927,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_SEP | CPUID_CMOV;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_SEP | CPUID_CMOV;
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}
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else if (EAX == 2)
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{
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@@ -1947,7 +1948,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_CMOV;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_CMOV;
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}
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else if (EAX == 2)
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{
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@@ -1971,7 +1972,7 @@ void cpu_CPUID()
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{
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_VME | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
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EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
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}
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else if (EAX == 2)
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{
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