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Merge branch 'master' of https://github.com/86Box/86Box

Browse Source
This commit is contained in:
RichardG867
2021-01-28 18:58:36 -03:00
parent 640fbf7c5c 67b3b7e02a
commit 53ee61d93c
35 changed files with 3363 additions and 1001 deletions
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9
src/chipset/CMakeLists.txt
View File

@@ -13,11 +13,11 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(chipset OBJECT acc2168.c cs8230.c ali1429.c headland.c intel_82335.c
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c headland.c intel_82335.c
cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
neat.c opti495.c opti895.c opti5x7.c scamp.c scat.c via_vt82c49x.c
via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
opti283.c opti291.c umc491.c via_apollo.c via_pipc.c wd76c10.c
opti283.c opti291.c via_apollo.c via_pipc.c wd76c10.c
vl82c480.c)
if(STPC)
@@ -28,6 +28,11 @@ if(M1489)
target_sources(chipset PRIVATE ali1489.c)
endif()
if(M154X)
target_sources(chipset PRIVATE ali1531.c)
target_sources(chipset PRIVATE ali1543.c)
endif()
if(M6117)
target_sources(chipset PRIVATE ali6117.c)
endif()

152
src/chipset/ali1217.c Normal file
View File

@@ -0,0 +1,152 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1217 chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
* Authors: Tiseno100
*
* Copyright 2021 Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_ALI1217_LOG
int ali1217_do_log = ENABLE_ALI1217_LOG;
static void
ali1217_log(const char *fmt, ...)
{
va_list ap;
if (ali1217_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1217_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256];
int cfg_locked;
} ali1217_t;
static void ali1217_shadow_recalc(ali1217_t *dev)
{
for (uint8_t i = 0; i < 4; i++)
{
mem_set_mem_state_both(0xc0000 + (i << 15), 0x8000, ((dev->regs[0x14] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, ((dev->regs[0x15] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x15] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
shadowbios = !!(dev->regs[0x15] & 5);
shadowbios_write = !!(dev->regs[0x15] & 0x0a);
flushmmucache();
}
static void
ali1217_write(uint16_t addr, uint8_t val, void *priv)
{
ali1217_t *dev = (ali1217_t *)priv;
switch (addr)
{
case 0x22:
dev->index = val;
break;
case 0x23:
if (dev->index != 0x13)
ali1217_log("ALi M1217: dev->regs[%02x] = %02x\n", dev->index, val);
if (dev->index == 0x13)
dev->cfg_locked = !(val == 0xc5);
if (!dev->cfg_locked)
{
dev->regs[dev->index] = val;
if ((dev->index == 0x14) || (dev->index == 0x15))
ali1217_shadow_recalc(dev);
}
break;
}
}
static uint8_t
ali1217_read(uint16_t addr, void *priv)
{
ali1217_t *dev = (ali1217_t *)priv;
return !(addr == 0x22) ? dev->regs[dev->index] : dev->index;
}
static void
ali1217_close(void *priv)
{
ali1217_t *dev = (ali1217_t *)priv;
free(dev);
}
static void *
ali1217_init(const device_t *info)
{
ali1217_t *dev = (ali1217_t *)malloc(sizeof(ali1217_t));
memset(dev, 0, sizeof(ali1217_t));
device_add(&port_92_device);
dev->cfg_locked = 1;
/*
ALi M1217 Ports
22h Index Port
23h Data Port
*/
io_sethandler(0x0022, 0x0002, ali1217_read, NULL, NULL, ali1217_write, NULL, NULL, dev);
ali1217_shadow_recalc(dev);
return dev;
}
const device_t ali1217_device = {
"ALi M1217",
0,
0,
ali1217_init,
ali1217_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

11
src/chipset/ali1429.c
View File

@@ -101,17 +101,16 @@ ali1429_write(uint16_t addr, uint8_t val, void *priv)
/* Don't log register unlock patterns */
if(dev->index != 0x03)
{
ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
}
dev->regs[dev->index] = val;
/* Unlock/Lock Registers */
dev->cfg_locked = !(dev->regs[0x03] && 0xc5);
if(dev->index == 0x03)
dev->cfg_locked = !(val == 0xc5);
if(dev->cfg_locked == 0)
if(!dev->cfg_locked)
{
dev->regs[dev->index] = val;
switch(dev->index){
/* Shadow RAM */
case 0x13:

316
src/chipset/ali1531.c Normal file
View File

@@ -0,0 +1,316 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1531B CPU-to-PCI Bridge.
*
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1531_t
{
uint8_t pci_conf[256];
smram_t *smram;
} ali1531_t;
void ali1531_shadow_recalc(ali1531_t *dev)
{
for (uint32_t i = 0; i < 8; i++)
{
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
shadowbios = !!(dev->pci_conf[0x4d] & 0xf0);
shadowbios_write = !!(dev->pci_conf[0x4f] & 0xf0);
flushmmucache();
}
void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
{
if (!!(dev->pci_conf[0x48] & 1))
{
switch (smm_state)
{
case 0:
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 0, 1);
smram_map(1, 0xd0000, 0x10000, 1);
break;
case 1:
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 1, 1);
smram_map(1, 0xd0000, 0x10000, 1);
break;
case 2:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 0, 1);
smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
break;
case 3:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 1, 1);
smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
break;
case 4:
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 0, 1);
smram_map(1, 0x30000, 0x10000, 1);
break;
case 5:
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 1, 1);
smram_map(1, 0x30000, 0x10000, 1);
break;
}
}
else
smram_disable_all();
flushmmucache();
}
static void
ali1531_write(int func, int addr, uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
switch (addr)
{
case 0x05:
dev->pci_conf[addr] = val & 1;
break;
case 0x07:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x40:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0x41:
dev->pci_conf[addr] = val & 0xdf;
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val & 0xf7;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* L1 Cache */
dev->pci_conf[addr] = val;
cpu_cache_int_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x47:
dev->pci_conf[addr] = val & 0xfc;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, !(val & 0x20) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, !(val & 0x10) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
break;
case 0x48: /* SMRAM */
dev->pci_conf[addr] = val;
ali1531_smm_recalc((val >> 1) & 7, dev);
break;
case 0x49:
dev->pci_conf[addr] = val & 0x73;
break;
case 0x4c: /* Shadow RAM */
case 0x4d:
case 0x4e:
case 0x4f:
dev->pci_conf[addr] = val;
ali1531_shadow_recalc(dev);
break;
case 0x57: /* H2PO */
dev->pci_conf[addr] = val & 0x60;
if (!(val & 0x20))
outb(0x92, 0x01);
break;
case 0x58:
dev->pci_conf[addr] = val & 0x83;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0x4f;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x53;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x60: /* DRB's */
case 0x61:
case 0x62:
case 0x63:
case 0x64:
case 0x65:
case 0x66:
case 0x67:
case 0x68:
case 0x69:
case 0x6a:
case 0x6b:
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f:
dev->pci_conf[addr] = val;
spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 2);
break;
case 0x72:
dev->pci_conf[addr] = val & 0xf;
break;
case 0x74:
dev->pci_conf[addr] = val & 0x2b;
break;
case 0x80:
dev->pci_conf[addr] = val & 0x84;
break;
case 0x81:
dev->pci_conf[addr] = val & 0x81;
break;
case 0x83:
dev->pci_conf[addr] = val & 0x10;
break;
default:
dev->pci_conf[addr] = val;
break;
}
}
static uint8_t
ali1531_read(int func, int addr, void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
return dev->pci_conf[addr];
}
static void
ali1531_reset(void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x31;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0xb0;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0x20;
dev->pci_conf[0x0e] = 0x00;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x2c] = 0xb9;
dev->pci_conf[0x2d] = 0x10;
dev->pci_conf[0x2e] = 0x31;
dev->pci_conf[0x2f] = 0x15;
dev->pci_conf[0x52] = 0xf0;
dev->pci_conf[0x54] = 0xff;
dev->pci_conf[0x55] = 0xff;
dev->pci_conf[0x59] = 0x20;
dev->pci_conf[0x5a] = 0x20;
dev->pci_conf[0x70] = 0x22;
ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev);
ali1531_shadow_recalc(dev);
ali1531_write(0, 0x60, 0x08, dev);
ali1531_write(0, 0x61, 0x40, dev);
}
static void
ali1531_close(void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1531_init(const device_t *info)
{
ali1531_t *dev = (ali1531_t *)malloc(sizeof(ali1531_t));
memset(dev, 0, sizeof(ali1531_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev);
dev->smram = smram_add();
ali1531_reset(dev);
return dev;
}
const device_t ali1531_device = {
"ALi M1531 CPU-to-PCI Bridge",
DEVICE_PCI,
0,
ali1531_init,
ali1531_close,
ali1531_reset,
{NULL},
NULL,
NULL,
NULL};

957
src/chipset/ali1543.c Normal file
View File

@@ -0,0 +1,957 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1543 Desktop South Bridge.
*
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/ddma.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/smbus_piix4.h>
#include <86box/usb.h>
#include <86box/acpi.h>
#include <86box/chipset.h>
#ifdef ENABLE_ALI1543_LOG
int ali1543_do_log = ENABLE_ALI1543_LOG;
static void
ali1543_log(const char *fmt, ...)
{
va_list ap;
if (ali1543_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1543_log(fmt, ...)
#endif
typedef struct ali1543_t
{
uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256],
sio_regs[256], device_regs[8][256], sio_index, in_configuration_mode,
pci_slot, ide_slot, usb_slot, pmu_slot;
apm_t *apm;
acpi_t *acpi;
ddma_t *ddma;
fdc_t *fdc_controller;
nvr_t *nvr;
port_92_t *port_92;
serial_t *uart[2];
sff8038i_t *ide_controller[2];
smbus_piix4_t *smbus;
usb_t *usb;
} ali1543_t;
/*
Notes:
- Power Managment isn't functioning properly
- IDE isn't functioning properly
- 1543C differences have to be examined
- Some Chipset functionality might be missing
- Device numbers and types might be incorrect
- Code quality is abysmal and needs lot's of cleanup.
*/
void ali1533_ddma_handler(ali1543_t *dev)
{
for (uint8_t i = 0; i < 8; i++)
{
if (i != 4)
ddma_update_io_mapping(dev->ddma, i & 7, dev->pci_conf[0x73] & 0xf, dev->pci_conf[0x73] & 0xf0, dev->pci_conf[0x45] & 2);
}
}
void ali5229_ide_handler(ali1543_t *dev);
static void
ali1533_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
switch (addr)
{
case 0x04:
if (dev->pci_conf[0x5f] & 8)
dev->pci_conf[addr] = val;
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pci_conf[0x74] & 0x40)
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x42:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0x43:
dev->pci_conf[addr] = val;
if (val & 0x80)
port_92_add(dev->port_92);
else
port_92_remove(dev->port_92);
break;
case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */
dev->pci_conf[addr] = 0xdf;
if (dev->ide_conf[0x09] & 1)
sff_set_irq_line(dev->ide_controller[0], val & 0x0f);
break;
case 0x45: /* DDMA Enable */
dev->pci_conf[addr] = 0xcf;
ali1533_ddma_handler(dev);
break;
case 0x48: /* PCI IRQ Routing */
case 0x49:
dev->pci_conf[addr] = val;
pci_set_irq_routing(((addr & 1) * 2) + 2, ((val & 0xf0) == 0) ? (val & 0xf0) : PCI_IRQ_DISABLED);
pci_set_irq_routing(((addr & 1) * 2) + 1, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break;
case 0x53: /* USB Enable */
dev->pci_conf[addr] = val & 0xe7;
ohci_update_mem_mapping(dev->usb, 0x11, 0x12, 0x13, (dev->usb_conf[0x04] & 1) && (!(dev->pci_conf[0x53] & 0x40)));
break;
case 0x54: /* USB Control ? */
dev->pci_conf[addr] = val & 0xdf;
break;
case 0x57:
dev->pci_conf[addr] = val & 0xc7;
break;
case 0x58: /* IDE Enable */
dev->pci_conf[addr] = val & 0x7f;
ali5229_ide_handler(dev);
break;
case 0x59:
case 0x5a:
dev->pci_conf[addr] = val & 0x0e;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0x02;
break;
case 0x5c:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x02;
break;
case 0x5e:
dev->pci_conf[addr] = val & 0xe0;
break;
case 0x5f:
dev->pci_conf[addr] = val;
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0x6d:
dev->pci_conf[addr] = val & 0xbf;
break;
case 0x71:
case 0x72:
dev->pci_conf[addr] = val & 0xef;
break;
case 0x73: /* DDMA Base Address */
dev->pci_conf[addr] = val;
ali1533_ddma_handler(dev);
break;
case 0x74: /* USB IRQ Routing */
dev->pci_conf[addr] = val & 0xdf;
pci_set_irq_routing(dev->usb_slot, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break;
case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */
dev->pci_conf[addr] = val & 0x1f;
if (dev->ide_conf[0x09] & 8)
sff_set_irq_line(dev->ide_controller[1], val & 0x0f);
break;
case 0x76: /* PMU IRQ Routing */
dev->pci_conf[addr] = val & 0x1f;
acpi_set_irq_line(dev->acpi, val & 0x0f);
break;
case 0x77: /* SMBus IRQ Routing */
dev->pci_conf[addr] = val & 0x1f;
break;
default:
dev->pci_conf[addr] = val;
break;
}
}
static uint8_t
ali1533_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4)))
return 0;
else
return dev->pci_conf[addr];
}
void ali5229_ide_handler(ali1543_t *dev)
{
uint16_t native_base_pri_addr = (dev->ide_conf[0x11] | dev->ide_conf[0x10] << 8);
uint16_t native_side_pri_addr = (dev->ide_conf[0x15] | dev->ide_conf[0x14] << 8);
uint16_t native_base_sec_addr = (dev->ide_conf[0x19] | dev->ide_conf[0x18] << 8);
uint16_t native_side_sec_addr = (dev->ide_conf[0x1c] | dev->ide_conf[0x1b] << 8);
uint16_t comp_base_pri_addr = 0x01f0;
uint16_t comp_side_pri_addr = 0x03f6;
uint16_t comp_base_sec_addr = 0x0170;
uint16_t comp_side_sec_addr = 0x0376;
uint16_t current_pri_base, current_pri_side, current_sec_base, current_sec_side;
/* Primary Channel Programming */
if (!(dev->ide_conf[0x52] & 0x10))
{
current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_pri_addr : native_base_pri_addr;
current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_pri_addr : native_side_pri_addr;
}
else
{
current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_sec_addr : native_base_sec_addr;
current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_sec_addr : native_side_sec_addr;
}
/* Secondary Channel Programming */
if (!(dev->ide_conf[0x52] & 0x10))
{
current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_sec_addr : native_base_sec_addr;
current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_sec_addr : native_side_sec_addr;
}
else
{
current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_pri_addr : native_base_pri_addr;
current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_pri_addr : native_side_pri_addr;
}
/* Both channels use one port */
if (dev->ide_conf[0x52] & 0x40)
{
current_pri_base = current_sec_base;
current_pri_side = current_sec_side;
}
if (dev->ide_conf[0x52] & 0x20)
{
current_sec_base = current_pri_base;
current_sec_side = current_pri_side;
}
ide_pri_disable();
ide_sec_disable();
if (dev->pci_conf[0x58] & 0x40)
{
sff_set_irq_pin(dev->ide_controller[0], dev->ide_conf[0x3d] & 4);
sff_set_irq_pin(dev->ide_controller[1], dev->ide_conf[0x3d] & 4);
/* Primary Channel Setup */
if (dev->ide_conf[0x09] & 0x10)
{
if (!(dev->ide_conf[0x09] & 1))
sff_set_irq_line(dev->ide_controller[0], dev->ide_conf[0x3c] & 0xf);
ide_set_base(0, current_pri_base);
ide_set_side(0, current_pri_side);
sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x09] & 0x80, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8));
ide_pri_enable();
ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side);
}
/* Secondary Channel Setup */
if (dev->ide_conf[0x09] & 8)
{
if (!(dev->ide_conf[0x09] & 4))
sff_set_irq_line(dev->ide_controller[1], dev->ide_conf[0x3c] & 0xf);
ide_set_base(1, current_sec_base);
ide_set_side(1, current_sec_side);
sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x09] & 0x80, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8);
ide_sec_enable();
ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side);
}
}
}
static void
ali5229_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M5229: dev->ide_conf[%02x] = %02x\n", addr, val);
switch (addr)
{
case 0x09: /* Control */
if (dev->ide_conf[0x4d] & 0x80)
dev->ide_conf[addr] |= val & 0x8f;
else
dev->ide_conf[addr] = val;
ali5229_ide_handler(dev);
break;
case 0x10: /* Primary Base Address */
case 0x11:
case 0x12:
case 0x13:
case 0x14:
case 0x18: /* Secondary Base Address */
case 0x19:
case 0x1a:
case 0x1b:
case 0x1c:
case 0x20: /* Bus Mastering Base Address */
case 0x21:
case 0x22:
case 0x23:
dev->ide_conf[addr] = val;
ali5229_ide_handler(dev);
break;
/* The machines don't touch anything beyond that point so we avoid any programming */
case 0x2c: /* Subsystem Vendor */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->ide_conf[0x53] & 0x80)
dev->ide_conf[addr] = val;
break;
case 0x4d:
dev->ide_conf[addr] = val & 0x80;
break;
case 0x4f:
dev->ide_conf[addr] = val & 0x3f;
break;
case 0x50: /* Configuration */
dev->ide_conf[addr] = val & 0x2b;
break;
case 0x51:
dev->ide_conf[addr] = val & 0xf7;
break;
case 0x53: /* Subsystem Vendor ID */
dev->ide_conf[addr] = val & 0x8b;
break;
case 0x58:
dev->ide_conf[addr] = val & 3;
break;
case 0x59:
case 0x5a:
case 0x5b:
dev->ide_conf[addr] = val & 0x7f;
break;
case 0x5c:
dev->ide_conf[addr] = val & 3;
break;
case 0x5d:
case 0x5e:
case 0x5f:
dev->ide_conf[addr] = val & 0x7f;
break;
default:
dev->ide_conf[addr] = val;
break;
}
}
static uint8_t
ali5229_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
return dev->ide_conf[addr];
}
static void
ali5237_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val);
switch (addr)
{
case 0x04: /* USB Enable */
dev->usb_conf[addr] = val;
ohci_update_mem_mapping(dev->usb, 0x10, 0x11, 0x12, (dev->usb_conf[0x04] & 1) && (!(dev->pci_conf[0x53] & 0x40)));
break;
case 0x05:
dev->usb_conf[addr] = 0x03;
break;
case 0x06:
dev->usb_conf[addr] = 0xc0;
break;
case 0x11:
case 0x12:
case 0x13: /* USB Base I/O */
dev->usb_conf[addr] = val;
ohci_update_mem_mapping(dev->usb, 0x11, 0x12, 0x13, (dev->usb_conf[0x04] & 1) && (!(dev->pci_conf[0x53] & 0x40)));
break;
case 0x42:
dev->usb_conf[addr] = 0x10;
break;
default:
dev->usb_conf[addr] = val;
break;
}
}
static uint8_t
ali5237_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
return dev->usb_conf[addr];
}
static void
ali7101_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M7101: dev->pmu_conf[%02x] = %02x\n", addr, val);
switch (addr)
{
case 0x04: /* Enable PMU */
dev->pmu_conf[addr] = val & 0x1f;
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0x07:
dev->pmu_conf[addr] = val & 0xfe;
break;
case 0x10: /* PMU Base I/O */
case 0x11:
if (addr == 0x10)
dev->pmu_conf[addr] = (val & 0xe0) | 1;
else if (addr == 0x11)
dev->pmu_conf[addr] = val;
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0x14: /* SMBus Base I/O */
case 0x15:
dev->pmu_conf[addr] = val;
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pmu_conf[0xd8] & 0x10)
dev->pmu_conf[addr] = val;
case 0x40:
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x41:
dev->pmu_conf[addr] = val & 0x10;
break;
case 0x45:
dev->pmu_conf[addr] = val & 0x9f;
break;
case 0x46:
dev->pmu_conf[addr] = val & 0x18;
break;
case 0x48:
dev->pmu_conf[addr] = val & 0x9f;
break;
case 0x49:
dev->pmu_conf[addr] = val & 0x38;
break;
case 0x4c:
dev->pmu_conf[addr] = val & 5;
break;
case 0x4d:
dev->pmu_conf[addr] = val & 1;
break;
case 0x4e:
dev->pmu_conf[addr] = val & 5;
break;
case 0x4f:
dev->pmu_conf[addr] = val & 1;
break;
case 0x55: /* APM Timer */
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x59:
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x5b: /* ACPI/SMB Base I/O Control */
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x61:
dev->pmu_conf[addr] = val & 0x13;
break;
case 0x62:
dev->pmu_conf[addr] = val & 0xf1;
break;
case 0x63:
dev->pmu_conf[addr] = val & 3;
break;
case 0x65:
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x68:
dev->pmu_conf[addr] = val & 7;
break;
case 0x6e:
dev->pmu_conf[addr] = val & 0xef;
break;
case 0x6f:
dev->pmu_conf[addr] = val & 7;
break;
/* Continue Further Later */
case 0xc0: /* GPO Registers */
case 0xc1:
case 0xc2:
case 0xc3:
dev->pmu_conf[addr] = val;
acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2], dev->pmu_conf[0xc3]);
break;
case 0xe0:
dev->pmu_conf[addr] = val;
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
default:
dev->pmu_conf[addr] = val;
break;
}
}
static uint8_t
ali7101_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
return dev->pmu_conf[addr];
}
void ali1533_sio_fdc_handler(ali1543_t *dev)
{
fdc_remove(dev->fdc_controller);
if (dev->device_regs[0][0x30] & 1)
{
fdc_set_base(dev->fdc_controller, dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8));
fdc_set_irq(dev->fdc_controller, dev->device_regs[0][0x70] & 0xf);
fdc_set_dma_ch(dev->fdc_controller, dev->device_regs[0][0x74] & 0x07);
ali1543_log("M1543-SIO FDC: ADDR %04x IRQ %02x DMA %02x\n", dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8), dev->device_regs[0][0x70] & 0xf, dev->device_regs[0][0x74] & 0x07);
}
}
void ali1533_sio_uart_handler(int num, ali1543_t *dev)
{
serial_remove(dev->uart[num]);
if (dev->device_regs[num + 4][0x30] & 1)
{
serial_setup(dev->uart[num], dev->device_regs[num + 4][0x61] | (dev->device_regs[num + 4][0x60] << 8), dev->device_regs[num + 4][0x70] & 0xf);
ali1543_log("M1543-SIO UART%d: ADDR %04x IRQ %02x\n", num, dev->device_regs[num + 4][0x61] | (dev->device_regs[num + 4][0x60] << 8), dev->device_regs[num + 4][0x70] & 0xf);
}
}
void ali1533_sio_lpt_handler(ali1543_t *dev)
{
lpt1_remove();
if (dev->device_regs[3][0x30] & 1)
{
lpt1_init(dev->device_regs[3][0x61] | (dev->device_regs[3][0x60] << 8));
lpt1_irq(dev->device_regs[3][0x70] & 0xf);
ali1543_log("M1543-SIO LPT: ADDR %04x IRQ %02x\n", dev->device_regs[3][0x61] | (dev->device_regs[3][0x60] << 8), dev->device_regs[3][0x70] & 0xf);
}
}
void ali1533_sio_ldn(uint16_t ldn, ali1543_t *dev)
{
/* We don't include all LDN's */
switch (ldn)
{
case 0: /* FDC */
ali1533_sio_fdc_handler(dev);
break;
case 3: /* LPT */
ali1533_sio_lpt_handler(dev);
break;
case 4: /* UART */
case 5:
ali1533_sio_uart_handler(ldn - 4, dev);
break;
}
}
static void
ali1533_sio_write(uint16_t addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
switch (addr)
{
case 0x3f0:
dev->sio_index = val;
if (dev->sio_index == 0x51)
{
dev->in_configuration_mode = 1;
}
else if (dev->sio_index == 0xbb)
dev->in_configuration_mode = 0;
break;
case 0x3f1:
if (dev->in_configuration_mode)
{
switch (dev->sio_index)
{
case 0x07:
dev->sio_regs[dev->sio_index] = val & 0x7;
break;
case 0x22:
dev->sio_regs[dev->sio_index] = val & 0x39;
break;
case 0x23:
dev->sio_regs[dev->sio_index] = val & 0x38;
break;
default:
if ((dev->sio_index < 0x30) || (dev->sio_index == 0x51) || (dev->sio_index == 0xbb))
dev->sio_regs[dev->sio_index] = val;
else if (dev->sio_regs[0x07] <= 7)
dev->device_regs[dev->sio_regs[0x07]][dev->sio_index] = val;
break;
}
}
break;
}
if ((!dev->in_configuration_mode) && (dev->sio_regs[0x07] <= 7) && (addr == 0x03f0))
{
ali1533_sio_ldn(dev->sio_regs[0x07], dev);
}
}
static uint8_t
ali1533_sio_read(uint16_t addr, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
if (dev->sio_index >= 0x30)
return dev->device_regs[dev->sio_regs[0x07]][dev->sio_index];
else
return dev->sio_regs[dev->sio_index];
}
static void
ali1543_reset(void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
/* M1533 */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x33;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x0f;
dev->pci_conf[0x08] = 0xb4;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x48, 0x00, dev); // Disables all IRQ's
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
/* M5229 */
dev->ide_conf[0x00] = 0xb9;
dev->ide_conf[0x01] = 0x10;
dev->ide_conf[0x02] = 0x29;
dev->ide_conf[0x03] = 0x52;
dev->ide_conf[0x06] = 0x80;
dev->ide_conf[0x07] = 0x02;
dev->ide_conf[0x08] = 0x20;
dev->ide_conf[0x09] = 0xfa;
dev->ide_conf[0x0a] = 0x01;
dev->ide_conf[0x0b] = 0x01;
dev->ide_conf[0x10] = 0xf1;
dev->ide_conf[0x11] = 0x01;
dev->ide_conf[0x14] = 0xf5;
dev->ide_conf[0x15] = 0x03;
dev->ide_conf[0x18] = 0x71;
dev->ide_conf[0x19] = 0x01;
dev->ide_conf[0x1a] = 0x75;
dev->ide_conf[0x1b] = 0x03;
dev->ide_conf[0x20] = 0x01;
dev->ide_conf[0x23] = 0xf0;
dev->ide_conf[0x3d] = 0x01;
dev->ide_conf[0x3c] = 0x02;
dev->ide_conf[0x3d] = 0x03;
dev->ide_conf[0x54] = 0x55;
dev->ide_conf[0x55] = 0x55;
dev->ide_conf[0x63] = 0x01;
dev->ide_conf[0x64] = 0x02;
dev->ide_conf[0x67] = 0x01;
dev->ide_conf[0x78] = 0x21;
sff_set_slot(dev->ide_controller[0], dev->ide_slot);
sff_set_slot(dev->ide_controller[1], dev->ide_slot);
sff_bus_master_reset(dev->ide_controller[0], (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8));
sff_bus_master_reset(dev->ide_controller[1], ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8);
ali5229_ide_handler(dev);
/* M5237 */
dev->usb_conf[0x00] = 0xb9;
dev->usb_conf[0x01] = 0x10;
dev->usb_conf[0x02] = 0x37;
dev->usb_conf[0x03] = 0x52;
dev->usb_conf[0x06] = 0x80;
dev->usb_conf[0x07] = 0x02;
dev->usb_conf[0x08] = 0x03;
dev->usb_conf[0x09] = 0x10;
dev->usb_conf[0x0a] = 0x03;
dev->usb_conf[0x0b] = 0x0c;
dev->usb_conf[0x3d] = 0x01;
ali5237_write(0, 0x04, 0x00, dev);
/* M7101 */
dev->pmu_conf[0x00] = 0xb9;
dev->pmu_conf[0x01] = 0x10;
dev->pmu_conf[0x02] = 0x01;
dev->pmu_conf[0x03] = 0x71;
dev->pmu_conf[0x04] = 0x0f;
dev->pmu_conf[0x05] = 0x00;
dev->pmu_conf[0x0a] = 0x01;
dev->pmu_conf[0x0b] = 0x06;
acpi_set_slot(dev->acpi, dev->pmu_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
ali7101_write(0, 0x04, 0x00, dev);
ali7101_write(0, 0xc0, 0x00, dev);
/* M1543 Super I/O */
dev->device_regs[0][0x60] = 0x03;
dev->device_regs[0][0x61] = 0xf0;
dev->device_regs[0][0x70] = 0x06;
dev->device_regs[0][0x74] = 0x02;
dev->device_regs[0][0xf0] = 0x08;
dev->device_regs[0][0xf2] = 0xff;
dev->device_regs[3][0x60] = 0x03;
dev->device_regs[3][0x61] = 0x78;
dev->device_regs[3][0x70] = 0x05;
dev->device_regs[3][0x74] = 0x04;
dev->device_regs[3][0xf0] = 0x0c;
dev->device_regs[3][0xf1] = 0x05;
dev->device_regs[4][0x60] = 0x03;
dev->device_regs[4][0x61] = 0xf8;
dev->device_regs[4][0x70] = 0x04;
dev->device_regs[4][0xf1] = 0x02;
dev->device_regs[4][0xf2] = 0x0c;
dev->device_regs[5][0x60] = 0x02;
dev->device_regs[5][0x61] = 0xf8;
dev->device_regs[5][0x70] = 0x03;
dev->device_regs[5][0xf1] = 0x02;
dev->device_regs[5][0xf2] = 0x0c;
dev->device_regs[7][0x70] = 0x01;
ali1533_sio_fdc_handler(dev);
ali1533_sio_uart_handler(0, dev);
ali1533_sio_uart_handler(1, dev);
ali1533_sio_lpt_handler(dev);
}
static void
ali1543_close(void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
free(dev);
}
static void *
ali1543_init(const device_t *info)
{
ali1543_t *dev = (ali1543_t *)malloc(sizeof(ali1543_t));
memset(dev, 0, sizeof(ali1543_t));
/* Device 02: M1533 Southbridge */
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev);
/* Device 0B: M5229 IDE Controller*/
dev->ide_slot = pci_add_card(PCI_ADD_IDE, ali5229_read, ali5229_write, dev);
/* Device 0D: M5237 USB */
dev->usb_slot = pci_add_card(PCI_ADD_NORMAL_NOBRIDGE, ali5237_read, ali5237_write, dev);
/* Device 0C: M7101 Power Managment Controller */
dev->pmu_slot = pci_add_card(PCI_ADD_BRIDGE, ali7101_read, ali7101_write, dev);
/* Ports 3F0-1h: M1543 Super I/O */
io_sethandler(0x03f0, 0x0002, ali1533_sio_read, NULL, NULL, ali1533_sio_write, NULL, NULL, dev);
/* ACPI */
dev->acpi = device_add(&acpi_ali_device);
dev->nvr = device_add(&at_nvr_device); // Generic NVR
/* APM */
dev->apm = device_add(&apm_pci_device);
/* DMA */
dma_alias_set();
dma_high_page_init();
/* DDMA */
dev->ddma = device_add(&ddma_device);
/* Floppy Disk Controller */
dev->fdc_controller = device_add(&fdc_at_device);
/* IDE Controllers */
dev->ide_controller[0] = device_add_inst(&sff8038i_device, 1);
dev->ide_controller[1] = device_add_inst(&sff8038i_device, 2);
/* Port 92h */
dev->port_92 = device_add(&port_92_pci_device);
/* Serial NS16500 */
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
/* Standard SMBus */
dev->smbus = device_add(&piix4_smbus_device);
/* Super I/O Configuration Mechanism */
dev->in_configuration_mode = 1;
/* USB */
dev->usb = device_add(&usb_device);
ali1543_reset(dev);
return dev;
}
const device_t ali1543_device = {
"ALi M1543 Desktop South Bridge",
DEVICE_PCI,
0,
ali1543_init,
ali1543_close,
ali1543_reset,
{NULL},
NULL,
NULL,
NULL};

190
src/chipset/cs4031.c
View File

@@ -12,7 +12,7 @@
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
* Copyright 2021 Tiseno100
*
*/
@@ -28,19 +28,15 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t index,
regs[256];
port_92_t * port_92;
uint8_t index,
regs[256];
port_92_t *port_92;
} cs4031_t;
#ifdef ENABLE_CS4031_LOG
@@ -50,10 +46,11 @@ cs4031_log(const char *fmt, ...)
{
va_list ap;
if (cs4031_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
if (cs4031_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
@@ -62,139 +59,130 @@ cs4031_log(const char *fmt, ...)
static void cs4031_shadow_recalc(cs4031_t *dev)
{
mem_set_mem_state_both(0xa0000, 0x10000, (dev->regs[0x18] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xb0000, 0x10000, (dev->regs[0x18] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
uint32_t romc0000, romc4000, romc8000, romcc000, romd0000, rome0000, romf0000;
/* Register 18h */
if(dev->regs[0x18] & 0x01)
mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if(dev->regs[0x18] & 0x02)
mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
/* Register 19h-1ah-1bh*/
shadowbios = (dev->regs[0x19] & 0x40);
shadowbios_write = (dev->regs[0x1a] & 0x40);
/* ROMCS only functions if shadow write is disabled */
romc0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x01)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
romc4000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x02)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
romc8000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x04)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
romcc000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x08)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
romd0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
rome0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x20)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
romf0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x40)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0x19] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x01) ? MEM_WRITE_INTERNAL : romc0000));
mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0x19] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x02) ? MEM_WRITE_INTERNAL : romc4000));
mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0x19] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x04) ? MEM_WRITE_INTERNAL : romc8000));
mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0x19] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x08) ? MEM_WRITE_INTERNAL : romcc000));
mem_set_mem_state_both(0xd0000, 0x10000, ((dev->regs[0x19] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x10) ? MEM_WRITE_INTERNAL : romd0000));
mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x19] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x20) ? MEM_WRITE_INTERNAL : rome0000));
mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x19] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x40) ? MEM_WRITE_INTERNAL : romf0000));
for (uint32_t i = 0; i < 7; i++)
{
if (i < 4)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
else
mem_set_mem_state_both(0xd0000 + ((i - 4) << 16), 0x10000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
shadowbios = !!(dev->regs[0x19] & 0x40);
shadowbios_write = !!(dev->regs[0x1a] & 0x40);
}
static void
cs4031_write(uint16_t addr, uint8_t val, void *priv)
{
cs4031_t *dev = (cs4031_t *) priv;
cs4031_t *dev = (cs4031_t *)priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
switch (addr)
{
case 0x22:
dev->index = val;
break;
case 0x23:
cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
dev->regs[dev->index] = val;
switch(dev->index){
case 0x06:
cpu_update_waitstates();
switch (dev->index)
{
case 0x05:
dev->regs[dev->index] = val & 0x3f;
break;
case 0x18:
case 0x19:
case 0x1a:
case 0x1b:
case 0x06:
dev->regs[dev->index] = val & 0xbc;
break;
case 0x07:
dev->regs[dev->index] = val & 0x0f;
break;
case 0x10:
dev->regs[dev->index] = val & 0x3d;
break;
case 0x11:
dev->regs[dev->index] = val & 0x8d;
break;
case 0x12:
case 0x13:
dev->regs[dev->index] = val & 0x8d;
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
dev->regs[dev->index] = val & 0x7f;
break;
case 0x18:
dev->regs[dev->index] = val & 0xf3;
cs4031_shadow_recalc(dev);
break;
case 0x1c:
if(dev->regs[0x1c] & 0x20)
port_92_add(dev->port_92);
else
port_92_remove(dev->port_92);
case 0x19:
case 0x1a:
dev->regs[dev->index] = val & 0x7f;
cs4031_shadow_recalc(dev);
break;
case 0x1b:
dev->regs[dev->index] = val;
break;
case 0x1c:
dev->regs[dev->index] = val & 0xb3;
port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
break;
}
break;
break;
}
}
static uint8_t
cs4031_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
cs4031_t *dev = (cs4031_t *) priv;
cs4031_t *dev = (cs4031_t *)priv;
switch (addr) {
case 0x23:
ret = dev->regs[dev->index];
break;
}
return ret;
return (addr == 0x23) ? dev->regs[dev->index] : 0xff;
}
static void
cs4031_close(void *priv)
{
cs4031_t *dev = (cs4031_t *) priv;
cs4031_t *dev = (cs4031_t *)priv;
free(dev);
}
static void *
cs4031_init(const device_t *info)
{
cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
cs4031_t *dev = (cs4031_t *)malloc(sizeof(cs4031_t));
memset(dev, 0, sizeof(cs4031_t));
dev->port_92 = device_add(&port_92_device);
io_sethandler(0x022, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
io_sethandler(0x023, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
dev->regs[0x05] = 0x05;
dev->regs[0x18] = 0x00;
dev->regs[0x19] = 0x00;
dev->regs[0x1a] = 0x00;
dev->regs[0x1b] = 0x60;
cs4031_shadow_recalc(dev);
io_sethandler(0x0022, 0x0002, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
return dev;
}
const device_t cs4031_device = {
"Chips & Technogies CS4031",
0,
0,
cs4031_init, cs4031_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
cs4031_init,
cs4031_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

4
src/chipset/intel_82335.c
View File

@@ -104,8 +104,8 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
if (!EXTENDED_GRANULARITY_ENABLED)
{
shadowbios = (dev->regs[0x22] & 0x01);
shadowbios_write = (dev->regs[0x22] & 0x01);
shadowbios = !!(dev->regs[0x22] & 0x01);
shadowbios_write = !!(dev->regs[0x22] & 0x01);
/* Base System 512/640KB set */
mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);

151
src/chipset/opti283.c
View File

@@ -12,7 +12,7 @@
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
* Copyright 2021 Tiseno100
*
*/
@@ -28,144 +28,125 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#ifdef ENABLE_OPTI283_LOG
int opti283_do_log = ENABLE_OPTI283_LOG;
static void
opti283_log(const char *fmt, ...)
{
va_list ap;
if (opti283_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define opti283_log(fmt, ...)
#endif
typedef struct
{
uint8_t index,
regs[256];
uint8_t index,
regs[256];
} opti283_t;
static void opti283_shadow_recalc(opti283_t *dev)
{
uint32_t base, i;
uint32_t shflagsc, shflagsd, shflagse, shflagsf;
mem_set_mem_state_both(0xf0000, 0x10000, (dev->regs[0x11] & 0x80) ? (MEM_READ_EXTANY | MEM_WRITE_INTERNAL) : (MEM_READ_INTERNAL | ((dev->regs[0x14] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED)));
shadowbios = !(dev->regs[0x11] & 0x80);
shadowbios_write = (dev->regs[0x11] & 0x80);
for (uint32_t i = 0; i < 4; i++)
{
if (dev->regs[0x11] & 0x40)
mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (dev->regs[0x12] & (1 << (4 + i))) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 4) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if(dev->regs[0x11] & 0x10){
shflagsc = MEM_READ_INTERNAL;
shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagsc = disabled_shadow;
if(dev->regs[0x11] & 0x20){
shflagsd = MEM_READ_INTERNAL;
shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagsd = disabled_shadow;
if(dev->regs[0x11] & 0x40){
shflagse = MEM_READ_INTERNAL;
shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagse = disabled_shadow;
if(!(dev->regs[0x11] & 0x80)){
shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
mem_set_mem_state_both(0xf0000, 0x10000, shflagsf);
for(i = 4; i < 8; i++){
base = 0xc0000 + ((i-4) << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow);
}
for(i = 0; i < 4; i++){
base = 0xd0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow);
}
for(i = 4; i < 8; i++){
base = 0xe0000 + ((i-4) << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow);
}
if (dev->regs[0x11] & 0x20)
mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, (dev->regs[0x12] & (1 << i)) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
else
mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->regs[0x11] & 0x10)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (dev->regs[0x13] & (1 << (4 + i))) ? (MEM_READ_INTERNAL | ((dev->regs[0x11] & 1) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
else
mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
static void
opti283_write(uint16_t addr, uint8_t val, void *priv)
{
opti283_t *dev = (opti283_t *) priv;
opti283_t *dev = (opti283_t *)priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x24:
/* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */
dev->regs[dev->index] = val;
switch (addr)
{
case 0x22:
dev->index = val;
break;
case 0x24:
opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);
switch(dev->index){
case 0x10:
cpu_update_waitstates();
switch (dev->index)
{
case 0x10:
dev->regs[dev->index] = val;
break;
case 0x11:
case 0x12:
case 0x13:
case 0x11:
case 0x12:
case 0x13:
case 0x14:
dev->regs[dev->index] = val;
opti283_shadow_recalc(dev);
break;
}
break;
break;
}
}
static uint8_t
opti283_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti283_t *dev = (opti283_t *) priv;
switch (addr) {
case 0x24:
ret = dev->regs[dev->index];
break;
}
return ret;
opti283_t *dev = (opti283_t *)priv;
return (addr == 0x24) ? dev->regs[dev->index] : 0xff;
}
static void
opti283_close(void *priv)
{
opti283_t *dev = (opti283_t *) priv;
opti283_t *dev = (opti283_t *)priv;
free(dev);
}
static void *
opti283_init(const device_t *info)
{
opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
opti283_t *dev = (opti283_t *)malloc(sizeof(opti283_t));
memset(dev, 0, sizeof(opti283_t));
io_sethandler(0x022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
dev->regs[0x10] = 0x3f;
dev->regs[0x11] = 0xf0;
opti283_shadow_recalc(dev);
return dev;
}
const device_t opti283_device = {
"OPTi 82C283",
0,
0,
opti283_init, opti283_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
opti283_init,
opti283_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

30
src/chipset/sis_5571.c
View File

@@ -88,8 +88,8 @@ sis_5571_shadow_recalc(sis_5571_t *dev)
can_read = (dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
can_write = (dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shadowbios = (dev->pci_conf[0x76] & 0x80);
shadowbios_write = (dev->pci_conf[0x76] & 0x20);
shadowbios = !!(dev->pci_conf[0x76] & 0x80);
shadowbios_write = !!(dev->pci_conf[0x76] & 0x20);
mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
flushmmucache();
@@ -210,9 +210,9 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0xec;
break;
case 0x51: /* Cache */
case 0x51: /* L2 Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x40);
cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates();
break;
@@ -263,7 +263,7 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x83:
dev->pci_conf[addr] = val;
port_92_set_features(dev->port_92, (val & 0x40), (val & 0x80));
port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
break;
case 0x87:
@@ -272,7 +272,9 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x93: /* APM SMI */
dev->pci_conf[addr] = val;
apm_set_do_smi(dev->apm, ((dev->pci_conf[0x9b] & 0x01) && (val & 0x02)));
apm_set_do_smi(dev->apm, !!((dev->pci_conf[0x9b] & 0x01) && (val & 0x02)));
if (val & 0x02)
dev->pci_conf[0x9d] |= 1;
break;
case 0x94:
@@ -326,7 +328,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x43:
case 0x44:
dev->pci_conf_sb[0][addr] = val & 0x8f;
pci_set_irq_routing(PCI_INTA + (val & 0x07), !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
pci_set_irq_routing((addr & 0x07), !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break;
case 0x45:
@@ -415,7 +417,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
}
sis_5571_log("IDE Controller: dev->pci_conf[%02x] = %02x\n", addr, val);
if ((addr == 0x09) || ((addr >= 0x10) && (addr <= 0x23)) || (addr == 0x4a))
if (((addr >= 0x09) && (addr <= 0x23)) || (addr == 0x4a))
sis_5571_ide_handler(dev);
break;
@@ -593,7 +595,6 @@ sis_5571_init(const device_t *info)
pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev);
dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev);
pci_enable_mirq(1);
/* APM */
dev->apm = device_add(&apm_pci_device);
@@ -601,16 +602,19 @@ sis_5571_init(const device_t *info)
/* DMA */
dma_alias_set();
/* MIRQ */
pci_enable_mirq(0);
/* Port 92 & SMRAM */
dev->port_92 = device_add(&port_92_pci_device);
dev->smram = smram_add();
/* SFF IDE */
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
dev->program_status_pri = 0;
dev->program_status_sec = 0;
/* Port 92 & SMRAM */
dev->port_92 = device_add(&port_92_pci_device);
dev->smram = smram_add();
/* USB */
dev->usb = device_add(&usb_device);

179
src/chipset/umc491.c
View File

@@ -1,179 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 491/493 chipset.
*
*
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC491_LOG
int ali1429_do_log = ENABLE_UMC491_LOG;
static void
umc491_log(const char *fmt, ...)
{
va_list ap;
if (umc491_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define umc491_log(fmt, ...)
#endif
typedef struct
{
uint8_t index,
regs[256];
} umc491_t;
static void umc491_shadow_recalc(umc491_t *dev)
{
shadowbios = (dev->regs[0xcc] & 0x40);
shadowbios_write = (dev->regs[0xcc] & 0x80);
mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0xcd] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0xcd] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0xcd] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0xcd] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcd] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd0000, 0x4000, ((dev->regs[0xce] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd4000, 0x4000, ((dev->regs[0xce] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xd8000, 0x4000, ((dev->regs[0xce] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xdc000, 0x4000, ((dev->regs[0xce] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xce] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
/*
Our machine has the E segment into parts although most AMI machines treat it as one.
Probably a flaw by the BIOS as only one register gets enabled for it anyways.
*/
mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0xcc] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcc] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0xcc] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0xcc] & 0x80) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
flushmmucache();
}
static void
umc491_write(uint16_t addr, uint8_t val, void *priv)
{
umc491_t *dev = (umc491_t *) priv;
switch (addr) {
case 0x8022:
dev->index = val;
break;
case 0x8024:
umc491_log("UMC 491: dev->regs[%02x] = %02x\n", dev->index, val);
dev->regs[dev->index] = val;
switch(dev->index)
{
case 0xcc:
case 0xcd:
case 0xce:
umc491_shadow_recalc(dev);
break;
case 0xd0:
cpu_update_waitstates();
break;
case 0xd1:
cpu_cache_ext_enabled = (val & 0x01);
break;
}
break;
}
}
static uint8_t
umc491_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
umc491_t *dev = (umc491_t *) priv;
switch (addr) {
case 0x8024:
ret = dev->regs[dev->index];
break;
}
return ret;
}
static void
umc491_close(void *priv)
{
umc491_t *dev = (umc491_t *) priv;
free(dev);
}
static void *
umc491_init(const device_t *info)
{
umc491_t *dev = (umc491_t *) malloc(sizeof(umc491_t));
memset(dev, 0, sizeof(umc491_t));
device_add(&port_92_device);
/*
UMC 491/493 Ports
8022h Index Port
8024h Data Port
*/
io_sethandler(0x8022, 0x0001, umc491_read, NULL, NULL, umc491_write, NULL, NULL, dev);
io_sethandler(0x8024, 0x0001, umc491_read, NULL, NULL, umc491_write, NULL, NULL, dev);
dev->regs[0xcc] = 0x00;
dev->regs[0xcd] = 0x00;
dev->regs[0xce] = 0x00;
umc491_shadow_recalc(dev);
return dev;
}
const device_t umc491_device = {
"UMC 491/493",
0,
0,
umc491_init, umc491_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/via_apollo.c
View File

@@ -36,11 +36,11 @@
#include <86box/chipset.h>
#include <86box/spd.h>
#define VIA_585 0x05850000
#define VIA_585 0x05851000
#define VIA_595 0x05950000
#define VIA_597 0x05970100
#define VIA_598 0x05980000
#define VIA_691 0x06910000
#define VIA_691 0x06910600
#define VIA_693A 0x06914400
#define VIA_694 0x0691c200
#define VIA_8601 0x86010500

688
src/chipset/wd76c10.c
View File

@@ -6,234 +6,424 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the WD76C10 System Controller chip.
* Implementation of the Western Digital WD76C10 chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
* Authors: Tiseno100
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Copyright 2021 Tiseno100
*
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
* Copyright 2017-2019 Fred N. van Kempen.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/keyboard.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/video.h>
#include <86box/chipset.h>
/* Lock/Unlock Procedures */
#define LOCK dev->lock
#define UNLOCKED !dev->lock
typedef struct {
int type;
#define ENABLE_WD76C10_LOG 1
uint16_t reg_0092;
uint16_t reg_2072;
uint16_t reg_2872;
uint16_t reg_5872;
#ifdef ENABLE_WD76C10_LOG
int wd76c10_do_log = ENABLE_WD76C10_LOG;
static void
wd76c10_log(const char *fmt, ...)
{
va_list ap;
uint16_t reg_f872;
if (wd76c10_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define wd76c10_log(fmt, ...)
#endif
serial_t *uart[2];
typedef struct
{
uint16_t lock_reg, oscillator_40mhz, cache_flush, ems_page_reg,
ems_page_reg_pointer, port_shadow, pmc_interrupt,
high_mem_protect_boundry, delay_line, diagnostic,
nmi_status, pmc_input, pmc_timer,
pmc_output, ems_control_low_address_boundry, shadow_ram,
split_addr, bank32staddr, bank10staddr,
non_page_mode_dram_timing, mem_control,
refresh_control, disk_chip_select, prog_chip_sel_addr,
bus_timing_power_down_ctl, clk_control;
fdc_t *fdc;
int lock;
mem_mapping_t extram_mapping;
uint8_t extram[65536];
fdc_t *fdc_controller;
mem_mapping_t *mem_mapping;
serial_t *uart[2];
} wd76c10_t;
static void wd76c10_refresh_control(wd76c10_t *dev)
{
serial_remove(dev->uart[1]);
/* Serial B */
switch ((dev->refresh_control >> 1) & 7)
{
case 1:
serial_setup(dev->uart[1], 0x3f8, 3);
break;
case 2:
serial_setup(dev->uart[1], 0x2f8, 3);
break;
case 3:
serial_setup(dev->uart[1], 0x3e8, 3);
break;
case 4:
serial_setup(dev->uart[1], 0x2e8, 3);
break;
}
serial_remove(dev->uart[0]);
/* Serial A */
switch ((dev->refresh_control >> 5) & 7)
{
case 1:
serial_setup(dev->uart[0], 0x3f8, 4);
break;
case 2:
serial_setup(dev->uart[0], 0x2f8, 4);
break;
case 3:
serial_setup(dev->uart[0], 0x3e8, 4);
break;
case 4:
serial_setup(dev->uart[0], 0x2e8, 4);
break;
}
lpt1_remove();
/* LPT */
switch ((dev->refresh_control >> 9) & 3)
{
case 1:
lpt1_init(0x3bc);
lpt1_irq(7);
break;
case 2:
lpt1_init(0x378);
lpt1_irq(7);
break;
case 3:
lpt1_init(0x278);
lpt1_irq(7);
break;
}
}
static void wd76c10_split_addr(wd76c10_t *dev)
{
switch ((dev->split_addr >> 8) & 3)
{
case 1:
if (((dev->shadow_ram >> 8) & 3) == 2)
mem_remap_top(256);
break;
case 2:
if (((dev->shadow_ram >> 8) & 3) == 1)
mem_remap_top(320);
break;
case 3:
if (((dev->shadow_ram >> 8) & 3) == 3)
mem_remap_top(384);
break;
}
}
static void wd76c10_disk_chip_select(wd76c10_t *dev)
{
ide_pri_disable();
if (!(dev->disk_chip_select & 1))
{
ide_set_base(0, !(dev->disk_chip_select & 0x0010) ? 0x1f0 : 0x170);
ide_set_side(0, !(dev->disk_chip_select & 0x0010) ? 0x3f6 : 0x376);
}
ide_pri_enable();
fdc_remove(dev->fdc_controller);
if (!(dev->disk_chip_select & 2))
fdc_set_base(dev->fdc_controller, !(dev->disk_chip_select & 0x0010) ? 0x3f0 : 0x370);
}
static void wd76c10_shadow_recalc(wd76c10_t *dev)
{
switch ((dev->shadow_ram >> 14) & 3)
{
case 0:
mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 1:
mem_set_mem_state_both(0x80000, 0x20000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
break;
case 2:
mem_set_mem_state_both(0x40000, 0x60000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
break;
case 3:
mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
break;
}
switch ((dev->shadow_ram >> 8) & 3)
{
case 0:
mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
break;
case 2:
mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
break;
case 3:
mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
break;
}
}
static void
wd76c10_write(uint16_t addr, uint16_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
if (UNLOCKED)
{
switch (addr)
{
case 0x1072:
dev->clk_control = val;
break;
case 0x1872:
dev->bus_timing_power_down_ctl = val;
break;
case 0x2072:
dev->refresh_control = val;
wd76c10_refresh_control(dev);
break;
case 0x2872:
dev->disk_chip_select = val;
wd76c10_disk_chip_select(dev);
break;
case 0x3072:
dev->prog_chip_sel_addr = val;
break;
case 0x3872:
dev->non_page_mode_dram_timing = val;
break;
case 0x4072:
dev->mem_control = val;
break;
case 0x4872:
dev->bank10staddr = val;
break;
case 0x5072:
dev->bank32staddr = val;
break;
case 0x5872:
dev->split_addr = val;
wd76c10_split_addr(dev);
break;
case 0x6072:
dev->shadow_ram = val & 0xffbf;
wd76c10_shadow_recalc(dev);
break;
case 0x6872:
dev->ems_control_low_address_boundry = val & 0xecff;
break;
case 0x7072:
dev->pmc_output = (val >> 8) & 0x00ff;
break;
case 0x7872:
dev->pmc_output = val & 0xff00;
break;
case 0x8072:
dev->pmc_timer = val;
break;
case 0x8872:
dev->pmc_input = val;
break;
case 0x9072:
dev->nmi_status = val & 0x00fc;
break;
case 0x9872:
dev->diagnostic = val & 0xfdff;
break;
case 0xa072:
dev->delay_line = val;
break;
case 0xc872:
dev->pmc_interrupt = val & 0xfcfc;
break;
case 0xf072:
dev->oscillator_40mhz = 0;
break;
case 0xf472:
dev->oscillator_40mhz = 1;
break;
case 0xf872:
dev->cache_flush = val;
flushmmucache();
break;
}
wd76c10_log("WD76C10: dev->regs[%04x] = %04x\n", addr, val);
}
switch (addr)
{
case 0xe072:
dev->ems_page_reg_pointer = val & 0x003f;
break;
case 0xe872:
dev->ems_page_reg = val & 0x8fff;
break;
case 0xf073:
dev->lock_reg = val & 0x00ff;
LOCK = !(val && 0x00da);
break;
}
}
static uint16_t
wd76c10_read(uint16_t port, void *priv)
wd76c10_read(uint16_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
int16_t ret = 0xffff;
wd76c10_log("WD76C10: R dev->regs[%04x]\n", addr);
switch (addr)
{
case 0x1072:
return dev->clk_control;
switch (port) {
case 0x2072:
ret = dev->reg_2072;
break;
case 0x1872:
return dev->bus_timing_power_down_ctl;
case 0x2872:
ret = dev->reg_2872;
break;
case 0x2072:
return dev->refresh_control;
case 0x5872:
ret = dev->reg_5872;
break;
case 0x2872:
return dev->disk_chip_select;
case 0xf872:
ret = dev->reg_f872;
break;
}
case 0x3072:
return dev->prog_chip_sel_addr;
return(ret);
}
case 0x3872:
return dev->non_page_mode_dram_timing;
case 0x4072:
return dev->mem_control;
static void
wd76c10_write(uint16_t port, uint16_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
case 0x4872:
return dev->bank10staddr;
switch (port) {
case 0x2072:
dev->reg_2072 = val;
case 0x5072:
return dev->bank32staddr;
serial_remove(dev->uart[0]);
if (!(val & 0x10))
{
switch ((val >> 5) & 7)
{
case 1: serial_setup(dev->uart[0], 0x3f8, 4); break;
case 2: serial_setup(dev->uart[0], 0x2f8, 4); break;
case 3: serial_setup(dev->uart[0], 0x3e8, 4); break;
case 4: serial_setup(dev->uart[0], 0x2e8, 4); break;
default: break;
}
}
serial_remove(dev->uart[1]);
if (!(val & 0x01))
{
switch ((val >> 1) & 7)
{
case 1: serial_setup(dev->uart[1], 0x3f8, 3); break;
case 2: serial_setup(dev->uart[1], 0x2f8, 3); break;
case 3: serial_setup(dev->uart[1], 0x3e8, 3); break;
case 4: serial_setup(dev->uart[1], 0x2e8, 3); break;
default: break;
}
}
break;
case 0x5872:
return dev->split_addr;
case 0x2872:
dev->reg_2872 = val;
case 0x6072:
return dev->shadow_ram;
fdc_remove(dev->fdc);
if (! (val & 1))
fdc_set_base(dev->fdc, 0x03f0);
break;
case 0x6872:
return dev->ems_control_low_address_boundry;
case 0x5872:
dev->reg_5872 = val;
break;
case 0x7072:
return (dev->pmc_output << 8) & 0xff00;
case 0xf872:
dev->reg_f872 = val;
switch (val & 3) {
case 0:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
if (val & 4)
mem_mapping_enable(&dev->extram_mapping);
else
mem_mapping_disable(&dev->extram_mapping);
flushmmucache_nopc();
break;
case 0x7872:
return (dev->pmc_output) & 0xff00;
case 0x8072:
return dev->pmc_timer;
case 0x8872:
return dev->pmc_input;
case 0x9072:
return dev->nmi_status;
case 0x9872:
return dev->diagnostic;
case 0xa072:
return dev->delay_line;
case 0xb872:
return (inb(0x040b) << 8) | inb(0x04d6);
case 0xc872:
return dev->pmc_interrupt;
case 0xd072:
return dev->port_shadow;
case 0xe072:
return dev->ems_page_reg_pointer;
case 0xe872:
return dev->ems_page_reg;
case 0xfc72:
return 0x0ff0;
default:
return 0xffff;
}
}
static uint8_t
wd76c10_readb(uint16_t port, void *priv)
{
if (port & 1)
return(wd76c10_read(port & ~1, priv) >> 8);
return(wd76c10_read(port, priv) & 0xff);
}
static void
wd76c10_writeb(uint16_t port, uint8_t val, void *priv)
{
uint16_t temp = wd76c10_read(port, priv);
if (port & 1)
wd76c10_write(port & ~1, (temp & 0x00ff) | (val << 8), priv);
else
wd76c10_write(port , (temp & 0xff00) | val, priv);
}
uint8_t
wd76c10_read_extram(uint32_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
return dev->extram[addr & 0xffff];
}
uint16_t
wd76c10_read_extramw(uint32_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
return *(uint16_t *)&dev->extram[addr & 0xffff];
}
uint32_t
wd76c10_read_extraml(uint32_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
return *(uint32_t *)&dev->extram[addr & 0xffff];
}
void
wd76c10_write_extram(uint32_t addr, uint8_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
dev->extram[addr & 0xffff] = val;
}
void
wd76c10_write_extramw(uint32_t addr, uint16_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
*(uint16_t *)&dev->extram[addr & 0xffff] = val;
}
void
wd76c10_write_extraml(uint32_t addr, uint32_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
*(uint32_t *)&dev->extram[addr & 0xffff] = val;
}
static void
wd76c10_close(void *priv)
{
@@ -242,51 +432,119 @@ wd76c10_close(void *priv)
free(dev);
}
static void *
wd76c10_init(const device_t *info)
{
wd76c10_t *dev;
wd76c10_t *dev = (wd76c10_t *)malloc(sizeof(wd76c10_t));
memset(dev, 0, sizeof(wd76c10_t));
dev = (wd76c10_t *) malloc(sizeof(wd76c10_t));
memset(dev, 0x00, sizeof(wd76c10_t));
dev->type = info->local;
device_add(&port_92_inv_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
dev->fdc_controller = device_add(&fdc_at_device);
device_add(&ide_isa_device);
dev->fdc = (fdc_t *)device_add(&fdc_at_device);
/* Lock Configuration */
LOCK = 1;
dev->uart[0] = device_add_inst(&i8250_device, 1);
dev->uart[1] = device_add_inst(&i8250_device, 2);
/* Clock Control */
io_sethandler(0x1072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
device_add(&port_92_word_device);
/* Bus Timing & Power Down Control */
io_sethandler(0x1872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
io_sethandler(0x2072, 2,
wd76c10_readb,wd76c10_read,NULL,
wd76c10_writeb,wd76c10_write,NULL, dev);
io_sethandler(0x2872, 2,
wd76c10_readb,wd76c10_read,NULL,
wd76c10_writeb,wd76c10_write,NULL, dev);
io_sethandler(0x5872, 2,
wd76c10_readb,wd76c10_read,NULL,
wd76c10_writeb,wd76c10_write,NULL, dev);
io_sethandler(0xf872, 2,
wd76c10_readb,wd76c10_read,NULL,
wd76c10_writeb,wd76c10_write,NULL, dev);
/* Refresh Control(Serial & Parallel) */
io_sethandler(0x2072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
mem_mapping_add(&dev->extram_mapping, 0xd0000, 0x10000,
wd76c10_read_extram,wd76c10_read_extramw,wd76c10_read_extraml,
wd76c10_write_extram,wd76c10_write_extramw,wd76c10_write_extraml,
dev->extram, MEM_MAPPING_EXTERNAL, dev);
mem_mapping_disable(&dev->extram_mapping);
/* Disk Chip Select */
io_sethandler(0x2872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
return(dev);
/* Programmable Chip Select Address(Needs more further examination!) */
io_sethandler(0x3072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Bank 1 & 0 Start Address */
io_sethandler(0x4872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Bank 3 & 2 Start Address */
io_sethandler(0x5072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Split Address */
io_sethandler(0x5872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* EMS Control & EMS Low level boundry */
io_sethandler(0x6072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* EMS Control & EMS Low level boundry */
io_sethandler(0x6872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* PMC Output */
io_sethandler(0x7072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* PMC Output */
io_sethandler(0x7872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* PMC Status */
io_sethandler(0x8072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* PMC Status */
io_sethandler(0x8872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* NMI Status (Needs further checkup) */
io_sethandler(0x9072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Diagnostics */
io_sethandler(0x9872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Delay Line */
io_sethandler(0xa072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* DMA Mode Shadow(Needs Involvement on the DMA code) */
io_sethandler(0xb872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
/* High Memory Protection Boundry */
io_sethandler(0xc072, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
/* PMC Interrupt Enable */
io_sethandler(0xc872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
/* Port Shadow (Needs further lookup) */
io_sethandler(0xd072, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
/* EMS Page Register Pointer */
io_sethandler(0xe072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* EMS Page Register */
io_sethandler(0xe872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
/* Lock/Unlock Configuration */
io_sethandler(0xf073, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
/* 40Mhz Oscillator Enable Disable */
io_sethandler(0xf072, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
io_sethandler(0xf472, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
/* Lock Status */
io_sethandler(0xfc72, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
/* Cache Flush */
io_sethandler(0xf872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
dma_ext_mode_init();
wd76c10_shadow_recalc(dev);
wd76c10_refresh_control(dev);
wd76c10_disk_chip_select(dev);
return dev;
}
const device_t wd76c10_device = {
"WD 76C10",
"Western Digital WD76C10",
0,
0,
wd76c10_init, wd76c10_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
wd76c10_init,
wd76c10_close,
NULL,
{NULL},
NULL,
NULL,
NULL};