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Added the IBM 5161 ISA expansion for PC and XT;

Browse Source 
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g  / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
This commit is contained in:
OBattler
2019-09-20 14:02:30 +02:00
parent b06296bbf6
commit 552a87ea3d
524 changed files with 129555 additions and 21862 deletions
Download Patch File Download Diff File Expand all files Collapse all files

276
src/cpu/x86_ops_string.h
View File

@@ -1,8 +1,12 @@
static int opMOVSB_a16(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI--; SI--; }
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
@@ -10,9 +14,13 @@ static int opMOVSB_a16(uint32_t fetchdat)
}
static int opMOVSB_a32(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI--; ESI--; }
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
@@ -21,9 +29,13 @@ static int opMOVSB_a32(uint32_t fetchdat)
static int opMOVSW_a16(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
@@ -31,9 +43,13 @@ static int opMOVSW_a16(uint32_t fetchdat)
}
static int opMOVSW_a32(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
@@ -42,9 +58,13 @@ static int opMOVSW_a32(uint32_t fetchdat)
static int opMOVSL_a16(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 0);
@@ -52,9 +72,13 @@ static int opMOVSL_a16(uint32_t fetchdat)
}
static int opMOVSL_a32(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 1);
@@ -64,10 +88,14 @@ static int opMOVSL_a32(uint32_t fetchdat)
static int opCMPSB_a16(uint32_t fetchdat)
{
uint8_t src = readmemb(cpu_state.ea_seg->base, SI);
uint8_t dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
uint8_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmemb(cpu_state.ea_seg->base, SI);
dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
setsub8(src, dst);
if (flags & D_FLAG) { DI--; SI--; }
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
@@ -75,10 +103,14 @@ static int opCMPSB_a16(uint32_t fetchdat)
}
static int opCMPSB_a32(uint32_t fetchdat)
{
uint8_t src = readmemb(cpu_state.ea_seg->base, ESI);
uint8_t dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
uint8_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmemb(cpu_state.ea_seg->base, ESI);
dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
setsub8(src, dst);
if (flags & D_FLAG) { EDI--; ESI--; }
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
@@ -87,10 +119,14 @@ static int opCMPSB_a32(uint32_t fetchdat)
static int opCMPSW_a16(uint32_t fetchdat)
{
uint16_t src = readmemw(cpu_state.ea_seg->base, SI);
uint16_t dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
uint16_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmemw(cpu_state.ea_seg->base, SI);
dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
setsub16(src, dst);
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
@@ -98,10 +134,14 @@ static int opCMPSW_a16(uint32_t fetchdat)
}
static int opCMPSW_a32(uint32_t fetchdat)
{
uint16_t src = readmemw(cpu_state.ea_seg->base, ESI);
uint16_t dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
uint16_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmemw(cpu_state.ea_seg->base, ESI);
dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
setsub16(src, dst);
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
@@ -110,10 +150,14 @@ static int opCMPSW_a32(uint32_t fetchdat)
static int opCMPSL_a16(uint32_t fetchdat)
{
uint32_t src = readmeml(cpu_state.ea_seg->base, SI);
uint32_t dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
uint32_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmeml(cpu_state.ea_seg->base, SI);
dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
setsub32(src, dst);
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 0);
@@ -121,10 +165,14 @@ static int opCMPSL_a16(uint32_t fetchdat)
}
static int opCMPSL_a32(uint32_t fetchdat)
{
uint32_t src = readmeml(cpu_state.ea_seg->base, ESI);
uint32_t dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
uint32_t src, dst;
SEG_CHECK_READ(cpu_state.ea_seg);
SEG_CHECK_READ(&cpu_state.seg_es);
src = readmeml(cpu_state.ea_seg->base, ESI);
dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
setsub32(src, dst);
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 1);
@@ -133,8 +181,9 @@ static int opCMPSL_a32(uint32_t fetchdat)
static int opSTOSB_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememb(es, DI, AL); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI--;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
@@ -142,8 +191,9 @@ static int opSTOSB_a16(uint32_t fetchdat)
}
static int opSTOSB_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememb(es, EDI, AL); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI--;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
@@ -152,8 +202,9 @@ static int opSTOSB_a32(uint32_t fetchdat)
static int opSTOSW_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememw(es, DI, AX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
@@ -161,8 +212,9 @@ static int opSTOSW_a16(uint32_t fetchdat)
}
static int opSTOSW_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememw(es, EDI, AX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
@@ -171,8 +223,9 @@ static int opSTOSW_a32(uint32_t fetchdat)
static int opSTOSL_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememl(es, DI, EAX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
@@ -180,8 +233,9 @@ static int opSTOSL_a16(uint32_t fetchdat)
}
static int opSTOSL_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememl(es, EDI, EAX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 1);
@@ -191,9 +245,12 @@ static int opSTOSL_a32(uint32_t fetchdat)
static int opLODSB_a16(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
AL = temp;
if (flags & D_FLAG) SI--;
if (cpu_state.flags & D_FLAG) SI--;
else SI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
@@ -201,9 +258,12 @@ static int opLODSB_a16(uint32_t fetchdat)
}
static int opLODSB_a32(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
AL = temp;
if (flags & D_FLAG) ESI--;
if (cpu_state.flags & D_FLAG) ESI--;
else ESI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
@@ -212,9 +272,12 @@ static int opLODSB_a32(uint32_t fetchdat)
static int opLODSW_a16(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
AX = temp;
if (flags & D_FLAG) SI -= 2;
if (cpu_state.flags & D_FLAG) SI -= 2;
else SI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
@@ -222,9 +285,12 @@ static int opLODSW_a16(uint32_t fetchdat)
}
static int opLODSW_a32(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
AX = temp;
if (flags & D_FLAG) ESI -= 2;
if (cpu_state.flags & D_FLAG) ESI -= 2;
else ESI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
@@ -233,9 +299,12 @@ static int opLODSW_a32(uint32_t fetchdat)
static int opLODSL_a16(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
EAX = temp;
if (flags & D_FLAG) SI -= 4;
if (cpu_state.flags & D_FLAG) SI -= 4;
else SI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
@@ -243,9 +312,12 @@ static int opLODSL_a16(uint32_t fetchdat)
}
static int opLODSL_a32(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
EAX = temp;
if (flags & D_FLAG) ESI -= 4;
if (cpu_state.flags & D_FLAG) ESI -= 4;
else ESI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 1);
@@ -255,9 +327,12 @@ static int opLODSL_a32(uint32_t fetchdat)
static int opSCASB_a16(uint32_t fetchdat)
{
uint8_t temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
setsub8(AL, temp);
if (flags & D_FLAG) DI--;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
@@ -265,9 +340,12 @@ static int opSCASB_a16(uint32_t fetchdat)
}
static int opSCASB_a32(uint32_t fetchdat)
{
uint8_t temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
setsub8(AL, temp);
if (flags & D_FLAG) EDI--;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
@@ -276,9 +354,12 @@ static int opSCASB_a32(uint32_t fetchdat)
static int opSCASW_a16(uint32_t fetchdat)
{
uint16_t temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
setsub16(AX, temp);
if (flags & D_FLAG) DI -= 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
@@ -286,9 +367,12 @@ static int opSCASW_a16(uint32_t fetchdat)
}
static int opSCASW_a32(uint32_t fetchdat)
{
uint16_t temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
setsub16(AX, temp);
if (flags & D_FLAG) EDI -= 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
@@ -297,9 +381,12 @@ static int opSCASW_a32(uint32_t fetchdat)
static int opSCASL_a16(uint32_t fetchdat)
{
uint32_t temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
setsub32(EAX, temp);
if (flags & D_FLAG) DI -= 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 0);
@@ -307,9 +394,12 @@ static int opSCASL_a16(uint32_t fetchdat)
}
static int opSCASL_a32(uint32_t fetchdat)
{
uint32_t temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
setsub32(EAX, temp);
if (flags & D_FLAG) EDI -= 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 1);
@@ -319,10 +409,12 @@ static int opSCASL_a32(uint32_t fetchdat)
static int opINSB_a16(uint32_t fetchdat)
{
uint8_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
temp = inb(DX);
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI--;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
@@ -331,10 +423,12 @@ static int opINSB_a16(uint32_t fetchdat)
static int opINSB_a32(uint32_t fetchdat)
{
uint8_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
temp = inb(DX);
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI--;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
@@ -344,11 +438,13 @@ static int opINSB_a32(uint32_t fetchdat)
static int opINSW_a16(uint32_t fetchdat)
{
uint16_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
temp = inw(DX);
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
@@ -357,11 +453,13 @@ static int opINSW_a16(uint32_t fetchdat)
static int opINSW_a32(uint32_t fetchdat)
{
uint16_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
temp = inw(DX);
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
@@ -371,13 +469,15 @@ static int opINSW_a32(uint32_t fetchdat)
static int opINSL_a16(uint32_t fetchdat)
{
uint32_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
temp = inl(DX);
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 0);
@@ -386,13 +486,15 @@ static int opINSL_a16(uint32_t fetchdat)
static int opINSL_a32(uint32_t fetchdat)
{
uint32_t temp;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
temp = inl(DX);
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 1);
@@ -401,9 +503,12 @@ static int opINSL_a32(uint32_t fetchdat)
static int opOUTSB_a16(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
if (flags & D_FLAG) SI--;
if (cpu_state.flags & D_FLAG) SI--;
else SI++;
outb(DX, temp);
CLOCK_CYCLES(14);
@@ -412,9 +517,12 @@ static int opOUTSB_a16(uint32_t fetchdat)
}
static int opOUTSB_a32(uint32_t fetchdat)
{
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint8_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
if (flags & D_FLAG) ESI--;
if (cpu_state.flags & D_FLAG) ESI--;
else ESI++;
outb(DX, temp);
CLOCK_CYCLES(14);
@@ -424,10 +532,13 @@ static int opOUTSB_a32(uint32_t fetchdat)
static int opOUTSW_a16(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
if (flags & D_FLAG) SI -= 2;
if (cpu_state.flags & D_FLAG) SI -= 2;
else SI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
@@ -436,10 +547,13 @@ static int opOUTSW_a16(uint32_t fetchdat)
}
static int opOUTSW_a32(uint32_t fetchdat)
{
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint16_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
if (flags & D_FLAG) ESI -= 2;
if (cpu_state.flags & D_FLAG) ESI -= 2;
else ESI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
@@ -449,12 +563,15 @@ static int opOUTSW_a32(uint32_t fetchdat)
static int opOUTSL_a16(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
if (flags & D_FLAG) SI -= 4;
if (cpu_state.flags & D_FLAG) SI -= 4;
else SI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);
@@ -463,12 +580,15 @@ static int opOUTSL_a16(uint32_t fetchdat)
}
static int opOUTSL_a32(uint32_t fetchdat)
{
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
uint32_t temp;
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
if (flags & D_FLAG) ESI -= 4;
if (cpu_state.flags & D_FLAG) ESI -= 4;
else ESI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);