Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port; Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX); Finished the 586MC1; Added 8087 emulation; Moved Cyrix 6x86'es to the Dev branch; Sanitized/cleaned up memregs.c/h and intel.c/h; Split the chipsets from machines and sanitized Port 92 emulation; Added support for the 15bpp mode to the Compaq ATI 28800; Moved the MR 386DX and 486 machines to the Dev branch; Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00; Ported the new timer code from PCem; Cleaned up the CPU table of unused stuff and better optimized its structure; Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch; Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem; Added the AHA-1540A and the BusTek BT-542B; Moved the Sumo SCSI-AT to the Dev branch; Minor IDE, FDC, and floppy drive code clean-ups; Made NCR 5380/53C400-based cards' BIOS address configurable; Got rid of the legacy romset variable; Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit; Added the Amstead PPC512 per PCem patch by John Elliott; Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages); Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing; Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem; Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit; Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement; Amstrad MegaPC does now works correctly with non-internal graphics card; The SLiRP code no longer casts a packed struct type to a non-packed struct type; The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present; The S3 Virge on BeOS is no longer broken (was broken by build #1591); OS/2 2.0 build 6.167 now sees key presses again; Xi8088 now work on CGA again; 86F images converted from either the old or new variants of the HxC MFM format now work correctly; Hardware interrupts with a vector of 0xFF are now handled correctly; OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct; Fixed VNC keyboard input bugs; Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver; Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly; Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4; Compaq Portable now works with all graphics cards; Fixed various MDSI Genius bugs; Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly; Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355; OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400. Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391. Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389. Fixed a minor IDE timing bug, fixes #388. Fixed Toshiba T1000 RAM issues, fixes #379. Fixed EGA/(S)VGA overscan border handling, fixes #378; Got rid of the now long useless IDE channel 2 auto-removal, fixes #370; Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366; Ported the Unicode CD image file name fix from VARCem, fixes #365; Fixed high density floppy disks on the Xi8088, fixes #359; Fixed some bugs in the Hercules emulation, fixes #346, fixes #358; Fixed the SCSI hard disk mode sense pages, fixes #356; Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349; Fixed bugs in the serial mouse emulation, fixes #344; Compiled 86Box binaries now include all the required .DLL's, fixes #341; Made some combo boxes in the Settings dialog slightly wider, fixes #276.
This commit is contained in:
OBattler
501
src/intel_piix.c
501
src/intel_piix.c
@@ -27,46 +27,36 @@
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#define HAVE_STDARG_H
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#include "86box.h"
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#include "cdrom/cdrom.h"
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#include "cpu/cpu.h"
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#include "scsi/scsi_device.h"
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#include "scsi/scsi_cdrom.h"
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#include "dma.h"
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#include "io.h"
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#include "device.h"
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#include "apm.h"
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#include "keyboard.h"
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#include "mem.h"
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#include "pci.h"
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#include "pic.h"
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#include "port_92.h"
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#include "disk/hdc.h"
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#include "disk/hdc_ide.h"
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#include "disk/hdc_ide_sff8038i.h"
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#include "disk/zip.h"
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#include "machine/machine.h"
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#include "piix.h"
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typedef struct
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{
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uint8_t command, status,
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ptr0;
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uint32_t ptr, ptr_cur,
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addr;
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int count, eot;
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} piix_busmaster_t;
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typedef struct
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{
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int type;
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uint8_t regs[256], regs_ide[256];
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piix_busmaster_t bm[2];
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uint8_t cur_readout_reg,
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readout_regs[256],
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regs[256], regs_ide[256];
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sff8038i_t *bm[2];
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} piix_t;
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static uint8_t piix_bus_master_read(uint16_t port, void *priv);
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static uint16_t piix_bus_master_readw(uint16_t port, void *priv);
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static uint32_t piix_bus_master_readl(uint16_t port, void *priv);
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static void piix_bus_master_write(uint16_t port, uint8_t val, void *priv);
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static void piix_bus_master_writew(uint16_t port, uint16_t val, void *priv);
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static void piix_bus_master_writel(uint16_t port, uint32_t val, void *priv);
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#ifdef ENABLE_PIIX_LOG
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int piix_do_log = ENABLE_PIIX_LOG;
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@@ -93,25 +83,9 @@ piix_bus_master_handlers(piix_t *dev, uint16_t old_base)
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uint16_t base;
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base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
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io_removehandler(old_base, 0x08,
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piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
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piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
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&dev->bm[0]);
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io_removehandler(old_base + 8, 0x08,
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piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
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piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
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&dev->bm[1]);
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if ((dev->regs_ide[0x04] & 1) && base) {
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io_sethandler(base, 0x08,
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piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
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piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
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&dev->bm[0]);
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io_sethandler(base + 8, 0x08,
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piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
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piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
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&dev->bm[1]);
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}
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sff_bus_master_handlers(dev->bm[0], old_base, base, (dev->regs_ide[0x04] & 1));
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sff_bus_master_handlers(dev->bm[1], old_base + 8, base + 8, (dev->regs_ide[0x04] & 1));
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}
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@@ -120,11 +94,16 @@ piix_write(int func, int addr, uint8_t val, void *priv)
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{
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piix_t *dev = (piix_t *) priv;
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uint8_t valxor;
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uint16_t old_base;
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if ((func == 1) && (dev->type & 0x100)) /* PB640's PIIX has no IDE part. */
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return;
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uint16_t old_base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
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if (func > 1)
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return;
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old_base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
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if (func == 1) { /*IDE*/
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piix_log("PIIX IDE write: %02X %02X\n", addr, val);
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valxor = val ^ dev->regs_ide[addr];
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@@ -204,12 +183,11 @@ piix_write(int func, int addr, uint8_t val, void *priv)
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case 0x4c:
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if (valxor) {
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if (val & 0x80) {
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if (dev->type == 3)
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dma_alias_remove();
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else
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dma_alias_remove_piix();
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} else
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if (dev->type == 3)
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dma_alias_remove();
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else
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dma_alias_remove_piix();
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if (!(val & 0x80))
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dma_alias_set();
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}
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break;
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@@ -409,330 +387,43 @@ piix_read(int func, int addr, void *priv)
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static void
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piix_bus_master_next_addr(piix_busmaster_t *dev)
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board_write(uint16_t port, uint8_t val, void *priv)
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{
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DMAPageRead(dev->ptr_cur, (uint8_t *)&(dev->addr), 4);
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DMAPageRead(dev->ptr_cur + 4, (uint8_t *)&(dev->count), 4);
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piix_log("PIIX Bus master DWORDs: %08X %08X\n", dev->addr, dev->count);
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dev->eot = dev->count >> 31;
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dev->count &= 0xfffe;
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if (!dev->count)
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dev->count = 65536;
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dev->addr &= 0xfffffffe;
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dev->ptr_cur += 8;
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}
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piix_t *dev = (piix_t *) priv;
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static void
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piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
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{
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
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#ifdef ENABLE_PIIX_LOG
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int channel = (port & 8) ? 1 : 0;
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#endif
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piix_log("PIIX Bus master BYTE write: %04X %02X\n", port, val);
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switch (port & 7) {
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case 0:
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piix_log("PIIX Cmd : val = %02X, old = %02X\n", val, dev->command);
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if ((val & 1) && !(dev->command & 1)) { /*Start*/
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piix_log("PIIX Bus Master start on channel %i\n", channel);
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dev->ptr_cur = dev->ptr;
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piix_bus_master_next_addr(dev);
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dev->status |= 1;
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}
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if (!(val & 1) && (dev->command & 1)) { /*Stop*/
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piix_log("PIIX Bus Master stop on channel %i\n", channel);
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dev->status &= ~1;
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}
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dev->command = val;
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break;
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case 2:
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piix_log("PIIX Status: val = %02X, old = %02X\n", val, dev->status);
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dev->status &= 0x07;
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dev->status |= (val & 0x60);
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if (val & 0x04)
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dev->status &= ~0x04;
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if (val & 0x02)
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dev->status &= ~0x02;
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffffff00) | (val & 0xfc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val;
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break;
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case 5:
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dev->ptr = (dev->ptr & 0xffff00fc) | (val << 8);
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dev->ptr %= (mem_size * 1024);
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break;
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case 6:
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dev->ptr = (dev->ptr & 0xff00fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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case 7:
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dev->ptr = (dev->ptr & 0x00fffffc) | (val << 24);
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dev->ptr %= (mem_size * 1024);
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break;
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}
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}
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static void
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piix_bus_master_writew(uint16_t port, uint16_t val, void *priv)
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{
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
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piix_log("PIIX Bus master WORD write: %04X %04X\n", port, val);
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switch (port & 7) {
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case 0:
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case 2:
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piix_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffff0000) | (val & 0xfffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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case 6:
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dev->ptr = (dev->ptr & 0x0000fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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}
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}
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static void
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piix_bus_master_writel(uint16_t port, uint32_t val, void *priv)
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{
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
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piix_log("PIIX Bus master DWORD write: %04X %08X\n", port, val);
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switch (port & 7) {
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case 0:
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case 2:
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piix_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (val & 0xfffffffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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}
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if (port == 0x00e0)
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dev->cur_readout_reg = val;
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else if (port == 0x00e1)
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dev->readout_regs[dev->cur_readout_reg] = val;
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}
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static uint8_t
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piix_bus_master_read(uint16_t port, void *priv)
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board_read(uint16_t port, void *priv)
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{
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
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piix_t *dev = (piix_t *) priv;
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uint8_t ret = 0xff;
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switch (port & 7) {
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case 0:
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ret = dev->command;
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break;
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case 2:
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ret = dev->status & 0x67;
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break;
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case 4:
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ret = dev->ptr0;
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break;
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case 5:
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ret = dev->ptr >> 8;
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break;
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case 6:
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ret = dev->ptr >> 16;
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break;
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case 7:
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ret = dev->ptr >> 24;
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break;
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}
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piix_log("PIIX Bus master BYTE read : %04X %02X\n", port, ret);
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if (port == 0x00e0)
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ret = dev->cur_readout_reg;
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else if (port == 0x00e1)
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ret = dev->readout_regs[dev->cur_readout_reg];
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return ret;
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}
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static uint16_t
|
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piix_bus_master_readw(uint16_t port, void *priv)
|
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{
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
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uint16_t ret = 0xffff;
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switch (port & 7) {
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case 0:
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case 2:
|
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ret = (uint16_t) piix_bus_master_read(port, priv);
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break;
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case 4:
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ret = dev->ptr0 | (dev->ptr & 0xff00);
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break;
|
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case 6:
|
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ret = dev->ptr >> 16;
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break;
|
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}
|
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|
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piix_log("PIIX Bus master WORD read : %04X %04X\n", port, ret);
|
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|
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return ret;
|
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}
|
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|
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|
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static uint32_t
|
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piix_bus_master_readl(uint16_t port, void *priv)
|
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{
|
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
|
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|
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uint32_t ret = 0xffffffff;
|
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|
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switch (port & 7) {
|
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case 0:
|
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case 2:
|
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ret = (uint32_t) piix_bus_master_read(port, priv);
|
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break;
|
||||
case 4:
|
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ret = dev->ptr0 | (dev->ptr & 0xffffff00);
|
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break;
|
||||
}
|
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|
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piix_log("PIIX Bus master DWORD read : %04X %08X\n", port, ret);
|
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|
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return ret;
|
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}
|
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|
||||
|
||||
static int
|
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piix_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv)
|
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{
|
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piix_busmaster_t *dev = (piix_busmaster_t *) priv;
|
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#ifdef ENABLE_PIIX_LOG
|
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char *sop;
|
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#endif
|
||||
|
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int force_end = 0, buffer_pos = 0;
|
||||
|
||||
#ifdef ENABLE_PIIX_LOG
|
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sop = out ? "Read" : "Writ";
|
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#endif
|
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|
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if (!(dev->status & 1))
|
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return 2; /*DMA disabled*/
|
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|
||||
piix_log("PIIX Bus master %s: %i bytes\n", out ? "write" : "read", transfer_length);
|
||||
|
||||
while (1) {
|
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if (dev->count <= transfer_length) {
|
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piix_log("%sing %i bytes to %08X\n", sop, dev->count, dev->addr);
|
||||
if (out)
|
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DMAPageRead(dev->addr, (uint8_t *)(data + buffer_pos), dev->count);
|
||||
else
|
||||
DMAPageWrite(dev->addr, (uint8_t *)(data + buffer_pos), dev->count);
|
||||
transfer_length -= dev->count;
|
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buffer_pos += dev->count;
|
||||
} else {
|
||||
piix_log("%sing %i bytes to %08X\n", sop, transfer_length, dev->addr);
|
||||
if (out)
|
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DMAPageRead(dev->addr, (uint8_t *)(data + buffer_pos), transfer_length);
|
||||
else
|
||||
DMAPageWrite(dev->addr, (uint8_t *)(data + buffer_pos), transfer_length);
|
||||
/* Increase addr and decrease count so that resumed transfers do not mess up. */
|
||||
dev->addr += transfer_length;
|
||||
dev->count -= transfer_length;
|
||||
transfer_length = 0;
|
||||
force_end = 1;
|
||||
}
|
||||
|
||||
if (force_end) {
|
||||
piix_log("Total transfer length smaller than sum of all blocks, partial block\n");
|
||||
dev->status &= ~2;
|
||||
return 1; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
|
||||
} else {
|
||||
if (!transfer_length && !dev->eot) {
|
||||
piix_log("Total transfer length smaller than sum of all blocks, full block\n");
|
||||
dev->status &= ~2;
|
||||
return 1; /* We have exhausted the data to transfer but there's more blocks left, break. */
|
||||
} else if (transfer_length && dev->eot) {
|
||||
piix_log("Total transfer length greater than sum of all blocks\n");
|
||||
dev->status |= 2;
|
||||
return 0; /* There is data left to transfer but we have reached EOT - return with error. */
|
||||
} else if (dev->eot) {
|
||||
piix_log("Regular EOT\n");
|
||||
dev->status &= ~3;
|
||||
return 1; /* We have regularly reached EOT - clear status and break. */
|
||||
} else {
|
||||
/* We have more to transfer and there are blocks left, get next block. */
|
||||
piix_bus_master_next_addr(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
piix_bus_master_set_irq(int channel, void *priv)
|
||||
{
|
||||
piix_busmaster_t *dev = (piix_busmaster_t *) priv;
|
||||
dev->status &= ~4;
|
||||
dev->status |= (channel >> 4);
|
||||
|
||||
channel &= 0x01;
|
||||
if (dev->status & 0x04) {
|
||||
if (channel && pci_use_mirq(0))
|
||||
pci_set_mirq(0);
|
||||
else
|
||||
picint(1 << (14 + channel));
|
||||
} else {
|
||||
if ((channel & 1) && pci_use_mirq(0))
|
||||
pci_clear_mirq(0);
|
||||
else
|
||||
picintc(1 << (14 + channel));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
piix_bus_master_reset(piix_t *dev)
|
||||
{
|
||||
uint8_t i;
|
||||
|
||||
uint16_t old_base = (dev->regs_ide[0x20] & 0xf0) | (dev->regs_ide[0x21] << 8);
|
||||
if (old_base) {
|
||||
io_removehandler(old_base, 0x08,
|
||||
piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
|
||||
piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
|
||||
&dev->bm[0]);
|
||||
io_removehandler(old_base + 8, 0x08,
|
||||
piix_bus_master_read, piix_bus_master_readw, piix_bus_master_readl,
|
||||
piix_bus_master_write, piix_bus_master_writew, piix_bus_master_writel,
|
||||
&dev->bm[1]);
|
||||
}
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
dev->bm[i].command = 0x00;
|
||||
dev->bm[i].status = 0x00;
|
||||
dev->bm[i].ptr = dev->bm[i].ptr_cur = 0x00000000;
|
||||
dev->bm[i].addr = 0x00000000;
|
||||
dev->bm[i].ptr0 = 0x00;
|
||||
dev->bm[i].count = dev->bm[i].eot = 0x00000000;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
piix_reset_hard(void *priv)
|
||||
{
|
||||
piix_t *piix = (piix_t *) priv;
|
||||
|
||||
piix_bus_master_reset(piix);
|
||||
uint16_t old_base = (piix->regs_ide[0x20] & 0xf0) | (piix->regs_ide[0x21] << 8);
|
||||
|
||||
if (!(piix->type & 0x100)) { /* PB640's PIIX has no IDE part. */
|
||||
sff_bus_master_reset(piix->bm[0], old_base);
|
||||
sff_bus_master_reset(piix->bm[1], old_base + 8);
|
||||
}
|
||||
|
||||
memset(piix->regs, 0, 256);
|
||||
memset(piix->regs_ide, 0, 256);
|
||||
@@ -806,25 +497,6 @@ piix_reset_hard(void *priv)
|
||||
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
|
||||
if (piix->type != 3)
|
||||
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
|
||||
|
||||
ide_pri_disable();
|
||||
ide_sec_disable();
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
piix_reset(void *p)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < CDROM_NUM; i++) {
|
||||
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && cdrom[i].priv)
|
||||
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
|
||||
}
|
||||
for (i = 0; i < ZIP_NUM; i++) {
|
||||
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && zip_drives[i].priv)
|
||||
zip_reset((scsi_common_t *) zip_drives[i].priv);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -843,25 +515,96 @@ static void
|
||||
piix_t *piix = (piix_t *) malloc(sizeof(piix_t));
|
||||
memset(piix, 0, sizeof(piix_t));
|
||||
|
||||
device_add(&ide_pci_2ch_device);
|
||||
|
||||
pci_add_card(7, piix_read, piix_write, piix);
|
||||
|
||||
piix->type = info->local;
|
||||
|
||||
device_add(&apm_device);
|
||||
|
||||
if (!(piix->type & 0x100)) { /* PB640's PIIX has no IDE part. */
|
||||
piix->bm[0] = device_add_inst(&sff8038i_device, 1);
|
||||
piix->bm[1] = device_add_inst(&sff8038i_device, 2);
|
||||
}
|
||||
|
||||
piix_reset_hard(piix);
|
||||
|
||||
ide_set_bus_master(piix_bus_master_dma, piix_bus_master_set_irq,
|
||||
&piix->bm[0], &piix->bm[1]);
|
||||
|
||||
port_92_reset();
|
||||
|
||||
port_92_add();
|
||||
device_add(&port_92_pci_device);
|
||||
|
||||
dma_alias_set();
|
||||
|
||||
pci_enable_mirq(0);
|
||||
pci_enable_mirq(1);
|
||||
|
||||
piix->readout_regs[1] = 0x40;
|
||||
|
||||
/* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined):
|
||||
|
||||
Bit 6: 1 = can boot, 0 = no;
|
||||
Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5);
|
||||
Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????):
|
||||
Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz;
|
||||
0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz;
|
||||
1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz;
|
||||
1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */
|
||||
|
||||
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].pci_speed) {
|
||||
case 20000000:
|
||||
piix->readout_regs[1] |= 0x30;
|
||||
break;
|
||||
case 25000000:
|
||||
default:
|
||||
piix->readout_regs[1] |= 0x00;
|
||||
break;
|
||||
case 30000000:
|
||||
piix->readout_regs[1] |= 0x20;
|
||||
break;
|
||||
case 33333333:
|
||||
piix->readout_regs[1] |= 0x10;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed) {
|
||||
case 75000000:
|
||||
piix->readout_regs[1] |= 0x82; /* 50 MHz * 1.5 multiplier */
|
||||
break;
|
||||
case 90000000:
|
||||
piix->readout_regs[1] |= 0x82; /* 60 MHz * 1.5 multiplier */
|
||||
break;
|
||||
case 100000000:
|
||||
if ((piix->readout_regs[1] & 0x30) == 0x10)
|
||||
piix->readout_regs[1] |= 0x82; /* 66 MHz * 1.5 multiplier */
|
||||
else
|
||||
piix->readout_regs[1] |= 0x02; /* 50 MHz * 2.0 multiplier */
|
||||
break;
|
||||
case 12000000:
|
||||
piix->readout_regs[1] |= 0x02; /* 60 MHz * 2.0 multiplier */
|
||||
break;
|
||||
case 125000000:
|
||||
piix->readout_regs[1] |= 0x00; /* 50 MHz * 2.5 multiplier */
|
||||
break;
|
||||
case 133333333:
|
||||
piix->readout_regs[1] |= 0x02; /* 66 MHz * 2.0 multiplier */
|
||||
break;
|
||||
case 150000000:
|
||||
if ((piix->readout_regs[1] & 0x30) == 0x20)
|
||||
piix->readout_regs[1] |= 0x00; /* 60 MHz * 2.5 multiplier */
|
||||
else
|
||||
piix->readout_regs[1] |= 0x80; /* 50 MHz * 3.0 multiplier */
|
||||
break;
|
||||
case 166666666:
|
||||
piix->readout_regs[1] |= 0x00; /* 66 MHz * 2.5 multiplier */
|
||||
break;
|
||||
case 180000000:
|
||||
piix->readout_regs[1] |= 0x80; /* 60 MHz * 3.0 multiplier */
|
||||
break;
|
||||
case 200000000:
|
||||
piix->readout_regs[1] |= 0x80; /* 66 MHz * 3.0 multiplier */
|
||||
break;
|
||||
}
|
||||
|
||||
io_sethandler(0x0078, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, piix);
|
||||
io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, piix);
|
||||
|
||||
return piix;
|
||||
}
|
||||
|
||||
@@ -873,7 +616,7 @@ const device_t piix_device =
|
||||
1,
|
||||
piix_init,
|
||||
piix_close,
|
||||
piix_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
@@ -887,7 +630,7 @@ const device_t piix_pb640_device =
|
||||
0x101,
|
||||
piix_init,
|
||||
piix_close,
|
||||
piix_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
@@ -901,7 +644,7 @@ const device_t piix3_device =
|
||||
3,
|
||||
piix_init,
|
||||
piix_close,
|
||||
piix_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
Reference in New Issue
Block a user