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Added the IBM 5161 ISA expansion for PC and XT;

Browse Source 
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g  / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
This commit is contained in:
OBattler
2019-09-20 14:02:30 +02:00
parent b06296bbf6
commit 552a87ea3d
524 changed files with 129555 additions and 21862 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1611
src/machine/m_amstrad.c
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26
src/machine/m_amstrad.h Normal file
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@@ -0,0 +1,26 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the emulation of the Amstrad series of PC's:
* PC1512, PC1640 and PC200, including their keyboard, mouse and
* video devices, as well as the PC2086 and PC3086 systems.
*
* Version: @(#)m_amstrad.h 1.0.0 2019/03/21
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
*
* Copyright 2008-2019 Sarah Walker.
*/
extern int amstrad_latch;
enum
{
AMSTRAD_NOLATCH,
AMSTRAD_SW9,
AMSTRAD_SW10
};

108
src/machine/m_at.c
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@@ -41,6 +41,7 @@
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../timer.h"
#include "../pic.h"
#include "../pit.h"
#include "../dma.h"
@@ -52,12 +53,13 @@
#include "../game/gameport.h"
#include "../keyboard.h"
#include "../lpt.h"
#include "../rom.h"
#include "../disk/hdc.h"
#include "machine.h"
void
machine_at_common_init(const machine_t *model)
machine_at_common_init_ex(const machine_t *model, int is_ibm)
{
machine_common_init(model);
@@ -65,16 +67,23 @@ machine_at_common_init(const machine_t *model)
pic2_init();
dma16_init();
if (lpt_enabled)
lpt2_remove();
device_add(&at_nvr_device);
if (is_ibm)
device_add(&ibmat_nvr_device);
else
device_add(&at_nvr_device);
if (joystick_type != 7)
device_add(&gameport_device);
}
void
machine_at_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 0);
}
void
machine_at_init(const machine_t *model)
{
@@ -84,22 +93,10 @@ machine_at_init(const machine_t *model)
}
void
machine_at_ibm_init(const machine_t *model)
static void
machine_at_ibm_common_init(const machine_t *model)
{
machine_common_init(model);
pit_set_out_func(&pit, 1, pit_refresh_timer_at);
pic2_init();
dma16_init();
if (lpt_enabled)
lpt2_remove();
device_add(&ibmat_nvr_device);
if (joystick_type != 7)
device_add(&gameport_device);
machine_at_common_init_ex(model, 1);
device_add(&keyboard_at_device);
@@ -108,6 +105,7 @@ machine_at_ibm_init(const machine_t *model)
device_add(&fdc_at_device);
}
void
machine_at_ps2_init(const machine_t *model)
{
@@ -122,7 +120,16 @@ machine_at_common_ide_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_isa_2ch_opt_device);
device_add(&ide_isa_device);
}
void
machine_at_ibm_common_ide_init(const machine_t *model)
{
machine_at_common_init_ex(model, 1);
device_add(&ide_isa_device);
}
@@ -131,7 +138,7 @@ machine_at_ide_init(const machine_t *model)
{
machine_at_init(model);
device_add(&ide_isa_2ch_opt_device);
device_add(&ide_isa_device);
}
@@ -140,5 +147,60 @@ machine_at_ps2_ide_init(const machine_t *model)
{
machine_at_ps2_init(model);
device_add(&ide_isa_2ch_opt_device);
device_add(&ide_isa_device);
}
int
machine_at_ibm_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmat/62x0820.u27",
L"roms/machines/ibmat/62x0821.u47",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
int
machine_at_ibmxt286_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmxt286/bios_5162_21apr86_u34_78x7460_27256.bin",
L"roms/machines/ibmxt286/bios_5162_21apr86_u35_78x7461_27256.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
int
machine_at_open_at_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/open_at/bios.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
#endif

318
src/machine/m_at_286_386sx.c Normal file
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@@ -0,0 +1,318 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of 286 and 386SX machines.
*
* Version: @(#)m_at_286_386sx.c 1.0.0 2019/05/16
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../io.h"
#include "../device.h"
#include "../chipset/chipset.h"
#include "../keyboard.h"
#include "../mem.h"
#include "../rom.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../disk/hdc.h"
#include "../video/video.h"
#include "../video/vid_et4000.h"
#include "../video/vid_oak_oti.h"
#include "../video/vid_paradise.h"
#include "machine.h"
static void
machine_at_headland_common_init(int ht386)
{
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
if (ht386)
device_add(&headland_386_device);
else
device_add(&headland_device);
}
#if defined(DEV_BRANCH) && defined(USE_AMI386SX)
int
machine_at_headland_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ami386/ami386.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
return ret;
}
#endif
int
machine_at_tg286m_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/tg286m/ami.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
machine_at_headland_common_init(0);
return ret;
}
const device_t *
at_ama932j_get_device(void)
{
return &oti067_ama932j_device;
}
int
machine_at_ama932j_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ama932j/ami.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
if (gfxcard == VID_INTERNAL)
device_add(&oti067_ama932j_device);
return ret;
}
int
machine_at_neat_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/dtk386/3cto001.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
device_add(&neat_device);
device_add(&fdc_at_device);
return ret;
}
int
machine_at_neat_ami_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ami286/amic206.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&neat_device);
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
static void
machine_at_scat_init(const machine_t *model, int is_v4)
{
machine_at_init(model);
device_add(&fdc_at_device);
if (is_v4)
device_add(&scat_4_device);
else
device_add(&scat_device);
}
static void
machine_at_scatsx_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
device_add(&scat_sx_device);
}
int
machine_at_award286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/award286/award.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0);
return ret;
}
int
machine_at_gw286ct_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/gw286ct/2ctc001.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 1);
return ret;
}
int
machine_at_super286tr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/super286tr/hyundai_award286.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0);
return ret;
}
int
machine_at_spc4200p_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/spc4200p/u8.01",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0);
return ret;
}
int
machine_at_spc4216p_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/spc4216p/7101.u8",
L"roms/machines/spc4216p/ac64.u10",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 1);
return ret;
}
int
machine_at_kmxc02_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/kmxc02/3ctm005.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scatsx_init(model);
return ret;
}
int
machine_at_wd76c10_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/megapc/41651-bios lo.u18",
L"roms/machines/megapc/211253-bios hi.u19",
0x000f0000, 65536, 0x08000);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&keyboard_ps2_quadtel_device);
device_add(&wd76c10_device);
if (gfxcard == VID_INTERNAL)
device_add(&paradise_wd90c11_megapc_device);
return ret;
}

341
src/machine/m_at_386dx_486.c Normal file
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@@ -0,0 +1,341 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of 386DX and 486 machines.
*
* Version: @(#)m_at_386dx_486.c 1.0.0 2019/05/16
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../io.h"
#include "../device.h"
#include "../chipset/chipset.h"
#include "../keyboard.h"
#include "../mem.h"
#include "../pci.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../rom.h"
#include "../sio.h"
#include "../disk/hdc.h"
#include "../video/video.h"
#include "../video/vid_ht216.h"
#include "../intel_flash.h"
#include "../intel_sio.h"
#include "machine.h"
int
machine_at_pb410a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pb410a/pb410a.080337.4abf.u25.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_ide_init(model);
device_add(&keyboard_ps2_device);
device_add(&acc3221_device);
device_add(&acc2168_device);
if (gfxcard == VID_INTERNAL)
device_add(&ht216_32_pb410a_device);
return ret;
}
static void
machine_at_ali1429_common_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&ali1429_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
}
int
machine_at_ali1429_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ami486/ami486.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ali1429_common_init(model);
return ret;
}
int
machine_at_winbios1429_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/win486/ali1429g.amw",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ali1429_common_init(model);
return ret;
}
int
machine_at_opti495_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/award495/opt495s.awa",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&opti495_device);
device_add(&keyboard_at_device);
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_opti495_ami_common_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&opti495_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
}
int
machine_at_opti495_ami_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ami495/opt495sx.ami",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_opti495_ami_common_init(model);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_MR495)
int
machine_at_opti495_mr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/mr495/opt495sx.mr",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_opti495_ami_common_init(model);
return ret;
}
#endif
static void
machine_at_sis_85c471_common_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&fdc_at_device);
device_add(&sis_85c471_device);
}
int
machine_at_ami471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ami471/SIS471BE.AMI",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_dtk486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/dtk486/4siw005.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_device);
return ret;
}
int
machine_at_px471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/px471/SIS471A1.PHO",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_device);
return ret;
}
int
machine_at_win471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/win471/4sim001.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
static void
machine_at_sis_85c496_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&keyboard_ps2_pci_device);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
device_add(&sis_85c496_device);
}
int
machine_at_r418_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/r418/r418i.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c496_common_init(model);
device_add(&fdc37c665_device);
return ret;
}
int
machine_at_alfredo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/alfredo/1010AQ0_.BIO",
L"roms/machines/alfredo/1010AQ0_.BI1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sio_device);
device_add(&fdc37c663_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420tx_device);
return ret;
}

938
src/machine/m_at_4x0.c
View File

@@ -1,938 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel PCISet chips from 430LX to 440FX.
*
* Version: @(#)m_at_430lx_nx.c 1.0.4 2018/11/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "../memregs.h"
#include "../io.h"
#include "../rom.h"
#include "../pci.h"
#include "../device.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "../keyboard.h"
#include "../intel.h"
#include "../intel_flash.h"
#include "../intel_sio.h"
#include "../piix.h"
#include "../sio.h"
#include "../video/video.h"
#include "../video/vid_cl54xx.h"
#include "../video/vid_s3.h"
#include "machine.h"
enum
{
INTEL_430LX,
INTEL_430NX,
INTEL_430FX,
INTEL_430FX_PB640,
INTEL_430HX,
INTEL_430VX
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX
#endif
};
typedef struct
{
uint8_t regs[256];
int type;
} i4x0_t;
typedef struct
{
int index;
} acerm3a_t;
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
if (dev->type >= INTEL_430FX) {
if (dev->type == INTEL_430FX_PB640)
val &= 0x06;
else
val &= 0x02;
} else
val &= 0x42;
val |= 0x04;
break;
case 0x05:
if (dev->type >= INTEL_430FX)
val = 0;
else
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
if (dev->type >= INTEL_430HX) {
val &= 0x80;
val |= 0x02;
} else {
val = 0x02;
if (dev->type == INTEL_430FX_PB640)
val |= 0x20;
}
break;
case 0x59: /*PAM0*/
if ((dev->regs[0x59] ^ val) & 0xf0) {
i4x0_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
break;
case 0x5a: /*PAM1*/
if ((dev->regs[0x5a] ^ val) & 0x0f)
i4x0_map(0xc0000, 0x04000, val & 0xf);
if ((dev->regs[0x5a] ^ val) & 0xf0)
i4x0_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((dev->regs[0x5b] ^ val) & 0x0f)
i4x0_map(0xc8000, 0x04000, val & 0xf);
if ((dev->regs[0x5b] ^ val) & 0xf0)
i4x0_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((dev->regs[0x5c] ^ val) & 0x0f)
i4x0_map(0xd0000, 0x04000, val & 0xf);
if ((dev->regs[0x5c] ^ val) & 0xf0)
i4x0_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((dev->regs[0x5d] ^ val) & 0x0f)
i4x0_map(0xd8000, 0x04000, val & 0xf);
if ((dev->regs[0x5d] ^ val) & 0xf0)
i4x0_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((dev->regs[0x5e] ^ val) & 0x0f)
i4x0_map(0xe0000, 0x04000, val & 0xf);
if ((dev->regs[0x5e] ^ val) & 0xf0)
i4x0_map(0xe4000, 0x04000, val >> 4);
break;
case 0x5f: /*PAM6*/
if ((dev->regs[0x5f] ^ val) & 0x0f)
i4x0_map(0xe8000, 0x04000, val & 0xf);
if ((dev->regs[0x5f] ^ val) & 0xf0)
i4x0_map(0xec000, 0x04000, val >> 4);
break;
case 0x72: /*SMRAM*/
if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48))
i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
break;
}
dev->regs[addr] = val;
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
if (func)
return 0xff;
return dev->regs[addr];
}
static void
i4x0_reset(void *priv)
{
i4x0_t *i4x0 = (i4x0_t *)priv;
i4x0_write(0, 0x59, 0x00, priv);
if (i4x0->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, priv);
}
static void
i4x0_close(void *p)
{
i4x0_t *i4x0 = (i4x0_t *)p;
free(i4x0);
}
static void
*i4x0_init(const device_t *info)
{
i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t));
memset(i4x0, 0, sizeof(i4x0_t));
i4x0->type = info->local;
i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/
switch(i4x0->type) {
case INTEL_430LX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x03; /*A3 stepping*/
i4x0->regs[0x50] = 0x80;
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430NX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x10; /*A0 stepping*/
i4x0->regs[0x50] = 0xA0;
i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/
i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
break;
case INTEL_430FX:
case INTEL_430FX_PB640:
i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
if (i4x0->type == INTEL_430FX_PB640)
i4x0->regs[0x08] = 0x02; /*???? stepping*/
else
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430HX:
i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x51] = 0x20;
i4x0->regs[0x52] = 0xB5; /*512kb cache*/
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x59] = 0x40;
i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44;
i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44;
i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
i4x0->regs[0x68] = 0x11;
break;
case INTEL_430VX:
i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
i4x0->regs[0x53] = 0x14;
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x67] = 0x11;
i4x0->regs[0x69] = 0x03;
i4x0->regs[0x70] = 0x20;
i4x0->regs[0x74] = 0x0e;
i4x0->regs[0x78] = 0x23;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/
i4x0->regs[0x08] = 0x02; /*A0 stepping*/
i4x0->regs[0x2c] = 0xf4;
i4x0->regs[0x2d] = 0x1a;
i4x0->regs[0x2f] = 0x11;
i4x0->regs[0x51] = 0x01;
i4x0->regs[0x53] = 0x80;
i4x0->regs[0x58] = 0x10;
i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11;
i4x0->regs[0x5e] = 0x11;
i4x0->regs[0x5f] = 0x31;
break;
#endif
}
i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00;
#if defined(DEV_BRANCH) && defined(USE_I686)
if (i4x0->type == INTEL_440FX)
i4x0->regs[0x06] = 0x80;
#endif
if (i4x0->type == INTEL_430FX)
i4x0->regs[0x07] = 0x82;
#if defined(DEV_BRANCH) && defined(USE_I686)
else if (i4x0->type != INTEL_440FX)
#else
else
#endif
i4x0->regs[0x07] = 0x02;
i4x0->regs[0x0b] = 0x06;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x57] = 0x01;
else
i4x0->regs[0x57] = 0x31;
i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02;
i4x0->regs[0x64] = 0x02;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x72] = 0x02;
pci_add_card(0, i4x0_read, i4x0_write, i4x0);
return i4x0;
}
const device_t i430lx_device =
{
"Intel 82434LX",
DEVICE_PCI,
INTEL_430LX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430nx_device =
{
"Intel 82434NX",
DEVICE_PCI,
INTEL_430NX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_device =
{
"Intel SB82437FX-66",
DEVICE_PCI,
INTEL_430FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_pb640_device =
{
"Intel SB82437FX-66 (PB640)",
DEVICE_PCI,
INTEL_430FX_PB640,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430hx_device =
{
"Intel 82439HX",
DEVICE_PCI,
INTEL_430HX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430vx_device =
{
"Intel 82437VX",
DEVICE_PCI,
INTEL_430VX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#if defined(DEV_BRANCH) && defined(USE_I686)
const device_t i440fx_device =
{
"Intel 82441FX",
DEVICE_PCI,
INTEL_440FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#endif
static void
acerm3a_out(uint16_t port, uint8_t val, void *p)
{
acerm3a_t *dev = (acerm3a_t *) p;
if (port == 0xea)
dev->index = val;
}
static uint8_t
acerm3a_in(uint16_t port, void *p)
{
acerm3a_t *dev = (acerm3a_t *) p;
if (port == 0xeb) {
switch (dev->index) {
case 2:
return 0xfd;
}
}
return 0xff;
}
static void
acerm3a_close(void *p)
{
acerm3a_t *dev = (acerm3a_t *)p;
free(dev);
}
static void
*acerm3a_init(const device_t *info)
{
acerm3a_t *acerm3a = (acerm3a_t *) malloc(sizeof(acerm3a_t));
memset(acerm3a, 0, sizeof(acerm3a_t));
io_sethandler(0x00ea, 0x0002, acerm3a_in, NULL, NULL, acerm3a_out, NULL, NULL, acerm3a);
return acerm3a;
}
const device_t acerm3a_device =
{
"Acer M3A Register",
0,
0,
acerm3a_init,
acerm3a_close,
NULL,
NULL,
NULL,
NULL,
NULL
};
static void
machine_at_premiere_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_pci_2ch_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_batman_device);
device_add(&intel_flash_bxt_ami_device);
}
void
machine_at_batman_init(const machine_t *model)
{
machine_at_premiere_common_init(model);
device_add(&i430lx_device);
}
void
machine_at_plato_init(const machine_t *model)
{
machine_at_premiere_common_init(model);
device_add(&i430nx_device);
}
void
machine_at_p54tp4xe_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_endeavor_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
device_add(&s3_phoenix_trio64_onboard_pci_device);
}
const device_t *
at_endeavor_get_device(void)
{
return &s3_phoenix_trio64_onboard_pci_device;
}
void
machine_at_zappa_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
void
machine_at_mb500n_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_president_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&w83877f_president_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_thor_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
void
machine_at_pb640_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_pb640_device);
device_add(&piix_pb640_device);
ide_enable_pio_override();
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5440_onboard_pci_device);
}
const device_t *
at_pb640_get_device(void)
{
return &gd5440_onboard_pci_device;
}
void
machine_at_acerm3a_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x10, PCI_CARD_ONBOARD, 4, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
}
void
machine_at_acerv35n_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
}
void
machine_at_ap53_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_ONBOARD, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_p55t2p4_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_p55t2s_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
powermate_memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_p55tvp4_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_i430vx_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_p55va_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_j656vxd_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
}
#if defined(DEV_BRANCH) && defined(USE_I686)
void
machine_at_i440fx_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
void
machine_at_s1668_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_ami_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
#endif

111
src/machine/m_at_ali1429.c
View File

@@ -1,111 +0,0 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../mem.h"
#include "../device.h"
#include "../keyboard.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "machine.h"
static int ali1429_index;
static uint8_t ali1429_regs[256];
static void ali1429_recalc(void)
{
int c;
for (c = 0; c < 8; c++)
{
uint32_t base = 0xc0000 + (c << 15);
if (ali1429_regs[0x13] & (1 << c))
{
switch (ali1429_regs[0x14] & 3)
{
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
flushmmucache();
}
void ali1429_write(uint16_t port, uint8_t val, void *priv)
{
if (!(port & 1))
ali1429_index = val;
else
{
ali1429_regs[ali1429_index] = val;
switch (ali1429_index)
{
case 0x13:
ali1429_recalc();
break;
case 0x14:
shadowbios = val & 1;
shadowbios_write = val & 2;
ali1429_recalc();
break;
}
}
}
uint8_t ali1429_read(uint16_t port, void *priv)
{
if (!(port & 1))
return ali1429_index;
if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && cpu_iscyrix)
return 0xff; /*Don't conflict with Cyrix config registers*/
return ali1429_regs[ali1429_index];
}
static void ali1429_reset(void)
{
memset(ali1429_regs, 0xff, 256);
}
static void ali1429_init(void)
{
io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, NULL);
}
void
machine_at_ali1429_init(const machine_t *model)
{
ali1429_reset();
machine_at_common_ide_init(model);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
ali1429_init();
}

17
src/machine/m_at_commodore.c
View File

@@ -42,9 +42,11 @@
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../timer.h"
#include "../io.h"
#include "../mem.h"
#include "../lpt.h"
#include "../rom.h"
#include "../serial.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
@@ -90,10 +92,19 @@ cbm_io_init()
}
void
int
machine_at_cmdpc_init(const machine_t *model)
{
machine_at_ide_init(model);
int ret;
ret = bios_load_interleaved(L"roms/machines/cmdpc30/commodore pc 30 iii even.bin",
L"roms/machines/cmdpc30/commodore pc 30 iii odd.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
mem_remap_top(384);
@@ -101,4 +112,6 @@ machine_at_cmdpc_init(const machine_t *model)
cmd_uart = device_add(&i8250_device);
cbm_io_init();
return ret;
}

93
src/machine/m_at_compaq.c
View File

@@ -23,6 +23,7 @@
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../mem.h"
#include "../rom.h"
#include "../device.h"
@@ -33,6 +34,16 @@
#include "machine.h"
enum
{
COMPAQ_PORTABLEII = 0
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
, COMPAQ_PORTABLEIII,
COMPAQ_PORTABLEIII386
#endif
};
/* Compaq Deskpro 386 remaps RAM from 0xA0000-0xFFFFF to 0xFA0000-0xFFFFFF */
static mem_mapping_t ram_mapping;
@@ -97,8 +108,8 @@ write_raml(uint32_t addr, uint32_t val, void *priv)
}
void
machine_at_compaq_init(const machine_t *model)
static void
machine_at_compaq_init(const machine_t *model, int type)
{
machine_at_init(model);
@@ -111,30 +122,74 @@ machine_at_compaq_init(const machine_t *model)
write_ram, write_ramw, write_raml,
0xa0000+ram, MEM_MAPPING_INTERNAL, NULL);
switch(model->id) {
#ifdef PORTABLE3
case ROM_DESKPRO_386:
if (hdc_current == 1)
device_add(&ide_isa_device);
break;
#endif
case ROM_PORTABLE:
switch(type) {
case COMPAQ_PORTABLEII:
break;
case ROM_PORTABLEII:
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
case COMPAQ_PORTABLEIII:
break;
#ifdef PORTABLE3
case ROM_PORTABLEIII:
machine_olim24_video_init();
break;
case ROM_PORTABLEIII386:
machine_olim24_video_init();
case COMPAQ_PORTABLEIII386:
if (hdc_current == 1)
device_add(&ide_isa_device);
break;
#endif
}
}
int
machine_at_portableii_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/portableii/109740-001.rom",
L"roms/machines/portableii/109739-001.rom",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEII);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
int
machine_at_portableiii_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/portableiii/109738-002.bin",
L"roms/machines/portableiii/109737-002.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEIII);
return ret;
}
int
machine_at_portableiii386_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/portableiii/109738-002.bin",
L"roms/machines/portableiii/109737-002.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEIII386);
return ret;
}
#endif

568
src/machine/m_at_headland.c
View File

@@ -1,568 +0,0 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../cpu/x86.h"
#include "../io.h"
#include "../mem.h"
#include "../rom.h"
#include "../device.h"
#include "../keyboard.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "machine.h"
#include "../video/video.h"
#include "../video/vid_et4000.h"
#include "../video/vid_oak_oti.h"
static int headland_index;
static uint8_t headland_regs[256];
static uint8_t headland_port_92 = 0xFC, headland_ems_mar = 0, headland_cri = 0;
static uint8_t headland_regs_cr[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
static uint16_t headland_ems_mr[64];
static mem_mapping_t headland_low_mapping;
static mem_mapping_t headland_ems_mapping[64];
static mem_mapping_t headland_mid_mapping;
static mem_mapping_t headland_high_mapping;
static mem_mapping_t headland_4000_9FFF_mapping[24];
/* TODO - Headland chipset's memory address mapping emulation isn't fully implemented yet,
so memory configuration is hardcoded now. */
static int headland_mem_conf_cr0[41] = { 0x00, 0x00, 0x20, 0x40, 0x60, 0xA0, 0x40, 0xE0,
0xA0, 0xC0, 0xE0, 0xE0, 0xC0, 0xE0, 0xE0, 0xE0,
0xE0, 0x20, 0x40, 0x40, 0xA0, 0xC0, 0xE0, 0xE0,
0xC0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
0x20, 0x40, 0x60, 0x60, 0xC0, 0xE0, 0xE0, 0xE0,
0xE0 };
static int headland_mem_conf_cr1[41] = { 0x00, 0x40, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40,
0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x40 };
static uint32_t
get_headland_addr(uint32_t addr, uint16_t *mr)
{
if (mr && (headland_regs_cr[0] & 2) && (*mr & 0x200)) {
addr = (addr & 0x3fff) | ((*mr & 0x1F) << 14);
if (headland_regs_cr[1] & 0x40) {
if ((headland_regs_cr[4] & 0x80) && (headland_regs_cr[6] & 1)) {
if (headland_regs_cr[0] & 0x80) {
addr |= (*mr & 0x60) << 14;
if (*mr & 0x100)
addr += ((*mr & 0xC00) << 13) + (((*mr & 0x80) + 0x80) << 15);
else
addr += (*mr & 0x80) << 14;
} else if (*mr & 0x100)
addr += ((*mr & 0xC00) << 13) + (((*mr & 0x80) + 0x20) << 15);
else
addr += (*mr & 0x80) << 12;
} else if (headland_regs_cr[0] & 0x80)
addr |= (*mr & 0x100) ? ((*mr & 0x80) + 0x400) << 12 : (*mr & 0xE0) << 14;
else
addr |= (*mr & 0x100) ? ((*mr & 0xE0) + 0x40) << 14 : (*mr & 0x80) << 12;
} else {
if ((headland_regs_cr[4] & 0x80) && (headland_regs_cr[6] & 1)) {
if (headland_regs_cr[0] & 0x80) {
addr |= ((*mr & 0x60) << 14);
if (*mr & 0x180)
addr += ((*mr & 0xC00) << 13) + (((*mr & 0x180) - 0x60) << 16);
} else
addr |= ((*mr & 0x60) << 14) | ((*mr & 0x180) << 16) | ((*mr & 0xC00) << 13);
} else if (headland_regs_cr[0] & 0x80)
addr |= (*mr & 0x1E0) << 14;
else
addr |= (*mr & 0x180) << 12;
}
} else if (mr == NULL && (headland_regs_cr[0] & 4) == 0 && mem_size >= 1024 && addr >= 0x100000)
addr -= 0x60000;
return addr;
}
static void
headland_set_global_EMS_state(int state)
{
int i;
uint32_t base_addr, virt_addr;
for (i=0; i<32; i++) {
base_addr = (i + 16) << 14;
if (i >= 24)
base_addr += 0x20000;
if ((state & 2) && (headland_ems_mr[((state & 1) << 5) | i] & 0x200)) {
virt_addr = get_headland_addr(base_addr, &headland_ems_mr[((state & 1) << 5) | i]);
if (i < 24)
mem_mapping_disable(&headland_4000_9FFF_mapping[i]);
mem_mapping_disable(&headland_ems_mapping[(((state ^ 1) & 1) << 5) | i]);
mem_mapping_enable(&headland_ems_mapping[((state & 1) << 5) | i]);
if (virt_addr < (mem_size << 10))
mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], ram + virt_addr);
else
mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], NULL);
} else {
mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], ram + base_addr);
mem_mapping_disable(&headland_ems_mapping[(((state ^ 1) & 1) << 5) | i]);
mem_mapping_disable(&headland_ems_mapping[((state & 1) << 5) | i]);
if (i < 24)
mem_mapping_enable(&headland_4000_9FFF_mapping[i]);
}
}
flushmmucache();
}
static void
headland_memmap_state_update(void)
{
int i;
uint32_t addr;
for (i=0; i<24; i++) {
addr = get_headland_addr(0x40000 + (i << 14), NULL);
mem_mapping_set_exec(&headland_4000_9FFF_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
}
mem_set_mem_state(0xA0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
if (mem_size > 640) {
if ((headland_regs_cr[0] & 4) == 0) {
mem_mapping_set_addr(&headland_mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
mem_mapping_set_exec(&headland_mid_mapping, ram + 0xA0000);
if (mem_size > 1024) {
mem_mapping_set_addr(&headland_high_mapping, 0x160000, (mem_size - 1024) << 10);
mem_mapping_set_exec(&headland_high_mapping, ram + 0x100000);
}
} else {
mem_mapping_set_addr(&headland_mid_mapping, 0xA0000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
mem_mapping_set_exec(&headland_mid_mapping, ram + 0xA0000);
if (mem_size > 1024) {
mem_mapping_set_addr(&headland_high_mapping, 0x100000, (mem_size - 1024) << 10);
mem_mapping_set_exec(&headland_high_mapping, ram + 0x100000);
}
}
}
headland_set_global_EMS_state(headland_regs_cr[0] & 3);
}
static void
headland_write(uint16_t addr, uint8_t val, void *priv)
{
uint8_t old_val, index;
uint32_t base_addr, virt_addr;
switch(addr) {
case 0x22:
headland_index = val;
break;
case 0x23:
old_val = headland_regs[headland_index];
if ((headland_index == 0xc1) && !is486)
val = 0;
headland_regs[headland_index] = val;
if (headland_index == 0x82) {
shadowbios = val & 0x10;
shadowbios_write = !(val & 0x10);
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
} else if (headland_index == 0x87) {
if ((val & 1) && !(old_val & 1))
softresetx86();
}
break;
case 0x92:
if ((mem_a20_alt ^ val) & 2) {
mem_a20_alt = val & 2;
mem_a20_recalc();
}
if ((~headland_port_92 & val) & 1) {
softresetx86();
cpu_set_edx();
}
headland_port_92 = val | 0xFC;
break;
case 0x1EC:
headland_ems_mr[headland_ems_mar & 0x3F] = val | 0xFF00;
index = headland_ems_mar & 0x1F;
base_addr = (index + 16) << 14;
if (index >= 24)
base_addr += 0x20000;
if ((headland_regs_cr[0] & 2) && ((headland_regs_cr[0] & 1) == ((headland_ems_mar & 0x20) >> 5))) {
virt_addr = get_headland_addr(base_addr, &headland_ems_mr[headland_ems_mar & 0x3F]);
if (index < 24)
mem_mapping_disable(&headland_4000_9FFF_mapping[index]);
if (virt_addr < (mem_size << 10))
mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + virt_addr);
else
mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], NULL);
mem_mapping_enable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
flushmmucache();
}
if (headland_ems_mar & 0x80)
headland_ems_mar++;
break;
case 0x1ED:
headland_cri = val;
break;
case 0x1EE:
headland_ems_mar = val;
break;
case 0x1EF:
old_val = headland_regs_cr[headland_cri];
switch(headland_cri) {
case 0:
headland_regs_cr[0] = (val & 0x1F) | headland_mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
mem_set_mem_state(0xE0000, 0x10000, (val & 8 ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
mem_set_mem_state(0xF0000, 0x10000, (val & 0x10 ? MEM_READ_INTERNAL: MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
headland_memmap_state_update();
break;
case 1:
headland_regs_cr[1] = (val & 0xBF) | headland_mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
headland_memmap_state_update();
break;
case 2:
case 3:
case 5:
headland_regs_cr[headland_cri] = val;
headland_memmap_state_update();
break;
case 4:
headland_regs_cr[4] = (headland_regs_cr[4] & 0xF0) | (val & 0x0F);
if (val & 1) {
mem_mapping_disable(&bios_mapping[0]);
mem_mapping_disable(&bios_mapping[1]);
mem_mapping_disable(&bios_mapping[2]);
mem_mapping_disable(&bios_mapping[3]);
} else {
mem_mapping_enable(&bios_mapping[0]);
mem_mapping_enable(&bios_mapping[1]);
mem_mapping_enable(&bios_mapping[2]);
mem_mapping_enable(&bios_mapping[3]);
}
break;
case 6:
if (headland_regs_cr[4] & 0x80) {
headland_regs_cr[headland_cri] = (val & 0xFE) | (mem_size > 8192 ? 1 : 0);
headland_memmap_state_update();
}
break;
default:
break;
}
break;
default:
break;
}
}
static void
headland_writew(uint16_t addr, uint16_t val, void *priv)
{
uint8_t index;
uint32_t base_addr, virt_addr;
switch(addr) {
case 0x1EC:
headland_ems_mr[headland_ems_mar & 0x3F] = val;
index = headland_ems_mar & 0x1F;
base_addr = (index + 16) << 14;
if (index >= 24)
base_addr += 0x20000;
if ((headland_regs_cr[0] & 2) && (headland_regs_cr[0] & 1) == ((headland_ems_mar & 0x20) >> 5)) {
if(val & 0x200) {
virt_addr = get_headland_addr(base_addr, &headland_ems_mr[headland_ems_mar & 0x3F]);
if (index < 24)
mem_mapping_disable(&headland_4000_9FFF_mapping[index]);
if (virt_addr < (mem_size << 10))
mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + virt_addr);
else
mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], NULL);
mem_mapping_enable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
} else {
mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + base_addr);
mem_mapping_disable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
if (index < 24)
mem_mapping_enable(&headland_4000_9FFF_mapping[index]);
}
flushmmucache();
}
if (headland_ems_mar & 0x80)
headland_ems_mar++;
break;
default:
break;
}
}
static uint8_t
headland_read(uint16_t addr, void *priv)
{
uint8_t val;
switch(addr) {
case 0x22:
val = headland_index;
break;
case 0x23:
if ((headland_index >= 0xc0 || headland_index == 0x20) && cpu_iscyrix)
val = 0xff; /*Don't conflict with Cyrix config registers*/
else
val = headland_regs[headland_index];
break;
case 0x92:
val = headland_port_92 | 0xFC;
break;
case 0x1EC:
val = headland_ems_mr[headland_ems_mar & 0x3F];
if (headland_ems_mar & 0x80)
headland_ems_mar++;
break;
case 0x1ED:
val = headland_cri;
break;
case 0x1EE:
val = headland_ems_mar;
break;
case 0x1EF:
switch(headland_cri) {
case 0:
val = (headland_regs_cr[0] & 0x1F) | headland_mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
break;
case 1:
val = (headland_regs_cr[1] & 0xBF) | headland_mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
break;
case 6:
if (headland_regs_cr[4] & 0x80)
val = (headland_regs_cr[6] & 0xFE) | (mem_size > 8192 ? 1 : 0);
else
val = 0;
break;
default:
val = headland_regs_cr[headland_cri];
break;
}
break;
default:
val = 0xFF;
break;
}
return val;
}
static uint16_t
headland_readw(uint16_t addr, void *priv)
{
uint16_t val;
switch(addr) {
case 0x1EC:
val = headland_ems_mr[headland_ems_mar & 0x3F] | ((headland_regs_cr[4] & 0x80) ? 0xF000 : 0xFC00);
if (headland_ems_mar & 0x80)
headland_ems_mar++;
break;
default:
val = 0xFFFF;
break;
}
return val;
}
static uint8_t
mem_read_headlandb(uint32_t addr, void *priv)
{
uint8_t val = 0xff;
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
val = ram[addr];
return val;
}
static uint16_t
mem_read_headlandw(uint32_t addr, void *priv)
{
uint16_t val = 0xffff;
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
val = *(uint16_t *)&ram[addr];
return val;
}
static uint32_t
mem_read_headlandl(uint32_t addr, void *priv)
{
uint32_t val = 0xffffffff;
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
val = *(uint32_t *)&ram[addr];
return val;
}
static void
mem_write_headlandb(uint32_t addr, uint8_t val, void *priv)
{
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
ram[addr] = val;
}
static void
mem_write_headlandw(uint32_t addr, uint16_t val, void *priv)
{
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
*(uint16_t *)&ram[addr] = val;
}
static void
mem_write_headlandl(uint32_t addr, uint32_t val, void *priv)
{
addr = get_headland_addr(addr, priv);
if (addr < (mem_size << 10))
*(uint32_t *)&ram[addr] = val;
}
static void
headland_init(int ht386)
{
int i;
for(i=0; i<8; i++)
headland_regs_cr[i] = 0;
headland_regs_cr[0] = 4;
if (ht386) {
headland_regs_cr[4] = 0x20;
io_sethandler(0x0092, 0x0001, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
} else
headland_regs_cr[4] = 0;
io_sethandler(0x01EC, 0x0001, headland_read, headland_readw, NULL, headland_write, headland_writew, NULL, NULL);
io_sethandler(0x01ED, 0x0003, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
for(i=0; i<64; i++)
headland_ems_mr[i] = 0;
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
mem_mapping_add(&headland_low_mapping, 0, 0x40000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram, MEM_MAPPING_INTERNAL, NULL);
if(mem_size > 640) {
mem_mapping_add(&headland_mid_mapping, 0xA0000, 0x60000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&headland_mid_mapping);
}
if(mem_size > 1024) {
mem_mapping_add(&headland_high_mapping, 0x100000, ((mem_size - 1024) * 1024), mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram + 0x100000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&headland_high_mapping);
}
for (i = 0; i < 24; i++) {
mem_mapping_add(&headland_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, mem_size > 256 + (i << 4) ? ram + 0x40000 + (i << 14) : NULL, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&headland_4000_9FFF_mapping[i]);
}
for (i = 0; i < 64; i++) {
headland_ems_mr[i] = 0;
mem_mapping_add(&headland_ems_mapping[i], ((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14), 0, &headland_ems_mr[i]);
mem_mapping_disable(&headland_ems_mapping[i]);
}
headland_memmap_state_update();
}
static void
machine_at_headland_common_init(int ht386)
{
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
headland_init(ht386);
}
void
machine_at_headland_init(const machine_t *model)
{
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
}
void
machine_at_tg286m_init(const machine_t *model)
{
machine_at_common_ide_init(model);
machine_at_headland_common_init(0);
}
const device_t *
at_ama932j_get_device(void)
{
return &oti067_ama932j_device;
}
void
machine_at_ama932j_init(const machine_t *model)
{
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
if (gfxcard == VID_INTERNAL)
device_add(&oti067_ama932j_device);
}

890
src/machine/m_at_neat.c
View File

@@ -1,890 +0,0 @@
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* This file is part of the VARCem Project.
*
* Emulation of C&T CS8121 ("NEAT") 82C206/211/212/215 chipset.
*
* Note: The datasheet mentions that the chipset supports up to 8MB
* of DRAM. This is intepreted as 'being able to refresh up to
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
* Version: @(#)m_at_neat.c 1.0.5 2018/10/22
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2018 Fred N. van Kempen.
*
* Redistribution and use in source and binary forms, with
or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../keyboard.h"
#include "../io.h"
#include "../mem.h"
#include "../nmi.h"
#include "machine.h"
#define NEAT_DEBUG 0
#define EMS_MAXPAGE 4
#define EMS_PGSIZE 16384
/* CS8221 82C211 controller registers. */
#define REG_RA0 0x60 /* PROCCLK selector */
# define RA0_MASK 0x34 /* RR11 X1XR */
# define RA0_READY 0x01 /* local bus READY timeout */
# define RA0_RDYNMIEN 0x04 /* local bus READY tmo NMI enable */
# define RA0_PROCCLK 0x10 /* PROCCLK=BCLK (1) or CLK2IN (0) */
# define RA0_ALTRST 0x20 /* alternate CPU reset (1) */
# define RA0_REV 0xc0 /* chip revision ID */
# define RA0_REV_SH 6
# define RA0_REV_ID 2 /* faked revision# for 82C211 */
#define REG_RA1 0x61 /* Command Delay */
# define RA1_MASK 0xff /* 1111 1111 */
# define RA1_BUSDLY 0x03 /* AT BUS command delay */
# define RA1_BUSDLY_SH 0
# define RA1_BUS8DLY 0x0c /* AT BUS 8bit command delay */
# define RA1_BUS8DLY_SH 2
# define RA1_MEMDLY 0x30 /* AT BUS 16bit memory delay */
# define RA1_MEMDLY_SH 4
# define RA1_QUICKEN 0x40 /* Quick Mode enable */
# define RA1_HOLDDLY 0x80 /* Hold Time Delay */
#define REG_RA2 0x62 /* Wait State / BCLK selector */
# define RA2_MASK 0x3f /* XX11 1111 */
# define RA2_BCLK 0x03 /* BCLK select */
# define RA2_BCLK_SH 0
# define BCLK_IN2 0 /* BCLK = CLK2IN/2 */
# define BCLK_IN 1 /* BCLK = CLK2IN */
# define BCLK_AT 2 /* BCLK = ATCLK */
# define RA2_AT8WS 0x0c /* AT 8-bit wait states */
# define RA2_AT8WS_SH 2
# define AT8WS_2 0 /* 2 wait states */
# define AT8WS_3 1 /* 3 wait states */
# define AT8WS_4 2 /* 4 wait states */
# define AT8WS_5 4 /* 5 wait states */
# define RA2_ATWS 0x30 /* AT 16-bit wait states */
# define RA2_ATWS_SH 4
# define ATWS_2 0 /* 2 wait states */
# define ATWS_3 1 /* 3 wait states */
# define ATWS_4 2 /* 4 wait states */
# define ATWS_5 4 /* 5 wait states */
/* CS8221 82C212 controller registers. */
#define REG_RB0 0x64 /* Version ID */
# define RB0_MASK 0x60 /* R11X XXXX */
# define RB0_REV 0x60 /* Chip revsion number */
# define RB0_REV_SH 5
# define RB0_REV_ID 2 /* faked revision# for 82C212 */
# define RB0_VERSION 0x80 /* Chip version (0=82C212) */
#define REG_RB1 0x65 /* ROM configuration */
# define RB1_MASK 0xff /* 1111 1111 */
# define RB1_ROMF0 0x01 /* ROM F0000 enabled (0) */
# define RB1_ROME0 0x02 /* ROM E0000 disabled (1) */
# define RB1_ROMD0 0x04 /* ROM D0000 disabled (1) */
# define RB1_ROMC0 0x08 /* ROM C0000 disabled (1) */
# define RB1_SHADOWF0 0x10 /* Shadow F0000 R/W (0) */
# define RB1_SHADOWE0 0x20 /* Shadow E0000 R/W (0) */
# define RB1_SHADOWD0 0x40 /* Shadow D0000 R/W (0) */
# define RB1_SHADOWC0 0x80 /* Shadow C0000 R/W (0) */
#define REG_RB2 0x66 /* Memory Enable 1 */
# define RB2_MASK 0x80 /* 1XXX XXXX */
# define RB2_TOP128 0x80 /* top 128K is on sysboard (1) */
#define REG_RB3 0x67 /* Memory Enable 2 */
# define RB3_MASK 0xff /* 1111 1111 */
# define RB3_SHENB0 0x01 /* enable B0000-B3FFF shadow (1) */
# define RB3_SHENB4 0x02 /* enable B4000-B7FFF shadow (1) */
# define RB3_SHENB8 0x04 /* enable B8000-BBFFF shadow (1) */
# define RB3_SHENBC 0x08 /* enable BC000-BFFFF shadow (1) */
# define RB3_SHENA0 0x10 /* enable A0000-A3FFF shadow (1) */
# define RB3_SHENA4 0x20 /* enable A4000-A7FFF shadow (1) */
# define RB3_SHENA8 0x40 /* enable A8000-ABFFF shadow (1) */
# define RB3_SHENAC 0x80 /* enable AC000-AFFFF shadow (1) */
#define REG_RB4 0x68 /* Memory Enable 3 */
# define RB4_MASK 0xff /* 1111 1111 */
# define RB4_SHENC0 0x01 /* enable C0000-C3FFF shadow (1) */
# define RB4_SHENC4 0x02 /* enable C4000-C7FFF shadow (1) */
# define RB4_SHENC8 0x04 /* enable C8000-CBFFF shadow (1) */
# define RB4_SHENCC 0x08 /* enable CC000-CFFFF shadow (1) */
# define RB4_SHEND0 0x10 /* enable D0000-D3FFF shadow (1) */
# define RB4_SHEND4 0x20 /* enable D4000-D7FFF shadow (1) */
# define RB4_SHEND8 0x40 /* enable D8000-DBFFF shadow (1) */
# define RB4_SHENDC 0x80 /* enable DC000-DFFFF shadow (1) */
#define REG_RB5 0x69 /* Memory Enable 4 */
# define RB5_MASK 0xff /* 1111 1111 */
# define RB5_SHENE0 0x01 /* enable E0000-E3FFF shadow (1) */
# define RB5_SHENE4 0x02 /* enable E4000-E7FFF shadow (1) */
# define RB5_SHENE8 0x04 /* enable E8000-EBFFF shadow (1) */
# define RB5_SHENEC 0x08 /* enable EC000-EFFFF shadow (1) */
# define RB5_SHENF0 0x10 /* enable F0000-F3FFF shadow (1) */
# define RB5_SHENF4 0x20 /* enable F4000-F7FFF shadow (1) */
# define RB5_SHENF8 0x40 /* enable F8000-FBFFF shadow (1) */
# define RB5_SHENFC 0x80 /* enable FC000-FFFFF shadow (1) */
#define REG_RB6 0x6a /* Bank 0/1 Enable */
# define RB6_MASK 0xe0 /* 111R RRRR */
# define RB6_BANKS 0x20 /* #banks used (1=two) */
# define RB6_RTYPE 0xc0 /* DRAM chip size used */
# define RTYPE_SH 6
# define RTYPE_NONE 0 /* Disabled */
# define RTYPE_MIXED 1 /* 64K/256K mixed (for 640K) */
# define RTYPE_256K 2 /* 256K (default) */
# define RTYPE_1M 3 /* 1M */
#define REG_RB7 0x6b /* DRAM configuration */
# define RB7_MASK 0xff /* 1111 1111 */
# define RB7_ROMWS 0x03 /* ROM access wait states */
# define RB7_ROMWS_SH 0
# define ROMWS_0 0 /* 0 wait states */
# define ROMWS_1 1 /* 1 wait states */
# define ROMWS_2 2 /* 2 wait states */
# define ROMWS_3 3 /* 3 wait states (default) */
# define RB7_EMSWS 0x0c /* EMS access wait states */
# define RB7_EMSWS_SH 2
# define EMSWS_0 0 /* 0 wait states */
# define EMSWS_1 1 /* 1 wait states */
# define EMSWS_2 2 /* 2 wait states */
# define EMSWS_3 3 /* 3 wait states (default) */
# define RB7_EMSEN 0x10 /* enable EMS (1=on) */
# define RB7_RAMWS 0x20 /* RAM access wait state (1=1ws) */
# define RB7_UMAREL 0x40 /* relocate 640-1024K to 1M */
# define RB7_PAGEEN 0x80 /* enable Page/Interleaved mode */
#define REG_RB8 0x6c /* Bank 2/3 Enable */
# define RB8_MASK 0xf0 /* 1111 RRRR */
# define RB8_4WAY 0x10 /* enable 4-way interleave mode */
# define RB8_BANKS 0x20 /* enable 2 banks (1) */
# define RB8_RTYPE 0xc0 /* DRAM chip size used */
# define RB8_RTYPE_SH 6
#define REG_RB9 0x6d /* EMS base address */
# define RB9_MASK 0xff /* 1111 1111 */
# define RB9_BASE 0x0f /* I/O base address selection */
# define RB9_BASE_SH 0
# define RB9_FRAME 0xf0 /* frame address selection */
# define RB9_FRAME_SH 4
#define REG_RB10 0x6e /* EMS address extension */
# define RB10_MASK 0xff /* 1111 1111 */
# define RB10_P3EXT 0x03 /* page 3 extension */
# define RB10_P3EXT_SH 0
# define PEXT_0M 0 /* page is at 0-2M */
# define PEXT_2M 1 /* page is at 2-4M */
# define PEXT_4M 2 /* page is at 4-6M */
# define PEXT_6M 3 /* page is at 6-8M */
# define RB10_P2EXT 0x0c /* page 2 extension */
# define RB10_P2EXT_SH 2
# define RB10_P1EXT 0x30 /* page 1 extension */
# define RB10_P1EXT_SH 4
# define RB10_P0EXT 0xc0 /* page 0 extension */
# define RB10_P0EXT_SH 6
#define REG_RB11 0x6f /* Miscellaneous */
# define RB11_MASK 0xe6 /* 111R R11R */
# define RB11_GA20 0x02 /* gate for A20 */
# define RB11_RASTMO 0x04 /* enable RAS timeout counter */
# define RB11_EMSLEN 0xe0 /* EMS memory chunk size */
# define RB11_EMSLEN_SH 5
typedef struct {
int8_t enabled; /* 1=ENABLED */
char pad;
uint16_t page; /* selected page in EMS block */
uint32_t start; /* start of EMS in RAM */
uint8_t *addr; /* start addr in EMS RAM */
mem_mapping_t mapping; /* mapping entry for page */
} emspage_t;
typedef struct {
uint8_t regs[128]; /* all the CS8221 registers */
uint8_t indx; /* programmed index into registers */
char pad;
uint16_t ems_base, /* configured base address */
ems_oldbase;
uint32_t ems_frame, /* configured frame address */
ems_oldframe;
uint16_t ems_size, /* EMS size in KB */
ems_pages; /* EMS size in pages */
emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */
} neat_t;
#ifdef ENABLE_NEAT_LOG
int neat_do_log = ENABLE_NEAT_LOG;
static void
neat_log(const char *fmt, ...)
{
va_list ap;
if (neat_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define neat_log(fmt, ...)
#endif
/* Read one byte from paged RAM. */
static uint8_t
ems_readb(uint32_t addr, void *priv)
{
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
uint8_t ret = 0xff;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Grab the data. */
ret = *(uint8_t *)(dev->ems[vpage].addr + (addr - map->base));
return(ret);
}
/* Read one word from paged RAM. */
static uint16_t
ems_readw(uint32_t addr, void *priv)
{
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
uint16_t ret = 0xffff;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Grab the data. */
ret = *(uint16_t *)(dev->ems[vpage].addr + (addr - map->base));
return(ret);
}
/* Write one byte to paged RAM. */
static void
ems_writeb(uint32_t addr, uint8_t val, void *priv)
{
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Write the data. */
*(uint8_t *)(dev->ems[vpage].addr + (addr - map->base)) = val;
}
/* Write one word to paged RAM. */
static void
ems_writew(uint32_t addr, uint16_t val, void *priv)
{
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Write the data. */
*(uint16_t *)(dev->ems[vpage].addr + (addr - map->base)) = val;
}
/* Re-calculate the active-page physical address. */
static void
ems_recalc(neat_t *dev, emspage_t *ems)
{
if (ems->page >= dev->ems_pages) {
/* That page does not exist. */
ems->enabled = 0;
}
/* Pre-calculate the page address in EMS RAM. */
ems->addr = ram + ems->start + (ems->page * EMS_PGSIZE);
if (ems->enabled) {
/* Update the EMS RAM address for this page. */
mem_mapping_set_exec(&ems->mapping, ems->addr);
/* Enable this page. */
mem_mapping_enable(&ems->mapping);
#if NEAT_DEBUG > 1
neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n",
ems->page, ems->addr-ram, ems->enabled?"en":"dis");
#endif
} else {
/* Disable this page. */
mem_mapping_disable(&ems->mapping);
}
}
static void
ems_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *)priv;
emspage_t *ems;
int vpage;
#if NEAT_DEBUG > 1
neat_log("NEAT: ems_write(%04x, %02x)\n", port, val);
#endif
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
ems = &dev->ems[vpage];
switch(port & 0x000f) {
case 0x0008:
case 0x0009:
ems->enabled = !!(val & 0x80);
ems->page &= 0x0180; /* clear lower bits */
ems->page |= (val & 0x7f); /* add new bits */
ems_recalc(dev, ems);
break;
}
}
static uint8_t
ems_read(uint16_t port, void *priv)
{
neat_t *dev = (neat_t *)priv;
uint8_t ret = 0xff;
int vpage;
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
switch(port & 0x000f) {
case 0x0008: /* page number register */
ret = dev->ems[vpage].page & 0x7f;
if (dev->ems[vpage].enabled)
ret |= 0x80;
break;
}
#if NEAT_DEBUG > 1
neat_log("NEAT: ems_read(%04x) = %02x\n", port, ret);
#endif
return(ret);
}
/* Initialize the EMS module. */
static void
ems_init(neat_t *dev, int en)
{
int i;
/* Remove if needed. */
if (! en) {
if (dev->ems_base > 0) for (i = 0; i < EMS_MAXPAGE; i++) {
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Remove I/O handler. */
io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read,NULL,NULL, ems_write,NULL,NULL, dev);
}
neat_log("NEAT: EMS disabled\n");
return;
}
/* Get configured I/O address. */
i = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
dev->ems_base = 0x0208 + (0x10 * i);
/* Get configured frame address. */
i = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
dev->ems_frame = 0xC0000 + (EMS_PGSIZE * i);
/*
* For each supported page (we can have a maximum of 4),
* create, initialize and disable the mappings, and set
* up the I/O control handler.
*/
for (i = 0; i < EMS_MAXPAGE; i++) {
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i].mapping,
dev->ems_frame + (EMS_PGSIZE*i), EMS_PGSIZE,
ems_readb, ems_readw, NULL,
ems_writeb, ems_writew, NULL,
ram, MEM_MAPPING_EXTERNAL,
&dev->ems[i].mapping);
mem_mapping_set_dev(&dev->ems[i].mapping, dev);
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Set up an I/O port handler. */
io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read,NULL,NULL, ems_write,NULL,NULL, dev);
/*
* TODO: update the 'high_mem' mapping to reflect that we now
* have NN MB less extended memory available..
*/
}
neat_log("NEAT: EMS enabled, I/O=%04xH, Frame=%05XH\n",
dev->ems_base, dev->ems_frame);
}
static void
neat_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *)priv;
uint8_t xval, *reg;
int i;
#if NEAT_DEBUG > 2
neat_log("NEAT: write(%04x, %02x)\n", port, val);
#endif
switch (port) {
case 0x22:
dev->indx = val;
break;
case 0x23:
reg = &dev->regs[dev->indx];
xval = *reg ^ val;
switch (dev->indx) {
case REG_RA0:
val &= RA0_MASK;
*reg = (*reg & ~RA0_MASK) | val | \
(RA0_REV_ID << RA0_REV_SH);
#if NEAT_DEBUG > 1
neat_log("NEAT: RA0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA1:
val &= RA1_MASK;
*reg = (*reg & ~RA1_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RA1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA2:
val &= RA2_MASK;
*reg = (*reg & ~RA2_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RA2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB0:
val &= RB0_MASK;
*reg = (*reg & ~RB0_MASK) | val | \
(RB0_REV_ID << RB0_REV_SH);
#if NEAT_DEBUG > 1
neat_log("NEAT: RB0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB1:
val &= RB1_MASK;
*reg = (*reg & ~RB1_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB2:
val &= RB2_MASK;
*reg = (*reg & ~RB2_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB3:
val &= RB3_MASK;
*reg = (*reg & ~RB3_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB3=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB4:
val &= RB4_MASK;
*reg = (*reg & ~RB4_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB4=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB5:
val &= RB5_MASK;
*reg = (*reg & ~RB5_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB5=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB6:
val &= RB6_MASK;
*reg = (*reg & ~RB6_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB6=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB7:
val &= RB7_MASK;
*reg = (*reg & ~RB7_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg);
#endif
if (val & RB7_EMSEN)
ems_init(dev, 1);
else if (xval & RB7_EMSEN)
ems_init(dev, 0);
if (xval & RB7_UMAREL) {
if (val & RB7_UMAREL)
mem_remap_top(384);
else
mem_remap_top(0);
}
break;
case REG_RB8:
val &= RB8_MASK;
*reg = (*reg & ~RB8_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB8=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB9:
val &= RB9_MASK;
*reg = (*reg & ~RB9_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg);
#endif
if (dev->regs[REG_RB7] & RB7_EMSEN) {
ems_init(dev, 0);
ems_init(dev, 1);
}
break;
case REG_RB10:
val &= RB10_MASK;
*reg = (*reg & ~RB10_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg);
#endif
dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21;
dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21;
dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21;
dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21;
for (i = 0; i < EMS_MAXPAGE; i++)
ems_recalc(dev, &dev->ems[i]);
break;
case REG_RB11:
val &= RB11_MASK;
*reg = (*reg & ~RB11_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB11=%02x(%02x)\n", val, *reg);
#endif
i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH;
switch(i) {
case 0: /* "less than 2MB" */
dev->ems_size = 512;
break;
case 1: /* 1 MB */
case 2: /* 2 MB */
case 3: /* 3 MB */
case 4: /* 4 MB */
case 5: /* 5 MB */
case 6: /* 6 MB */
case 7: /* 7 MB */
dev->ems_size = i << 10;
break;
}
dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE;
if (dev->regs[REG_RB7] & RB7_EMSEN)
neat_log("NEAT: EMS %iKB (%i pages)\n",
dev->ems_size, dev->ems_pages);
break;
default:
neat_log("NEAT: inv write to reg %02x (%02x)\n",
dev->indx, val);
break;
}
break;
}
}
static uint8_t
neat_read(uint16_t port, void *priv)
{
neat_t *dev = (neat_t *)priv;
uint8_t ret = 0xff;
switch (port) {
case 0x22:
ret = dev->indx;
break;
case 0x23:
ret = dev->regs[dev->indx];
break;
default:
break;
}
#if NEAT_DEBUG > 2
neat_log("NEAT: read(%04x) = %02x\n", port, ret);
#endif
return(ret);
}
static void
neat_init(void)
{
neat_t *dev;
int i;
/* Create an instance. */
dev = (neat_t *)malloc(sizeof(neat_t));
memset(dev, 0x00, sizeof(neat_t));
/* Initialize some of the registers to specific defaults. */
for (i = REG_RA0; i <= REG_RB11; i++) {
dev->indx = i;
neat_write(0x0023, 0x00, dev);
}
/*
* Based on the value of mem_size, we have to set up
* a proper DRAM configuration (so that EMS works.)
*
* TODO: We might also want to set 'valid' waitstate
* bits, based on our cpu speed.
*/
i = 0;
switch(mem_size) {
case 512: /* 512KB */
/* 256K, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 2;
break;
case 640: /* 640KB */
/* 256K, 64K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 4;
break;
case 1024: /* 1MB */
/* 256K, 256K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 5;
break;
case 1536: /* 1.5MB */
/* 256K, 256K, 256K, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
i = 7;
break;
case 1664: /* 1.64MB */
/* 256K, 64K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
i = 10;
break;
case 2048: /* 2MB */
#if 1
/* 256K, 256K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 11;
#else
/* 1M, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 3;
#endif
break;
case 3072: /* 3MB */
/* 256K, 256K, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 8;
break;
case 4096: /* 4MB */
/* 1M, 1M, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 6;
break;
case 4224: /* 4.64MB */
/* 256K, 64K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 12;
break;
case 5120: /* 5MB */
/* 256K, 256K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 13;
break;
case 6144: /* 6MB */
/* 1M, 1M, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 9;
break;
case 8192: /* 8MB */
/* 1M, 1M, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 14;
break;
default:
neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size);
}
if (i > 0)
neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size);
/* Set up an I/O handler for the chipset. */
io_sethandler(0x0022, 2,
neat_read,NULL,NULL, neat_write,NULL,NULL, dev);
}
void
machine_at_neat_init(const machine_t *model)
{
machine_at_init(model);
neat_init();
device_add(&fdc_at_device);
}
void
machine_at_neat_ami_init(const machine_t *model)
{
machine_at_common_init(model);
neat_init();
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
}

347
src/machine/m_at_opti495.c
View File

@@ -1,347 +0,0 @@
/*OPTi 82C495 emulation
This is the chipset used in the AMI386 model
Details for the chipset from Ralph Brown's interrupt list
This describes the OPTi 82C493, the 82C495 seems similar except there is one
more register (2C)
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
Desc: The OPTi 486SXWB contains three chips and is designed for systems
running at 20, 25 and 33MHz. The chipset includes an 82C493 System
Controller (SYSC), the 82C392 Data Buffer Controller, and the
82C206 Integrated peripheral Controller (IPC).
Note: every access to PORT 0024h must be preceded by a write to PORT 0022h,
even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"
0022 ?W configuration register index (see #P0178)
0024 RW configuration register data
(Table P0178)
Values for OPTi 82C493 System Controller configuration register index:
20h Control Register 1 (see #P0179)
21h Control Register 2 (see #P0180)
22h Shadow RAM Control Register 1 (see #P0181)
23h Shadow RAM Control Register 2 (see #P0182)
24h DRAM Control Register 1 (see #P0183)
25h DRAM Control Register 2 (see #P0184)
26h Shadow RAM Control Register 3 (see #P0185)
27h Control Register 3 (see #P0186)
28h Non-cachable Block 1 Register 1 (see #P0187)
29h Non-cachable Block 1 Register 2 (see #P0188)
2Ah Non-cachable Block 2 Register 1 (see #P0187)
2Bh Non-cachable Block 2 Register 2 (see #P0188)
Bitfields for OPTi-82C493 Control Register 1:
Bit(s) Description (Table P0179)
7-6 Revision of 82C493 (readonly) (default=01)
5 Burst wait state control
1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
(if bit 5 is set to 1, bit 4 must be set to 0)
4 Cache memory data buffer output enable control
0 = disable (default)
1 = enable
(must be disabled for frequency <= 33Mhz)
3 Single Address Latch Enable (ALE)
0 = disable (default)
1 = enable
(if enabled, SYSC will activate single ALE rather than multiples
during bus conversion cycles)
2 enable Extra AT Cycle Wait State (default is 0 = disabled)
1 Emulation keyboard Reset Control
0 = disable (default)
1 = enable
Note: This bit must be enabled in BIOS default value; enabling this
bit requires HALT instruction to be executed before SYSC
generates processor reset (CPURST)
0 enable Alternative Fast Reset (default is 0 = disabled)
SeeAlso: #P0180,#P0186
Bitfields for OPTi-82C493 Control Register 2:
Bit(s) Description (Table P0180)
7 Master Mode Byte Swap Enable
0 = disable (default)
1 = enable
6 Emulation Keyboard Reset Delay Control
0 = Generate reset pulse 2us later (default)
1 = Generate reset pulse immediately
5 disable Parity Check (default is 0 = enabled)
4 Cache Enable
0 = Cache disabled and DRAM burst mode enabled (default)
1 = Cache enabled and DRAM burst mode disabled
3-2 Cache Size
00 64KB (default)
01 128KB
10 256KB
11 512KB
1 Secondary Cache Read Burst Cycles Control
0 = 3-1-1-1 cycle (default)
1 = 2-1-1-1 cycle
0 Cache Write Wait State Control
0 = 1 wait state (default)
1 = 0 wait state
SeeAlso: #P0179,#P0186
Bitfields for OPTi-82C493 Shadow RAM Control Register 1:
Bit(s) Description (Table P0181)
7 ROM(F0000h - FFFFFh) Enable
0 = read/write on write-protected DRAM
1 = read from ROM, write to DRAM (default)
6 Shadow RAM at D0000h - EFFFFh Area
0 = disable (default)
1 = enable
5 Shadow RAM at E0000h - EFFFFh Area
0 = disable shadow RAM (default)
E0000h - EFFFFh ROM is defaulted to reside on XD bus
1 = enable shadow RAM
4 enable write-protect for Shadow RAM at D0000h - DFFFFh Area
0 = disable (default)
1 = enable
3 enable write-protect for Shadow RAM at E0000h - EFFFFh Area
0 = disable (default)
1 = enable
2 Hidden refresh enable (with holding CPU)
(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used)
1 = disable (default)
0 = enable
1 unused
0 enable Slow Refresh (four times slower than normal refresh)
(default is 0 = disable)
SeeAlso: #P0182
Bitfields for OPTi-82C493 Shadow RAM Control Register 2:
Bit(s) Description (Table P0182)
7 enable Shadow RAM at EC000h - EFFFFh area
6 enable Shadow RAM at E8000h - EBFFFh area
5 enable Shadow RAM at E4000h - E7FFFh area
4 enable Shadow RAM at E0000h - E3FFFh area
3 enable Shadow RAM at DC000h - DFFFFh area
2 enable Shadow RAM at D8000h - DBFFFh area
1 enable Shadow RAM at D4000h - D7FFFh area
0 enable Shadow RAM at D0000h - D3FFFh area
Note: the default is disabled (0) for all areas
Bitfields for OPTi-82C493 DRAM Control Register 1:
Bit(s) Description (Table P0183)
7 DRAM size
0 = 256K DRAM mode
1 = 1M and 4M DRAM mode
6-4 DRAM types used for bank0 and bank1
bits 7-4 Bank0 Bank1
0000 256K x
0001 256K 256K
0010 256K 1M
0011 x x
01xx x x
1000 1M x (default)
1001 1M 1M
1010 1M 4M
1011 4M 1M
1100 4M x
1101 4M 4M
111x x x
3 unused
2-0 DRAM types used for bank2 and bank3
bits 7,2-0 Bank2 Bank3
x000 1M x
x001 1M 1M
x010 x x
x011 4M 1M
x100 4M x
x101 4M 4M
x11x x x (default)
SeeAlso: #P0184
Bitfields for OPTi-82C493 DRAM Control Register 2:
Bit(s) Description (Table P0184)
7-6 Read cycle additional wait states
00 not used
01 = 0
10 = 1
11 = 2 (default)
5-4 Write cycle additional wait states
00 = 0
01 = 1
10 = 2
11 = 3 (default)
3 Fast decode enable
0 = disable fast decode. DRAM base wait states not changed (default)
1 = enable fast decode. DRAM base wait state is decreased by 1
Note: This function may be enabled in 20/25Mhz operation to speed up
DRAM access. If bit 4 of index register 21h (cache enable
bit) is enabled, this bit is automatically disabled--even if
set to 1
2 unused
1-0 ATCLK selection
00 ATCLK = CLKI/6 (default)
01 ATCLK = CLKI/4 (default)
10 ATCLK = CLKI/3
11 ATCLK = CLK2I/5 (CLKI * 2 /5)
Note: bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
set to 0 when 82C493 is reset.
SeeAlso: #P0183,#P0185
Bitfields for OPTi-82C493 Shadow RAM Control Register 3:
Bit(s) Description (Table P0185)
7 unused
6 Shadow RAM copy enable for address C0000h - CFFFFh
0 = Read/write at AT bus (default)
1 = Read from AT bus and write into shadow RAM
5 Shadow write protect at address C0000h - CFFFFh
0 = Write protect disable (default)
1 = Write protect enable
4 enable Shadow RAM at C0000h - CFFFFh
3 enable Shadow RAM at CC000h - CFFFFh
2 enable Shadow RAM at C8000h - CBFFFh
1 enable Shadow RAM at C4000h - C7FFFh
0 enable Shadow RAM at C0000h - C3FFFh
Note: the default is disabled (0) for bits 4-0
SeeAlso: #P0183,#P0184
Bitfields for OPTi-82C493 Control Register 3:
Bit(s) Description (Table P0186)
7 enable NCA# pin to low state (default is 1 = enabled)
6-5 unused
4 Video BIOS at C0000h - C8000h non-cacheable
0 = cacheable
1 = non-cacheable (default)
3-0 Cacheable address range for local memory
0000 0 - 64MB
0001 0 - 4MB (default)
0010 0 - 8MB
0011 0 - 12MB
0100 0 - 16MB
0101 0 - 20MB
0110 0 - 24MB
0111 0 - 28MB
1000 0 - 32MB
1001 0 - 36MB
1010 0 - 40MB
1011 0 - 44MB
1100 0 - 48MB
1101 0 - 52MB
1110 0 - 56MB
1111 0 - 60MB
Note: If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
0-2 MB and independent of the value of bits 3-0
SeeAlso: #P0179,#P0180
Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
Bit(s) Description (Table P0187)
7-5 Size of non-cachable memory block
000 64K
001 128K
010 256K
011 512K
1xx disabled (default)
4-2 unused
1-0 Address bits 25 and 24 of non-cachable memory block (default = 00)
Note: this register is used together with configuration register 29h
(non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
define a non-cacheable block. The starting address must be a
multiple of the block size
SeeAlso: #P0178,#P0188
Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
Bit(s) Description (Table P0188)
7-0 Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
Note: the block address is forced to be a multiple of the block size by
ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../device.h"
#include "../keyboard.h"
#include "../mem.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "machine.h"
static uint8_t optiregs[0x10];
static int optireg;
static void opti495_write(uint16_t addr, uint8_t val, void *p)
{
switch (addr)
{
case 0x22:
optireg=val;
break;
case 0x24:
if (optireg>=0x20 && optireg<=0x2C)
{
optiregs[optireg-0x20]=val;
if (optireg == 0x21)
{
cpu_cache_ext_enabled = val & 0x10;
cpu_update_waitstates();
}
if (optireg == 0x22)
{
shadowbios = !(val & 0x80);
shadowbios_write = val & 0x80;
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
}
}
break;
}
}
static uint8_t opti495_read(uint16_t addr, void *p)
{
switch (addr)
{
case 0x24:
if (optireg>=0x20 && optireg<=0x2C) return optiregs[optireg-0x20];
break;
}
return 0xFF;
}
static void opti495_init(void)
{
io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
optiregs[0x22-0x20] = 0x80;
}
void
machine_at_opti495_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&keyboard_at_device);
device_add(&fdc_at_device);
opti495_init();
}
void
machine_at_opti495_ami_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
opti495_init();
}

1393
src/machine/m_at_scat.c
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233
src/machine/m_at_sis_85c471.c
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@@ -1,233 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 85c471 chip.
*
* SiS sis85c471 Super I/O Chip
* Used by DTK PKM-0038S E-2
*
* Version: @(#)m_at_sis85c471.c 1.0.13 2018/11/12
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../io.h"
#include "../memregs.h"
#include "../device.h"
#include "../lpt.h"
#include "../serial.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "machine.h"
typedef struct {
uint8_t cur_reg,
regs[39];
serial_t *uart[2];
} sis_85c471_t;
static void
sis_85c471_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor;
if (index) {
if ((val >= 0x50) && (val <= 0x76))
dev->cur_reg = val;
return;
} else {
if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76))
return;
valxor = val ^ dev->regs[dev->cur_reg - 0x50];
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (dev->cur_reg != 0x52)
dev->regs[dev->cur_reg - 0x50] = val;
}
switch(dev->cur_reg) {
case 0x73:
if (valxor & 0x40) {
ide_pri_disable();
if (val & 0x40)
ide_pri_enable();
}
if (valxor & 0x20) {
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
if (val & 0x20) {
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(dev->uart[0], SERIAL2_ADDR, SERIAL2_IRQ);
}
}
if (valxor & 0x10) {
lpt1_remove();
if (val & 0x10)
lpt1_init(0x378);
}
break;
}
dev->cur_reg = 0;
}
static uint8_t
sis_85c471_read(uint16_t port, void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;;
if (index)
ret = dev->cur_reg;
else {
if ((dev->cur_reg >= 0x50) && (dev->cur_reg <= 0x76)) {
ret = dev->regs[dev->cur_reg - 0x50];
dev->cur_reg = 0;
}
}
return ret;
}
static void
sis_85c471_close(void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
free(dev);
}
static void *
sis_85c471_init(const device_t *info)
{
int mem_size_mb, i = 0;
sis_85c471_t *dev = (sis_85c471_t *) malloc(sizeof(sis_85c471_t));
memset(dev, 0, sizeof(sis_85c471_t));
lpt2_remove();
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
dev->uart[0] = device_add_inst(&i8250_device, 1);
dev->uart[1] = device_add_inst(&i8250_device, 2);
io_sethandler(0x0022, 0x0002,
sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, dev);
return dev;
}
const device_t sis_85c471_device = {
"SiS 85c471",
0,
0,
sis_85c471_init, sis_85c471_close, NULL,
NULL, NULL, NULL,
NULL
};
void
machine_at_dtk486_init(const machine_t *model)
{
machine_at_ide_init(model);
device_add(&fdc_at_device);
memregs_init();
device_add(&sis_85c471_device);
}

371
src/machine/m_at_sis_85c496.c
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 85c496/85c497 chip.
*
* Version: @(#)m_at_sis_85c496.c 1.0.3 2018/11/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../keyboard.h"
#include "../io.h"
#include "../pci.h"
#include "../mem.h"
#include "../memregs.h"
#include "../sio.h"
#include "../disk/hdc.h"
#include "machine.h"
typedef struct sis_85c496_t
{
uint8_t cur_reg,
regs[39],
pci_conf[256];
} sis_85c496_t;
static void
sis_85c497_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
if (index) {
if ((val >= 0x50) && (val <= 0x76))
dev->cur_reg = val;
return;
} else {
if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76))
return;
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (dev->cur_reg != 0x52)
dev->regs[dev->cur_reg - 0x50] = val;
}
dev->cur_reg = 0;
}
static uint8_t
sis_85c497_read(uint16_t port, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
if (index)
ret = dev->cur_reg;
else {
if ((dev->cur_reg >= 0x50) && (dev->cur_reg <= 0x76)) {
ret = dev->regs[dev->cur_reg - 0x50];
dev->cur_reg = 0;
}
}
return ret;
}
static void
sis_85c496_recalcmapping(sis_85c496_t *dev)
{
int c;
uint32_t base;
for (c = 0; c < 8; c++) {
base = 0xc0000 + (c << 15);
if (dev->pci_conf[0x44] & (1 << c)) {
switch (dev->pci_conf[0x45] & 3) {
case 0:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 1:
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
flushmmucache();
shadowbios = (dev->pci_conf[0x44] & 0xf0);
}
static void
sis_85c496_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
switch (addr) {
case 0x44: /*Shadow configure*/
if ((dev->pci_conf[0x44] & val) ^ 0xf0) {
dev->pci_conf[0x44] = val;
sis_85c496_recalcmapping(dev);
}
break;
case 0x45: /*Shadow configure*/
if ((dev->pci_conf[0x45] & val) ^ 0x01) {
dev->pci_conf[0x45] = val;
sis_85c496_recalcmapping(dev);
}
break;
case 0x82:
sis_85c497_write(0x22, val, priv);
break;
case 0xc0:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, val & 0xf);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
break;
case 0xc1:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, val & 0xf);
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
case 0xc2:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, val & 0xf);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
break;
case 0xc3:
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, val & 0xf);
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
}
if ((addr >= 4 && addr < 8) || addr >= 0x40)
dev->pci_conf[addr] = val;
}
static uint8_t
sis_85c496_read(int func, int addr, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
return dev->pci_conf[addr];
}
static void
sis_85c497_reset(sis_85c496_t *dev)
{
int mem_size_mb, i = 0;
memset(dev->regs, 0, sizeof(dev->regs));
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
io_removehandler(0x0022, 0x0002,
sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
io_sethandler(0x0022, 0x0002,
sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
}
static void
sis_85c496_reset(void *priv)
{
uint8_t val = 0;
val = sis_85c496_read(0, 0x44, priv); /* Read current value of 0x44. */
sis_85c496_write(0, 0x44, val & 0xf, priv); /* Turn off shadow BIOS but keep the lower 4 bits. */
sis_85c497_reset((sis_85c496_t *) priv);
}
static void
sis_85c496_close(void *p)
{
sis_85c496_t *sis_85c496 = (sis_85c496_t *)p;
free(sis_85c496);
}
static void
*sis_85c496_init(const device_t *info)
{
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
memset(dev, 0, sizeof(sis_85c496_t));
dev->pci_conf[0x00] = 0x39; /*SiS*/
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x96; /*496/497*/
dev->pci_conf[0x03] = 0x04;
dev->pci_conf[0x04] = 7;
dev->pci_conf[0x05] = 0;
dev->pci_conf[0x06] = 0x80;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 2; /*Device revision*/
dev->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0e] = 0x00; /*Single function device*/
pci_add_card(5, sis_85c496_read, sis_85c496_write, dev);
sis_85c497_reset(dev);
return dev;
}
const device_t sis_85c496_device =
{
"SiS 85c496/85c497",
DEVICE_PCI,
0,
sis_85c496_init,
sis_85c496_close,
sis_85c496_reset,
NULL,
NULL,
NULL,
NULL
};
static void
machine_at_sis_85c496_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_pci_device);
device_add(&ide_pci_device);
memregs_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
device_add(&sis_85c496_device);
}
void
machine_at_r418_init(const machine_t *model)
{
machine_at_sis_85c496_common_init(model);
device_add(&fdc37c665_device);
}

323
src/machine/m_at_sis_85c50x.c
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@@ -1,323 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SiS 50x PCI chips.
*
* Version: @(#)m_at_sis_85c50x.c 1.0.7 2018/04/29
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2018 Miran Grca.
*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include "../86box.h"
#include "../io.h"
#include "../pci.h"
#include "../mem.h"
#include "machine.h"
typedef struct sis_85c501_t
{
uint8_t pci_conf[256];
uint8_t turbo_reg;
} sis_85c501_t;
sis_85c501_t sis_85c501;
typedef struct sis_85c503_t
{
uint8_t pci_conf[256];
} sis_85c503_t;
sis_85c503_t sis_85c503;
typedef struct sis_85c50x_t
{
uint8_t isa_conf[12];
uint8_t reg;
} sis_85c50x_isa_t;
sis_85c50x_isa_t sis_85c50x_isa;
static void sis_85c501_recalcmapping(void)
{
int c, d;
for (c = 0; c < 1; c++)
{
for (d = 0; d < 4; d++)
{
uint32_t base = 0xe0000 + (d << 14);
if (sis_85c501.pci_conf[0x54 + c] & (1 << (d + 4)))
{
switch (sis_85c501.pci_conf[0x53] & 0x60)
{
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
flushmmucache();
shadowbios = 1;
}
static void sis_85c501_write(int func, int addr, uint8_t val, void *p)
{
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
break;
case 0x05:
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((sis_85c501.pci_conf[0x54] & val) ^ 0xf0)
{
sis_85c501.pci_conf[0x54] = val;
sis_85c501_recalcmapping();
}
break;
}
sis_85c501.pci_conf[addr] = val;
}
static void sis_85c503_write(int func, int addr, uint8_t val, void *p)
{
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x41)
return;
switch(addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
}
sis_85c503.pci_conf[addr] = val;
}
static void sis_85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB) sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg] = val;
}
else
{
sis_85c50x_isa.reg = val;
}
}
static uint8_t sis_85c501_read(int func, int addr, void *p)
{
if (func)
return 0xff;
return sis_85c501.pci_conf[addr];
}
static uint8_t sis_85c503_read(int func, int addr, void *p)
{
if (func > 0)
return 0xff;
return sis_85c503.pci_conf[addr];
}
static uint8_t sis_85c50x_isa_read(uint16_t port, void *priv)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB)
return sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg];
else
return 0xff;
}
else
{
return sis_85c50x_isa.reg;
}
}
static void sis_85c501_reset(void)
{
memset(&sis_85c501, 0, sizeof(sis_85c501_t));
sis_85c501.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c501.pci_conf[0x01] = 0x10;
sis_85c501.pci_conf[0x02] = 0x06; /*501/502*/
sis_85c501.pci_conf[0x03] = 0x04;
sis_85c501.pci_conf[0x04] = 7;
sis_85c501.pci_conf[0x05] = 0;
sis_85c501.pci_conf[0x06] = 0x80;
sis_85c501.pci_conf[0x07] = 0x02;
sis_85c501.pci_conf[0x08] = 0; /*Device revision*/
sis_85c501.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c501.pci_conf[0x0a] = 0x00;
sis_85c501.pci_conf[0x0b] = 0x06;
sis_85c501.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c501.pci_conf[0x50] = 0xbc;
sis_85c501.pci_conf[0x51] = 0xfb;
sis_85c501.pci_conf[0x52] = 0xad;
sis_85c501.pci_conf[0x53] = 0xfe;
shadowbios = 1;
}
static void sis_85c501_init(void)
{
pci_add_card(0, sis_85c501_read, sis_85c501_write, NULL);
sis_85c501_reset();
pci_reset_handler.pci_master_reset = NULL;
}
static void sis_85c503_reset(void)
{
memset(&sis_85c503, 0, sizeof(sis_85c503_t));
sis_85c503.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c503.pci_conf[0x01] = 0x10;
sis_85c503.pci_conf[0x02] = 0x08; /*503*/
sis_85c503.pci_conf[0x03] = 0x00;
sis_85c503.pci_conf[0x04] = 7;
sis_85c503.pci_conf[0x05] = 0;
sis_85c503.pci_conf[0x06] = 0x80;
sis_85c503.pci_conf[0x07] = 0x02;
sis_85c503.pci_conf[0x08] = 0; /*Device revision*/
sis_85c503.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c503.pci_conf[0x0a] = 0x01;
sis_85c503.pci_conf[0x0b] = 0x06;
sis_85c503.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c503.pci_conf[0x41] = sis_85c503.pci_conf[0x42] = sis_85c503.pci_conf[0x43] = sis_85c503.pci_conf[0x44] = 0x80;
}
static void sis_85c503_init(int card)
{
pci_add_card(card, sis_85c503_read, sis_85c503_write, NULL);
sis_85c503_reset();
trc_init();
port_92_reset();
port_92_add();
pci_reset_handler.pci_set_reset = sis_85c503_reset;
}
static void sis_85c50x_isa_init(void)
{
memset(&sis_85c50x_isa, 0, sizeof(sis_85c50x_isa_t));
io_sethandler(0x22, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, NULL);
}

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 4 and 5 machines.
*
* Version: @(#)m_at_socket4_5.c 1.0.0 2019/05/16
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "../io.h"
#include "../rom.h"
#include "../pci.h"
#include "../device.h"
#include "../chipset/chipset.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "../timer.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../keyboard.h"
#include "../intel_flash.h"
#include "../intel_sio.h"
#include "../piix.h"
#include "../sio.h"
#include "../video/video.h"
#include "../video/vid_cl54xx.h"
#include "../video/vid_s3.h"
#include "machine.h"
static void
machine_at_premiere_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
}
static void
machine_at_award_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 03 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 05 = Slot 3 */
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */
pci_register_slot(0x07, PCI_CARD_SCSI, 1, 2, 3, 4); /* 07 = SCSI */
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&fdc_at_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_batman_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/revenge/1009af2_.bio",
L"roms/machines/revenge/1009af2_.bi1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model);
device_add(&i430lx_device);
return ret;
}
int
machine_at_586mc1_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/586mc1/IS.34",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&i430lx_device);
return ret;
}
int
machine_at_plato_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/plato/1016ax1_.bio",
L"roms/machines/plato/1016ax1_.bi1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model);
device_add(&i430nx_device);
return ret;
}
int
machine_at_430nx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/430nx/IP.20",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&i430nx_device);
return ret;
}
int
machine_at_p54tp4xe_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p54tp4xe/t15i0302.awd",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
/* Award BIOS, SMC FDC37C665. */
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_endeavor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/endeavor/1006cb0_.bio",
L"roms/machines/endeavor/1006cb0_.bi1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
device_add(&s3_phoenix_trio64_onboard_pci_device);
return ret;
}
const device_t *
at_endeavor_get_device(void)
{
return &s3_phoenix_trio64_onboard_pci_device;
}
int
machine_at_zappa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/zappa/1006bs0_.bio",
L"roms/machines/zappa/1006bs0_.bi1", 0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_mb500n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/mb500n/031396s.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_president_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/president/bios.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_president_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
int
machine_at_vectra54_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/vectra54/GT0724.22",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c932qf_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#endif

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src/machine/m_at_socket7_s7.c Normal file
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 7 and Super Socket 7 machines.
*
* Version: @(#)m_at_socket7_s7.c 1.0.0 2019/05/16
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "../io.h"
#include "../rom.h"
#include "../pci.h"
#include "../device.h"
#include "../chipset/chipset.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "../keyboard.h"
#include "../intel_flash.h"
#include "../intel_sio.h"
#include "../piix.h"
#include "../sio.h"
#include "../video/video.h"
#include "../video/vid_cl54xx.h"
#include "../video/vid_s3.h"
#include "machine.h"
static void
machine_at_thor_common_init(const machine_t *model, int mr)
{
machine_at_common_init_ex(model, mr);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
int
machine_at_thor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/thor/1006cn0_.bio",
L"roms/machines/thor/1006cn0_.bi1", 0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 0);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
int
machine_at_mrthor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/mrthor/mr_atx.bio",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 1);
return ret;
}
#endif
int
machine_at_pb640_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/pb640/1007CP0R.BIO",
L"roms/machines/pb640/1007CP0R.BI1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_pb640_device);
device_add(&piix_pb640_device);
device_add(&ide_isa_2ch_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5440_onboard_pci_device);
return ret;
}
const device_t *
at_pb640_get_device(void)
{
return &gd5440_onboard_pci_device;
}
int
machine_at_acerm3a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/acerm3a/r01-b3.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x10, PCI_CARD_ONBOARD, 4, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
return ret;
}
int
machine_at_acerv35n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/acerv35n/v35nd1s1.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
return ret;
}
int
machine_at_ap53_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ap53/ap53r2c0.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_ONBOARD, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2p4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p55t2p4/0207_j2.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2s_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p55t2s/s6y08t.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_TC430HX)
int
machine_at_tc430hx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2(L"roms/machines/tc430hx/1007dh0_.bio",
L"roms/machines/tc430hx/1007dh0_.bi1",
L"roms/machines/tc430hx/1007dh0_.bi2",
L"roms/machines/tc430hx/1007dh0_.bi3",
L"roms/machines/tc430hx/1007dh0_.rcv",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxtw_ami_device);
return ret;
}
#endif
int
machine_at_p55tvp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p55tvp4/tv5i0204.awd",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_i430vx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/430vx/55xwuq0e.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55va_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p55va/va021297.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_j656vxd_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/j656vxd/J656VXD.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}

107
src/machine/m_at_socket8.c Normal file
View File

@@ -0,0 +1,107 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 8 machines.
*
* Version: @(#)m_at_socket8.c 1.0.0 2019/05/16
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "../io.h"
#include "../rom.h"
#include "../pci.h"
#include "../device.h"
#include "../chipset/chipset.h"
#include "../disk/hdc.h"
#include "../disk/hdc_ide.h"
#include "../keyboard.h"
#include "../intel_flash.h"
#include "../intel_sio.h"
#include "../piix.h"
#include "../sio.h"
#include "../video/video.h"
#include "../video/vid_cl54xx.h"
#include "../video/vid_s3.h"
#include "machine.h"
#if defined(DEV_BRANCH) && defined(USE_I686)
int
machine_at_i440fx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_s1668_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#endif

14
src/machine/m_at_t3100e.c
View File

@@ -153,11 +153,13 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../timer.h"
#include "../io.h"
#include "../mouse.h"
#include "../mem.h"
#include "../device.h"
#include "../keyboard.h"
#include "../rom.h"
#include "../cpu/cpu.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
@@ -734,8 +736,16 @@ static void upper_write_raml(uint32_t addr, uint32_t val, void *priv)
void machine_at_t3100e_init(const machine_t *model)
int machine_at_t3100e_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/t3100e/t3100e.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
int pg;
memset(&t3100e_ems, 0, sizeof(t3100e_ems));
@@ -779,4 +789,6 @@ void machine_at_t3100e_init(const machine_t *model)
mem_mapping_disable(&t3100e_ems.upper_mapping);
device_add(&t3100e_device);
return ret;
}

27
src/machine/m_at_t3100e_vid.c
View File

@@ -28,9 +28,9 @@
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2019 Miran Grca.
* Copyright 2008-2019 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -71,6 +71,9 @@
#define T3100E_XSIZE 640
#define T3100E_YSIZE 400
/*Very rough estimate*/
#define VID_CLOCK (double)(651 * 416 * 60)
/* Mapping of attributes to colours */
static uint32_t amber, black;
@@ -117,7 +120,7 @@ typedef struct t3100e_t
int internal; /* Using internal display? */
uint8_t attrmap; /* Attribute mapping register */
int dispontime, dispofftime;
uint64_t dispontime, dispofftime;
int linepos, displine;
int vc;
@@ -201,7 +204,7 @@ void t3100e_write(uint32_t addr, uint8_t val, void *p)
egawrites++;
t3100e->vram[addr & 0x7fff] = val;
cycles -= 4;
sub_cycles(4);
}
@@ -210,7 +213,7 @@ uint8_t t3100e_read(uint32_t addr, void *p)
{
t3100e_t *t3100e = (t3100e_t *)p;
egareads++;
cycles -= 4;
sub_cycles(4);
return t3100e->vram[addr & 0x7fff];
}
@@ -230,8 +233,8 @@ void t3100e_recalctimings(t3100e_t *t3100e)
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
t3100e->dispontime = (int)(_dispontime * (1 << TIMER_SHIFT));
t3100e->dispofftime = (int)(_dispofftime * (1 << TIMER_SHIFT));
t3100e->dispontime = (uint64_t)(_dispontime * (cpuclock / VID_CLOCK) * (double)(1ull << 32));
t3100e->dispofftime = (uint64_t)(_dispofftime * (cpuclock / VID_CLOCK) * (double)(1ull << 32));
}
@@ -525,7 +528,7 @@ void t3100e_poll(void *p)
if (!t3100e->linepos)
{
t3100e->cga.vidtime += t3100e->dispofftime;
timer_advance_u64(&t3100e->cga.timer, t3100e->dispofftime);
t3100e->cga.cgastat |= 1;
t3100e->linepos = 1;
if (t3100e->dispon)
@@ -572,7 +575,7 @@ void t3100e_poll(void *p)
{
t3100e->cga.cgastat &= ~1;
}
t3100e->cga.vidtime += t3100e->dispontime;
timer_advance_u64(&t3100e->cga.timer, t3100e->dispontime);
t3100e->linepos = 0;
if (t3100e->displine == 400)
@@ -709,6 +712,7 @@ void *t3100e_init(const device_t *info)
{
t3100e_t *t3100e = malloc(sizeof(t3100e_t));
memset(t3100e, 0, sizeof(t3100e_t));
loadfont(L"roms/machines/t3100e/t3100e_font.bin", 5);
cga_init(&t3100e->cga);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_t3100e);
@@ -717,7 +721,8 @@ void *t3100e_init(const device_t *info)
/* 32k video RAM */
t3100e->vram = malloc(0x8000);
timer_add(t3100e_poll, &t3100e->cga.vidtime, TIMER_ALWAYS_ENABLED, t3100e);
timer_set_callback(&t3100e->cga.timer, t3100e_poll);
timer_set_p(&t3100e->cga.timer, t3100e);
/* Occupy memory between 0xB8000 and 0xBFFFF */
mem_mapping_add(&t3100e->mapping, 0xb8000, 0x8000, t3100e_read, NULL, NULL, t3100e_write, NULL, NULL, NULL, 0, t3100e);

158
src/machine/m_at_wd76c10.c
View File

@@ -1,158 +0,0 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../io.h"
#include "../keyboard.h"
#include "../mem.h"
#include "../serial.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../video/vid_paradise.h"
#include "machine.h"
static uint16_t wd76c10_0092;
static uint16_t wd76c10_2072;
static uint16_t wd76c10_2872;
static uint16_t wd76c10_5872;
static serial_t *wd76c10_uart[2];
static fdc_t *wd76c10_fdc;
static uint16_t
wd76c10_read(uint16_t port, void *priv)
{
switch (port)
{
case 0x0092:
return wd76c10_0092;
case 0x2072:
return wd76c10_2072;
case 0x2872:
return wd76c10_2872;
case 0x5872:
return wd76c10_5872;
}
return 0;
}
static void
wd76c10_write(uint16_t port, uint16_t val, void *priv)
{
switch (port)
{
case 0x0092:
wd76c10_0092 = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x2072:
wd76c10_2072 = val;
serial_remove(wd76c10_uart[0]);
if (!(val & 0x10))
{
switch ((val >> 5) & 7)
{
case 1: serial_setup(wd76c10_uart[0], 0x3f8, 4); break;
case 2: serial_setup(wd76c10_uart[0], 0x2f8, 4); break;
case 3: serial_setup(wd76c10_uart[0], 0x3e8, 4); break;
case 4: serial_setup(wd76c10_uart[0], 0x2e8, 4); break;
default: break;
}
}
serial_remove(wd76c10_uart[1]);
if (!(val & 0x01))
{
switch ((val >> 1) & 7)
{
case 1: serial_setup(wd76c10_uart[1], 0x3f8, 3); break;
case 2: serial_setup(wd76c10_uart[1], 0x2f8, 3); break;
case 3: serial_setup(wd76c10_uart[1], 0x3e8, 3); break;
case 4: serial_setup(wd76c10_uart[1], 0x2e8, 3); break;
default: break;
}
}
break;
case 0x2872:
wd76c10_2872 = val;
fdc_remove(wd76c10_fdc);
if (!(val & 1))
fdc_set_base(wd76c10_fdc, 0x03f0);
break;
case 0x5872:
wd76c10_5872 = val;
break;
}
}
static uint8_t
wd76c10_readb(uint16_t port, void *priv)
{
if (port & 1)
return wd76c10_read(port & ~1, priv) >> 8;
return wd76c10_read(port, priv) & 0xff;
}
static void
wd76c10_writeb(uint16_t port, uint8_t val, void *priv)
{
uint16_t temp = wd76c10_read(port, priv);
if (port & 1)
wd76c10_write(port & ~1, (temp & 0x00ff) | (val << 8), priv);
else
wd76c10_write(port , (temp & 0xff00) | val, priv);
}
static void wd76c10_init(void)
{
io_sethandler(0x0092, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x2072, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x2872, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
io_sethandler(0x5872, 2,
wd76c10_readb, wd76c10_read, NULL,
wd76c10_writeb, wd76c10_write, NULL, NULL);
}
void
machine_at_wd76c10_init(const machine_t *model)
{
machine_at_common_ide_init(model);
device_add(&keyboard_ps2_quadtel_device);
wd76c10_fdc = device_add(&fdc_at_device);
wd76c10_uart[0] = device_add_inst(&i8250_device, 1);
wd76c10_uart[1] = device_add_inst(&i8250_device, 2);
wd76c10_init();
device_add(&paradise_wd90c11_megapc_device);
}

14
src/machine/m_europc.c
View File

@@ -119,6 +119,7 @@
#define HAVE_STDARG_H
#include "../86box.h"
#include "../io.h"
#include "../timer.h"
#include "../nmi.h"
#include "../mem.h"
#include "../pit.h"
@@ -591,6 +592,7 @@ europc_boot(const device_t *info)
* with values set by the user.
*/
b = (sys->nvr.regs[MRTC_CONF_D] & ~0x17);
video_reset(gfxcard);
if (video_is_cga())
b |= 0x12; /* external video, CGA80 */
else if (video_is_mda())
@@ -730,9 +732,17 @@ const device_t europc_device = {
* allows it to reset (dev init) and configured by the
* user.
*/
void
int
machine_europc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/europc/50145",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
@@ -756,4 +766,6 @@ machine_europc_init(const machine_t *model)
/* Enable and set up the mainboard device. */
device_add(&europc_device);
return ret;
}

136
src/machine/m_olivetti_m24.c
View File

@@ -25,17 +25,18 @@
#include <stdarg.h>
#include <wchar.h>
#include "../86box.h"
#include "../timer.h"
#include "../io.h"
#include "../pic.h"
#include "../pit.h"
#include "../ppi.h"
#include "../nmi.h"
#include "../mem.h"
#include "../timer.h"
#include "../device.h"
#include "../nvr.h"
#include "../keyboard.h"
#include "../mouse.h"
#include "../rom.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../game/gameport.h"
@@ -70,13 +71,13 @@ typedef struct {
int linepos, displine;
int sc, vc;
int con, coff, cursoron, blink;
int64_t vsynctime;
int vsynctime;
int vadj;
int lineff;
uint16_t ma, maback;
int dispon;
int64_t dispontime, dispofftime;
int64_t vidtime;
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int firstline, lastline;
/* Keyboard stuff. */
@@ -93,6 +94,7 @@ typedef struct {
/* Mouse stuff. */
int mouse_mode;
int x, y, b;
pc_timer_t send_delay_timer;
} olim24_t;
static video_timings_t timing_m24 = {VIDEO_ISA, 8,16,32, 8,16,32};
@@ -147,8 +149,8 @@ recalc_timings(olim24_t *m24)
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST / 2;
_dispofftime *= CGACONST / 2;
m24->dispontime = (int64_t)(_dispontime * (1 << TIMER_SHIFT));
m24->dispofftime = (int64_t)(_dispofftime * (1 << TIMER_SHIFT));
m24->dispontime = (uint64_t)(_dispontime);
m24->dispofftime = (uint64_t)(_dispofftime);
}
@@ -234,10 +236,12 @@ static void
vid_write(uint32_t addr, uint8_t val, void *priv)
{
olim24_t *m24 = (olim24_t *)priv;
int offset;
m24->vram[addr & 0x7FFF]=val;
m24->charbuffer[ ((int)(((m24->dispontime - m24->vidtime) * 2) / (CGACONST / 2))) & 0xfc] = val;
m24->charbuffer[(((int)(((m24->dispontime - m24->vidtime) * 2) / (CGACONST / 2))) & 0xfc) | 1] = val;
offset = ((timer_get_remaining_u64(&m24->timer) / CGACONST) * 4) & 0xfc;
m24->charbuffer[offset] = m24->vram[addr & 0x7fff];
m24->charbuffer[offset | 1] = m24->vram[addr & 0x7fff];
}
@@ -265,7 +269,7 @@ vid_poll(void *priv)
int oldsc;
if (!m24->linepos) {
m24->vidtime += m24->dispofftime;
timer_advance_u64(&m24->timer, m24->dispofftime);
m24->stat |= 1;
m24->linepos = 1;
oldsc = m24->sc;
@@ -279,17 +283,17 @@ vid_poll(void *priv)
for (c = 0; c < 8; c++)
{
if ((m24->cgamode & 0x12) == 0x12) {
buffer->line[m24->displine][c] = 0;
((uint32_t *)buffer32->line[m24->displine])[c] = 0;
if (m24->cgamode & 1)
buffer->line[m24->displine][c + (m24->crtc[1] << 3) + 8] = 0;
((uint32_t *)buffer32->line[m24->displine])[c + (m24->crtc[1] << 3) + 8] = 0;
else
buffer->line[m24->displine][c + (m24->crtc[1] << 4) + 8] = 0;
((uint32_t *)buffer32->line[m24->displine])[c + (m24->crtc[1] << 4) + 8] = 0;
} else {
buffer->line[m24->displine][c] = (m24->cgacol & 15) + 16;
((uint32_t *)buffer32->line[m24->displine])[c] = (m24->cgacol & 15) + 16;
if (m24->cgamode & 1)
buffer->line[m24->displine][c + (m24->crtc[1] << 3) + 8] = (m24->cgacol & 15) + 16;
((uint32_t *)buffer32->line[m24->displine])[c + (m24->crtc[1] << 3) + 8] = (m24->cgacol & 15) + 16;
else
buffer->line[m24->displine][c + (m24->crtc[1] << 4) + 8] = (m24->cgacol & 15) + 16;
((uint32_t *)buffer32->line[m24->displine])[c + (m24->crtc[1] << 4) + 8] = (m24->cgacol & 15) + 16;
}
}
if (m24->cgamode & 1) {
@@ -308,10 +312,10 @@ vid_poll(void *priv)
}
if (drawcursor) {
for (c = 0; c < 8; c++)
buffer->line[m24->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
((uint32_t *)buffer32->line[m24->displine])[(x << 3) + c + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer->line[m24->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0];
((uint32_t *)buffer32->line[m24->displine])[(x << 3) + c + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
m24->ma++;
}
@@ -332,12 +336,12 @@ vid_poll(void *priv)
m24->ma++;
if (drawcursor) {
for (c = 0; c < 8; c++)
buffer->line[m24->displine][(x << 4) + (c << 1) + 8] =
buffer->line[m24->displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer->line[m24->displine][(x << 4) + (c << 1) + 8] =
buffer->line[m24->displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0];
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((m24->sc & 7) << 1) | m24->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
}
} else if (!(m24->cgamode & 16)) {
@@ -361,8 +365,8 @@ vid_poll(void *priv)
m24->vram[((m24->ma << 1) & 0x1fff) + ((m24->sc & 1) * 0x2000) + 1 + m24->base];
m24->ma++;
for (c = 0; c < 8; c++) {
buffer->line[m24->displine][(x << 4) + (c << 1) + 8] =
buffer->line[m24->displine][(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
dat <<= 2;
}
}
@@ -379,15 +383,15 @@ vid_poll(void *priv)
dat = (m24->vram[((m24->ma << 1) & 0x1fff) + dat2] << 8) | m24->vram[((m24->ma << 1) & 0x1fff) + dat2 + 1];
m24->ma++;
for (c = 0; c < 16; c++) {
buffer->line[m24->displine][(x << 4) + c + 8] = cols[dat >> 15];
((uint32_t *)buffer32->line[m24->displine])[(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
}
}
} else {
cols[0] = ((m24->cgamode & 0x12) == 0x12) ? 0 : (m24->cgacol & 15) + 16;
if (m24->cgamode & 1) hline(buffer, 0, m24->displine, (m24->crtc[1] << 3) + 16, cols[0]);
else hline(buffer, 0, m24->displine, (m24->crtc[1] << 4) + 16, cols[0]);
if (m24->cgamode & 1) hline(buffer32, 0, m24->displine, (m24->crtc[1] << 3) + 16, cols[0]);
else hline(buffer32, 0, m24->displine, (m24->crtc[1] << 4) + 16, cols[0]);
}
if (m24->cgamode & 1)
@@ -401,7 +405,7 @@ vid_poll(void *priv)
m24->displine++;
if (m24->displine >= 720) m24->displine = 0;
} else {
m24->vidtime += m24->dispontime;
timer_advance_u64(&m24->timer, m24->dispontime);
if (m24->dispon) m24->stat &= ~1;
m24->linepos = 0;
m24->lineff ^= 1;
@@ -525,7 +529,7 @@ kbd_poll(void *priv)
{
olim24_t *m24 = (olim24_t *)priv;
keyboard_delay += (1000LL * TIMER_USEC);
timer_advance_u64(&m24->send_delay_timer, 1000 * TIMER_USEC);
if (m24->wantirq) {
m24->wantirq = 0;
picint(2);
@@ -634,9 +638,6 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
case 0x61:
ppi.pb = val;
timer_process();
timer_update_outstanding();
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
@@ -803,9 +804,39 @@ const device_t m24_device = {
};
void
static void
kbd_reset(void *priv)
{
olim24_t *m24 = (olim24_t *)priv;
/* Initialize the keyboard. */
m24->status = STAT_LOCK | STAT_CD;
m24->wantirq = 0;
keyboard_scan = 1;
m24->param = m24->param_total = 0;
m24->mouse_mode = 0;
m24->scan[0] = 0x1c;
m24->scan[1] = 0x53;
m24->scan[2] = 0x01;
m24->scan[3] = 0x4b;
m24->scan[4] = 0x4d;
m24->scan[5] = 0x48;
m24->scan[6] = 0x50;
}
int
machine_olim24_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/olivetti_m24/olivetti_m24_version_1.43_low.bin",
L"roms/machines/olivetti_m24/olivetti_m24_version_1.43_high.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
olim24_t *m24;
m24 = (olim24_t *)malloc(sizeof(olim24_t));
@@ -823,31 +854,25 @@ machine_olim24_init(const machine_t *model)
vid_read, NULL, NULL,
vid_write, NULL, NULL, NULL, 0, m24);
io_sethandler(0x03d0, 16, vid_in, NULL, NULL, vid_out, NULL, NULL, m24);
timer_add(vid_poll, &m24->vidtime, TIMER_ALWAYS_ENABLED, m24);
timer_add(&m24->timer, vid_poll, m24, 1);
device_add_ex(&m24_device, m24);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_m24);
/* Initialize the keyboard. */
m24->status = STAT_LOCK | STAT_CD;
m24->scan[0] = 0x1c;
m24->scan[1] = 0x53;
m24->scan[2] = 0x01;
m24->scan[3] = 0x4b;
m24->scan[4] = 0x4d;
m24->scan[5] = 0x48;
m24->scan[6] = 0x50;
io_sethandler(0x0060, 2,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, m24);
io_sethandler(0x0064, 1,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, m24);
keyboard_set_table(scancode_xt);
keyboard_send = kbd_adddata_ex;
keyboard_scan = 1;
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, m24);
kbd_reset(m24);
timer_add(&m24->send_delay_timer, kbd_poll, m24, 1);
/* Tell mouse driver about our internal mouse. */
mouse_reset();
mouse_set_poll(ms_poll, m24);
keyboard_set_table(scancode_xt);
if (joystick_type != 7)
device_add(&gameport_device);
@@ -855,25 +880,6 @@ machine_olim24_init(const machine_t *model)
device_add(&at_nvr_device);
nmi_init();
}
void machine_olim24_video_init(void) {
olim24_t *m24;
m24 = (olim24_t *)malloc(sizeof(olim24_t));
memset(m24, 0x00, sizeof(olim24_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_m24);
/* Initialize the video adapter. */
m24->vram = malloc(0x8000);
overscan_x = overscan_y = 16;
mem_mapping_add(&m24->mapping, 0xb8000, 0x08000,
vid_read, NULL, NULL,
vid_write, NULL, NULL, NULL, 0, m24);
io_sethandler(0x03d0, 16, vid_in, NULL, NULL, vid_out, NULL, NULL, m24);
io_sethandler(0x13c6, 1, vid_in, NULL, NULL, vid_out, NULL, NULL, m24);
io_sethandler(0x23c6, 1, vid_in, NULL, NULL, vid_out, NULL, NULL, m24);
timer_add(vid_poll, &m24->vidtime, TIMER_ALWAYS_ENABLED, m24);
device_add_ex(&m24_device, m24);
return ret;
}

150
src/machine/m_pcjr.c
View File

@@ -28,15 +28,16 @@
#define HAVE_STDARG_H
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../io.h"
#include "../nmi.h"
#include "../pic.h"
#include "../pit.h"
#include "../mem.h"
#include "../timer.h"
#include "../device.h"
#include "../serial.h"
#include "../keyboard.h"
#include "../rom.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../sound/sound.h"
@@ -77,10 +78,11 @@ typedef struct {
int sc, vc;
int dispon;
int con, coff, cursoron, blink;
int64_t vsynctime;
int vsynctime;
int vadj;
uint16_t ma, maback;
int64_t dispontime, dispofftime, vidtime;
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int firstline, lastline;
int composite;
@@ -91,6 +93,7 @@ typedef struct {
int serial_pos;
uint8_t pa;
uint8_t pb;
pc_timer_t send_delay_timer;
} pcjr_t;
static video_timings_t timing_dram = {VIDEO_BUS, 0,0,0, 0,0,0}; /*No additional waitstates*/
@@ -136,8 +139,8 @@ recalc_timings(pcjr_t *pcjr)
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
pcjr->dispontime = (int64_t)(_dispontime * (1 << TIMER_SHIFT));
pcjr->dispofftime = (int64_t)(_dispofftime * (1 << TIMER_SHIFT));
pcjr->dispontime = (uint64_t)(_dispontime);
pcjr->dispofftime = (uint64_t)(_dispofftime);
}
@@ -249,7 +252,7 @@ vid_poll(void *p)
int oldsc;
if (! pcjr->linepos) {
pcjr->vidtime += pcjr->dispofftime;
timer_advance_u64(&pcjr->timer, pcjr->dispofftime);
pcjr->stat &= ~1;
pcjr->linepos = 1;
oldsc = pcjr->sc;
@@ -266,11 +269,11 @@ vid_poll(void *p)
pcjr->lastline = pcjr->displine;
cols[0] = (pcjr->array[2] & 0xf) + 16;
for (c = 0; c < 8; c++) {
buffer->line[pcjr->displine][c] = cols[0];
((uint32_t *)buffer32->line[pcjr->displine])[c] = cols[0];
if (pcjr->array[0] & 1)
buffer->line[pcjr->displine][c + (pcjr->crtc[1] << 3) + 8] = cols[0];
((uint32_t *)buffer32->line[pcjr->displine])[c + (pcjr->crtc[1] << 3) + 8] = cols[0];
else
buffer->line[pcjr->displine][c + (pcjr->crtc[1] << 4) + 8] = cols[0];
((uint32_t *)buffer32->line[pcjr->displine])[c + (pcjr->crtc[1] << 4) + 8] = cols[0];
}
switch (pcjr->addr_mode) {
@@ -291,14 +294,14 @@ vid_poll(void *p)
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
buffer->line[pcjr->displine][(x << 3) + 8] =
buffer->line[pcjr->displine][(x << 3) + 9] = pcjr->array[((dat >> 12) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 3) + 10] =
buffer->line[pcjr->displine][(x << 3) + 11] = pcjr->array[((dat >> 8) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 3) + 12] =
buffer->line[pcjr->displine][(x << 3) + 13] = pcjr->array[((dat >> 4) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 3) + 14] =
buffer->line[pcjr->displine][(x << 3) + 15] = pcjr->array[(dat & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 8] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 9] = pcjr->array[((dat >> 12) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 10] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 11] = pcjr->array[((dat >> 8) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 12] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 13] = pcjr->array[((dat >> 4) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 14] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 15] = pcjr->array[(dat & pcjr->array[1]) + 16] + 16;
}
break;
case 0x12: /*160x200x16*/
@@ -306,22 +309,22 @@ vid_poll(void *p)
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
buffer->line[pcjr->displine][(x << 4) + 8] =
buffer->line[pcjr->displine][(x << 4) + 9] =
buffer->line[pcjr->displine][(x << 4) + 10] =
buffer->line[pcjr->displine][(x << 4) + 11] = pcjr->array[((dat >> 12) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 4) + 12] =
buffer->line[pcjr->displine][(x << 4) + 13] =
buffer->line[pcjr->displine][(x << 4) + 14] =
buffer->line[pcjr->displine][(x << 4) + 15] = pcjr->array[((dat >> 8) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 4) + 16] =
buffer->line[pcjr->displine][(x << 4) + 17] =
buffer->line[pcjr->displine][(x << 4) + 18] =
buffer->line[pcjr->displine][(x << 4) + 19] = pcjr->array[((dat >> 4) & pcjr->array[1]) + 16] + 16;
buffer->line[pcjr->displine][(x << 4) + 20] =
buffer->line[pcjr->displine][(x << 4) + 21] =
buffer->line[pcjr->displine][(x << 4) + 22] =
buffer->line[pcjr->displine][(x << 4) + 23] = pcjr->array[(dat & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 8] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 9] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 10] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 11] = pcjr->array[((dat >> 12) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 12] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 13] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 14] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 15] = pcjr->array[((dat >> 8) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 16] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 17] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 18] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 19] = pcjr->array[((dat >> 4) & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 20] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 21] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 22] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + 23] = pcjr->array[(dat & pcjr->array[1]) + 16] + 16;
}
break;
case 0x03: /*640x200x4*/
@@ -332,7 +335,7 @@ vid_poll(void *p)
for (c = 0; c < 8; c++) {
chr = (dat >> 7) & 1;
chr |= ((dat >> 14) & 2);
buffer->line[pcjr->displine][(x << 3) + 8 + c] = pcjr->array[(chr & pcjr->array[1]) + 16] + 16;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + 8 + c] = pcjr->array[(chr & pcjr->array[1]) + 16] + 16;
dat <<= 1;
}
}
@@ -353,14 +356,14 @@ vid_poll(void *p)
}
if (pcjr->sc & 8) {
for (c = 0; c < 8; c++)
buffer->line[pcjr->displine][(x << 3) + c + 8] = cols[0];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + c + 8] = cols[0];
} else {
for (c = 0; c < 8; c++)
buffer->line[pcjr->displine][(x << 3) + c + 8] = cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + c + 8] = cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
if (drawcursor) {
for (c = 0; c < 8; c++)
buffer->line[pcjr->displine][(x << 3) + c + 8] ^= 15;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 3) + c + 8] ^= 15;
}
pcjr->ma++;
}
@@ -382,16 +385,16 @@ vid_poll(void *p)
pcjr->ma++;
if (pcjr->sc & 8) {
for (c = 0; c < 8; c++)
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 8] =
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 1 + 8] = cols[0];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[0];
} else {
for (c = 0; c < 8; c++)
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 8] =
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
if (drawcursor) {
for (c = 0; c < 16; c++)
buffer->line[pcjr->displine][(x << 4) + c + 8] ^= 15;
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + c + 8] ^= 15;
}
}
break;
@@ -405,8 +408,8 @@ vid_poll(void *p)
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
for (c = 0; c < 8; c++) {
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 8] =
buffer->line[pcjr->displine][(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 8] =
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
dat <<= 2;
}
}
@@ -419,7 +422,7 @@ vid_poll(void *p)
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
for (c = 0; c < 16; c++) {
buffer->line[pcjr->displine][(x << 4) + c + 8] = cols[dat >> 15];
((uint32_t *)buffer32->line[pcjr->displine])[(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
}
@@ -427,22 +430,18 @@ vid_poll(void *p)
}
} else {
if (pcjr->array[3] & 4) {
if (pcjr->array[0] & 1) hline(buffer, 0, pcjr->displine, (pcjr->crtc[1] << 3) + 16, (pcjr->array[2] & 0xf) + 16);
else hline(buffer, 0, pcjr->displine, (pcjr->crtc[1] << 4) + 16, (pcjr->array[2] & 0xf) + 16);
if (pcjr->array[0] & 1) hline(buffer32, 0, pcjr->displine, (pcjr->crtc[1] << 3) + 16, (pcjr->array[2] & 0xf) + 16);
else hline(buffer32, 0, pcjr->displine, (pcjr->crtc[1] << 4) + 16, (pcjr->array[2] & 0xf) + 16);
} else {
cols[0] = pcjr->array[0 + 16] + 16;
if (pcjr->array[0] & 1) hline(buffer, 0, pcjr->displine, (pcjr->crtc[1] << 3) + 16, cols[0]);
else hline(buffer, 0, pcjr->displine, (pcjr->crtc[1] << 4) + 16, cols[0]);
if (pcjr->array[0] & 1) hline(buffer32, 0, pcjr->displine, (pcjr->crtc[1] << 3) + 16, cols[0]);
else hline(buffer32, 0, pcjr->displine, (pcjr->crtc[1] << 4) + 16, cols[0]);
}
}
if (pcjr->array[0] & 1) x = (pcjr->crtc[1] << 3) + 16;
else x = (pcjr->crtc[1] << 4) + 16;
if (pcjr->composite) {
for (c = 0; c < x; c++)
buffer32->line[pcjr->displine][c] = buffer->line[pcjr->displine][c] & 0xf;
Composite_Process(pcjr->array[0], 0, x >> 2, buffer32->line[pcjr->displine]);
}
if (pcjr->composite)
Composite_Process(pcjr->array[0], 0, x >> 2, ((uint32_t *)buffer32->line[pcjr->displine]));
pcjr->sc = oldsc;
if (pcjr->vc == pcjr->crtc[7] && !pcjr->sc) {
pcjr->stat |= 8;
@@ -451,7 +450,7 @@ vid_poll(void *p)
if (pcjr->displine >= 360)
pcjr->displine = 0;
} else {
pcjr->vidtime += pcjr->dispontime;
timer_advance_u64(&pcjr->timer, pcjr->dispontime);
if (pcjr->dispon)
pcjr->stat |= 1;
pcjr->linepos = 0;
@@ -542,6 +541,9 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
{
pcjr_t *pcjr = (pcjr_t *)priv;
if ((port >= 0xa0) && (port <= 0xa7))
port = 0xa0;
switch (port) {
case 0x60:
pcjr->pa = val;
@@ -550,9 +552,6 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
case 0x61:
pcjr->pb = val;
timer_process();
timer_update_outstanding();
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
@@ -585,6 +584,9 @@ kbd_read(uint16_t port, void *priv)
pcjr_t *pcjr = (pcjr_t *)priv;
uint8_t ret = 0xff;
if ((port >= 0xa0) && (port <= 0xa7))
port = 0xa0;
switch (port) {
case 0x60:
ret = pcjr->pa;
@@ -620,7 +622,7 @@ kbd_poll(void *priv)
pcjr_t *pcjr = (pcjr_t *)priv;
int c, p = 0, key;
keyboard_delay += (220LL * TIMER_USEC);
timer_advance_u64(&pcjr->send_delay_timer, 220 * TIMER_USEC);
if (key_queue_start != key_queue_end &&
!pcjr->serial_pos && !pcjr->latched) {
@@ -734,27 +736,31 @@ pcjr_get_device(void)
}
void
int
machine_pcjr_init(const machine_t *model)
{
int display_type;
pcjr_t *pcjr;
int ret;
ret = bios_load_linear(L"roms/machines/ibmpcjr/bios.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
pcjr = malloc(sizeof(pcjr_t));
memset(pcjr, 0x00, sizeof(pcjr_t));
pcjr->memctrl = -1;
display_type = machine_get_config_int("display_type");
pcjr->composite = (display_type != PCJR_RGB);
pic_init();
pic_init_pcjr();
pit_init();
pit_set_out_func(&pit, 0, pit_irq0_timer_pcjr);
cpu_set();
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286)
setrtcconst(machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed);
else
setrtcconst(14318184.0);
/* Initialize the video controller. */
mem_mapping_add(&pcjr->mapping, 0xb8000, 0x08000,
@@ -762,7 +768,7 @@ machine_pcjr_init(const machine_t *model)
vid_write, NULL, NULL, NULL, 0, pcjr);
io_sethandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, pcjr);
timer_add(vid_poll, &pcjr->vidtime, TIMER_ALWAYS_ENABLED, pcjr);
timer_add(&pcjr->timer, vid_poll, pcjr, 1);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_dram);
device_add_ex(&pcjr_device, pcjr);
@@ -773,13 +779,19 @@ machine_pcjr_init(const machine_t *model)
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
io_sethandler(0x00a0, 8,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, pcjr);
timer_add(&pcjr->send_delay_timer, kbd_poll, pcjr, 1);
keyboard_set_table(scancode_xt);
keyboard_send = kbd_adddata_ex;
device_add(&sn76489_device);
/* Technically it's the SN76496N, but the NCR 8496 is a drop-in replacement for it. */
device_add(&ncr8496_device);
nmi_mask = 0x80;
device_add(&fdc_pcjr_device);
device_add(&i8250_pcjr_device);
serial_set_next_inst(2); /* So that serial_standalone_init() won't do anything. */
return ret;
}

86
src/machine/m_ps1.c
View File

@@ -28,15 +28,15 @@
* boot. Sometimes, they do, and then it shows an "Incorrect
* DOS" error message?? --FvK
*
* Version: @(#)m_ps1.c 1.0.14 2018/11/12
* Version: @(#)m_ps1.c 1.0.15 2019/03/08
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
* Copyright 2017-2019 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdint.h>
@@ -45,6 +45,7 @@
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../io.h"
#include "../dma.h"
#include "../pic.h"
@@ -52,7 +53,6 @@
#include "../mem.h"
#include "../nmi.h"
#include "../rom.h"
#include "../timer.h"
#include "../device.h"
#include "../nvr.h"
#include "../game/gameport.h"
@@ -74,7 +74,9 @@
typedef struct {
sn76489_t sn76489;
uint8_t status, ctrl;
int64_t timer_latch, timer_count, timer_enable;
uint64_t timer_latch;
pc_timer_t timer_count;
int timer_enable;
uint8_t fifo[2048];
int fifo_read_idx, fifo_write_idx;
int fifo_threshold;
@@ -177,8 +179,10 @@ snd_write(uint16_t port, uint8_t val, void *priv)
case 3: /* timer reload value */
snd->timer_latch = val;
snd->timer_count = (int64_t) ((0xff-val) * TIMER_USEC);
snd->timer_enable = (val != 0);
if (val)
timer_set_delay_u64(&snd->timer_count, ((0xff-val) * TIMER_USEC));
else
timer_disable(&snd->timer_count);
break;
case 4: /* almost empty */
@@ -213,8 +217,8 @@ snd_callback(void *priv)
snd->status |= 0x10; /*ADC data ready*/
update_irq_status(snd);
snd->timer_count += snd->timer_latch * TIMER_USEC;
timer_advance_u64(&snd->timer_count, snd->timer_latch * TIMER_USEC);
}
@@ -246,7 +250,7 @@ snd_init(const device_t *info)
io_sethandler(0x0200, 1, snd_read,NULL,NULL, snd_write,NULL,NULL, snd);
io_sethandler(0x0202, 6, snd_read,NULL,NULL, snd_write,NULL,NULL, snd);
timer_add(snd_callback, &snd->timer_count, &snd->timer_enable, snd);
timer_add(&snd->timer_count, snd_callback, snd, 0);
sound_add_handler(snd_get_buffer, snd);
@@ -449,7 +453,7 @@ ps1_setup(int model)
io_sethandler(0x0190, 1,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
ps->uart = device_add_inst(&i8250_device, 1);
ps->uart = device_add_inst(&ns16450_device, 1);
lpt1_remove();
lpt1_init(0x3bc);
@@ -475,12 +479,8 @@ ps1_setup(int model)
if (hdc_current == 1) {
priv = device_add(&ps1_hdc_device);
ps1_hdc_inform(priv, ps);
ps1_hdc_inform(priv, &ps->ps1_91);
}
mem_mapping_add(&romext_mapping, 0xc8000, 0x08000,
mem_read_romext,mem_read_romextw,mem_read_romextl,
NULL,NULL, NULL, romext, 0, NULL);
}
if (model == 2121) {
@@ -504,11 +504,13 @@ ps1_setup(int model)
device_add(&snd_device);
}
#if defined(DEV_BRANCH) && defined(USE_PS1M2133)
if (model == 2133) {
device_add(&fdc_at_device);
device_add(&ide_isa_device);
}
#endif
}
@@ -526,7 +528,7 @@ ps1_common_init(const machine_t *model)
device_add(&ps_nvr_device);
device_add(&keyboard_ps2_device);
device_add(&keyboard_ps2_ps1_device);
/* Audio uses ports 200h and 202-207h, so only initialize gameport on 201h. */
if (joystick_type != 7)
@@ -534,40 +536,62 @@ ps1_common_init(const machine_t *model)
}
/* Set the Card Selected Flag */
void
ps1_set_feedback(void *priv)
{
ps1_t *ps = (ps1_t *)priv;
ps->ps1_91 |= 0x01;
}
void
int
machine_ps1_m2011_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmps1es/f80000.bin",
0x000e0000, 131072, 0x60000);
if (bios_only || !ret)
return ret;
ps1_common_init(model);
ps1_setup(2011);
return ret;
}
void
int
machine_ps1_m2121_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmps1_2121/fc0000.bin",
0x000e0000, 131072, 0x20000);
if (bios_only || !ret)
return ret;
ps1_common_init(model);
ps1_setup(2121);
return ret;
}
void
#if defined(DEV_BRANCH) && defined(USE_PS1M2133)
int
machine_ps1_m2133_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmps1_2133/ps1_2133_52g2974_rom.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
ps1_common_init(model);
ps1_setup(2133);
nmi_mask = 0x80;
return ret;
}
#endif

65
src/machine/m_ps1_hdc.c
View File

@@ -43,14 +43,14 @@
* Type table with the main code, so the user can only select
* items from that list...
*
* Version: @(#)m_ps1_hdc.c 1.0.7 2018/10/22
* Version: @(#)m_ps1_hdc.c 1.0.8 2019/03/08
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Based on my earlier HD20 driver for the EuroPC.
* Thanks to Marco Bortolin for the help and feedback !!
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
@@ -93,11 +93,11 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#include "../timer.h"
#include "../io.h"
#include "../dma.h"
#include "../pic.h"
#include "../device.h"
#include "../timer.h"
#include "../disk/hdc.h"
#include "../disk/hdd.h"
#include "../plat.h"
@@ -105,7 +105,7 @@
#include "machine.h"
#define HDC_TIME (200*TIMER_USEC)
#define HDC_TIME (50*TIMER_USEC)
#define HDC_TYPE_USER 47 /* user drive type */
@@ -387,10 +387,11 @@ typedef struct {
status, /* Status register (ASR) */
intstat; /* Interrupt Status register (ISR) */
void *sys; /* handle to system board */
uint8_t *reg_91; /* handle to system board's register 0x91 */
/* Controller state. */
int64_t callback;
uint64_t callback;
pc_timer_t timer;
int8_t state, /* controller state */
reset; /* reset state counter */
@@ -492,6 +493,21 @@ ps1_hdc_log(const char *fmt, ...)
#define ps1_hdc_log(fmt, ...)
#endif
static void
hdc_set_callback(hdc_t *dev, uint64_t callback)
{
if (!dev) {
return;
}
if (callback) {
dev->callback = callback;
timer_set_delay_u64(&dev->timer, dev->callback);
} else {
dev->callback = 0;
timer_disable(&dev->timer);
}
}
/* FIXME: we should use the disk/hdd_table.c code with custom tables! */
static int
@@ -635,7 +651,7 @@ do_format(hdc_t *dev, drive_t *drive, ccb_t *ccb)
/* Enable for PIO or DMA, as needed. */
#if NOT_USED
if (dev->ctrl & ACR_DMA_EN)
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
else
#endif
dev->status |= ASR_DATA_REQ;
@@ -655,7 +671,7 @@ do_format(hdc_t *dev, drive_t *drive, ccb_t *ccb)
dev->buf_idx++;
}
dev->state = STATE_RDONE;
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
break;
case STATE_RDONE:
@@ -813,20 +829,20 @@ do_send:
dev->buf_idx = 0;
if (no_data) {
/* Delay a bit, no actual transfer. */
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
} else {
if (dev->ctrl & ACR_DMA_EN) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
} else {
/* No DMA, do PIO. */
dev->status |= (ASR_DATA_REQ|ASR_DIR);
/* Copy from sector to data. */
memcpy(dev->data,
dev->sector_buf,
(128<<dev->ssb.sect_size));
dev->sector_buf,
dev->buf_len);
dev->buf_ptr = dev->data;
}
}
@@ -853,7 +869,7 @@ do_send:
}
}
dev->state = STATE_SDONE;
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
break;
case STATE_SDONE:
@@ -941,12 +957,12 @@ do_recv:
dev->buf_idx = 0;
if (no_data) {
/* Delay a bit, no actual transfer. */
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
} else {
if (dev->ctrl & ACR_DMA_EN) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
} else {
/* No DMA, do PIO. */
dev->buf_ptr = dev->data;
@@ -976,14 +992,15 @@ do_recv:
}
}
dev->state = STATE_RDONE;
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
break;
case STATE_RDONE:
/* Copy from data to sector if PIO. */
if (! (dev->ctrl & ACR_DMA_EN))
memcpy(dev->sector_buf, dev->data,
(128<<dev->ssb.sect_size));
memcpy(dev->sector_buf,
dev->data,
dev->buf_len);
/* Get address of sector to write. */
if (get_sector(dev, drive, &addr)) {
@@ -1100,7 +1117,7 @@ hdc_read(uint16_t port, void *priv)
uint8_t ret = 0xff;
/* TRM: tell system board we are alive. */
ps1_set_feedback(dev->sys);
*dev->reg_91 |= 0x01;
switch (port & 7) {
case 0: /* DATA register */
@@ -1143,7 +1160,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
hdc_t *dev = (hdc_t *)priv;
/* TRM: tell system board we are alive. */
ps1_set_feedback(dev->sys);
*dev->reg_91 |= 0x01;
switch (port & 7) {
case 0: /* DATA register */
@@ -1176,7 +1193,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
dev->status |= ASR_BUSY;
/* Schedule command execution. */
dev->callback = HDC_TIME;
hdc_set_callback(dev, HDC_TIME);
}
}
}
@@ -1303,7 +1320,7 @@ ps1_hdc_init(const device_t *info)
hdc_read,NULL,NULL, hdc_write,NULL,NULL, dev);
/* Create a timer for command delays. */
timer_add(hdc_callback, &dev->callback, &dev->callback, dev);
timer_add(&dev->timer, hdc_callback, dev, 0);
return(dev);
}
@@ -1356,9 +1373,9 @@ const device_t ps1_hdc_device = {
* agree that the current solution is nasty.
*/
void
ps1_hdc_inform(void *priv, void *arg)
ps1_hdc_inform(void *priv, uint8_t *reg_91)
{
hdc_t *dev = (hdc_t *)priv;
dev->sys = arg;
dev->reg_91 = reg_91;
}

36
src/machine/m_ps2_isa.c
View File

@@ -4,6 +4,7 @@
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../io.h"
#include "../dma.h"
#include "../pic.h"
@@ -14,14 +15,16 @@
#include "../nvr.h"
#include "../keyboard.h"
#include "../lpt.h"
#include "../port_92.h"
#include "../serial.h"
#include "../disk/hdc.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../video/vid_vga.h"
#include "machine.h"
static uint8_t ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190;
static uint8_t ps2_91, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190;
static serial_t *ps2_uart;
@@ -39,7 +42,9 @@ static uint8_t ps2_read(uint16_t port, void *p)
switch (port)
{
case 0x91:
return 0;
temp = ps2_91;
ps2_91 = 0;
return temp;
case 0x94:
return ps2_94;
case 0x102:
@@ -136,9 +141,7 @@ static void ps2board_init(void)
io_sethandler(0x0322, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
port_92_reset();
port_92_add();
device_add(&port_92_device);
ps2_190 = 0;
@@ -150,17 +153,36 @@ static void ps2board_init(void)
}
void
int
machine_ps2_m30_286_init(const machine_t *model)
{
void *priv;
int ret;
ret = bios_load_linear(L"roms/machines/ibmps2_m30_286/33f5381a.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
device_add(&fdc_at_ps1_device);
pit_set_out_func(&pit, 1, pit_refresh_timer_at);
dma16_init();
device_add(&keyboard_ps2_device);
device_add(&keyboard_ps2_ps2_device);
device_add(&ps_nvr_device);
pic2_init();
ps2board_init();
device_add(&ps1vga_device);
/* Enable the builtin HDC. */
if (hdc_current == 1) {
priv = device_add(&ps1_hdc_device);
ps1_hdc_inform(priv, &ps2_91);
}
return ret;
}

114
src/machine/m_ps2_mca.c
View File

@@ -43,8 +43,14 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include "../86box.h"
#ifdef USE_NEW_DYNAREC
#include "../cpu_new/cpu.h"
#include "../cpu_new/x86.h"
#else
#include "../cpu/cpu.h"
#include "../cpu/x86.h"
#endif
#include "../timer.h"
#include "../io.h"
#include "../dma.h"
#include "../pic.h"
@@ -61,6 +67,7 @@
#include "../keyboard.h"
#include "../lpt.h"
#include "../mouse.h"
#include "../port_92.h"
#include "../serial.h"
#include "../video/video.h"
#include "../video/vid_vga.h"
@@ -609,7 +616,17 @@ uint8_t ps2_mca_read(uint16_t port, void *p)
switch (port)
{
case 0x91:
fatal("Read 91 setup=%02x adapter=%02x\n", ps2.setup, ps2.adapter_setup);
// fatal("Read 91 setup=%02x adapter=%02x\n", ps2.setup, ps2.adapter_setup);
if (!(ps2.setup & PS2_SETUP_IO))
temp = 0x00;
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0x00;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = 0x00;
else
temp = !mca_feedb();
temp |= 0xfe;
break;
case 0x94:
temp = ps2.setup;
break;
@@ -769,10 +786,8 @@ static void ps2_mca_board_common_init()
io_sethandler(0x0094, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
port_92_reset();
port_92_add();
device_add(&port_92_device);
ps2.setup = 0xff;
@@ -797,6 +812,11 @@ static void ps2_mem_expansion_write(int port, uint8_t val, void *p)
mem_mapping_disable(&ps2.expansion_mapping);
}
static uint8_t ps2_mem_expansion_feedb(void *p)
{
return (ps2.mem_pos_regs[2] & 1);
}
static void ps2_mca_mem_fffc_init(int start_mb)
{
uint32_t planar_size, expansion_start;
@@ -842,7 +862,7 @@ static void ps2_mca_mem_fffc_init(int start_mb)
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, ps2_mem_expansion_feedb, NULL);
mem_mapping_add(&ps2.expansion_mapping,
expansion_start,
(mem_size - (start_mb << 10)) << 10,
@@ -864,7 +884,8 @@ static void ps2_mca_board_model_50_init()
mem_remap_top(384);
mca_init(4);
device_add(&keyboard_ps2_mca_2_device);
ps2.planar_read = model_50_read;
ps2.planar_write = model_50_write;
@@ -935,7 +956,8 @@ static void ps2_mca_board_model_55sx_init()
}
mca_init(4);
device_add(&keyboard_ps2_mca_device);
ps2.planar_read = model_55sx_read;
ps2.planar_write = model_55sx_write;
@@ -1082,7 +1104,8 @@ static void ps2_mca_board_model_70_type34_init(int is_type4)
ps2.split_addr = mem_size * 1024;
mca_init(4);
device_add(&keyboard_ps2_mca_device);
ps2.planar_read = model_70_type3_read;
ps2.planar_write = model_70_type3_write;
@@ -1160,6 +1183,7 @@ static void ps2_mca_board_model_80_type2_init(int is486)
ps2.split_addr = mem_size * 1024;
mca_init(8);
device_add(&keyboard_ps2_mca_device);
ps2.planar_read = model_80_read;
ps2.planar_write = model_80_write;
@@ -1233,7 +1257,6 @@ machine_ps2_common_init(const machine_t *model)
dma16_init();
ps2_dma_init();
device_add(&keyboard_ps2_mca_device);
device_add(&ps_nvr_device);
pic2_init();
@@ -1241,49 +1264,110 @@ machine_ps2_common_init(const machine_t *model)
nmi_mask = 0x80;
ps2.uart = device_add_inst(&i8250_device, 1);
ps2.uart = device_add_inst(&ns16550_device, 1);
}
void
int
machine_ps2_model_50_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmps2_m50/90x7420.zm13",
L"roms/machines/ibmps2_m50/90x7429.zm18",
0x000f0000, 131072, 0);
ret &= bios_load_aux_interleaved(L"roms/machines/ibmps2_m50/90x7423.zm14",
L"roms/machines/ibmps2_m50/90x7426.zm16",
0x000e0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2_mca_board_model_50_init();
return ret;
}
void
int
machine_ps2_model_55sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmps2_m55sx/33f8146.zm41",
L"roms/machines/ibmps2_m55sx/33f8145.zm40",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2_mca_board_model_55sx_init();
return ret;
}
void
int
machine_ps2_model_70_type3_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmps2_m70_type3/70-a_even.bin",
L"roms/machines/ibmps2_m70_type3/70-a_odd.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2_mca_board_model_70_type34_init(0);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
void
int
machine_ps2_model_70_type4_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmps2_m70_type4/70-b_even.bin",
L"roms/machines/ibmps2_m70_type4/70-b_odd.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2_mca_board_model_70_type34_init(1);
return ret;
}
#endif
void
int
machine_ps2_model_80_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved(L"roms/machines/ibmps2_m80/15f6637.bin",
L"roms/machines/ibmps2_m80/15f6639.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2_mca_board_model_80_type2_init(0);
return ret;
}

865
src/machine/m_tandy.c
View File

File diff suppressed because it is too large Load Diff

215
src/machine/m_xt.c
View File

@@ -4,13 +4,16 @@
#include <wchar.h>
#include "../86box.h"
#include "../nmi.h"
#include "../timer.h"
#include "../pit.h"
#include "../mem.h"
#include "../device.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../game/gameport.h"
#include "../ibm_5161.h"
#include "../keyboard.h"
#include "../rom.h"
#include "machine.h"
@@ -28,26 +31,71 @@ machine_xt_common_init(const machine_t *model)
}
void
int
machine_pc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmpc/BIOS_5150_24APR81_U33.BIN",
0x000fe000, 40960, 0);
if (ret) {
bios_load_aux_linear(L"roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U29 - 5700019.bin",
0x000f6000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U30 - 5700027.bin",
0x000f8000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U31 - 5700035.bin",
0x000fa000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U32 - 5700043.bin",
0x000fc000, 8192, 0);
}
if (bios_only || !ret)
return ret;
machine_xt_common_init(model);
device_add(&keyboard_pc_device);
return ret;
}
void
int
machine_pc82_init(const machine_t *model)
{
int ret, ret2;
ret = bios_load_linear(L"roms/machines/ibmpc82/pc102782.bin",
0x000fe000, 40960, 0);
if (ret) {
ret2 = bios_load_aux_linear(L"roms/machines/ibmpc82/ibm-basic-1.10.rom",
0x000f6000, 32768, 0);
if (!ret2) {
bios_load_aux_linear(L"roms/machines/ibmpc82/basicc11.f6",
0x000f6000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc82/basicc11.f8",
0x000f8000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc82/basicc11.fa",
0x000fa000, 8192, 0);
bios_load_aux_linear(L"roms/machines/ibmpc82/basicc11.fc",
0x000fc000, 8192, 0);
}
}
if (bios_only || !ret)
return ret;
machine_xt_common_init(model);
device_add(&keyboard_pc82_device);
device_add(&ibm_5161_device);
return ret;
}
void
machine_xt_init(const machine_t *model)
static void
machine_xt_init_ex(const machine_t *model)
{
machine_xt_common_init(model);
@@ -55,10 +103,167 @@ machine_xt_init(const machine_t *model)
}
void
int
machine_xt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmxt/xt.rom",
0x000f0000, 65536, 0);
if (!ret) {
ret = bios_load_linear(L"roms/machines/ibmxt/1501512.u18",
0x000fe000, 65536, 0x6000);
if (ret) {
bios_load_aux_linear(L"roms/machines/ibmxt/1501512.u18",
0x000f8000, 24576, 0);
bios_load_aux_linear(L"roms/machines/ibmxt/5000027.u19",
0x000f0000, 32768, 0);
}
}
if (bios_only || !ret)
return ret;
machine_xt_init_ex(model);
device_add(&ibm_5161_device);
return ret;
}
int
machine_genxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/genxt/pcxt.rom",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_init_ex(model);
return ret;
}
int
machine_xt86_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ibmxt86/BIOS_5160_09MAY86_U18_59X7268_62X0890_27256_F800.BIN",
0x000fe000, 65536, 0x6000);
if (ret) {
bios_load_aux_linear(L"roms/machines/ibmxt86/BIOS_5160_09MAY86_U18_59X7268_62X0890_27256_F800.BIN",
0x000f8000, 24576, 0);
bios_load_aux_linear(L"roms/machines/ibmxt86/BIOS_5160_09MAY86_U19_62X0819_68X4370_27256_F000.BIN",
0x000f0000, 32768, 0);
}
if (bios_only || !ret)
return ret;
machine_xt_common_init(model);
device_add(&keyboard_xt86_device);
device_add(&ibm_5161_device);
return ret;
}
static void
machine_xt_clone_init(const machine_t *model)
{
machine_xt_common_init(model);
device_add(&keyboard_xt86_device);
}
int
machine_xt_amixt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/amixt/ami_8088_bios_31jan89.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
return ret;
}
int
machine_xt_dtk_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/dtk/dtk_erso_2.42_2764.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
return ret;
}
int
machine_xt_jukopc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/jukopc/000o001.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
return ret;
}
int
machine_xt_open_xt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/open_xt/pcxt31.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
return ret;
}
int
machine_xt_pxxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pxxt/000p001.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
return 1;
}

23
src/machine/m_xt_compaq.c
View File

@@ -24,6 +24,7 @@
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../nmi.h"
#include "../timer.h"
#include "../pit.h"
#include "../mem.h"
#include "../rom.h"
@@ -36,23 +37,29 @@
#include "machine.h"
void
int
machine_xt_compaq_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/portable/compaq portable plus 100666-001 rev c u47.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_device);
device_add(&keyboard_xt_compaq_device);
device_add(&fdc_xt_device);
nmi_init();
if (joystick_type != 7)
device_add(&gameport_device);
switch(model->id) {
case ROM_PORTABLE:
lpt1_remove();
lpt1_init(0x03bc);
break;
}
lpt1_remove();
lpt1_init(0x03bc);
return ret;
}

34
src/machine/m_xt_laserxt.c
View File

@@ -8,10 +8,12 @@
#include "../io.h"
#include "../mem.h"
#include "../nmi.h"
#include "../timer.h"
#include "../pit.h"
#include "../rom.h"
#include "machine.h"
#include "../device.h"
#include "../timer.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../game/gameport.h"
@@ -64,14 +66,6 @@ static void laserxt_write(uint16_t port, uint8_t val, void *priv)
{
laserxt_ems_baseaddr_index |= (laserxt_emscontrol[i] & 0x80) >> (7 - i);
}
if(laserxt_ems_baseaddr_index < 3)
{
mem_mapping_disable(&romext_mapping);
}
else
{
mem_mapping_enable(&romext_mapping);
}
mem_mapping_set_addr(&laserxt_ems_mapping[0], 0xC0000 + (((laserxt_ems_baseaddr_index + 4) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[1], 0xC4000 + (((laserxt_ems_baseaddr_index + 3) & 0x0C) << 14), 0x4000);
@@ -140,18 +134,36 @@ static void laserxt_init(int is_lxt3)
}
void
int
machine_xt_laserxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/ltxt/27c64.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_init(model);
laserxt_init(0);
return ret;
}
void
int
machine_xt_lxt3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/lxt3/27c64d.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
@@ -163,4 +175,6 @@ machine_xt_lxt3_init(const machine_t *model)
device_add(&gameport_device);
laserxt_init(1);
return ret;
}

27
src/machine/m_xt_t1000.c
View File

@@ -90,6 +90,7 @@
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../io.h"
#include "../timer.h"
#include "../pit.h"
#include "../nmi.h"
#include "../mem.h"
@@ -601,7 +602,7 @@ read_ctl(uint16_t addr, void *priv)
case 0x0f: /* Detect EMS board */
switch (sys->sys_ctl[0x0e]) {
case 0x50:
case 0x50:
if (mem_size > 512)
ret = (0x90 | sys->ems_port_index);
break;
@@ -847,12 +848,20 @@ t1000_get_device(void)
return(&t1000_video_device);
}
int
machine_xt_t1000_init(const machine_t *model)
{
FILE *f;
int pg;
int ret;
ret = bios_load_linear(L"roms/machines/t1000/t1000.rom",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
memset(&t1000, 0x00, sizeof(t1000));
t1000.is_t1200 = 0;
@@ -920,6 +929,8 @@ machine_xt_t1000_init(const machine_t *model)
nvr_set_ven_save(t1000_nvr_save);
if (gfxcard == VID_INTERNAL)
device_add(&t1000_video_device);
return ret;
}
@@ -930,11 +941,19 @@ t1200_get_device(void)
return(&t1200_video_device);
}
int
machine_xt_t1200_init(const machine_t *model)
{
int pg;
int ret;
ret = bios_load_linear(L"roms/machines/t1200/t1200_019e.ic15.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
memset(&t1000, 0x00, sizeof(t1000));
t1000.is_t1200 = 1;
@@ -978,6 +997,8 @@ machine_xt_t1200_init(const machine_t *model)
nvr_set_ven_save(t1200_nvr_save);
if (gfxcard == VID_INTERNAL)
device_add(&t1200_video_device);
return ret;
}

20
src/machine/m_xt_t1000_vid.c
View File

@@ -9,7 +9,7 @@
* Implementation of the Toshiba T1000 plasma display, which
* has a fixed resolution of 640x200 pixels.
*
* Version: @(#)m_xt_t1000_vid.c 1.0.9 2018/09/19
* Version: @(#)m_xt_t1000_vid.c 1.0.10 2018/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -112,7 +112,7 @@ typedef struct t1000_t
int internal; /* Using internal display? */
uint8_t attrmap; /* Attribute mapping register */
int dispontime, dispofftime;
uint64_t dispontime, dispofftime;
int linepos, displine;
int vc;
@@ -194,14 +194,14 @@ static void t1000_write(uint32_t addr, uint8_t val, void *p)
egawrites++;
t1000->vram[addr & 0x3fff] = val;
cycles -= 4;
sub_cycles(4);
}
static uint8_t t1000_read(uint32_t addr, void *p)
{
t1000_t *t1000 = (t1000_t *)p;
egareads++;
cycles -= 4;
sub_cycles(4);
return t1000->vram[addr & 0x3fff];
}
@@ -221,8 +221,8 @@ static void t1000_recalctimings(t1000_t *t1000)
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
t1000->dispontime = (int)(_dispontime * (1 << TIMER_SHIFT));
t1000->dispofftime = (int)(_dispofftime * (1 << TIMER_SHIFT));
t1000->dispontime = (uint64_t)(_dispontime * xt_cpu_multi);
t1000->dispofftime = (uint64_t)(_dispofftime * xt_cpu_multi);
}
/* Draw a row of text in 80-column mode */
@@ -493,7 +493,7 @@ static void t1000_poll(void *p)
if (!t1000->linepos)
{
t1000->cga.vidtime += t1000->dispofftime;
timer_advance_u64(&t1000->cga.timer, t1000->dispofftime);
t1000->cga.cgastat |= 1;
t1000->linepos = 1;
if (t1000->dispon)
@@ -540,7 +540,7 @@ static void t1000_poll(void *p)
{
t1000->cga.cgastat &= ~1;
}
t1000->cga.vidtime += t1000->dispontime;
timer_advance_u64(&t1000->cga.timer, t1000->dispontime);
t1000->linepos = 0;
if (t1000->displine == 200)
@@ -675,6 +675,7 @@ static void *t1000_init(const device_t *info)
{
t1000_t *t1000 = malloc(sizeof(t1000_t));
memset(t1000, 0, sizeof(t1000_t));
loadfont(L"roms/machines/t1000/t1000font.bin", 2);
cga_init(&t1000->cga);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_t1000);
@@ -683,7 +684,8 @@ static void *t1000_init(const device_t *info)
/* 16k video RAM */
t1000->vram = malloc(0x4000);
timer_add(t1000_poll, &t1000->cga.vidtime, TIMER_ALWAYS_ENABLED, t1000);
timer_set_callback(&t1000->cga.timer, t1000_poll);
timer_set_p(&t1000->cga.timer, t1000);
/* Occupy memory between 0xB8000 and 0xBFFFF */
mem_mapping_add(&t1000->mapping, 0xb8000, 0x8000, t1000_read, NULL, NULL, t1000_write, NULL, NULL, NULL, 0, t1000);

135
src/machine/m_xt_xi8088.c
View File

@@ -3,6 +3,7 @@
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../timer.h"
#include "../pic.h"
#include "../pit.h"
#include "../dma.h"
@@ -15,7 +16,9 @@
#include "../game/gameport.h"
#include "../keyboard.h"
#include "../lpt.h"
#include "../rom.h"
#include "../disk/hdc.h"
#include "../video/video.h"
#include "machine.h"
#include "../cpu/cpu.h"
@@ -29,52 +32,54 @@ typedef struct xi8088_t
int bios_128kb;
} xi8088_t;
static xi8088_t xi8088;
uint8_t xi8088_turbo_get()
static xi8088_t xi8088;
uint8_t
xi8088_turbo_get()
{
return xi8088.turbo;
return xi8088.turbo;
}
void xi8088_turbo_set(uint8_t value)
{
if (!xi8088.turbo_setting)
return;
xi8088.turbo = value;
if (!value)
{
pclog("Xi8088 turbo off\n");
int c = cpu;
cpu = 0; /* 8088/4.77 */
cpu_set();
cpu = c;
}
else
{
pclog("Xi8088 turbo on\n");
cpu_set();
}
void
xi8088_turbo_set(uint8_t value)
{
int c;
if (!xi8088.turbo_setting)
return;
xi8088.turbo = value;
if (!value) {
c = cpu;
cpu = 0; /* 8088/4.77 */
cpu_set();
cpu = c;
} else
cpu_set();
}
void xi8088_bios_128kb_set(int val)
int
xi8088_bios_128kb(void)
{
xi8088.bios_128kb = val;
return xi8088.bios_128kb;
}
int xi8088_bios_128kb()
static void *
xi8088_init(const device_t *info)
{
return xi8088.bios_128kb;
/* even though the bios by default turns the turbo off when controlling by hotkeys, pcem always starts at full speed */
xi8088.turbo = 1;
xi8088.turbo_setting = device_get_config_int("turbo_setting");
xi8088.bios_128kb = device_get_config_int("bios_128kb");
return &xi8088;
}
static void *xi8088_init()
{
/* even though the bios by default turns the turbo off when controlling by hotkeys, pcem always starts at full speed */
xi8088.turbo = 1;
xi8088.turbo_setting = device_get_config_int("turbo_setting");
return &xi8088;
}
static const device_config_t xi8088_config[] =
{
@@ -95,6 +100,23 @@ static const device_config_t xi8088_config[] =
},
.default_int = 0
},
{
.name = "bios_128kb",
.description = "BIOS size",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "64KB",
.value = 0
},
{
.description = "128KB",
.value = 1
}
},
.default_int = 1
},
{
.type = -1
}
@@ -115,23 +137,46 @@ const device_t xi8088_device =
xi8088_config
};
const device_t *
xi8088_get_device(void)
{
return &xi8088_device;
}
void machine_xt_xi8088_init(const machine_t *model)
int
machine_xt_xi8088_init(const machine_t *model)
{
/* TODO: set UMBs? See if PCem always sets when we have > 640KB ram and avoids conflicts when a peripheral uses the same memory space */
if (xi8088_bios_128kb())
mem_add_upper_bios();
machine_common_init(model);
device_add(&fdc_xt_device);
device_add(&keyboard_ps2_xi8088_device);
nmi_init();
device_add(&at_nvr_device);
pic2_init();
if (joystick_type != 7)
device_add(&gameport_device);
int ret;
if (bios_only) {
ret = bios_load_linear(L"roms/machines/xi8088/bios-xi8088.bin",
0x000f0000, 65536, 0);
} else {
device_add(&xi8088_device);
if (xi8088_bios_128kb()) {
ret = bios_load_linear_inverted(L"roms/machines/xi8088/bios-xi8088.bin",
0x000e0000, 131072, 0);
} else {
ret = bios_load_linear(L"roms/machines/xi8088/bios-xi8088.bin",
0x000f0000, 65536, 0);
}
}
if (bios_only || !ret)
return ret;
/* TODO: set UMBs? See if PCem always sets when we have > 640KB ram and avoids conflicts when a peripheral uses the same memory space */
machine_common_init(model);
device_add(&fdc_at_device);
device_add(&keyboard_ps2_xi8088_device);
nmi_init();
device_add(&ibmat_nvr_device);
pic2_init();
if (joystick_type != 7)
device_add(&gameport_device);
return ret;
}

65
src/machine/m_xt_zenith.c
View File

@@ -26,7 +26,10 @@
#include <wchar.h>
#include "../86box.h"
#include "../cpu/cpu.h"
#include "../timer.h"
#include "../dma.h"
#include "../nmi.h"
#include "../pic.h"
#include "../pit.h"
#include "../mem.h"
#include "../rom.h"
@@ -36,24 +39,32 @@
#include "../game/gameport.h"
#include "../keyboard.h"
#include "../lpt.h"
#include "../serial.h"
#include "machine.h"
typedef struct {
mem_mapping_t scratchpad_mapping;
uint8_t *scratchpad_ram;
} zenith_t;
static uint8_t zenith_scratchpad_read(uint32_t addr, void *p)
static uint8_t
zenith_scratchpad_read(uint32_t addr, void *p)
{
zenith_t *dev = (zenith_t *)p;
return dev->scratchpad_ram[addr & 0x3fff];
zenith_t *dev = (zenith_t *)p;
return dev->scratchpad_ram[addr & 0x3fff];
}
static void zenith_scratchpad_write(uint32_t addr, uint8_t val, void *p)
static void
zenith_scratchpad_write(uint32_t addr, uint8_t val, void *p)
{
zenith_t *dev = (zenith_t *)p;
dev->scratchpad_ram[addr & 0x3fff] = val;
zenith_t *dev = (zenith_t *)p;
dev->scratchpad_ram[addr & 0x3fff] = val;
}
static void *
zenith_scratchpad_init(const device_t *info)
{
@@ -64,9 +75,6 @@ zenith_scratchpad_init(const device_t *info)
dev->scratchpad_ram = malloc(0x4000);
mem_mapping_disable(&bios_mapping[4]);
mem_mapping_disable(&bios_mapping[5]);
mem_mapping_add(&dev->scratchpad_mapping, 0xf0000, 0x4000,
zenith_scratchpad_read, NULL, NULL,
zenith_scratchpad_write, NULL, NULL,
@@ -75,13 +83,14 @@ zenith_scratchpad_init(const device_t *info)
return dev;
}
static void
zenith_scratchpad_close(void *p)
{
zenith_t *dev = (zenith_t *)p;
zenith_t *dev = (zenith_t *)p;
free(dev->scratchpad_ram);
free(dev);
free(dev->scratchpad_ram);
free(dev);
}
@@ -94,20 +103,30 @@ static const device_t zenith_scratchpad_device = {
NULL
};
void
int
machine_xt_zenith_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/zdsupers/z184m v3.1d.10d",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
lpt2_remove(); /* only one parallel port */
device_add(&zenith_scratchpad_device);
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_device);
device_add(&fdc_xt_device);
lpt1_remove(); /* only one parallel port */
lpt2_remove();
lpt1_init(0x278);
device_add(&i8250_device);
serial_set_next_inst(2); /* So that serial_standalone_init() won't do anything. */
device_add(&zenith_scratchpad_device);
pit_set_out_func(&pit, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_compaq_device);
nmi_init();
if (joystick_type != 7)
device_add(&gameport_device);
}
return ret;
}

78
src/machine/machine.c
View File

@@ -26,6 +26,7 @@
#define HAVE_STDARG_H
#include "../86box.h"
#include "../device.h"
#include "../timer.h"
#include "../dma.h"
#include "../pic.h"
#include "../pit.h"
@@ -38,9 +39,9 @@
#include "machine.h"
int bios_only = 0;
int machine;
int AT, PCI;
int romset;
#ifdef ENABLE_MACHINE_LOG
@@ -64,36 +65,57 @@ machine_log(const char *fmt, ...)
#endif
static int
machine_init_ex(int m)
{
int ret = 0;
if (!bios_only) {
machine_log("Initializing as \"%s\"\n", machine_getname_ex(m));
/* Set up the architecture flags. */
AT = IS_ARCH(machine, MACHINE_AT);
PCI = IS_ARCH(machine, MACHINE_PCI);
/* Resize the memory. */
mem_reset();
lpt_init();
}
/* All good, boot the machine! */
if (machines[m].init)
ret = machines[m].init(&machines[m]);
if (bios_only || !ret)
return ret;
/* Reset the graphics card (or do nothing if it was already done
by the machine's init function). */
video_reset(gfxcard);
return ret;
}
void
machine_init(void)
{
int MCA;
machine_log("Initializing as \"%s\"\n", machine_getname());
bios_only = 0;
(void) machine_init_ex(machine);
}
/* Set up the architecture flags. */
AT = IS_ARCH(machine, MACHINE_AT);
PCI = IS_ARCH(machine, MACHINE_PCI);
MCA = IS_ARCH(machine, MACHINE_MCA);
/* Resize the memory. */
mem_reset();
int
machine_available(int m)
{
int ret;
/* Load the machine's ROM BIOS. */
rom_load_bios(romset);
mem_add_bios();
bios_only = 1;
ret = machine_init_ex(m);
/* If it's not a PCI or MCA machine, reset the video card
before initializing the machine, to please the EuroPC. */
if (!PCI && !MCA)
video_reset(gfxcard);
/* All good, boot the machine! */
machines[machine].init(&machines[machine]);
/* If it's a PCI or MCA machine, reset the video card
after initializing the machine, so the slots work correctly. */
if (PCI || MCA)
video_reset(gfxcard);
bios_only = 0;
return ret;
}
@@ -103,14 +125,8 @@ machine_common_init(const machine_t *model)
/* System devices first. */
pic_init();
dma_init();
pit_init();
cpu_set();
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286)
setrtcconst(machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed);
else
setrtcconst(14318184.0);
if (lpt_enabled)
lpt_init();
pit_init();
}

356
src/machine/machine.h
View File

@@ -8,21 +8,22 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.h 1.0.33 2019/02/08
* Version: @(#)machine.h 1.0.34 2019/03/08
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
* Copyright 2017-2019 Fred N. van Kempen.
*/
#ifndef EMU_MACHINE_H
# define EMU_MACHINE_H
/* Machine feature flags. */
#ifdef NEW_FLAGS
#define MACHINE_PC 0x000000 /* PC architecture */
#define MACHINE_AT 0x000001 /* PC/AT architecture */
#define MACHINE_PS2 0x000002 /* PS/2 architecture */
@@ -34,17 +35,56 @@
#define MACHINE_PCI 0x000200 /* sys has PCI bus */
#define MACHINE_AGP 0x000400 /* sys has AGP bus */
#define MACHINE_HDC 0x001000 /* sys has int HDC */
#define MACHINE_HDC_PS2 0x002000 /* sys has int PS/2 HDC */
#define MACHINE_MOUSE 0x004000 /* sys has int mouse */
#define MACHINE_VIDEO 0x008000 /* sys has int video */
#define MACHINE_VIDEO 0x002000 /* sys has int video */
#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
#define MACHINE_NONMI 0x010000 /* sys does not have NMI's */
#else
#define MACHINE_PC 0x000000 /* PC architecture */
#define MACHINE_AT 0x000001 /* PC/AT architecture */
#define MACHINE_PS2 0x000002 /* PS/2 architecture */
#define MACHINE_ISA 0x000010 /* sys has ISA bus */
#define MACHINE_CBUS 0x000020 /* sys has C-BUS bus */
#define MACHINE_EISA 0x000040 /* sys has EISA bus */
#define MACHINE_VLB 0x000080 /* sys has VL bus */
#define MACHINE_MCA 0x000100 /* sys has MCA bus */
#define MACHINE_PCI 0x000200 /* sys has PCI bus */
#define MACHINE_AGP 0x000400 /* sys has AGP bus */
#define MACHINE_HDC 0x001000 /* sys has int HDC */
#define MACHINE_VIDEO 0x002000 /* sys has int video */
#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
#define MACHINE_NONMI 0x010000 /* sys does not have NMI's */
#endif
#define IS_ARCH(m, a) (machines[(m)].flags & (a)) ? 1 : 0;
#ifdef NEW_STRUCT
typedef struct _machine_ {
const char *name;
const char *internal_name;
#ifdef EMU_DEVICE_H
const device_t *device;
#else
void *device;
#endif
struct {
const char *name;
#ifdef EMU_CPU_H
CPU *cpus;
#else
void *cpus;
#endif
} cpu[5];
int flags;
uint32_t min_ram, max_ram;
int ram_granularity;
int nvrmask;
} machine_t;
#else
typedef struct _machine_ {
const char *name;
int id;
const char *internal_name;
struct {
const char *name;
@@ -54,39 +94,37 @@ typedef struct _machine_ {
void *cpus;
#endif
} cpu[5];
int fixed_gfxcard;
int flags;
uint32_t min_ram, max_ram;
int ram_granularity;
int nvrmask;
void (*init)(const struct _machine_ *);
int (*init)(const struct _machine_ *);
#ifdef EMU_DEVICE_H
const device_t *(*get_device)(void);
#else
void *get_device;
#endif
} machine_t;
#endif
/* Global variables. */
extern const machine_t machines[];
extern int bios_only;
extern int machine;
extern int romset;
extern int AT, PCI;
/* Core functions. */
extern int machine_count(void);
extern int machine_getromset(void);
extern int machine_getmachine(int romset);
extern int machine_available(int m);
extern char *machine_getname(void);
extern char *machine_get_internal_name(void);
extern int machine_get_machine_from_internal_name(char *s);
extern void machine_init(void);
#ifdef EMU_DEVICE_H
extern const device_t *machine_getdevice(int machine);
extern const device_t *machine_getdevice(int m);
#endif
extern int machine_getromset_ex(int m);
extern char *machine_get_internal_name_ex(int m);
extern int machine_get_nvrmask(int m);
extern void machine_close(void);
@@ -95,126 +133,240 @@ extern void machine_close(void);
/* Initialization functions for boards and systems. */
extern void machine_common_init(const machine_t *);
/* m_amstrad.c */
extern int machine_pc1512_init(const machine_t *);
extern int machine_pc1640_init(const machine_t *);
extern int machine_pc200_init(const machine_t *);
extern int machine_ppc512_init(const machine_t *);
extern int machine_pc2086_init(const machine_t *);
extern int machine_pc3086_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *pc1512_get_device(void);
extern const device_t *pc1640_get_device(void);
extern const device_t *pc200_get_device(void);
extern const device_t *ppc512_get_device(void);
extern const device_t *pc2086_get_device(void);
extern const device_t *pc3086_get_device(void);
#endif
/* m_at.c */
extern void machine_at_common_init_ex(const machine_t *, int is_ibm);
extern void machine_at_common_init(const machine_t *);
extern void machine_at_init(const machine_t *);
extern void machine_at_ibm_init(const machine_t *);
extern void machine_at_ps2_init(const machine_t *);
extern void machine_at_common_ide_init(const machine_t *);
extern void machine_at_ibm_common_ide_init(const machine_t *);
extern void machine_at_ide_init(const machine_t *);
extern void machine_at_ps2_ide_init(const machine_t *);
extern void machine_at_t3100e_init(const machine_t *);
extern int machine_at_ibm_init(const machine_t *);
extern int machine_at_ibmxt286_init(const machine_t *);
extern void machine_at_p54tp4xe_init(const machine_t *);
extern void machine_at_endeavor_init(const machine_t *);
extern void machine_at_zappa_init(const machine_t *);
extern void machine_at_mb500n_init(const machine_t *);
extern void machine_at_president_init(const machine_t *);
extern void machine_at_thor_init(const machine_t *);
extern void machine_at_pb640_init(const machine_t *);
extern void machine_at_acerm3a_init(const machine_t *);
extern void machine_at_acerv35n_init(const machine_t *);
extern void machine_at_ap53_init(const machine_t *);
extern void machine_at_p55t2p4_init(const machine_t *);
extern void machine_at_p55t2s_init(const machine_t *);
extern void machine_at_batman_init(const machine_t *);
extern void machine_at_plato_init(const machine_t *);
extern void machine_at_p55tvp4_init(const machine_t *);
extern void machine_at_i430vx_init(const machine_t *);
extern void machine_at_p55va_init(const machine_t *);
extern void machine_at_j656vxd_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_I686)
extern void machine_at_i440fx_init(const machine_t *);
extern void machine_at_s1668_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
extern int machine_at_open_at_init(const machine_t *);
#endif
extern void machine_at_ali1429_init(const machine_t *);
extern void machine_at_cmdpc_init(const machine_t *);
extern void machine_at_headland_init(const machine_t *);
extern void machine_at_tg286m_init(const machine_t *);
extern void machine_at_ama932j_init(const machine_t *);
extern void machine_at_neat_init(const machine_t *);
extern void machine_at_neat_ami_init(const machine_t *);
extern void machine_at_opti495_init(const machine_t *);
extern void machine_at_opti495_ami_init(const machine_t *);
extern void machine_at_scat_init(const machine_t *);
extern void machine_at_scatsx_init(const machine_t *);
extern void machine_at_compaq_init(const machine_t *);
/* m_at_286_386sx.c */
#if defined(DEV_BRANCH) && defined(USE_AMI386SX)
extern int machine_at_headland_init(const machine_t *);
#endif
extern int machine_at_tg286m_init(const machine_t *);
extern int machine_at_ama932j_init(const machine_t *);
extern void machine_at_dtk486_init(const machine_t *);
extern void machine_at_r418_init(const machine_t *);
extern int machine_at_neat_init(const machine_t *);
extern int machine_at_neat_ami_init(const machine_t *);
extern void machine_at_wd76c10_init(const machine_t *);
extern int machine_at_award286_init(const machine_t *);
extern int machine_at_gw286ct_init(const machine_t *);
extern int machine_at_super286tr_init(const machine_t *);
extern int machine_at_spc4200p_init(const machine_t *);
extern int machine_at_spc4216p_init(const machine_t *);
extern int machine_at_kmxc02_init(const machine_t *);
extern void machine_pc_init(const machine_t *);
extern void machine_pc82_init(const machine_t *);
extern int machine_at_wd76c10_init(const machine_t *);
extern void machine_pcjr_init(const machine_t *);
extern void machine_ps1_m2011_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern void ps1_hdc_inform(void *, void *);
extern void ps1_set_feedback(void *);
extern const device_t ps1_hdc_device;
extern const device_t *at_ama932j_get_device(void);
#endif
extern void machine_ps1_m2121_init(const machine_t *);
extern void machine_ps1_m2133_init(const machine_t *);
/* m_at_386dx_486.c */
extern int machine_at_pb410a_init(const machine_t *);
extern void machine_ps2_m30_286_init(const machine_t *);
extern void machine_ps2_model_50_init(const machine_t *);
extern void machine_ps2_model_55sx_init(const machine_t *);
extern void machine_ps2_model_70_type3_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
extern void machine_ps2_model_70_type4_init(const machine_t *);
extern int machine_at_ali1429_init(const machine_t *);
extern int machine_at_winbios1429_init(const machine_t *);
extern int machine_at_opti495_init(const machine_t *);
extern int machine_at_opti495_ami_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_MR495)
extern int machine_at_opti495_mr_init(const machine_t *);
#endif
extern void machine_ps2_model_80_init(const machine_t *);
extern void machine_amstrad_init(const machine_t *);
extern int machine_at_ami471_init(const machine_t *);
extern int machine_at_dtk486_init(const machine_t *);
extern int machine_at_px471_init(const machine_t *);
extern int machine_at_win471_init(const machine_t *);
extern void machine_europc_init(const machine_t *);
extern int machine_at_r418_init(const machine_t *);
extern int machine_at_alfredo_init(const machine_t *);
/* m_at_commodore.c */
extern int machine_at_cmdpc_init(const machine_t *);
/* m_at_compaq.c */
extern int machine_at_portableii_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
extern int machine_at_portableiii_init(const machine_t *);
extern int machine_at_portableiii386_init(const machine_t *);
#endif
/* m_at_socket4_5.c */
extern int machine_at_batman_init(const machine_t *);
extern int machine_at_586mc1_init(const machine_t *);
extern int machine_at_plato_init(const machine_t *);
extern int machine_at_430nx_init(const machine_t *);
extern int machine_at_p54tp4xe_init(const machine_t *);
extern int machine_at_endeavor_init(const machine_t *);
extern int machine_at_zappa_init(const machine_t *);
extern int machine_at_mb500n_init(const machine_t *);
extern int machine_at_president_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
extern int machine_at_vectra54_init(const machine_t *);
#endif
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
#endif
/* m_at_socket7_s7.c */
extern int machine_at_thor_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
extern int machine_at_mrthor_init(const machine_t *);
#endif
extern int machine_at_pb640_init(const machine_t *);
extern int machine_at_acerm3a_init(const machine_t *);
extern int machine_at_acerv35n_init(const machine_t *);
extern int machine_at_ap53_init(const machine_t *);
extern int machine_at_p55t2p4_init(const machine_t *);
extern int machine_at_p55t2s_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_TC430HX)
extern int machine_at_tc430hx_init(const machine_t *);
#endif
extern int machine_at_p55tvp4_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_p55va_init(const machine_t *);
extern int machine_at_j656vxd_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_pb640_get_device(void);
#endif
/* m_at_socket8.c */
#if defined(DEV_BRANCH) && defined(USE_I686)
extern int machine_at_i440fx_init(const machine_t *);
extern int machine_at_s1668_init(const machine_t *);
#endif
/* m_at_t3100e.c */
extern int machine_at_t3100e_init(const machine_t *);
/* m_europc.c */
extern int machine_europc_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t europc_device;
#endif
extern void machine_olim24_init(const machine_t *);
extern void machine_olim24_video_init(void);
/* m_oivetti_m24.c */
extern int machine_olim24_init(const machine_t *);
extern void machine_tandy1k_init(const machine_t *);
extern int tandy1k_eeprom_read(void);
/* m_pcjr.c */
extern int machine_pcjr_init(const machine_t *);
extern void machine_xt_init(const machine_t *);
extern void machine_xt86_init(const machine_t *);
extern void machine_xt_compaq_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
extern void machine_xt_laserxt_init(const machine_t *);
extern void machine_xt_lxt3_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *pcjr_get_device(void);
#endif
extern void machine_xt_t1000_init(const machine_t *);
extern void machine_xt_t1200_init(const machine_t *);
/* m_ps1.c */
extern int machine_ps1_m2011_init(const machine_t *);
extern int machine_ps1_m2121_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_PS1M2133)
extern int machine_ps1_m2133_init(const machine_t *);
#endif
extern void machine_xt_xi8088_init(const machine_t *);
extern void machine_xt_zenith_init(const machine_t *);
/* m_ps1_hdc.c */
#ifdef EMU_DEVICE_H
extern void ps1_hdc_inform(void *, uint8_t *);
extern const device_t ps1_hdc_device;
#endif
/* m_ps2_isa.c */
extern int machine_ps2_m30_286_init(const machine_t *);
/* m_ps2_mca.c */
extern int machine_ps2_model_50_init(const machine_t *);
extern int machine_ps2_model_55sx_init(const machine_t *);
extern int machine_ps2_model_70_type3_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
extern int machine_ps2_model_70_type4_init(const machine_t *);
#endif
extern int machine_ps2_model_80_init(const machine_t *);
/* m_tandy.c */
extern int tandy1k_eeprom_read(void);
extern int machine_tandy_init(const machine_t *);
extern int machine_tandy1000hx_init(const machine_t *);
extern int machine_tandy1000sl2_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *tandy1k_get_device(void);
extern const device_t *tandy1k_hx_get_device(void);
#endif
/* m_xt.c */
extern int machine_pc_init(const machine_t *);
extern int machine_pc82_init(const machine_t *);
extern int machine_xt_init(const machine_t *);
extern int machine_genxt_init(const machine_t *);
extern int machine_xt86_init(const machine_t *);
extern int machine_xt_amixt_init(const machine_t *);
extern int machine_xt_dtk_init(const machine_t *);
extern int machine_xt_jukopc_init(const machine_t *);
extern int machine_xt_open_xt_init(const machine_t *);
extern int machine_xt_pxxt_init(const machine_t *);
/* m_xt_compaq.c */
extern int machine_xt_compaq_init(const machine_t *);
/* m_xt_laserxt.c */
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
extern int machine_xt_laserxt_init(const machine_t *);
extern int machine_xt_lxt3_init(const machine_t *);
#endif
/* m_xt_t1000.c */
extern int machine_xt_t1000_init(const machine_t *);
extern int machine_xt_t1200_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *t1000_get_device(void);
extern const device_t *t1200_get_device(void);
#endif
/* m_xt_zenith.c */
extern int machine_xt_zenith_init(const machine_t *);
/* m_xt_xi8088.c */
extern int machine_xt_xi8088_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *xi8088_get_device(void);
extern const device_t *pcjr_get_device(void);
extern const device_t *tandy1k_get_device(void);
extern const device_t *tandy1k_hx_get_device(void);
extern const device_t *t1000_get_device(void);
extern const device_t *t1200_get_device(void);
extern const device_t *at_endeavor_get_device(void);
extern const device_t *at_ama932j_get_device(void);
#endif

295
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.46 2019/02/08
* Version: @(#)machine_table.c 1.0.47 2019/02/13
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -33,157 +33,168 @@
#include "machine.h"
#if defined(DEV_BRANCH) && defined(USE_AMD_K)
#define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#define MACHINE_CPUS_PENTIUM_S7 {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}
#else
#define MACHINE_CPUS_PENTIUM_S7 {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"", NULL}, {"", NULL}}
#endif
#else
#define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#define MACHINE_CPUS_PENTIUM_S7 {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}
#else
#define MACHINE_CPUS_PENTIUM_S7 {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}
#endif
#endif
const machine_t machines[] = {
{ "[8088] AMI XT clone", ROM_AMIXT, "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Compaq Portable", ROM_PORTABLE, "portable", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
{ "[8088] DTK XT clone", ROM_DTKXT, "dtk", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM PC (1981)", ROM_IBMPC, "ibmpc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 16, 64, 16, 0, machine_pc_init, NULL },
{ "[8088] IBM PC (1982)", ROM_IBMPC82, "ibmpc82", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 256, 64, 0, machine_pc82_init, NULL },
{ "[8088] IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT (1982)", ROM_IBMXT, "ibmxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 256, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM XT (1986)", ROM_IBMXT86, "ibmxt86", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 64, 0, machine_xt86_init, NULL },
{ "[8088] Generic XT clone", ROM_GENXT, "genxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Juko XT clone", ROM_JUKOPC, "jukopc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Phoenix XT clone", ROM_PXXT, "pxxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Schneider EuroPC", ROM_EUROPC, "europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Tandy 1000", ROM_TANDY, "tandy", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 128, 640, 128, 0, machine_tandy1k_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 256, 640, 128, 0, machine_tandy1k_init, tandy1k_hx_get_device },
{ "[8088] Toshiba T1000", ROM_T1000, "t1000", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
{ "[8088] AMI XT clone", "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Compaq Portable", "portable", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
{ "[8088] DTK XT clone", "dtk", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] IBM PC (1981)", "ibmpc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 16, 64, 16, 0, machine_pc_init, NULL },
{ "[8088] IBM PC (1982)", "ibmpc82", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 256, 256, 0, machine_pc82_init, NULL },
{ "[8088] IBM PCjr", "ibmpcjr", {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT (1982)", "ibmxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 256, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM XT (1986)", "ibmxt86", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 64, 0, machine_xt86_init, NULL },
{ "[8088] Generic XT clone", "genxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] Juko XT clone", "jukopc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] OpenXT", "open_xt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_open_xt_init, NULL },
{ "[8088] Phoenix XT clone", "pxxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_pxxt_init, NULL },
{ "[8088] Schneider EuroPC", "europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_HDC | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Tandy 1000", "tandy", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_tandy_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", "tandy1000hx", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 256, 640, 128, 0, machine_tandy1000hx_init, tandy1k_hx_get_device },
{ "[8088] Toshiba T1000", "t1000", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
{ "[8088] VTech Laser Turbo XT", "ltxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
#endif
{ "[8088] Xi8088", ROM_XI8088, "xi8088", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, NULL },
{ "[8088] Zenith Data SupersPort", ROM_ZD_SUPERS, "zdsupers", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 128, 640, 128, 0, machine_xt_zenith_init, NULL },
{ "[8088] Xi8088", "xi8088", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, xi8088_get_device },
{ "[8088] Zenith Data SupersPort", "zdsupers", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_zenith_init, NULL },
{ "[8086] Amstrad PC1512", ROM_PC1512, "pc1512", {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC1640", ROM_PC1640, "pc1640", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC2086", ROM_PC2086, "pc2086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC3086", ROM_PC3086, "pc3086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC20(0)", ROM_PC200, "pc200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL },
{ "[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, machine_tandy1k_init, NULL },
{ "[8086] Toshiba T1200", ROM_T1200, "t1200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
{ "[8086] Amstrad PC1512", "pc1512", {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_pc1512_init, pc1512_get_device },
{ "[8086] Amstrad PC1640", "pc1640", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc1640_init, pc1640_get_device },
{ "[8086] Amstrad PC2086", "pc2086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc2086_init, pc2086_get_device },
{ "[8086] Amstrad PC3086", "pc3086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Olivetti M24", "olivetti_m24", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, NULL },
{ "[8086] Toshiba T1200", "t1200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8086] VTech Laser XT3", ROM_LXT3, "lxt3", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
{ "[8086] VTech Laser XT3", "lxt3", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
#endif
{ "[286 ISA] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[286 ISA] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL },
{ "[286 ISA] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[286 ISA] Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_compaq_init, NULL },
{ "[286 ISA] AMI 286 clone", "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[286 ISA] Award 286 clone", "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL },
{ "[286 ISA] Commodore PC 30 III", "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[286 ISA] Compaq Portable II", "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[286 ISA] Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_compaq_init, NULL },
{ "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 640,16384, 128, 127, machine_at_portableiii_init, NULL },
#endif
{ "[286 ISA] GW-286CT GEAR", ROM_GW286CT, "gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL },
{ "[286 ISA] Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL },
{ "[286 ISA] IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL },
{ "[286 ISA] IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2 | MACHINE_HDC_PS2, 512,16384, 512, 63, machine_ps1_m2011_init, NULL },
{ "[286 ISA] IBM PS/2 model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{ "[286 ISA] IBM XT Model 286", ROM_IBMXT286, "ibmxt286", {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 127, machine_at_ibm_init, NULL },
{ "[286 ISA] Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 127, machine_at_scat_init, NULL },
{ "[286 ISA] Samsung SPC-4216P", ROM_SPC4216P, "spc4216p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 127, machine_at_scat_init, NULL },
{ "[286 ISA] Toshiba T3100e", ROM_T3100E, "t3100e", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
{ "[286 ISA] Trigem 286M", ROM_TG286M, "tg286m", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
{ "[286 ISA] GW-286CT GEAR", "gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL },
{ "[286 ISA] Hyundai Super-286TR", "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL },
{ "[286 ISA] IBM AT", "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL },
{ "[286 ISA] IBM PS/1 model 2011", "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 512,16384, 512, 63, machine_ps1_m2011_init, NULL },
{ "[286 ISA] IBM PS/2 model 30-286", "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{ "[286 ISA] IBM XT Model 286", "ibmxt286", {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 127, machine_at_ibmxt286_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
{ "[286 ISA] OpenAT", "open_at", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_open_at_init, NULL },
#endif
{ "[286 ISA] Samsung SPC-4200P", "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 127, machine_at_spc4200p_init, NULL },
{ "[286 ISA] Samsung SPC-4216P", "spc4216p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 127, machine_at_spc4216p_init, NULL },
{ "[286 ISA] Toshiba T3100e", "t3100e", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
{ "[286 ISA] Trigem 286M", "tg286m", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
{ "[286 MCA] IBM PS/2 model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[286 MCA] IBM PS/2 model 50", "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[386SX ISA] AMA-932J", ROM_AMA932J, "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
{ "[386DX ISA] AMI 386SX clone", ROM_AMI386SX_OPTI495, "ami386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386SX ISA] AMI Unknown 386SX", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
{ "[386SX ISA] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 16, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386SX ISA] Award 386SX clone", ROM_AWARD386SX_OPTI495, "award386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_init, NULL },
{ "[386SX ISA] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] KMX-C-02", ROM_KMXC02, "kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_scatsx_init, NULL },
{ "[386DX ISA] MR 386SX clone", ROM_MR386SX_OPTI495, "mr386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386SX ISA] AMA-932J", "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
#if defined(DEV_BRANCH) && defined(USE_AMI386SX)
{ "[386SX ISA] AMI Unknown 386SX", "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
#endif
{ "[386SX ISA] Amstrad MegaPC", "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386SX ISA] DTK 386SX clone", "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[386SX ISA] IBM PS/1 model 2121", "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] KMX-C-02", "kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
{ "[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386DX ISA] Award 386DX clone", ROM_AWARD386DX_OPTI495, "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{ "[386DX ISA] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] AMI 386DX clone", "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] Award 386DX clone", "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_MR495)
{ "[386DX ISA] MR 386DX clone", "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_compaq_init, NULL },
{ "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 1, 14, 1, 127, machine_at_portableiii386_init, NULL },
#endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibmps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL },
{ "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL },
{ "[386DX MCA] IBM PS/2 model 80", "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
{ "[486 ISA] AMI 486 clone", ROM_AMI486_OPTI495, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[486 ISA] AMI ALi 1429", ROM_AMI486, "ali1429", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{ "[486 ISA] AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{ "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_dtk486_init, NULL },
{ "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI, 1, 64, 1, 127, machine_ps1_m2133_init, NULL },
{ "[486 ISA] MR 486 clone", ROM_MR486_OPTI495, "mr486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[486 ISA] AMI 486 clone", "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[486 ISA] AMI ALi 1429", "ali1429", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{ "[486 ISA] AMI SiS 471", "ami471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_ami471_init, NULL },
{ "[486 ISA] AMI WinBIOS 486", "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_winbios1429_init, NULL },
{ "[486 ISA] AMI WinBIOS SiS 471", "win471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_win471_init, NULL },
{ "[486 ISA] Award 486 clone", "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_dtk486_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PS1M2133)
{ "[486 ISA] IBM PS/1 model 2133", "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI, 1, 64, 1, 127, machine_ps1_m2133_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_MR495)
{ "[486 ISA] MR 486 clone", "mr486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
#endif
{ "[486 ISA] Packard Bell PB410A", "pb410a", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 64, 1, 127, machine_at_pb410a_init, NULL },
{ "[486 ISA] Phoenix SiS 471", "px471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
{ "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibmps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type4_init, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", "ibmps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type4_init, NULL },
#endif
{ "[486 PCI] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL },
{ "[486 PCI] Intel Classic/PCI", "alfredo", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_alfredo_init, NULL },
{ "[486 PCI] Rise Computer R418", "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL },
{ "[Socket 4 LX] Intel Premiere/PCI", ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[Socket 4 LX] Intel Premiere/PCI", "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[Socket 4 LX] Micro Star 586MC1", "586mc1", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_AMD_K)
{ "[Socket 5 NX] Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[Socket 5 NX] Intel Premiere/PCI II", "plato", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[Socket 5 NX] Gigabyte GA-586IP", "430nx", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_430nx_init, NULL },
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
{ "[Socket 5 FX] Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[Socket 5 FX] PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
{ "[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT, "president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL },
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
{ "[Socket 5 FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_vectra54_init, NULL },
#endif
{ "[Socket 5 FX] Intel Advanced/ZP", "zappa", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[Socket 5 FX] PC Partner MB500N", "mb500n", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
{ "[Socket 5 FX] President Award 430FX PCI","president", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL },
{ "[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[Socket 7 FX] Intel Advanced/ATX", "thor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
{ "[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[Socket 7 FX] MR Intel Advanced/ATX", "mrthor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_mrthor_init, NULL },
#endif
{ "[Socket 7 FX] Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[Socket 7 FX] Packard Bell PB640", ROM_PB640, "pb640", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, NULL },
{ "[Socket 7 FX] Intel Advanced/EV", "endeavor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[Socket 7 FX] Packard Bell PB640", "pb640", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[Socket 7 HX] AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", ROM_P55T2P4, "p55t2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
{ "[Socket 7 VX] ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[Socket 7 VX] Award 430VX PCI", ROM_430VX, "430vx", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] Jetway J656VXD", ROM_J656VXD, "j656vxd", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
#else
{ "[Socket 5 NX] Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
{ "[Socket 5 FX] Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[Socket 5 FX] PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
{ "[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT, "president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL },
{ "[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
{ "[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[Socket 7 HX] Acer M3a", "acerm3a", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[Socket 7 HX] Acer V35n", "acerv35n", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[Socket 7 HX] AOpen AP53", "ap53", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_TC430HX)
{ "[Socket 7 HX] TC430HX", "tc430hx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_tc430hx_init, NULL },
#endif
{ "[Socket 7 FX] Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[Socket 7 FX] Packard Bell PB640", ROM_PB640, "pb640", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, NULL },
{ "[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[Socket 7 HX] AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", ROM_P55T2P4, "p55t2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
{ "[Socket 7 VX] ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[Socket 7 VX] Award 430VX PCI", ROM_430VX, "430vx", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] Jetway J656VXD", ROM_J656VXD, "j656vxd", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"Cyrix", cpus_6x86}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
#endif
{ "[Socket 7 VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_I686)
{ "[Socket 8 FX] Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
#endif
{ "", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0,0, 0 }
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
};
@@ -194,35 +205,6 @@ machine_count(void)
}
int
machine_getromset(void)
{
return(machines[machine].id);
}
int
machine_getromset_ex(int m)
{
return(machines[m].id);
}
int
machine_getmachine(int romset)
{
int c = 0;
while (machines[c].id != -1) {
if (machines[c].id == romset)
return(c);
c++;
}
return(0);
}
char *
machine_getname(void)
{
@@ -230,11 +212,18 @@ machine_getname(void)
}
const device_t *
machine_getdevice(int machine)
char *
machine_getname_ex(int m)
{
if (machines[machine].get_device)
return(machines[machine].get_device());
return((char *)machines[m].name);
}
const device_t *
machine_getdevice(int m)
{
if (machines[m].get_device)
return(machines[m].get_device());
return(NULL);
}
@@ -266,7 +255,7 @@ machine_get_machine_from_internal_name(char *s)
{
int c = 0;
while (machines[c].id != -1) {
while (machines[c].init != NULL) {
if (!strcmp(machines[c].internal_name, (const char *)s))
return(c);
c++;

252
src/machine/machine_table_new.c Normal file
View File

@@ -0,0 +1,252 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of the emulated machines.
*
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.47 2019/02/13
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
* Copyright 2017,2018 Fred N. van Kempen.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../cpu_new/cpu.h"
#include "../mem.h"
#include "../rom.h"
#include "../device.h"
#include "machine.h"
#define MACHINE_CPUS_PENTIUM_S5 {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}
#define MACHINE_CPUS_PENTIUM_S7 {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}
const machine_t machines[] = {
{ "[8088] AMI XT clone", "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Compaq Portable", "portable", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
{ "[8088] DTK XT clone", "dtk", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] IBM PC (1981)", "ibmpc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 16, 64, 16, 0, machine_pc_init, NULL },
{ "[8088] IBM PC (1982)", "ibmpc82", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 256, 256, 0, machine_pc82_init, NULL },
{ "[8088] IBM PCjr", "ibmpcjr", {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT (1982)", "ibmxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 256, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM XT (1986)", "ibmxt86", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 64, 0, machine_xt86_init, NULL },
{ "[8088] Generic XT clone", "genxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] Juko XT clone", "jukopc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] OpenXT", "open_xt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_open_xt_init, NULL },
{ "[8088] Phoenix XT clone", "pxxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_pxxt_init, NULL },
{ "[8088] Schneider EuroPC", "europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_HDC | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Tandy 1000", "tandy", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 128, 640, 128, 0, machine_tandy_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", "tandy1000hx", {{"Intel", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 256, 640, 128, 0, machine_tandy1000hx_init, tandy1k_hx_get_device },
{ "[8088] Toshiba T1000", "t1000", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", "ltxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
#endif
{ "[8088] Xi8088", "xi8088", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, xi8088_get_device },
{ "[8088] Zenith Data SupersPort", "zdsupers", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 128, 640, 128, 0, machine_xt_zenith_init, NULL },
{ "[8086] Amstrad PC1512", "pc1512", {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_pc1512_init, pc1512_get_device },
{ "[8086] Amstrad PC1640", "pc1640", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc1640_init, pc1640_get_device },
{ "[8086] Amstrad PC2086", "pc2086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc2086_init, pc2086_get_device },
{ "[8086] Amstrad PC3086", "pc3086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 0, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Olivetti M24", "olivetti_m24", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, NULL },
{ "[8086] Toshiba T1200", "t1200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8086] VTech Laser XT3", "lxt3", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
#endif
{ "[286 ISA] AMI 286 clone", "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[286 ISA] Award 286 clone", "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL },
{ "[286 ISA] Commodore PC 30 III", "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[286 ISA] Compaq Portable II", "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 640,16384, 128, 127, machine_at_portableiii_init, NULL },
#endif
{ "[286 ISA] GW-286CT GEAR", "gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL },
{ "[286 ISA] Hyundai Super-286TR", "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL },
{ "[286 ISA] IBM AT", "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL },
{ "[286 ISA] IBM PS/1 model 2011", "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 512,16384, 512, 63, machine_ps1_m2011_init, NULL },
{ "[286 ISA] IBM PS/2 model 30-286", "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC | MACHINE_PS2, 1, 16, 1, 127, machine_ps2_m30_286_init, NULL },
{ "[286 ISA] IBM XT Model 286", "ibmxt286", {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 127, machine_at_ibmxt286_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
{ "[286 ISA] OpenAT", "open_at", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_open_at_init, NULL },
#endif
{ "[286 ISA] Samsung SPC-4200P", "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 127, machine_at_spc4200p_init, NULL },
{ "[286 ISA] Samsung SPC-4216P", "spc4216p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 127, machine_at_spc4216p_init, NULL },
{ "[286 ISA] Toshiba T3100e", "t3100e", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED | MACHINE_HDC, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
{ "[286 ISA] Trigem 286M", "tg286m", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
{ "[286 MCA] IBM PS/2 model 50", "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[386SX ISA] AMA-932J", "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
#if defined(DEV_BRANCH) && defined(USE_AMI386SX)
{ "[386SX ISA] AMI Unknown 386SX", "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
#endif
{ "[386SX ISA] Amstrad MegaPC", "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386SX ISA] DTK 386SX clone", "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[386SX ISA] IBM PS/1 model 2121", "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] KMX-C-02", "kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
{ "[386DX ISA] AMI 386DX clone", "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] Award 386DX clone", "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_MR495)
{ "[386DX ISA] MR 386DX clone", "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 1, 14, 1, 127, machine_at_portableiii386_init, NULL },
#endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL },
{ "[386DX MCA] IBM PS/2 model 80", "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
{ "[486 ISA] AMI 486 clone", "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[486 ISA] AMI ALi 1429", "ali1429", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ali1429_init, NULL },
{ "[486 ISA] AMI SiS 471", "ami471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_ami471_init, NULL },
{ "[486 ISA] AMI WinBIOS 486", "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_winbios1429_init, NULL },
{ "[486 ISA] AMI WinBIOS SiS 471", "win471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_win471_init, NULL },
{ "[486 ISA] Award 486 clone", "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_dtk486_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PS1M2133)
{ "[486 ISA] IBM PS/1 model 2133", "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI, 1, 64, 1, 127, machine_ps1_m2133_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_MR495)
{ "[486 ISA] MR 486 clone", "mr486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
#endif
{ "[486 ISA] Packard Bell PB410A", "pb410a", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 64, 1, 127, machine_at_pb410a_init, NULL },
{ "[486 ISA] Phoenix SiS 471", "px471", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
{ "[486 MCA] IBM PS/2 model 70 (type 4)", "ibmps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type4_init, NULL },
#endif
{ "[486 PCI] Intel Classic/PCI", "alfredo", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_alfredo_init, NULL },
{ "[486 PCI] Rise Computer R418", "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL },
{ "[Socket 4 LX] Intel Premiere/PCI", "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[Socket 4 LX] Micro Star 586MC1", "586mc1", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
{ "[Socket 5 NX] Intel Premiere/PCI II", "plato", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[Socket 5 NX] Gigabyte GA-586IP", "430nx", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_430nx_init, NULL },
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
{ "[Socket 5 FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_vectra54_init, NULL },
#endif
{ "[Socket 5 FX] Intel Advanced/ZP", "zappa", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_zappa_init, NULL },
{ "[Socket 5 FX] PC Partner MB500N", "mb500n", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_mb500n_init, NULL },
{ "[Socket 5 FX] President Award 430FX PCI","president", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL },
{ "[Socket 7 FX] Intel Advanced/ATX", "thor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_MRTHOR)
{ "[Socket 7 FX] MR Intel Advanced/ATX", "mrthor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_mrthor_init, NULL },
#endif
{ "[Socket 7 FX] Intel Advanced/EV", "endeavor", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[Socket 7 FX] Packard Bell PB640", "pb640", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[Socket 7 HX] Acer M3a", "acerm3a", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[Socket 7 HX] Acer V35n", "acerv35n", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerv35n_init, NULL },
{ "[Socket 7 HX] AOpen AP53", "ap53", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_p55t2p4_init, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_TC430HX)
{ "[Socket 7 HX] TC430HX", "tc430hx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_tc430hx_init, NULL },
#endif
{ "[Socket 7 VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_I686)
{ "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
#endif
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
};
int
machine_count(void)
{
return((sizeof(machines) / sizeof(machine)) - 1);
}
char *
machine_getname(void)
{
return((char *)machines[machine].name);
}
char *
machine_getname_ex(int m)
{
return((char *)machines[m].name);
}
const device_t *
machine_getdevice(int m)
{
if (machines[m].get_device)
return(machines[m].get_device());
return(NULL);
}
char *
machine_get_internal_name(void)
{
return((char *)machines[machine].internal_name);
}
char *
machine_get_internal_name_ex(int m)
{
return((char *)machines[m].internal_name);
}
int
machine_get_nvrmask(int m)
{
return(machines[m].nvrmask);
}
int
machine_get_machine_from_internal_name(char *s)
{
int c = 0;
while (machines[c].init != NULL) {
if (!strcmp(machines[c].internal_name, (const char *)s))
return(c);
c++;
}
return(0);
}