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Overhauled DMA bus master reads and writes and cleaned up the AMD PCnet code a bit (network queue implementation is pending).

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OBattler
2020-04-28 01:01:39 +02:00
parent bc3a2a3b20
commit 59822c6c0e
13 changed files with 361 additions and 232 deletions
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13
src/cpu_common/386_common.c
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@@ -1044,16 +1044,12 @@ enter_smm(int in_hlt)
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_save_state_p6(saved_state, in_hlt);
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
mem_writel_phys(smram_state, saved_state[n]);
}
cr0 &= ~0x8000000d;
cpu_state.flags = 2;
cpu_state.eflags = 0;
cr4 = 0;
dr[7] = 0x400;
cpu_state.pc = 0x8000;
@@ -1089,6 +1085,11 @@ enter_smm(int in_hlt)
cpu_state.op32 = use32;
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
writememl(0, smram_state, saved_state[n]);
}
nmi_mask = 0;
if (smi_latched) {
@@ -1146,7 +1147,7 @@ leave_smm(void)
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
saved_state[n] = mem_readl_phys(smram_state);
saved_state[n] = readmeml(0, smram_state);
x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
}