UMC HB4 shadow RAM overhaul and SMRAM fixes, slight changes to SiS 85c4xx, a fix for SiS 85c50x, fixed SMBASE on 486 (it should *NOT* zero the most significant 8 bits!), various improvements to mem.c (eg. mem_invalidate_range() is now faster), fixed resetting PCI on soft reset, and made the KBC soft reset again.
This commit is contained in:
OBattler
@@ -22,6 +22,7 @@
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include "x86.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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@@ -39,6 +40,7 @@ typedef struct
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reg_base, reg_last,
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reg_00, is_471,
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regs[39], scratch[2];
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uint32_t mem_state[8];
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smram_t *smram;
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port_92_t *port_92;
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} sis_85c4xx_t;
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@@ -47,7 +49,7 @@ typedef struct
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static void
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sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
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{
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uint32_t base;
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uint32_t base, n = 0;
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uint32_t i, shflags = 0;
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uint32_t readext, writeext;
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uint8_t romcs = 0xc0, cur_romcs;
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@@ -73,12 +75,25 @@ sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
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shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
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shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : readext;
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shflags |= (dev->regs[0x02] & 0x40) ? writeext : MEM_WRITE_INTERNAL;
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mem_set_mem_state(base, 0x8000, shflags);
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} else
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mem_set_mem_state(base, 0x8000, readext | writeext);
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if (dev->mem_state[i] != shflags) {
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n++;
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mem_set_mem_state(base, 0x8000, shflags);
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if ((base >= 0xf0000) && (dev->mem_state[i] & MEM_READ_INTERNAL) && !(shflags & MEM_READ_INTERNAL))
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mem_invalidate_range(base, base + 0x7fff);
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dev->mem_state[i] = shflags;
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}
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} else {
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shflags = readext | writeext;
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if (dev->mem_state[i] != shflags) {
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n++;
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mem_set_mem_state(base, 0x8000, shflags);
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dev->mem_state[i] = shflags;
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}
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}
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}
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flushmmucache_nopc();
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if (n > 0)
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flushmmucache_nopc();
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}
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@@ -141,7 +156,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
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case 0x02: case 0x03:
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case 0x08:
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sis_85c4xx_recalcmapping(dev);
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if (valxor)
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sis_85c4xx_recalcmapping(dev);
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break;
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case 0x0b:
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@@ -237,6 +253,69 @@ sis_85c4xx_in(uint16_t port, void *priv)
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}
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static void
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sis_85c4xx_reset(void *priv)
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{
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sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
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int mem_size_mb = mem_size >> 10;
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static uint8_t ram_4xx[64] = { 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x00, 0x0b, 0x00, 0x00, 0x00,
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0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09, 0x04, 0x04, 0x05, 0x05, 0x0b, 0x0b, 0x0b, 0x0b,
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0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e,
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0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
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0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e };
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memset(dev->regs, 0x00, sizeof(dev->regs));
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if (cpu_s->rspeed < 25000000)
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dev->regs[0x08] = 0x80;
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if (dev->is_471) {
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dev->regs[0x09] = 0x40;
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if (mem_size_mb >= 64) {
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if ((mem_size_mb >= 65) && (mem_size_mb < 68))
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dev->regs[0x09] |= 0x22;
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else
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dev->regs[0x09] |= 0x24;
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} else
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dev->regs[0x09] |= ram_471[mem_size_mb];
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dev->regs[0x11] = 0x09;
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dev->regs[0x12] = 0xff;
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dev->regs[0x1f] = 0x20; /* Video access enabled. */
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dev->regs[0x23] = 0xf0;
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dev->regs[0x26] = 0x01;
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smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1);
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port_92_remove(dev->port_92);
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mem_remap_top(256);
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soft_reset_mask = 0;
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} else {
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/* Bits 6 and 7 must be clear on the SiS 40x. */
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if (dev->reg_base == 0x60)
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dev->reg_00 = 0x24;
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if (mem_size_mb == 64)
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dev->regs[0x00] = 0x1f;
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else if (mem_size_mb < 64)
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dev->regs[0x00] = ram_4xx[mem_size_mb];
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dev->regs[0x11] = 0x01;
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}
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dev->scratch[0] = dev->scratch[1] = 0xff;
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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sis_85c4xx_recalcmapping(dev);
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}
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static void
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sis_85c4xx_close(void *priv)
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{
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@@ -252,8 +331,6 @@ sis_85c4xx_close(void *priv)
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static void *
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sis_85c4xx_init(const device_t *info)
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{
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int mem_size_mb;
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sis_85c4xx_t *dev = (sis_85c4xx_t *) malloc(sizeof(sis_85c4xx_t));
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memset(dev, 0, sizeof(sis_85c4xx_t));
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@@ -261,161 +338,22 @@ sis_85c4xx_init(const device_t *info)
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dev->reg_base = info->local & 0xff;
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mem_size_mb = mem_size >> 10;
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if (cpu_s->rspeed < 25000000)
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dev->regs[0x08] = 0x80;
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if (dev->is_471) {
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dev->reg_last = dev->reg_base + 0x76;
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dev->regs[0x09] = 0x40;
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switch (mem_size_mb) {
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case 0: case 1:
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dev->regs[0x09] |= 0x00;
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break;
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case 2: case 3:
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dev->regs[0x09] |= 0x01;
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break;
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case 4:
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dev->regs[0x09] |= 0x02;
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break;
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case 5:
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dev->regs[0x09] |= 0x20;
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break;
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case 6: case 7:
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dev->regs[0x09] |= 0x09;
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break;
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case 8: case 9:
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dev->regs[0x09] |= 0x04;
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break;
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case 10: case 11:
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dev->regs[0x09] |= 0x05;
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break;
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case 12: case 13: case 14: case 15:
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dev->regs[0x09] |= 0x0b;
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break;
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case 16:
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dev->regs[0x09] |= 0x13;
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break;
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case 17:
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dev->regs[0x09] |= 0x21;
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break;
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case 18: case 19:
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dev->regs[0x09] |= 0x06;
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break;
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case 20: case 21: case 22: case 23:
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dev->regs[0x09] |= 0x0d;
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break;
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case 24: case 25: case 26: case 27:
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case 28: case 29: case 30: case 31:
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dev->regs[0x09] |= 0x0e;
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break;
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case 32: case 33: case 34: case 35:
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dev->regs[0x09] |= 0x1b;
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break;
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case 36: case 37: case 38: case 39:
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dev->regs[0x09] |= 0x0f;
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break;
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case 40: case 41: case 42: case 43:
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case 44: case 45: case 46: case 47:
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dev->regs[0x09] |= 0x17;
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break;
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case 48:
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dev->regs[0x09] |= 0x1e;
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break;
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default:
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if (mem_size_mb < 64)
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dev->regs[0x09] |= 0x1e;
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else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
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dev->regs[0x09] |= 0x22;
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else
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dev->regs[0x09] |= 0x24;
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break;
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}
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dev->regs[0x11] = 0x09;
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dev->regs[0x12] = 0xff;
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dev->regs[0x1f] = 0x20; /* Video access enabled. */
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dev->regs[0x23] = 0xf0;
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dev->regs[0x26] = 0x01;
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dev->smram = smram_add();
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smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1);
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dev->port_92 = device_add(&port_92_device);
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port_92_remove(dev->port_92);
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} else {
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} else
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dev->reg_last = dev->reg_base + 0x11;
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/* Bits 6 and 7 must be clear on the SiS 40x. */
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if (dev->reg_base == 0x60)
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dev->reg_00 = 0x24;
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switch (mem_size_mb) {
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case 1:
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default:
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dev->regs[0x00] = 0x00;
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break;
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case 2:
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dev->regs[0x00] = 0x01;
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break;
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case 4:
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dev->regs[0x00] = 0x02;
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break;
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case 6:
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dev->regs[0x00] = 0x03;
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break;
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case 8:
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dev->regs[0x00] = 0x04;
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break;
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case 10:
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dev->regs[0x00] = 0x05;
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break;
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case 12:
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dev->regs[0x00] = 0x0b;
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break;
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case 16:
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dev->regs[0x00] = 0x19;
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break;
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case 18:
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dev->regs[0x00] = 0x06;
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break;
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case 20:
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dev->regs[0x00] = 0x14;
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break;
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case 24:
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dev->regs[0x00] = 0x15;
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break;
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case 32:
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dev->regs[0x00] = 0x1b;
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break;
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case 36:
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dev->regs[0x00] = 0x16;
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break;
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case 40:
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dev->regs[0x00] = 0x17;
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break;
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case 48:
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dev->regs[0x00] = 0x1e;
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break;
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case 64:
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dev->regs[0x00] = 0x1f;
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break;
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}
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dev->regs[0x11] = 0x01;
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}
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io_sethandler(0x0022, 0x0002,
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sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
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dev->scratch[0] = dev->scratch[1] = 0xff;
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io_sethandler(0x00e1, 0x0002,
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sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
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sis_85c4xx_recalcmapping(dev);
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sis_85c4xx_reset(dev);
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return dev;
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}
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@@ -425,7 +363,7 @@ const device_t sis_85c401_device = {
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"SiS 85c401/85c402",
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0,
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0x060,
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sis_85c4xx_init, sis_85c4xx_close, NULL,
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sis_85c4xx_init, sis_85c4xx_close, sis_85c4xx_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@@ -434,7 +372,7 @@ const device_t sis_85c460_device = {
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"SiS 85c460",
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0,
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0x050,
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sis_85c4xx_init, sis_85c4xx_close, NULL,
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sis_85c4xx_init, sis_85c4xx_close, sis_85c4xx_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@@ -444,7 +382,7 @@ const device_t sis_85c461_device = {
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"SiS 85c461",
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0,
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0x050,
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sis_85c4xx_init, sis_85c4xx_close, NULL,
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sis_85c4xx_init, sis_85c4xx_close, sis_85c4xx_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@@ -453,7 +391,7 @@ const device_t sis_85c471_device = {
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"SiS 85c407/85c471",
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0,
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0x150,
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sis_85c4xx_init, sis_85c4xx_close, NULL,
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sis_85c4xx_init, sis_85c4xx_close, sis_85c4xx_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@@ -89,7 +89,7 @@ sis_85c50x_shadow_recalc(sis_85c50x_t *dev)
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mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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}
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flushmmucache();
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flushmmucache_nopc();
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}
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@@ -291,6 +291,9 @@ umc_8886_reset(void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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memset(dev->pci_conf_sb[0], 0x00, sizeof(dev->pci_conf_sb[0]));
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memset(dev->pci_conf_sb[1], 0x00, sizeof(dev->pci_conf_sb[1]));
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dev->pci_conf_sb[0][0] = 0x60; /* UMC */
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dev->pci_conf_sb[0][1] = 0x10;
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@@ -336,6 +339,9 @@ umc_8886_reset(void *priv)
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|
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for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
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pci_set_irq_routing(i, PCI_IRQ_DISABLED);
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|
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cpu_set_isa_pci_div(3);
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cpu_set_pci_speed(cpu_busspeed / 2);
|
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}
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||||
|
||||
|
||||
|
||||
@@ -97,6 +97,7 @@
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||||
#define HAVE_STDARG_H
|
||||
#include <86box/86box.h>
|
||||
#include "cpu.h"
|
||||
#include "x86.h"
|
||||
#include <86box/timer.h>
|
||||
#include <86box/io.h>
|
||||
#include <86box/device.h>
|
||||
@@ -106,6 +107,18 @@
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||||
#include <86box/port_92.h>
|
||||
#include <86box/smram.h>
|
||||
|
||||
#ifdef USE_DYNAREC
|
||||
# include "codegen_public.h"
|
||||
#else
|
||||
#ifdef USE_NEW_DYNAREC
|
||||
# define PAGE_MASK_SHIFT 6
|
||||
#else
|
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# define PAGE_MASK_INDEX_MASK 3
|
||||
# define PAGE_MASK_INDEX_SHIFT 10
|
||||
# define PAGE_MASK_SHIFT 4
|
||||
#endif
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||||
# define PAGE_MASK_MASK 63
|
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#endif
|
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#include <86box/chipset.h>
|
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|
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|
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@@ -131,34 +144,108 @@ hb4_log(const char *fmt, ...)
|
||||
|
||||
typedef struct hb4_t
|
||||
{
|
||||
uint8_t pci_conf[128]; /* PCI Registers */
|
||||
smram_t *smram; /* SMRAM Handler */
|
||||
uint8_t shadow,
|
||||
shadow_read, shadow_write,
|
||||
pci_conf[256]; /* PCI Registers */
|
||||
int mem_state[9];
|
||||
smram_t *smram[2]; /* SMRAM Handlers */
|
||||
} hb4_t;
|
||||
|
||||
|
||||
static int shadow_bios[4] = { (MEM_READ_EXTANY | MEM_WRITE_INTERNAL), (MEM_READ_EXTANY | MEM_WRITE_EXTANY),
|
||||
(MEM_READ_INTERNAL | MEM_WRITE_INTERNAL), (MEM_READ_INTERNAL | MEM_WRITE_EXTANY) };
|
||||
static int shadow_read[2] = { MEM_READ_EXTANY, MEM_READ_INTERNAL };
|
||||
static int shadow_write[2] = { MEM_WRITE_INTERNAL, MEM_WRITE_EXTANY };
|
||||
|
||||
|
||||
int
|
||||
hb4_shadow_bios_high(hb4_t *dev)
|
||||
{
|
||||
int state;
|
||||
|
||||
state = shadow_bios[dev->pci_conf[0x55] >> 6];
|
||||
|
||||
if (state != dev->mem_state[8]) {
|
||||
mem_set_mem_state_both(0xf0000, 0x10000, state);
|
||||
if ((dev->mem_state[8] & MEM_READ_INTERNAL) && !(state & MEM_READ_INTERNAL))
|
||||
mem_invalidate_range(0xf0000, 0xfffff);
|
||||
dev->mem_state[8] = state;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
hb4_shadow_bios_low(hb4_t *dev)
|
||||
{
|
||||
int state;
|
||||
|
||||
state = shadow_bios[(dev->pci_conf[0x55] >> 6) & (dev->shadow | 0x01)];
|
||||
|
||||
if (state != dev->mem_state[7]) {
|
||||
mem_set_mem_state_both(0xe0000, 0x10000, state);
|
||||
dev->mem_state[7] = state;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
hb4_shadow_main(hb4_t *dev)
|
||||
{
|
||||
int i, state;
|
||||
int n = 0;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> (i + 2)) & 0x01)] |
|
||||
shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
|
||||
|
||||
if (state != dev->mem_state[i + 1]) {
|
||||
n++;
|
||||
mem_set_mem_state_both(0xc8000 + (i << 14), 0x4000, state);
|
||||
dev->mem_state[i + 1] = state;
|
||||
}
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
hb4_shadow_video(hb4_t *dev)
|
||||
{
|
||||
int state;
|
||||
|
||||
state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> 1) & 0x01)] |
|
||||
shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
|
||||
|
||||
if (state != dev->mem_state[0]) {
|
||||
mem_set_mem_state_both(0xc0000, 0x8000, state);
|
||||
dev->mem_state[0] = state;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hb4_shadow(hb4_t *dev)
|
||||
{
|
||||
int state, i;
|
||||
int n = 0;
|
||||
pclog("SHADOW: %02X%02X\n", dev->pci_conf[0x55], dev->pci_conf[0x54]);
|
||||
|
||||
mem_set_mem_state_both(0xe0000, 0x20000, ((dev->pci_conf[0x55] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) |
|
||||
((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL));
|
||||
n = hb4_shadow_bios_high(dev);
|
||||
n += hb4_shadow_bios_low(dev);
|
||||
n += hb4_shadow_main(dev);
|
||||
n += hb4_shadow_video(dev);
|
||||
|
||||
if (dev->pci_conf[0x54] & 1) {
|
||||
state = (dev->pci_conf[0x54] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
|
||||
state |= (dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
|
||||
|
||||
mem_set_mem_state_both(0xc0000, 0x8000, state);
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
state = (dev->pci_conf[0x54] & (1 << (i + 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
|
||||
state |= (dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
|
||||
|
||||
mem_set_mem_state_both(0xc8000 + (i << 4), 0x4000, state);
|
||||
}
|
||||
}
|
||||
|
||||
flushmmucache_nopc();
|
||||
if (n > 0)
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
|
||||
|
||||
@@ -169,7 +256,9 @@ hb4_smram(hb4_t *dev)
|
||||
|
||||
/* Bit 0, if set, enables SMRAM access outside SMM. SMRAM appears to be always enabled
|
||||
in SMM, and is always set to A0000-BFFFF. */
|
||||
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
|
||||
smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
|
||||
/* There's a mirror of the SMRAM at 0E0A0000, mapped to A0000. */
|
||||
smram_enable(dev->smram[1], 0x0e0a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
|
||||
|
||||
/* Bit 5 seems to set data to go to PCI and code to DRAM. The Samsung SPC7700P-LW uses
|
||||
this. */
|
||||
@@ -185,6 +274,8 @@ static void
|
||||
hb4_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
hb4_t *dev = (hb4_t *)priv;
|
||||
uint8_t old;
|
||||
|
||||
hb4_log("UM8881: dev->regs[%02x] = %02x POST: %02x \n", addr, val, inb(0x80));
|
||||
|
||||
switch (addr) {
|
||||
@@ -207,11 +298,23 @@ hb4_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
|
||||
case 0x51: case 0x52:
|
||||
case 0x53:
|
||||
dev->pci_conf[addr] = val;
|
||||
break;
|
||||
|
||||
case 0x54: case 0x55:
|
||||
case 0x53:
|
||||
old = dev->pci_conf[addr];
|
||||
dev->pci_conf[addr] = val;
|
||||
pclog("HB53: %02X\n", val);
|
||||
break;
|
||||
|
||||
case 0x55:
|
||||
dev->shadow_read = (val & 0x80);
|
||||
dev->shadow_write = (val & 0x40);
|
||||
dev->pci_conf[addr] = val;
|
||||
hb4_shadow(dev);
|
||||
break;
|
||||
case 0x54:
|
||||
dev->shadow = (val & 0x01) << 1;
|
||||
dev->pci_conf[addr] = val;
|
||||
hb4_shadow(dev);
|
||||
break;
|
||||
@@ -236,8 +339,12 @@ static uint8_t
|
||||
hb4_read(int func, int addr, void *priv)
|
||||
{
|
||||
hb4_t *dev = (hb4_t *)priv;
|
||||
uint8_t ret = 0xff;
|
||||
|
||||
return dev->pci_conf[addr];
|
||||
if (func == 0)
|
||||
ret = dev->pci_conf[addr];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -245,6 +352,7 @@ static void
|
||||
hb4_reset(void *priv)
|
||||
{
|
||||
hb4_t *dev = (hb4_t *)priv;
|
||||
memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
|
||||
|
||||
dev->pci_conf[0] = 0x60; /* UMC */
|
||||
dev->pci_conf[1] = 0x10;
|
||||
@@ -269,7 +377,12 @@ hb4_reset(void *priv)
|
||||
|
||||
hb4_write(0, 0x54, 0x00, dev);
|
||||
hb4_write(0, 0x55, 0x00, dev);
|
||||
hb4_write(0, 0x60, 0x20, dev);
|
||||
hb4_write(0, 0x60, 0x80, dev);
|
||||
|
||||
cpu_cache_ext_enabled = 0;
|
||||
cpu_update_waitstates();
|
||||
|
||||
memset(dev->mem_state, 0x00, sizeof(dev->mem_state));
|
||||
}
|
||||
|
||||
|
||||
@@ -294,7 +407,8 @@ hb4_init(const device_t *info)
|
||||
device_add(&port_92_pci_device);
|
||||
|
||||
/* SMRAM */
|
||||
dev->smram = smram_add();
|
||||
dev->smram[0] = smram_add();
|
||||
dev->smram[1] = smram_add();
|
||||
|
||||
hb4_reset(dev);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user