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Clang-formatting in src/cpu

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This commit is contained in:
Jasmine Iwanek
2023-08-11 13:00:04 -04:00
parent be79ea78c7
commit 5cd18f3fbb
43 changed files with 1705 additions and 1622 deletions
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179
src/cpu/808x.c
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@@ -76,34 +76,34 @@ static int in_rep = 0;
static int repeating = 0;
static int rep_c_flag = 0;
static int oldc;
static int clear_lock = 0;
static int refresh = 0;
static int clear_lock = 0;
static int refresh = 0;
static int cycdiff;
static int access_code = 0;
static int hlda = 0;
static int not_ready = 0;
static int bus_request_type = 0;
static int pic_data = -1;
static int last_was_code = 0;
static uint16_t mem_data = 0;
static uint32_t mem_seg = 0;
static uint16_t mem_addr = 0;
static int schedule_fetch = 1;
static int pasv = 0;
static int access_code = 0;
static int hlda = 0;
static int not_ready = 0;
static int bus_request_type = 0;
static int pic_data = -1;
static int last_was_code = 0;
static uint16_t mem_data = 0;
static uint32_t mem_seg = 0;
static uint16_t mem_addr = 0;
static int schedule_fetch = 1;
static int pasv = 0;
#define BUS_OUT 1
#define BUS_HIGH 2
#define BUS_WIDE 4
#define BUS_CODE 8
#define BUS_IO 16
#define BUS_MEM 32
#define BUS_PIC 64
#define BUS_OUT 1
#define BUS_HIGH 2
#define BUS_WIDE 4
#define BUS_CODE 8
#define BUS_IO 16
#define BUS_MEM 32
#define BUS_PIC 64
#define BUS_ACCESS_TYPE (BUS_CODE | BUS_IO | BUS_MEM | BUS_PIC)
#define BUS_CYCLE (biu_cycles & 3)
#define BUS_CYCLE_T1 biu_cycles = 0
#define BUS_CYCLE_NEXT biu_cycles = (biu_cycles + 1) & 3
#define BUS_CYCLE (biu_cycles & 3)
#define BUS_CYCLE_T1 biu_cycles = 0
#define BUS_CYCLE_NEXT biu_cycles = (biu_cycles + 1) & 3
enum {
BUS_T1 = 0,
@@ -221,7 +221,7 @@ clock_end(void)
static void
process_timers(void)
{
{
clock_end();
clock_start();
}
@@ -258,7 +258,7 @@ bus_outw(uint16_t port, uint16_t val)
static uint8_t
bus_inb(uint16_t port)
{
int old_cycles = cycles;
int old_cycles = cycles;
uint8_t ret;
cycles--;
@@ -271,7 +271,7 @@ bus_inb(uint16_t port)
static uint16_t
bus_inw(uint16_t port)
{
int old_cycles = cycles;
int old_cycles = cycles;
uint16_t ret;
cycles--;
@@ -377,7 +377,7 @@ run_bus_cycle(int io_type)
not_ready = 0;
}
switch(BUS_CYCLE) {
switch (BUS_CYCLE) {
case BUS_T1:
access_code = !!(io_type & BUS_CODE);
break;
@@ -394,7 +394,7 @@ run_bus_cycle(int io_type)
bus_do_mem(io_type);
break;
case BUS_PIC:
pic_data = pic_irq_ack();
pic_data = pic_irq_ack();
last_was_code = 0;
break;
default:
@@ -455,17 +455,17 @@ cycles_biu(int bus, int init)
switch (BUS_CYCLE) {
case BUS_T1:
case BUS_T2:
BUS_CYCLE_T1; /* Simply abort the prefetch before actual scheduling, no penalty. */
BUS_CYCLE_T1; /* Simply abort the prefetch before actual scheduling, no penalty. */
break;
case BUS_T3:
case BUS_T4:
cycles_idle(5 - BUS_CYCLE); /* Leftover BIU cycles + 2 idle cycles. */
BUS_CYCLE_T1; /* Abort the prefetch. */
cycles_idle(5 - BUS_CYCLE); /* Leftover BIU cycles + 2 idle cycles. */
BUS_CYCLE_T1; /* Abort the prefetch. */
break;
}
schedule_fetch = 0;
access_code = 0;
access_code = 0;
}
}
@@ -570,7 +570,7 @@ cpu_io(int bits, int out, uint16_t port)
} else {
bus_request_type = BUS_IO | BUS_OUT;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_IO | BUS_OUT | BUS_HIGH;
wait(4, 1);
}
@@ -586,7 +586,7 @@ cpu_io(int bits, int out, uint16_t port)
} else {
bus_request_type = BUS_IO;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_IO | BUS_HIGH;
wait(4, 1);
}
@@ -609,11 +609,11 @@ readmemb(uint32_t s, uint16_t a)
bus_init();
#endif
mem_seg = s;
mem_addr = a;
mem_seg = s;
mem_addr = a;
bus_request_type = BUS_MEM;
wait(4, 1);
ret = mem_data & 0xff;
ret = mem_data & 0xff;
bus_request_type = 0;
return ret;
@@ -643,7 +643,7 @@ readmemw(uint32_t s, uint16_t a)
bus_init();
#endif
mem_seg = s;
mem_seg = s;
mem_addr = a;
if (is8086 && !(a & 1)) {
bus_request_type = BUS_MEM | BUS_WIDE;
@@ -651,11 +651,11 @@ readmemw(uint32_t s, uint16_t a)
} else {
bus_request_type = BUS_MEM | BUS_HIGH;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_MEM;
wait(4, 1);
}
ret = mem_data;
ret = mem_data;
bus_request_type = 0;
return ret;
@@ -716,9 +716,9 @@ writememb(uint32_t s, uint32_t a, uint8_t v)
bus_init();
#endif
mem_seg = s;
mem_addr = a;
mem_data = v;
mem_seg = s;
mem_addr = a;
mem_data = v;
bus_request_type = BUS_MEM | BUS_OUT;
wait(4, 1);
bus_request_type = 0;
@@ -737,7 +737,7 @@ writememw(uint32_t s, uint32_t a, uint16_t v)
bus_init();
#endif
mem_seg = s;
mem_seg = s;
mem_addr = a;
mem_data = v;
if (is8086 && !(a & 1)) {
@@ -746,7 +746,7 @@ writememw(uint32_t s, uint32_t a, uint16_t v)
} else {
bus_request_type = BUS_MEM | BUS_OUT | BUS_HIGH;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_MEM | BUS_OUT;
wait(4, 1);
}
@@ -791,13 +791,13 @@ pfq_write(void)
free in the queue. */
tempw = readmemwf(pfq_ip);
*(uint16_t *) &(pfq[pfq_pos]) = tempw;
pfq_ip = (pfq_ip + 2) & 0xffff;
pfq_ip = (pfq_ip + 2) & 0xffff;
pfq_pos += 2;
} else if (!fetch_word && (pfq_pos < pfq_size)) {
/* The 8088 fetches 1 byte at a time, and only if there's at least 1 byte
free in the queue. */
pfq[pfq_pos] = readmembf(pfq_ip);
pfq_ip = (pfq_ip + 1) & 0xffff;
pfq_ip = (pfq_ip + 1) & 0xffff;
pfq_pos++;
}
@@ -890,8 +890,8 @@ pfq_add(void)
static void
pfq_clear(void)
{
pfq_pos = 0;
prefetching = 0;
pfq_pos = 0;
prefetching = 0;
schedule_fetch = 0;
BUS_CYCLE_T1;
@@ -900,8 +900,8 @@ pfq_clear(void)
static void
pfq_suspend(void)
{
pfq_clear();
cycles_idle(3);
pfq_clear();
cycles_idle(3);
}
static void
@@ -955,20 +955,20 @@ reset_808x(int hard)
schedule_fetch = 1;
pasv = 0;
cpu_alu_op = 0;
cpu_alu_op = 0;
use_custom_nmi_vector = 0x00;
custom_nmi_vector = 0x00000000;
access_code = 0;
hlda = 0;
not_ready = 0;
bus_request_type = 0;
pic_data = -1;
last_was_code = 0;
mem_data = 0;
mem_seg = 0;
mem_addr = 0;
access_code = 0;
hlda = 0;
not_ready = 0;
bus_request_type = 0;
pic_data = -1;
last_was_code = 0;
mem_data = 0;
mem_seg = 0;
mem_addr = 0;
}
static void
@@ -976,7 +976,7 @@ set_ip(uint16_t new_ip)
{
pfq_ip = cpu_state.pc = new_ip;
prefetching = 1;
schedule_fetch = prefetching && (pfq_pos < pfq_size);
schedule_fetch = prefetching && (pfq_pos < pfq_size);
}
/* Memory refresh read - called by reads and writes on DMA channel 0. */
@@ -1025,16 +1025,17 @@ do_mod_rm(void)
easeg = ovr_seg ? *ovr_seg : ds;
wait(2, 0);
return;
} else switch (cpu_rm) {
case 0:
case 3:
wait(2, 0);
break;
case 1:
case 2:
wait(3, 0);
break;
}
} else
switch (cpu_rm) {
case 0:
case 3:
wait(2, 0);
break;
case 1:
case 2:
wait(3, 0);
break;
}
cpu_state.eaaddr = (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
easeg = ovr_seg ? *ovr_seg : *mod1seg[cpu_rm];
switch (rmdat & 0xc0) {
@@ -1220,11 +1221,11 @@ interrupt(uint16_t addr)
addr <<= 2;
cpu_state.eaaddr = addr;
old_cs = CS;
new_ip = readmemw(0, cpu_state.eaaddr);
new_ip = readmemw(0, cpu_state.eaaddr);
wait(1, 0);
cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff;
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
pfq_clear();
ovr_seg = NULL;
wait(2, 0);
@@ -1296,7 +1297,7 @@ bus_pic_ack(void)
{
int old_in_lock = in_lock;
in_lock = 1;
in_lock = 1;
bus_request_type = BUS_PIC;
wait(4, 1);
in_lock = old_in_lock;
@@ -1376,7 +1377,7 @@ rep_interrupt(void)
return 0;
}
completed = 1;
CX = tmpc;
CX = tmpc;
pfq_clear();
if (is_nec && (ovr_seg != NULL))
set_ip(cpu_state.pc - 3);
@@ -2011,9 +2012,9 @@ execx86(int cycs)
#if 0
opcode = pfq_fetchb();
#endif
opcode = pfq_fetchb_common();
handled = 0;
oldc = cpu_state.flags & C_FLAG;
opcode = pfq_fetchb_common();
handled = 0;
oldc = cpu_state.flags & C_FLAG;
if (clear_lock) {
in_lock = 0;
clear_lock = 0;
@@ -2587,7 +2588,7 @@ execx86(int cycs)
break;
default:
opcode = orig_opcode;
opcode = orig_opcode;
cpu_state.pc = (cpu_state.pc - 1) & 0xffff;
break;
}
@@ -3165,7 +3166,7 @@ execx86(int cycs)
wait(2, 0);
cpu_state.eaaddr = DI;
cpu_data = readmem(es);
DI = string_increment(bits);
DI = string_increment(bits);
cpu_src = cpu_data;
cpu_dest = tmpa;
sub(bits);
@@ -3582,7 +3583,7 @@ execx86(int cycs)
case 0xE5:
bits = 8 << (opcode & 1);
wait(1, 0);
cpu_data = pfq_fetchb();
cpu_data = pfq_fetchb();
cpu_state.eaaddr = cpu_data;
wait(1, 0);
cpu_io(bits, 0, cpu_state.eaaddr);
@@ -3591,16 +3592,16 @@ execx86(int cycs)
case 0xE7:
bits = 8 << (opcode & 1);
wait(1, 0);
cpu_data = pfq_fetchb();
cpu_data = pfq_fetchb();
cpu_state.eaaddr = cpu_data;
cpu_data = (bits == 16) ? AX : AL;
cpu_data = (bits == 16) ? AX : AL;
wait(2, 0);
cpu_io(bits, 1, cpu_state.eaaddr);
break;
case 0xEC:
case 0xED:
bits = 8 << (opcode & 1);
cpu_data = DX;
bits = 8 << (opcode & 1);
cpu_data = DX;
cpu_state.eaaddr = cpu_data;
wait(1, 0);
cpu_io(bits, 0, cpu_state.eaaddr);
@@ -3609,9 +3610,9 @@ execx86(int cycs)
case 0xEF:
bits = 8 << (opcode & 1);
wait(2, 0);
cpu_data = DX;
cpu_data = DX;
cpu_state.eaaddr = cpu_data;
cpu_data = (bits == 16) ? AX : AL;
cpu_data = (bits == 16) ? AX : AL;
cpu_io(bits, 1, cpu_state.eaaddr);
wait(1, 0);
break;