Changes to logging - nothing (other than some parts of pc.c) uses the global pclog anymore (and logs will be almost empty (until the base set logging flags is agreed upon);
Fixes to various hard disk controllers; Added the Packard Bell PB640; Fixed the InPort mouse emulation - now it works correctly on Windows NT 3.1; Removed the status window and the associated variables; Completely removed the Green B 486 machine; Fixed the MDSI Genius; Fixed the single-sided 5.25" floppy drive; Ported a CPU-related commit from VARCem.
This commit is contained in:
OBattler
@@ -1,7 +1,9 @@
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include "../86box.h"
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#include "../cpu/cpu.h"
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#include "../cpu/x86.h"
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@@ -94,9 +96,30 @@ static struct
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static uint8_t ps2_cache[65536];
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static int ps2_cache_valid[65536/8];
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#ifdef ENABLE_PS2_MCA_LOG
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int ps2_mca_do_log = ENABLE_PS2_MCA_LOG;
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#endif
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static void
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ps2_mca_log(const char *format, ...)
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{
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#ifdef ENABLE_PS2_MCA_LOG
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va_list ap;
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if (ps2_mca_do_log) {
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va_start(ap, format);
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pclog_ex(format, ap);
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va_end(ap);
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}
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#endif
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}
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static uint8_t ps2_read_cache_ram(uint32_t addr, void *priv)
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{
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// pclog("ps2_read_cache_ram: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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ps2_mca_log("ps2_read_cache_ram: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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if (!ps2_cache_valid[addr >> 3])
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{
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ps2_cache_valid[addr >> 3] = 1;
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@@ -109,7 +132,7 @@ static uint8_t ps2_read_cache_ram(uint32_t addr, void *priv)
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}
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static uint16_t ps2_read_cache_ramw(uint32_t addr, void *priv)
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{
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// pclog("ps2_read_cache_ramw: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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ps2_mca_log("ps2_read_cache_ramw: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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if (!ps2_cache_valid[addr >> 3])
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{
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ps2_cache_valid[addr >> 3] = 1;
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@@ -122,7 +145,7 @@ static uint16_t ps2_read_cache_ramw(uint32_t addr, void *priv)
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}
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static uint32_t ps2_read_cache_raml(uint32_t addr, void *priv)
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{
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// pclog("ps2_read_cache_raml: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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ps2_mca_log("ps2_read_cache_raml: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS,cpu_state.pc);
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if (!ps2_cache_valid[addr >> 3])
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{
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ps2_cache_valid[addr >> 3] = 1;
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@@ -135,7 +158,7 @@ static uint32_t ps2_read_cache_raml(uint32_t addr, void *priv)
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}
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static void ps2_write_cache_ram(uint32_t addr, uint8_t val, void *priv)
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{
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// pclog("ps2_write_cache_ram: addr=%08x val=%02x %04x:%04x %i\n", addr, val, CS,cpu_state.pc, ins);
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ps2_mca_log("ps2_write_cache_ram: addr=%08x val=%02x %04x:%04x %i\n", addr, val, CS,cpu_state.pc, ins);
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ps2_cache[addr] = val;
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}
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@@ -408,10 +431,10 @@ static void model_55sx_write(uint16_t port, uint8_t val)
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case 0x104:
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ps2.memory_bank[ps2.option[3] & 7] &= ~0xf;
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ps2.memory_bank[ps2.option[3] & 7] |= (val & 0xf);
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/* pclog("Write memory bank %i %02x\n", ps2.option[3] & 7, val); */
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ps2_mca_log("Write memory bank %i %02x\n", ps2.option[3] & 7, val);
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break;
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case 0x105:
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/* pclog("Write POS3 %02x\n", val); */
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ps2_mca_log("Write POS3 %02x\n", val);
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ps2.option[3] = val;
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shadowbios = !(val & 0x10);
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shadowbios_write = val & 0x10;
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@@ -636,14 +659,14 @@ uint8_t ps2_mca_read(uint16_t port, void *p)
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break;
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}
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/* pclog("ps2_read: port=%04x temp=%02x\n", port, temp); */
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return temp;
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ps2_mca_log("ps2_read: port=%04x temp=%02x\n", port, temp);
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return temp;
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}
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static void ps2_mca_write(uint16_t port, uint8_t val, void *p)
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{
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/* pclog("ps2_write: port=%04x val=%02x %04x:%04x\n", port, val, CS,cpu_state.pc); */
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ps2_mca_log("ps2_write: port=%04x val=%02x %04x:%04x\n", port, val, CS,cpu_state.pc);
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switch (port)
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{
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@@ -893,18 +916,18 @@ static void mem_encoding_update()
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if (ps2.mem_regs[1] & 2) {
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mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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/* pclog("PS/2 Model 80-111: ROM space enabled\n"); */
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ps2_mca_log("PS/2 Model 80-111: ROM space enabled\n");
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} else {
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mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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/* pclog("PS/2 Model 80-111: ROM space disabled\n"); */
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ps2_mca_log("PS/2 Model 80-111: ROM space disabled\n");
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}
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if (ps2.mem_regs[1] & 4) {
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mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0x80000);
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/* pclog("PS/2 Model 80-111: 00080000- 0009FFFF disabled\n"); */
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ps2_mca_log("PS/2 Model 80-111: 00080000- 0009FFFF disabled\n");
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} else {
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mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0xa0000);
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/* pclog("PS/2 Model 80-111: 00080000- 0009FFFF enabled\n"); */
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ps2_mca_log("PS/2 Model 80-111: 00080000- 0009FFFF enabled\n");
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}
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if (!(ps2.mem_regs[1] & 8))
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@@ -920,10 +943,9 @@ static void mem_encoding_update()
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mem_mapping_set_exec(&ps2.split_mapping, &ram[ps2.split_phys]);
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mem_mapping_set_addr(&ps2.split_mapping, ps2.split_addr, ps2.split_size << 10);
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/* pclog("PS/2 Model 80-111: Split memory block enabled at %08X\n", ps2.split_addr); */
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} /* else {
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pclog("PS/2 Model 80-111: Split memory block disabled\n");
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} */
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ps2_mca_log("PS/2 Model 80-111: Split memory block enabled at %08X\n", ps2.split_addr);
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} else
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ps2_mca_log("PS/2 Model 80-111: Split memory block disabled\n");
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}
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static uint8_t mem_encoding_read(uint16_t addr, void *p)
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@@ -982,7 +1004,7 @@ static void mem_encoding_write_cached(uint16_t addr, uint8_t val, void *p)
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ps2.mem_regs[2] = (ps2.mem_regs[2] & 0x80) | (val & ~0x88);
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if (val & 2)
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{
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// pclog("Clear latch - %i\n", ps2.pending_cache_miss);
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ps2_mca_log("Clear latch - %i\n", ps2.pending_cache_miss);
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if (ps2.pending_cache_miss)
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ps2.mem_regs[2] |= 0x80;
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else
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@@ -1000,7 +1022,7 @@ static void mem_encoding_write_cached(uint16_t addr, uint8_t val, void *p)
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ram_mid_mapping.flags &= ~MEM_MAPPING_ROM;
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break;
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}
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// pclog("mem_encoding_write: addr=%02x val=%02x %04x:%04x %02x %02x\n", addr, val, CS,cpu_state.pc, ps2.mem_regs[1],ps2.mem_regs[2]);
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ps2_mca_log("mem_encoding_write: addr=%02x val=%02x %04x:%04x %02x %02x\n", addr, val, CS,cpu_state.pc, ps2.mem_regs[1],ps2.mem_regs[2]);
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mem_encoding_update();
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if ((ps2.mem_regs[1] & 0x10) && (ps2.mem_regs[2] & 0x21) == 0x20)
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{
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