diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 2f0c7cc39..d8bb5582e 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -1303,13 +1303,13 @@ static void regs[0x0d] = 0x20; /* According to information from FreeBSD 3.x source code: 0x00 = 486DX, 0x20 = 486SX, 0x40 = 486DX2 or 486DX4, 0x80 = Pentium OverDrive. */ - if (is486sx) + if (!(hasfpu) && (cpu_multi = 1)) regs[0x50] = 0x20; - else if (is486sx2) + else if (!(hasfpu) && (cpu_multi = 2)) regs[0x50] = 0x60; /* Guess based on the SX, DX, and DX2 values. */ - else if (is486dx) + else if (hasfpu && (cpu_multi = 1)) regs[0x50] = 0x00; - else if (is486dx2 || isdx4) + else if (hasfpu && (cpu_multi >= 2) && !(cpu_s->cpu_type == CPU_P24T)) regs[0x50] = 0x40; else regs[0x50] = 0x80; /* Pentium OverDrive. */ diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 191754d7f..c9c6692c5 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -108,9 +108,9 @@ int isa_cycles, cpu_override, cpu_effective, cpu_multi, cpu_16bitbus, cpu_64bitbus, cpu_busspeed, cpu_cyrix_alignment, CPUID, - is286, is386, is486 = 1, is486sx, is486dx, is486sx2, is486dx2, isdx4, + is286, is386, is486 = 1, cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc, - is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu, + is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu, timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml, timing_mm, timing_mml, timing_bt, timing_bnt, @@ -368,23 +368,17 @@ cpu_set(void) isibm486 = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL); is486 = (cpu_s->cpu_type >= CPU_RAPIDCAD); - is486sx = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_i486SX2); - is486sx2 = (cpu_s->cpu_type >= CPU_i486SX2) && (cpu_s->cpu_type < CPU_i486DX); - is486dx = (cpu_s->cpu_type >= CPU_i486DX) && (cpu_s->cpu_type < CPU_i486DX2); - is486dx2 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4); - isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP); - is_486_org = (cpu_s->cpu_type == CPU_i486SX) || (cpu_s->cpu_type == CPU_i486DX) || - (cpu_s->cpu_type == CPU_Am486SX) || (cpu_s->cpu_type == CPU_Am486DX); - is_am486 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type >= CPU_Am486SX) && (cpu_s->cpu_type <= CPU_Am5x86); + is_am486 = (cpu_s->cpu_type == CPU_ENH_Am486DX); + is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL); cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel"); cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix"); - /* The 486DX2 and iDX4 have the same SMM save state table layout as Pentiums, - and the WinChip datasheet claims those are Pentium-compatible as well. */ - is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) || - !strcmp(cpu_f->manufacturer, "IDT"); - is_k5 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_Am5x86); + /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums, + and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/ + is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) || + !strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL); + is_k5 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX); is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD"); /* The Samuel 2 datasheet claims it's Celeron-compatible. */ is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA"); @@ -758,21 +752,18 @@ cpu_set(void) timing_misaligned = 3; break; - case CPU_iDX4: + case CPU_i486SX_SLENH: + case CPU_i486DX_SLENH: cpu_features = CPU_FEATURE_CR4 | CPU_FEATURE_VME; cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_VME; /* FALLTHROUGH */ case CPU_RAPIDCAD: case CPU_i486SX: - case CPU_i486SX2: case CPU_i486DX: - case CPU_i486DX2: case CPU_Am486SX: - case CPU_Am486SX2: case CPU_Am486DX: - case CPU_Am486DX2: - case CPU_Am486DX4: - case CPU_Am5x86: + case CPU_Am486DXL: + case CPU_ENH_Am486DX: /*AMD timing identical to Intel*/ #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); @@ -815,8 +806,6 @@ cpu_set(void) case CPU_Cx486S: case CPU_Cx486DX: - case CPU_Cx486DX2: - case CPU_Cx486DX4: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f); #else @@ -1468,9 +1457,7 @@ void cpu_CPUID(void) { switch (cpu_s->cpu_type) { - case CPU_RAPIDCAD: - case CPU_i486DX: - case CPU_i486DX2: + case CPU_i486SX_SLENH: if (!EAX) { EAX = 0x00000001; EBX = 0x756e6547; @@ -1479,12 +1466,12 @@ cpu_CPUID(void) } else if (EAX == 1) { EAX = CPUID; EBX = ECX = 0; - EDX = CPUID_FPU; /*FPU*/ + EDX = CPUID_VME; } else EAX = EBX = ECX = EDX = 0; break; - case CPU_iDX4: + case CPU_i486DX_SLENH: if (!EAX) { EAX = 0x00000001; EBX = 0x756e6547; @@ -1497,25 +1484,8 @@ cpu_CPUID(void) } else EAX = EBX = ECX = EDX = 0; break; - - case CPU_Am486SX: - case CPU_Am486SX2: - if (!EAX) { - EAX = 1; - EBX = 0x68747541; - ECX = 0x444D4163; - EDX = 0x69746E65; - } else if (EAX == 1) { - EAX = CPUID; - EBX = ECX = EDX = 0; /*No FPU*/ - } else - EAX = EBX = ECX = EDX = 0; - break; - - case CPU_Am486DX: - case CPU_Am486DX2: - case CPU_Am486DX4: - case CPU_Am5x86: + + case CPU_ENH_Am486DX: if (!EAX) { EAX = 1; EBX = 0x68747541; diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index 2a9996a06..177712fa7 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -50,18 +50,13 @@ enum { CPU_i486SX, /* 486 class CPUs */ CPU_Am486SX, CPU_Cx486S, - CPU_i486SX2, - CPU_Am486SX2, CPU_i486DX, CPU_Am486DX, + CPU_Am486DXL, CPU_Cx486DX, - CPU_i486DX2, - CPU_Am486DX2, - CPU_Cx486DX2, - CPU_iDX4, - CPU_Am486DX4, - CPU_Cx486DX4, - CPU_Am5x86, + CPU_i486SX_SLENH, + CPU_i486DX_SLENH, + CPU_ENH_Am486DX, CPU_Cx5x86, CPU_P24T, CPU_WINCHIP, /* 586 class CPUs */ @@ -482,8 +477,8 @@ extern double fpu_multi; extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/ -extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; -extern int is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm; +extern int is8086, is286, is386, is486; +extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm; extern int hascache; extern int isibm486; extern int is_rapidcad; diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 407021c0f..cfba9080c 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -313,17 +313,29 @@ const cpu_family_t cpu_families[] = { {"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, {"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, {"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"33", CPU_i486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, {"", 0} } - }, { + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486SX (SL-Enhanced)", + .internal_name = "i486sx_slenh", + .cpus = (const CPU[]) { + {"25", CPU_i486SX_SLENH, fpus_486sx, 25000000, 1, 5000, 0x423, 0x423, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"33", CPU_i486SX_SLENH, fpus_486sx, 33333333, 1, 5000, 0x42a, 0x42a, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"", 0} + } + }, + { .package = CPU_PKG_SOCKET1, .manufacturer = "Intel", .name = "i486SX2", .internal_name = "i486sx2", .cpus = (const CPU[]) { - {"50", CPU_i486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66 (Q0569)", CPU_i486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + {"50", CPU_i486SX_SLENH, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66 (Q0569)", CPU_i486SX_SLENH, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, {"", 0} } }, { @@ -333,49 +345,62 @@ const cpu_family_t cpu_families[] = { .internal_name = "i486dx", .cpus = (const CPU[]) { {"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, {"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, {"", 0} } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX (SL-Enhanced)", + .internal_name = "i486dx_slenh", + .cpus = (const CPU[]) { + {"33", CPU_i486DX_SLENH, fpus_internal, 33333333, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 1, 5000, 0x414, 0x414, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + {"", 0} + } }, { .package = CPU_PKG_SOCKET1, .manufacturer = "Intel", .name = "i486DX2", .internal_name = "i486dx2", .cpus = (const CPU[]) { - {"40", CPU_i486DX2, fpus_internal, 40000000, 2, 5000, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"40", CPU_i486DX, fpus_internal, 40000000, 2, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"50", CPU_i486DX, fpus_internal, 50000000, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX, fpus_internal, 66666666, 2, 5000, 0x433, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, {"", 0} } - }, { + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "Intel", + .name = "i486DX2 (SL-Enhanced)", + .internal_name = "i486dx2_slenh", + .cpus = (const CPU[]) { + {"40", CPU_i486DX_SLENH, fpus_internal, 40000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"", 0} + } + }, { .package = CPU_PKG_SOCKET3_PC330, .manufacturer = "Intel", .name = "i486DX2", .internal_name = "i486dx2_pc330", .cpus = (const CPU[]) { - {"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"50", CPU_i486DX_SLENH, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"66", CPU_i486DX_SLENH, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, {"", 0} } }, { - .package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330, + .package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. hey are functionally identical*/ .manufacturer = "Intel", .name = "iDX4", .internal_name = "idx4", .cpus = (const CPU[]) { - {"75", CPU_iDX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, /*CPUID available on DX4, >= 75 MHz*/ - {"100", CPU_iDX4, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/ - {"", 0} - } - }, { - .package = CPU_PKG_SOCKET1, - .manufacturer = "Intel", - .name = "iDX4 OverDrive", - .internal_name = "idx4_od", - .cpus = (const CPU[]) { - {"75", CPU_iDX4, fpus_internal, 75000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ - {"100", CPU_iDX4, fpus_internal, 100000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, + {"75", CPU_i486DX_SLENH, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_i486DX_SLENH, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, {"", 0} } }, { @@ -394,8 +419,8 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX", .internal_name = "am486sx", .cpus = (const CPU[]) { - {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, {"", 0} } }, { @@ -404,8 +429,8 @@ const cpu_family_t cpu_families[] = { .name = "Am486SX2", .internal_name = "am486sx2", .cpus = (const CPU[]) { - {"50", CPU_Am486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ - {"66", CPU_Am486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/ + {"50", CPU_Am486SX, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486SX, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, {"", 0} } }, { @@ -414,8 +439,8 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX", .internal_name = "am486dx", .cpus = (const CPU[]) { - {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x412, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, {"", 0} } }, { @@ -424,21 +449,65 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX2", .internal_name = "am486dx2", .cpus = (const CPU[]) { - {"50", CPU_Am486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Am486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Am486DX2, fpus_internal, 80000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"50", CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", 0} + } + }, + { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL", + .internal_name = "am486dxl", + .cpus = (const CPU[]) { + {"33", CPU_Am486DXL, fpus_internal, 33333333, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"40", CPU_Am486DXL, fpus_internal, 40000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, {"", 0} } }, { + .package = CPU_PKG_SOCKET1, + .manufacturer = "AMD", + .name = "Am486DXL2", + .internal_name = "am486dxl2", + .cpus = (const CPU[]) { + {"50", CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", 0} + } + }, { .package = CPU_PKG_SOCKET3, .manufacturer = "AMD", .name = "Am486DX4", .internal_name = "am486dx4", .cpus = (const CPU[]) { - {"75", CPU_Am486DX4, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"90", CPU_Am486DX4, fpus_internal, 90000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"100", CPU_Am486DX4, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Am486DX4, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"", 0} + } + }, + { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX2 (Enhanced)", + .internal_name = "enh_am486dx2", + .cpus = (const CPU[]) { + {"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", 0} + } + }, { + .package = CPU_PKG_SOCKET3, + .manufacturer = "AMD", + .name = "Am486DX4 (Enhanced)", + .internal_name = "enh_am486dx4", + .cpus = (const CPU[]) { + {"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, {"", 0} } }, { @@ -447,9 +516,9 @@ const cpu_family_t cpu_families[] = { .name = "Am5x86", .internal_name = "am5x86", .cpus = (const CPU[]) { - {"P75", CPU_Am5x86, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"P75+", CPU_Am5x86, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"P90", CPU_Am5x86, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + {"P75", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"P75+", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + {"P90", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ {"", 0} } }, { @@ -479,9 +548,9 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX2", .internal_name = "cx486dx2", .cpus = (const CPU[]) { - {"50", CPU_Cx486DX2, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"66", CPU_Cx486DX2, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_Cx486DX2, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"50", CPU_Cx486DX, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"66", CPU_Cx486DX, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"80", CPU_Cx486DX, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, {"", 0} } }, { @@ -490,8 +559,8 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX4", .internal_name = "cx486dx4", .cpus = (const CPU[]) { - {"75", CPU_Cx486DX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_Cx486DX4, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, {"", 0} } }, { @@ -522,7 +591,7 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX2", .internal_name = "stpc_dx2", .cpus = (const CPU[]) { - {"133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"133", CPU_Cx486DX, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, {"", 0} } }, { diff --git a/src/cpu/x86.c b/src/cpu/x86.c index f8e13764e..9ab8ce169 100644 --- a/src/cpu/x86.c +++ b/src/cpu/x86.c @@ -281,7 +281,7 @@ reset_common(int hard) smi_block = 0; if (hard) { - smbase = is_486_org ? 0x00060000 : 0x00030000; + smbase = is_am486dxl ? 0x00060000 : 0x00030000; ppi_reset(); } in_sys = 0; diff --git a/src/cpu/x86_ops_string.h b/src/cpu/x86_ops_string.h index fbec20dd9..54a22d4b8 100644 --- a/src/cpu/x86_ops_string.h +++ b/src/cpu/x86_ops_string.h @@ -5,10 +5,13 @@ static int opMOVSB_a16(uint32_t fetchdat) addr64 = addr64_2 = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI); high_page = 0; do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI); + do_mmut_wb(es, DI, &addr64_2); if (cpu_state.abrt) return 1; temp = readmemb_n(cpu_state.ea_seg->base, SI, addr64); if (cpu_state.abrt) return 1; @@ -26,10 +29,12 @@ static int opMOVSB_a32(uint32_t fetchdat) addr64 = addr64_2 = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI); high_page = 0; do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI); do_mmut_wb(es, EDI, &addr64_2); if (cpu_state.abrt) return 1; temp = readmemb_n(cpu_state.ea_seg->base, ESI, addr64); if (cpu_state.abrt) return 1; @@ -49,10 +54,12 @@ static int opMOVSW_a16(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL); high_page = 0; do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL); do_mmut_ww(es, DI, addr64a_2); if (cpu_state.abrt) return 1; temp = readmemw_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; @@ -71,10 +78,12 @@ static int opMOVSW_a32(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL); high_page = 0; do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL); do_mmut_ww(es, EDI, addr64a_2); if (cpu_state.abrt) return 1; temp = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; @@ -94,10 +103,12 @@ static int opMOVSL_a16(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL); high_page = 0; do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL); do_mmut_wl(es, DI, addr64a_2); if (cpu_state.abrt) return 1; temp = readmeml_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; @@ -116,10 +127,12 @@ static int opMOVSL_a32(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL); high_page = 0; do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL); do_mmut_wl(es, EDI, addr64a_2); if (cpu_state.abrt) return 1; temp = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; @@ -139,10 +152,12 @@ static int opCMPSB_a16(uint32_t fetchdat) addr64 = addr64_2 = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI); high_page = uncached = 0; do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI); do_mmut_rb2(es, DI, &addr64_2); if (cpu_state.abrt) return 1; src = readmemb_n(cpu_state.ea_seg->base, SI, addr64); if (cpu_state.abrt) return 1; @@ -165,10 +180,12 @@ static int opCMPSB_a32(uint32_t fetchdat) addr64 = addr64_2 = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI); high_page = uncached = 0; do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI); do_mmut_rb2(es, EDI, &addr64_2); if (cpu_state.abrt) return 1; src = readmemb_n(cpu_state.ea_seg->base, ESI, addr64); if (cpu_state.abrt) return 1; @@ -193,10 +210,12 @@ static int opCMPSW_a16(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL); high_page = uncached = 0; do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI + 1UL); do_mmut_rw2(es, DI, addr64a_2); if (cpu_state.abrt) return 1; src = readmemw_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; @@ -220,10 +239,12 @@ static int opCMPSW_a32(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL); high_page = uncached = 0; do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI + 1UL); do_mmut_rw2(es, EDI, addr64a_2); if (cpu_state.abrt) return 1; src = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; @@ -248,10 +269,12 @@ static int opCMPSL_a16(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL); high_page = uncached = 0; do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI + 3UL); do_mmut_rl2(es, DI, addr64a_2); if (cpu_state.abrt) return 1; src = readmeml_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1; @@ -275,10 +298,12 @@ static int opCMPSL_a32(uint32_t fetchdat) addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL); high_page = uncached = 0; do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI + 3UL); do_mmut_rl2(es, EDI, addr64a_2); if (cpu_state.abrt) return 1; src = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1; @@ -298,6 +323,7 @@ static int opCMPSL_a32(uint32_t fetchdat) static int opSTOSB_a16(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI); writememb(es, DI, AL); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) DI--; else DI++; @@ -308,6 +334,7 @@ static int opSTOSB_a16(uint32_t fetchdat) static int opSTOSB_a32(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI); writememb(es, EDI, AL); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) EDI--; else EDI++; @@ -319,6 +346,7 @@ static int opSTOSB_a32(uint32_t fetchdat) static int opSTOSW_a16(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL); writememw(es, DI, AX); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) DI -= 2; else DI += 2; @@ -329,6 +357,7 @@ static int opSTOSW_a16(uint32_t fetchdat) static int opSTOSW_a32(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL); writememw(es, EDI, AX); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) EDI -= 2; else EDI += 2; @@ -340,6 +369,7 @@ static int opSTOSW_a32(uint32_t fetchdat) static int opSTOSL_a16(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL); writememl(es, DI, EAX); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) DI -= 4; else DI += 4; @@ -350,6 +380,7 @@ static int opSTOSL_a16(uint32_t fetchdat) static int opSTOSL_a32(uint32_t fetchdat) { SEG_CHECK_WRITE(&cpu_state.seg_es); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL); writememl(es, EDI, EAX); if (cpu_state.abrt) return 1; if (cpu_state.flags & D_FLAG) EDI -= 4; else EDI += 4; @@ -364,6 +395,7 @@ static int opLODSB_a16(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI); temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; AL = temp; if (cpu_state.flags & D_FLAG) SI--; @@ -377,6 +409,7 @@ static int opLODSB_a32(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI); temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; AL = temp; if (cpu_state.flags & D_FLAG) ESI--; @@ -391,6 +424,7 @@ static int opLODSW_a16(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL); temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; AX = temp; if (cpu_state.flags & D_FLAG) SI -= 2; @@ -404,6 +438,7 @@ static int opLODSW_a32(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL); temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; AX = temp; if (cpu_state.flags & D_FLAG) ESI -= 2; @@ -418,6 +453,7 @@ static int opLODSL_a16(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL); temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; EAX = temp; if (cpu_state.flags & D_FLAG) SI -= 4; @@ -431,6 +467,7 @@ static int opLODSL_a32(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL); temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; EAX = temp; if (cpu_state.flags & D_FLAG) ESI -= 4; @@ -446,6 +483,7 @@ static int opSCASB_a16(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI); temp = readmemb(es, DI); if (cpu_state.abrt) return 1; setsub8(AL, temp); if (cpu_state.flags & D_FLAG) DI--; @@ -459,6 +497,7 @@ static int opSCASB_a32(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI); temp = readmemb(es, EDI); if (cpu_state.abrt) return 1; setsub8(AL, temp); if (cpu_state.flags & D_FLAG) EDI--; @@ -473,6 +512,7 @@ static int opSCASW_a16(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI + 1UL); temp = readmemw(es, DI); if (cpu_state.abrt) return 1; setsub16(AX, temp); if (cpu_state.flags & D_FLAG) DI -= 2; @@ -486,6 +526,7 @@ static int opSCASW_a32(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI + 1UL); temp = readmemw(es, EDI); if (cpu_state.abrt) return 1; setsub16(AX, temp); if (cpu_state.flags & D_FLAG) EDI -= 2; @@ -500,6 +541,7 @@ static int opSCASL_a16(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, DI, DI + 3UL); temp = readmeml(es, DI); if (cpu_state.abrt) return 1; setsub32(EAX, temp); if (cpu_state.flags & D_FLAG) DI -= 4; @@ -513,6 +555,7 @@ static int opSCASL_a32(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(&cpu_state.seg_es); + CHECK_READ(&cpu_state.seg_es, EDI, EDI + 3UL); temp = readmeml(es, EDI); if (cpu_state.abrt) return 1; setsub32(EAX, temp); if (cpu_state.flags & D_FLAG) EDI -= 4; @@ -530,6 +573,7 @@ static int opINSB_a16(uint32_t fetchdat) SEG_CHECK_WRITE(&cpu_state.seg_es); check_io_perm(DX); + CHECK_WRITE(&cpu_state.seg_es, DI, DI); high_page = 0; do_mmut_wb(es, DI, &addr64); if (cpu_state.abrt) return 1; temp = inb(DX); @@ -549,6 +593,7 @@ static int opINSB_a32(uint32_t fetchdat) SEG_CHECK_WRITE(&cpu_state.seg_es); check_io_perm(DX); high_page = 0; + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI); do_mmut_wb(es, EDI, &addr64); if (cpu_state.abrt) return 1; temp = inb(DX); writememb_n(es, EDI, addr64, temp); if (cpu_state.abrt) return 1; @@ -568,6 +613,7 @@ static int opINSW_a16(uint32_t fetchdat) SEG_CHECK_WRITE(&cpu_state.seg_es); check_io_perm(DX); check_io_perm(DX + 1); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL); high_page = 0; do_mmut_ww(es, DI, addr64a); if (cpu_state.abrt) return 1; temp = inw(DX); @@ -588,6 +634,7 @@ static int opINSW_a32(uint32_t fetchdat) high_page = 0; check_io_perm(DX); check_io_perm(DX + 1); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL); do_mmut_ww(es, EDI, addr64a); if (cpu_state.abrt) return 1; temp = inw(DX); writememw_n(es, EDI, addr64a, temp); if (cpu_state.abrt) return 1; @@ -609,6 +656,7 @@ static int opINSL_a16(uint32_t fetchdat) check_io_perm(DX + 1); check_io_perm(DX + 2); check_io_perm(DX + 3); + CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL); high_page = 0; do_mmut_wl(es, DI, addr64a); if (cpu_state.abrt) return 1; temp = inl(DX); @@ -630,6 +678,7 @@ static int opINSL_a32(uint32_t fetchdat) check_io_perm(DX + 1); check_io_perm(DX + 2); check_io_perm(DX + 3); + CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL); high_page = 0; do_mmut_wl(es, DI, addr64a); if (cpu_state.abrt) return 1; temp = inl(DX); @@ -646,6 +695,7 @@ static int opOUTSB_a16(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI); temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; check_io_perm(DX); if (cpu_state.flags & D_FLAG) SI--; @@ -660,6 +710,7 @@ static int opOUTSB_a32(uint32_t fetchdat) uint8_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI); temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; check_io_perm(DX); if (cpu_state.flags & D_FLAG) ESI--; @@ -675,6 +726,7 @@ static int opOUTSW_a16(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL); temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; check_io_perm(DX); check_io_perm(DX + 1); @@ -690,6 +742,7 @@ static int opOUTSW_a32(uint32_t fetchdat) uint16_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL); temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; check_io_perm(DX); check_io_perm(DX + 1); @@ -706,6 +759,7 @@ static int opOUTSL_a16(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL); temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1; check_io_perm(DX); check_io_perm(DX + 1); @@ -723,6 +777,7 @@ static int opOUTSL_a32(uint32_t fetchdat) uint32_t temp; SEG_CHECK_READ(cpu_state.ea_seg); + CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL); temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1; check_io_perm(DX); check_io_perm(DX + 1); diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c index 600c61bb4..7c844ec15 100644 --- a/src/device/keyboard_at.c +++ b/src/device/keyboard_at.c @@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val) /* Pin 0 selected. */ softresetx86(); /*Pulse reset!*/ cpu_set_edx(); - smbase = is_486_org ? 0x00060000 : 0x00030000; + smbase = is_am486dxl ? 0x00060000 : 0x00030000; } } /* Mask off the A20 stuff because we use mem_a20_key directly for that. */ diff --git a/src/machine/machine.c b/src/machine/machine.c index 045e81c30..685165f89 100644 --- a/src/machine/machine.c +++ b/src/machine/machine.c @@ -81,7 +81,7 @@ machine_init_ex(int m) /* Reset the memory state. */ mem_reset(); - smbase = is_486_org ? 0x00060000 : 0x00030000; + smbase = is_am486dxl ? 0x00060000 : 0x00030000; lpt_init(); } diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 4ed5f966b..13f76feb2 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -240,7 +240,7 @@ const machine_t machines[] = { { "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ls486e_init, NULL }, { "[SiS 496] Micronics M4Li", "m4li", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_m4li_init, NULL }, { "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_r418_init, NULL }, - { "[SiS 496] Soyo 4SA2", "4sa2", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4sa2_init, NULL }, + { "[SiS 496] Soyo 4SA2", "4sa2", MACHINE_TYPE_486, CPU_PKG_SOCKET3, CPU_BLOCK(CPU_i486SX, CPU_i486DX, CPU_Am486SX, CPU_Am486DX), 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4sa2_init, NULL }, { "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4dps_init, NULL }, { "[UMC 8881] A-Trend ATC-1415", "atc1415", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_atc1415_init, NULL }, { "[UMC 8881] ECS Elite UM8810PAIO", "ecs486", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ecs486_init, NULL }, diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index fae21a279..8fb271bbc 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -1006,17 +1006,21 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val) s3_accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3); break; case 0x200: - if (s3->accel.cmd & 0x1000) - s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3); - else - s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3); + if (s3->chip == S3_86C928) /*Windows 95's built-in driver expects this to be loaded regardless of the byte swap bit (0xE2E9)*/ + s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8)); + else { + if (s3->accel.cmd & 0x1000) + s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3); + else + s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3); + } break; case 0x400: if (svga->crtc[0x53] & 0x08) s3_accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3); break; } - } + } } break; case 0xe14a: case 0xe2ea: @@ -1052,7 +1056,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val) } break; } - } + } } else { if (s3->accel.cmd & 0x100) { switch (s3->accel.cmd & 0x600) { @@ -1060,11 +1064,15 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val) s3_accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3); break; case 0x200: - if (s3->accel.cmd & 0x1000) - s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3); - else - s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3); - break; + if (s3->chip == S3_86C928) /*Windows 95's built-in S3 928 driver expects the upper 16 bits to be loaded instead of the whole 32-bit one, regardless of the byte swap bit (0xE2EB)*/ + s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[2] | (s3->accel.pix_trans[3] << 8)); + else { + if (s3->accel.cmd & 0x1000) + s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3); + else + s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3); + } + break; case 0x400: s3_accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3); break; @@ -2552,7 +2560,7 @@ static void s3_recalctimings(svga_t *svga) if (s3->chip == S3_86C928) { if (s3->width == 2048 || s3->width == 1280 || s3->width == 1600) svga->hdisp *= 2; - } else { + } else if ((s3->chip != S3_86C801) && (s3->chip != S3_86C805)) { if (s3->width == 1280 || s3->width == 1600) svga->hdisp *= 2; } @@ -2710,7 +2718,7 @@ s3_updatemapping(s3_t *s3) { svga_t *svga = &s3->svga; - if (!(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) + if (s3->pci && !(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) { mem_mapping_disable(&svga->mapping); mem_mapping_disable(&s3->linear_mapping); @@ -2787,7 +2795,6 @@ s3_updatemapping(s3_t *s3) } break; } - s3->linear_base &= ~(s3->linear_size - 1); if (s3->linear_base == 0xa0000) { mem_mapping_disable(&s3->linear_mapping); @@ -2803,9 +2810,8 @@ s3_updatemapping(s3_t *s3) s3->linear_base &= 0xfe000000; mem_mapping_set_addr(&s3->linear_mapping, s3->linear_base, s3->linear_size); } - } else { + } else mem_mapping_disable(&s3->linear_mapping); - } /* Memory mapped I/O. */ if ((svga->crtc[0x53] & 0x10) || (s3->accel.advfunc_cntl & 0x20)) { @@ -2818,9 +2824,8 @@ s3_updatemapping(s3_t *s3) } else { mem_mapping_enable(&s3->mmio_mapping); } - } else { + } else mem_mapping_disable(&s3->mmio_mapping); - } /* New MMIO. */ if (svga->crtc[0x53] & 0x08) { @@ -5862,7 +5867,7 @@ static void *s3_init(const device_t *info) else if (s3->vlb) svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4); else - svga->crtc[0x36] = 3 | (3 << 2) | (1 << 4); + svga->crtc[0x36] = 3; if (chip >= S3_86C928) svga->crtc[0x36] |= (vram_sizes[vram] << 5); @@ -6021,8 +6026,7 @@ static void *s3_init(const device_t *info) case S3_PHOENIX_VISION868: svga->decode_mask = (4 << 20) - 1; s3->id = 0xe1; /*Vision868*/ - s3->id_ext = 0x90; - s3->id_ext_pci = 0x80; + s3->id_ext = s3->id_ext_pci = 0x80; s3->packed_mmio = 1; if (s3->pci) { svga->crtc[0x53] = 0x18; @@ -6045,8 +6049,7 @@ static void *s3_init(const device_t *info) case S3_DIAMOND_STEALTH_SE: svga->decode_mask = (4 << 20) - 1; s3->id = 0xe1; /*Trio32*/ - s3->id_ext = 0x10; - s3->id_ext_pci = 0x11; + s3->id_ext = s3->id_ext_pci = 0x10; s3->packed_mmio = 1; svga->clock_gen = s3;