Port code related to coreboot BIOS from MTRR

Only used if MACHINE_COREBOOT is set in machine flags, so this is a pretty safe one

src/device/keyboard_at.c

@@ -1120,11 +1120,20 @@ write_output(atkbd_t *dev, uint8_t val)
         if (!(val & 0x01)) {  /* Pin 0 selected. */
             /* Pin 0 selected. */
             kbd_log("write_output(): Pulse reset!\n");
-            softresetx86(); /*Pulse reset!*/
-            cpu_set_edx();
-            flushmmucache();
-            if (kbc_ven == KBC_VEN_ALI)
-                smbase = 0x00030000;
+            if (machines[machine].flags & MACHINE_COREBOOT) {
+                /* The SeaBIOS hard reset code attempts a KBC reset if ACPI RESET_REG
+                   is not available. However, the KBC reset is normally a soft reset, so
+                   SeaBIOS gets caught in a soft reset loop as it tries to hard reset the
+                   machine. Hack around this by making the KBC reset a hard reset only on
+                   coreboot machines. */
+                pc_reset_hard();
+            } else {
+                softresetx86(); /*Pulse reset!*/
+                cpu_set_edx();
+                flushmmucache();
+                if (kbc_ven == KBC_VEN_ALI)
+                    smbase = 0x00030000;
+            }
         }
     }
 

src/include/86box/machine.h

@@ -107,6 +107,7 @@
 #define MACHINE_SCSI_SEC 0x02000000 /* sys has int sec SCSI */
 #define MACHINE_USB_PRI  0x04000000 /* sys has int pri USB */
 #define MACHINE_USB_SEC  0x08000000 /* sys has int sec USB */
+#define MACHINE_COREBOOT 0x10000000 /* sys has coreboot BIOS */
 /* Combined flags. */
 #define MACHINE_IDE        (MACHINE_IDE_PRI)                   /* sys has int single IDE/ATAPI - mark as pri IDE/ATAPI */
 #define MACHINE_IDE_DUAL   (MACHINE_IDE_PRI | MACHINE_IDE_SEC) /* sys has int dual IDE/ATAPI - mark as both pri and sec IDE/ATAPI */