diff --git a/src/chipset/CMakeLists.txt b/src/chipset/CMakeLists.txt index 89998ff39..d61b5c53d 100644 --- a/src/chipset/CMakeLists.txt +++ b/src/chipset/CMakeLists.txt @@ -49,6 +49,7 @@ add_library(chipset OBJECT opti291.c opti391.c opti495.c + opti498.c opti499.c opti602.c opti822.c diff --git a/src/chipset/opti283.c b/src/chipset/opti283.c index 395ad4212..81780cf10 100644 --- a/src/chipset/opti283.c +++ b/src/chipset/opti283.c @@ -16,6 +16,7 @@ * Copyright 2021 Tiseno100. * Copyright 2021 Miran Grca. */ +#include #include #include #include @@ -158,7 +159,20 @@ opti283_shadow_recalc(opti283_t *dev) rom = dev->regs[0x11] & (1 << ((i >> 2) + 4)); opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4))); - if (sh_enable && rom) { + if (sh_copy) { + if (base >= 0x000e0000) + shadowbios_write |= 1; + if (base >= 0x000d0000) + dev->shadow_high |= 1; + + if (base >= 0xe0000) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_INTERNAL\n", base, base + 0x3fff); + } else { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); + } + } else if (sh_enable && rom) { if (base >= 0x000e0000) shadowbios |= 1; if (base >= 0x000d0000) @@ -171,13 +185,8 @@ opti283_shadow_recalc(opti283_t *dev) if (base >= 0x000e0000) shadowbios_write |= 1; - if (sh_copy) { - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); - } else { - mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL); - opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff); - } + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); } } else { if (base >= 0xe0000) { @@ -239,9 +248,21 @@ opti283_write(uint16_t addr, uint8_t val, void *priv) dev->regs[dev->index] = (dev->regs[dev->index] & 0x80) | (val & 0x7f); break; - case 0x14: + case 0x14: { + double bus_clk; + switch (val & 0x01) { + default: + case 0x00: + bus_clk = cpu_busspeed / 6.0; + break; + case 0x01: + bus_clk = cpu_busspeed / 4.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); reset_on_hlt = !!(val & 0x40); fallthrough; + } case 0x11: case 0x12: case 0x13: @@ -310,6 +331,8 @@ opti283_init(UNUSED(const device_t *info)) opti283_shadow_recalc(dev); + cpu_set_isa_speed((int) round(cpu_busspeed / 6.0)); + device_add(&port_92_device); return dev; diff --git a/src/chipset/opti495.c b/src/chipset/opti495.c index aa4e4b4c5..8521dbd17 100644 --- a/src/chipset/opti495.c +++ b/src/chipset/opti495.c @@ -8,14 +8,13 @@ * * Implementation of the OPTi 82C493/82C495 chipset. * - * - * * Authors: Tiseno100, * Miran Grca, * * Copyright 2008-2020 Tiseno100. * Copyright 2016-2020 Miran Grca. */ +#include #include #include #include @@ -28,6 +27,7 @@ #include <86box/io.h> #include <86box/device.h> #include <86box/mem.h> +#include <86box/plat_fallthrough.h> #include <86box/port_92.h> #include <86box/chipset.h> @@ -166,6 +166,27 @@ opti495_write(uint16_t addr, uint8_t val, void *priv) case 0x26: opti495_recalc(dev); break; + + case 0x25: { + double bus_clk; + switch (val & 0x03) { + default: + case 0x00: + bus_clk = cpu_busspeed / 6.0; + break; + case 0x01: + bus_clk = cpu_busspeed / 4.0; + break; + case 0x02: + bus_clk = cpu_busspeed / 3.0; + break; + case 0x03: + bus_clk = (cpu_busspeed * 2.0) / 5.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); + break; + } } } @@ -259,6 +280,8 @@ opti495_init(const device_t *info) io_sethandler(0x00e1, 0x0002, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev); + cpu_set_isa_speed((int) round(cpu_busspeed / 6.0)); + return dev; } @@ -276,11 +299,25 @@ const device_t opti493_device = { .config = NULL }; -const device_t opti495_device = { +const device_t opti495slc_device = { .name = "OPTi 82C495", - .internal_name = "opti495", + .internal_name = "opti495slc", .flags = 0, - .local = OPTI495XLC, + .local = OPTI495SLC, + .init = opti495_init, + .close = opti495_close, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +}; + +const device_t opti495sx_device = { + .name = "OPTi 82C495SX", + .internal_name = "opti495sx", + .flags = 0, + .local = OPTI495SX, .init = opti495_init, .close = opti495_close, .reset = NULL, diff --git a/src/chipset/opti498.c b/src/chipset/opti498.c new file mode 100644 index 000000000..2d3dc6709 --- /dev/null +++ b/src/chipset/opti498.c @@ -0,0 +1,360 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the OPTi 82C498 chipset. + * + * Authors: Miran Grca, + * + * Copyright 2025 Miran Grca. + */ +#include +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include <86box/86box.h> +#include "cpu.h" +#include <86box/timer.h> +#include <86box/io.h> +#include <86box/device.h> +#include <86box/mem.h> +#include <86box/plat_fallthrough.h> +#include <86box/plat_unused.h> +#include <86box/port_92.h> +#include <86box/chipset.h> + +#ifdef ENABLE_OPTI498_LOG +int opti498_do_log = ENABLE_OPTI498_LOG; + +static void +opti498_log(const char *fmt, ...) +{ + va_list ap; + + if (opti498_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +# define opti498_log(fmt, ...) +#endif + +typedef struct mem_remapping_t { + uint32_t phys; + uint32_t virt; +} mem_remapping_t; + +typedef struct opti498_t { + uint8_t index; + /* 0x30 for 496/497, 0x70 for 498. */ + uint8_t reg_base; + uint8_t shadow_high; + uint8_t regs[256]; + mem_remapping_t mem_remappings[2]; + mem_mapping_t mem_mappings[2]; +} opti498_t; + +static uint8_t +opti498_read_remapped_ram(uint32_t addr, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + return mem_read_ram((addr - dev->virt) + dev->phys, priv); +} + +static uint16_t +opti498_read_remapped_ramw(uint32_t addr, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + return mem_read_ramw((addr - dev->virt) + dev->phys, priv); +} + +static uint32_t +opti498_read_remapped_raml(uint32_t addr, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + return mem_read_raml((addr - dev->virt) + dev->phys, priv); +} + +static void +opti498_write_remapped_ram(uint32_t addr, uint8_t val, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + mem_write_ram((addr - dev->virt) + dev->phys, val, priv); +} + +static void +opti498_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + mem_write_ramw((addr - dev->virt) + dev->phys, val, priv); +} + +static void +opti498_write_remapped_raml(uint32_t addr, uint32_t val, void *priv) +{ + const mem_remapping_t *dev = (mem_remapping_t *) priv; + + mem_write_raml((addr - dev->virt) + dev->phys, val, priv); +} + +static void +opti498_shadow_recalc(opti498_t *dev) +{ + uint32_t base; + uint32_t rbase; + uint8_t sh_enable; + uint8_t sh_mode; + uint8_t rom; + uint8_t sh_copy; + + shadowbios = shadowbios_write = 0; + dev->shadow_high = 0; + + opti498_log("OPTI 498: %02X %02X %02X %02X\n", dev->regs[0x02], dev->regs[0x03], dev->regs[0x04], dev->regs[0x05]); + + if (dev->regs[0x02] & 0x80) { + if (dev->regs[0x04] & 0x02) { + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + opti498_log("OPTI 498: F0000-FFFFF READ_EXTANY, WRITE_EXTANY\n"); + } else { + shadowbios_write = 1; + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + opti498_log("OPTI 498: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n"); + } + } else { + shadowbios = 1; + mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + opti498_log("OPTI 498: F0000-FFFFF READ_INTERNAL, WRITE_DISABLED\n"); + } + + sh_copy = dev->regs[0x02] & 0x08; + for (uint8_t i = 0; i < 12; i++) { + base = 0xc0000 + (i << 14); + if (i >= 4) + sh_enable = dev->regs[0x03] & (1 << (i - 4)); + else + sh_enable = dev->regs[0x04] & (1 << (i + 4)); + sh_mode = dev->regs[0x02] & (1 << (i >> 2)); + rom = dev->regs[0x02] & (1 << ((i >> 2) + 4)); + opti498_log("OPTI 498: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4))); + + if (sh_copy) { + if (base >= 0x000e0000) + shadowbios_write |= 1; + if (base >= 0x000d0000) + dev->shadow_high |= 1; + + if (base >= 0xe0000) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + opti498_log("OPTI 498: %08X-%08X READ_EXTANY, WRITE_INTERNAL\n", base, base + 0x3fff); + } else { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL); + opti498_log("OPTI 498: %08X-%08X READ_EXTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); + } + } else if (sh_enable && rom) { + if (base >= 0x000e0000) + shadowbios |= 1; + if (base >= 0x000d0000) + dev->shadow_high |= 1; + + if (sh_mode) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); + opti498_log("OPTI 498: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); + } else { + if (base >= 0x000e0000) + shadowbios_write |= 1; + + mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + opti498_log("OPTI 498: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff); + } + } else { + if (base >= 0xe0000) { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED); + opti498_log("OPTI 498: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff); + } else { + mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED); + opti498_log("OPTI 498: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff); + } + } + } + + rbase = ((uint32_t) (dev->regs[0x05] & 0x3f)) << 20; + + if (rbase > 0) { + dev->mem_remappings[0].virt = rbase; + mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000); + + if (!dev->shadow_high) { + rbase += 0x00020000; + dev->mem_remappings[1].virt = rbase; + mem_mapping_set_addr(&dev->mem_mappings[1], rbase, 0x00020000); + } else + mem_mapping_disable(&dev->mem_mappings[1]); + } else { + mem_mapping_disable(&dev->mem_mappings[0]); + mem_mapping_disable(&dev->mem_mappings[1]); + } + + flushmmucache_nopc(); +} + +static void +opti498_write(uint16_t addr, uint8_t val, void *priv) +{ + opti498_t *dev = (opti498_t *) priv; + uint8_t reg = dev->index - dev->reg_base; + + switch (addr) { + default: + break; + + case 0x22: + dev->index = val; + break; + + case 0x24: + opti498_log("OPTi 498: dev->regs[%02x] = %02x\n", dev->index, val); + + if ((reg >= 0x00) && (reg <= 0x0b)) switch (reg) { + default: + break; + + case 0x00: + dev->regs[reg] = (dev->regs[reg] & 0xc0) | (val & 0x3f); + break; + + case 0x01: + case 0x07 ... 0x0b: + dev->regs[reg] = val; + break; + + case 0x02: + case 0x03: + case 0x04: + case 0x05: + dev->regs[reg] = val; + opti498_shadow_recalc(dev); + break; + + case 0x06: { + double bus_clk; + dev->regs[reg] = val; + switch (val & 0x03) { + default: + case 0x00: + bus_clk = cpu_busspeed / 8.0; + break; + case 0x01: + bus_clk = cpu_busspeed / 6.0; + break; + case 0x02: + bus_clk = cpu_busspeed / 5.0; + break; + case 0x03: + bus_clk = cpu_busspeed / 4.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); + reset_on_hlt = !!(val & 0x40); + break; + } + } + + dev->index = 0xff; + break; + } +} + +static uint8_t +opti498_read(uint16_t addr, void *priv) +{ + opti498_t *dev = (opti498_t *) priv; + uint8_t reg = dev->index - dev->reg_base; + uint8_t ret = 0xff; + + if (addr == 0x24) { + if ((reg >= 0x00) && (reg <= 0x0b)) + ret = dev->regs[reg]; + + dev->index = 0xff; + } + + return ret; +} + +static void +opti498_close(void *priv) +{ + opti498_t *dev = (opti498_t *) priv; + + free(dev); +} + +static void * +opti498_init(UNUSED(const device_t *info)) +{ + opti498_t *dev = (opti498_t *) calloc(1, sizeof(opti498_t)); + + dev->reg_base = info->local & 0xff; + + io_sethandler(0x0022, 0x0001, opti498_read, NULL, NULL, opti498_write, NULL, NULL, dev); + io_sethandler(0x0024, 0x0001, opti498_read, NULL, NULL, opti498_write, NULL, NULL, dev); + + dev->regs[0x00] = 0x1f; + dev->regs[0x01] = 0x8f; + dev->regs[0x02] = 0xf0; + dev->regs[0x07] = 0x70; + dev->regs[0x09] = 0x70; + + dev->mem_remappings[0].phys = 0x000a0000; + dev->mem_remappings[1].phys = 0x000d0000; + + mem_mapping_add(&dev->mem_mappings[0], 0, 0x00020000, + opti498_read_remapped_ram, opti498_read_remapped_ramw, opti498_read_remapped_raml, + opti498_write_remapped_ram, opti498_write_remapped_ramw, opti498_write_remapped_raml, + &ram[dev->mem_remappings[0].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[0]); + mem_mapping_disable(&dev->mem_mappings[0]); + + mem_mapping_add(&dev->mem_mappings[1], 0, 0x00020000, + opti498_read_remapped_ram, opti498_read_remapped_ramw, opti498_read_remapped_raml, + opti498_write_remapped_ram, opti498_write_remapped_ramw, opti498_write_remapped_raml, + &ram[dev->mem_remappings[1].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[1]); + mem_mapping_disable(&dev->mem_mappings[1]); + + opti498_shadow_recalc(dev); + + cpu_set_isa_speed((int) round(cpu_busspeed / 8.0)); + + device_add(&port_92_device); + + return dev; +} + +const device_t opti498_device = { + .name = "OPTi 82C498", + .internal_name = "opti498", + .flags = 0, + .local = 0x70, + .init = opti498_init, + .close = opti498_close, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +}; diff --git a/src/chipset/opti499.c b/src/chipset/opti499.c index d54e8184e..383b8e3e2 100644 --- a/src/chipset/opti499.c +++ b/src/chipset/opti499.c @@ -16,6 +16,7 @@ * Copyright 2008-2020 Tiseno100. * Copyright 2016-2020 Miran Grca. */ +#include #include #include #include @@ -148,9 +149,28 @@ opti499_write(uint16_t addr, uint8_t val, void *priv) default: break; - case 0x20: + case 0x20: { + double coeff = (val & 0x10) ? 1.0 : 2.0; + double bus_clk; + switch (dev->regs[0x25] & 0x03) { + default: + case 0x00: + bus_clk = (cpu_busspeed * coeff) / 6.0; + break; + case 0x01: + bus_clk = (cpu_busspeed * coeff) / 5.0; + break; + case 0x02: + bus_clk = (cpu_busspeed * coeff) / 4.0; + break; + case 0x03: + bus_clk = (cpu_busspeed * coeff) / 3.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); reset_on_hlt = !(val & 0x02); break; + } case 0x21: cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10); @@ -163,6 +183,28 @@ opti499_write(uint16_t addr, uint8_t val, void *priv) case 0x2d: opti499_recalc(dev); break; + + case 0x25: { + double coeff = (dev->regs[0x20] & 0x10) ? 1.0 : 2.0; + double bus_clk; + switch (val & 0x03) { + default: + case 0x00: + bus_clk = (cpu_busspeed * coeff) / 8.0; + break; + case 0x01: + bus_clk = (cpu_busspeed * coeff) / 6.0; + break; + case 0x02: + bus_clk = (cpu_busspeed * coeff) / 5.0; + break; + case 0x03: + bus_clk = (cpu_busspeed * coeff) / 4.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); + break; + } } } @@ -229,6 +271,8 @@ opti499_reset(void *priv) cpu_update_waitstates(); opti499_recalc(dev); + + cpu_set_isa_speed((int) round((cpu_busspeed * 2.0) / 6.0)); } static void diff --git a/src/chipset/opti895.c b/src/chipset/opti895.c index cb55ef2a7..16b324963 100644 --- a/src/chipset/opti895.c +++ b/src/chipset/opti895.c @@ -16,6 +16,7 @@ * Copyright 2008-2020 Tiseno100. * Copyright 2016-2020 Miran Grca. */ +#include #include #include #include @@ -182,6 +183,27 @@ opti895_write(uint16_t addr, uint8_t val, void *priv) smram_state_change(dev->smram, 0, !!(val & 0x80)); break; + case 0x25: { + double bus_clk; + switch (val & 0x03) { + default: + case 0x00: + bus_clk = cpu_busspeed / 6.0; + break; + case 0x01: + bus_clk = cpu_busspeed / 5.0; + break; + case 0x02: + bus_clk = cpu_busspeed / 4.0; + break; + case 0x03: + bus_clk = cpu_busspeed / 3.0; + break; + } + cpu_set_isa_speed((int) round(bus_clk)); + break; + } + case 0xe0: if (!(val & 0x01)) dev->forced_green = 0; @@ -294,6 +316,8 @@ opti895_init(const device_t *info) smram_enable(dev->smram, 0x00030000, 0x000b0000, 0x00010000, 0, 1); + cpu_set_isa_speed((int) round(cpu_busspeed / 6.0)); + return dev; } diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index 0d750c4cf..7ee8182ea 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -124,7 +124,9 @@ extern const device_t opti381_device; extern const device_t opti391_device; extern const device_t opti481_device; extern const device_t opti493_device; -extern const device_t opti495_device; +extern const device_t opti495slc_device; +extern const device_t opti495sx_device; +extern const device_t opti498_device; extern const device_t opti499_device; extern const device_t opti601_device; extern const device_t opti602_device; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 3dec461d0..6fba13dc5 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -241,7 +241,9 @@ enum { MACHINE_CHIPSET_OPTI_391, MACHINE_CHIPSET_OPTI_481, MACHINE_CHIPSET_OPTI_493, - MACHINE_CHIPSET_OPTI_495, + MACHINE_CHIPSET_OPTI_495SLC, + MACHINE_CHIPSET_OPTI_495SX, + MACHINE_CHIPSET_OPTI_498, MACHINE_CHIPSET_OPTI_499, MACHINE_CHIPSET_OPTI_895_802G, MACHINE_CHIPSET_OPTI_547_597, @@ -547,6 +549,7 @@ extern int machine_at_winbios1429_init(const machine_t *); extern int machine_at_opti495_init(const machine_t *); extern int machine_at_opti495_ami_init(const machine_t *); extern int machine_at_opti495_mr_init(const machine_t *); +extern int machine_at_c747_init(const machine_t *); extern int machine_at_exp4349_init(const machine_t *); extern int machine_at_vect486vl_init(const machine_t *); diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 6dd5b1cae..6de17101c 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -682,7 +682,7 @@ machine_at_opti495_init(const machine_t *model) machine_at_common_init(model); - device_add(&opti495_device); + device_add(&opti495slc_device); device_add(&keyboard_at_device); @@ -697,7 +697,7 @@ machine_at_opti495_ami_common_init(const machine_t *model) { machine_at_common_init(model); - device_add(&opti495_device); + device_add(&opti495sx_device); device_add(&keyboard_at_ami_device); @@ -737,6 +737,34 @@ machine_at_opti495_mr_init(const machine_t *model) return ret; } +int +machine_at_c747_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear("roms/machines/c747/486-C747 Tandon.BIN", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + /* The EFAR chipset is a rebrand of the OPTi 495SX. */ + device_add(&opti495sx_device); + + /* + No idea what KBC it actually has but this produces the + desired behavior: command A9 does absolutely nothing. + */ + device_add(&keyboard_at_siemens_device); + + device_add(&ide_isa_device); + device_add(&um82c862f_ide_device); + + return ret; +} + int machine_at_exp4349_init(const machine_t *model) { @@ -975,7 +1003,8 @@ machine_at_mvi486_init(const machine_t *model) machine_at_common_init(model); - device_add(&opti495_device); + device_add(&opti498_device); + device_add(&keyboard_at_device); device_add(&pc87311_ide_device); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index e90c1e3f1..39b5e05db 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -152,7 +152,9 @@ const machine_filter_t machine_chipsets[] = { { "OPTi 391", MACHINE_CHIPSET_OPTI_391 }, { "OPTi 481", MACHINE_CHIPSET_OPTI_481 }, { "OPTi 493", MACHINE_CHIPSET_OPTI_493 }, - { "OPTi 495", MACHINE_CHIPSET_OPTI_495 }, + { "OPTi 495SLC", MACHINE_CHIPSET_OPTI_495SLC }, + { "OPTi 495SX", MACHINE_CHIPSET_OPTI_495SX }, + { "OPTi 498", MACHINE_CHIPSET_OPTI_498 }, { "OPTi 499", MACHINE_CHIPSET_OPTI_499 }, { "OPTi 895/802G", MACHINE_CHIPSET_OPTI_895_802G }, { "OPTi 547/597", MACHINE_CHIPSET_OPTI_547_597 }, @@ -5800,10 +5802,10 @@ const machine_t machines[] = { but the BIOS sends commands C9 without a parameter and D5, both of which are Phoenix MultiKey commands. */ { - .name = "[OPTi 495] U-Board OPTi 495SLC", + .name = "[OPTi 495SLC] U-Board OPTi 495SLC", .internal_name = "award495", .type = MACHINE_TYPE_386DX, - .chipset = MACHINE_CHIPSET_OPTI_495, + .chipset = MACHINE_CHIPSET_OPTI_495SLC, .init = machine_at_opti495_init, .p1_handler = NULL, .gpio_handler = NULL, @@ -6042,12 +6044,52 @@ const machine_t machines[] = { }, /* 386DX/486 machines */ + /* Has AMIKey F KBC firmware. The EFAR chipst is a rebrand of OPTi 495SX. */ + { + .name = "[OPTi 495SX] CAF Technology C747", + .internal_name = "c747", + .type = MACHINE_TYPE_386DX_486, + .chipset = MACHINE_CHIPSET_OPTI_495SX, + .init = machine_at_c747_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_386DX | CPU_PKG_SOCKET1, + .block = CPU_BLOCK_NONE, + .min_bus = 0, + .max_bus = 0, + .min_voltage = 0, + .max_voltage = 0, + .min_multi = 0, + .max_multi = 0 + }, + .bus_flags = MACHINE_AT, + .flags = MACHINE_APM | MACHINE_IDE, + .ram = { + .min = 1024, + .max = 32768, + .step = 1024 + }, + .nvrmask = 127, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* Has AMIKey F KBC firmware. */ { - .name = "[OPTi 495] DataExpert SX495", + .name = "[OPTi 495SX] DataExpert SX495", .internal_name = "ami495", .type = MACHINE_TYPE_386DX_486, - .chipset = MACHINE_CHIPSET_OPTI_495, + .chipset = MACHINE_CHIPSET_OPTI_495SX, .init = machine_at_opti495_ami_init, .p1_handler = NULL, .gpio_handler = NULL, @@ -6084,10 +6126,10 @@ const machine_t machines[] = { }, /* Has AMIKey F KBC firmware (it's just the MR BIOS for the above machine). */ { - .name = "[OPTi 495] DataExpert SX495 (MR BIOS)", + .name = "[OPTi 495SX] DataExpert SX495 (MR BIOS)", .internal_name = "mr495", .type = MACHINE_TYPE_386DX_486, - .chipset = MACHINE_CHIPSET_OPTI_495, + .chipset = MACHINE_CHIPSET_OPTI_495SX, .init = machine_at_opti495_mr_init, .p1_handler = NULL, .gpio_handler = NULL, @@ -6409,10 +6451,10 @@ const machine_t machines[] = { /* Uses some variant of Phoenix MultiKey/42 as the Intel 8242 chip has a Phoenix copyright. */ { - .name = "[OPTi 495] Mylex MVI486", + .name = "[OPTi 498] Mylex MVI486", .internal_name = "mvi486", .type = MACHINE_TYPE_486, - .chipset = MACHINE_CHIPSET_OPTI_495, + .chipset = MACHINE_CHIPSET_OPTI_498, .init = machine_at_mvi486_init, .p1_handler = NULL, .gpio_handler = NULL,