Only flush write MMU cache on WP flag toggle as read and execute MMU cache is not affected by the flag.
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@@ -184,7 +184,7 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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switch (cpu_reg) {
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG))
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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if (is_p6 || cpu_use_dynarec)
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@@ -193,7 +193,8 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
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flushmmucache_nopc();
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cpu_flush_pending = 1;
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}
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}
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} else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
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flushmmucache_write();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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@@ -249,7 +250,7 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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switch (cpu_reg) {
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG))
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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if (is_p6 || cpu_use_dynarec)
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@@ -258,7 +259,8 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
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flushmmucache_nopc();
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cpu_flush_pending = 1;
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}
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}
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} else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
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flushmmucache_write();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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@@ -180,12 +180,13 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
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fetch_ea_16(fetchdat);
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switch (cpu_reg) {
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG))
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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flushmmucache_nopc();
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cpu_flush_pending = 1;
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}
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} else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
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flushmmucache_write();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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@@ -241,12 +242,13 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
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fetch_ea_32(fetchdat);
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switch (cpu_reg) {
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG))
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
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flushmmucache();
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else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
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flushmmucache_nopc();
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cpu_flush_pending = 1;
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}
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} else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
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flushmmucache_write();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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@@ -448,6 +448,7 @@ extern void mem_flush_write_page(uint32_t addr, uint32_t virt);
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extern void mem_reset_page_blocks(void);
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extern void flushmmucache(void);
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extern void flushmmucache_write(void);
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extern void flushmmucache_pc(void);
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extern void flushmmucache_nopc(void);
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@@ -225,6 +225,21 @@ flushmmucache(void)
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#endif
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}
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void
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flushmmucache_write(void)
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{
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for (uint16_t c = 0; c < 256; c++) {
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if (writelookup[c] != (int) 0xffffffff) {
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page_lookup[writelookup[c]] = NULL;
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page_lookupp[writelookup[c]] = 4;
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writelookup2[writelookup[c]] = LOOKUP_INV;
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writelookupp[writelookup[c]] = 4;
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writelookup[c] = 0xffffffff;
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}
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}
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mmuflush++;
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}
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void
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flushmmucache_pc(void)
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{
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