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Only flush write MMU cache on WP flag toggle as read and execute MMU cache is not affected by the flag.

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This commit is contained in:
OBattler
2025-03-23 15:36:05 +01:00
parent c5efce619f
commit 609f34cc49
4 changed files with 28 additions and 8 deletions
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10
src/cpu/x86_ops_mov_ctrl.h
View File

@@ -184,7 +184,7 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
switch (cpu_reg) { switch (cpu_reg) {
case 0: case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG)) if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache(); flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) { else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
if (is_p6 || cpu_use_dynarec) if (is_p6 || cpu_use_dynarec)
@@ -193,7 +193,8 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
flushmmucache_nopc(); flushmmucache_nopc();
cpu_flush_pending = 1; cpu_flush_pending = 1;
} }
} } else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
flushmmucache_write();
/* Make sure CPL = 0 when switching from real mode to protected mode. */ /* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01)) if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f; cpu_state.seg_cs.access &= 0x9f;
@@ -249,7 +250,7 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
switch (cpu_reg) { switch (cpu_reg) {
case 0: case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG)) if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache(); flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) { else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
if (is_p6 || cpu_use_dynarec) if (is_p6 || cpu_use_dynarec)
@@ -258,7 +259,8 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
flushmmucache_nopc(); flushmmucache_nopc();
cpu_flush_pending = 1; cpu_flush_pending = 1;
} }
} } else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
flushmmucache_write();
/* Make sure CPL = 0 when switching from real mode to protected mode. */ /* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01)) if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f; cpu_state.seg_cs.access &= 0x9f;

10
src/cpu/x86_ops_mov_ctrl_2386.h
View File

@@ -180,12 +180,13 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
switch (cpu_reg) { switch (cpu_reg) {
case 0: case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG)) if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache(); flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) { else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
flushmmucache_nopc(); flushmmucache_nopc();
cpu_flush_pending = 1; cpu_flush_pending = 1;
} } else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
flushmmucache_write();
/* Make sure CPL = 0 when switching from real mode to protected mode. */ /* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01)) if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f; cpu_state.seg_cs.access &= 0x9f;
@@ -241,12 +242,13 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
switch (cpu_reg) { switch (cpu_reg) {
case 0: case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & (0x00000001 | WP_FLAG)) if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache(); flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) { else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
flushmmucache_nopc(); flushmmucache_nopc();
cpu_flush_pending = 1; cpu_flush_pending = 1;
} } else if ((cpu_state.regs[cpu_rm].l ^ cr0) & WP_FLAG)
flushmmucache_write();
/* Make sure CPL = 0 when switching from real mode to protected mode. */ /* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01)) if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f; cpu_state.seg_cs.access &= 0x9f;

1
src/include/86box/mem.h
View File

@@ -448,6 +448,7 @@ extern void mem_flush_write_page(uint32_t addr, uint32_t virt);
extern void mem_reset_page_blocks(void); extern void mem_reset_page_blocks(void);
extern void flushmmucache(void); extern void flushmmucache(void);
extern void flushmmucache_write(void);
extern void flushmmucache_pc(void); extern void flushmmucache_pc(void);
extern void flushmmucache_nopc(void); extern void flushmmucache_nopc(void);

15
src/mem/mem.c
View File

@@ -225,6 +225,21 @@ flushmmucache(void)
#endif #endif
} }
void
flushmmucache_write(void)
{
for (uint16_t c = 0; c < 256; c++) {
if (writelookup[c] != (int) 0xffffffff) {
page_lookup[writelookup[c]] = NULL;
page_lookupp[writelookup[c]] = 4;
writelookup2[writelookup[c]] = LOOKUP_INV;
writelookupp[writelookup[c]] = 4;
writelookup[c] = 0xffffffff;
}
}
mmuflush++;
}
void void
flushmmucache_pc(void) flushmmucache_pc(void)
{ {