Merge branch 'master' of https://github.com/86Box/86Box
This commit is contained in:
@@ -722,7 +722,7 @@ extern int machine_at_pb680_init(const machine_t *);
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extern int machine_at_pb810_init(const machine_t *);
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extern int machine_at_pb810_init(const machine_t *);
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extern int machine_at_mb520n_init(const machine_t *);
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extern int machine_at_mb520n_init(const machine_t *);
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extern int machine_at_i430vx_init(const machine_t *);
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extern int machine_at_i430vx_init(const machine_t *);
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extern int machine_at_hitman_init(const machine_t *);
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extern int machine_at_gw2kte_init(const machine_t *);
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extern int machine_at_ma23c_init(const machine_t *);
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extern int machine_at_ma23c_init(const machine_t *);
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extern int machine_at_nupro592_init(const machine_t *);
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extern int machine_at_nupro592_init(const machine_t *);
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@@ -825,15 +825,15 @@ machine_at_i430vx_init(const machine_t *model)
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}
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}
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int
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int
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machine_at_hitman_init(const machine_t *model)
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machine_at_gw2kte_init(const machine_t *model)
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{
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{
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int ret;
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int ret;
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ret = bios_load_linear_combined2("roms/machines/hitman/1008CY1T.BIO",
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ret = bios_load_linear_combined2("roms/machines/gw2kte/1008CY1T.BIO",
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"roms/machines/hitman/1008CY1T.BI1",
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"roms/machines/gw2kte/1008CY1T.BI1",
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"roms/machines/hitman/1008CY1T.BI2",
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"roms/machines/gw2kte/1008CY1T.BI2",
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"roms/machines/hitman/1008CY1T.BI3",
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"roms/machines/gw2kte/1008CY1T.BI3",
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"roms/machines/hitman/1008CY1T.RCV",
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"roms/machines/gw2kte/1008CY1T.RCV",
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0x3a000, 128);
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0x3a000, 128);
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if (bios_only || !ret)
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if (bios_only || !ret)
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@@ -11953,16 +11953,14 @@ const machine_t machines[] = {
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.snd_device = NULL,
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.snd_device = NULL,
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.net_device = NULL
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.net_device = NULL
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},
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},
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/* 430VX */
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/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
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/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
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MegaKey (revision '5') KBC firmware. */
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MegaKey (revision '5') KBC firmware. */
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{
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{
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.name = "[i430VX] Gateway 2000 Hitman",
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.name = "[i430VX] Gateway 2000 Hitman",
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.internal_name = "hitman",
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.internal_name = "gw2kte",
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.type = MACHINE_TYPE_SOCKET7,
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.type = MACHINE_TYPE_SOCKET7,
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.chipset = MACHINE_CHIPSET_INTEL_430VX,
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.chipset = MACHINE_CHIPSET_INTEL_430VX,
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.init = machine_at_hitman_init,
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.init = machine_at_gw2kte_init,
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.p1_handler = NULL,
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.p1_handler = NULL,
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.gpio_handler = NULL,
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.gpio_handler = NULL,
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.available_flag = MACHINE_AVAILABLE,
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.available_flag = MACHINE_AVAILABLE,
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@@ -11996,8 +11994,6 @@ const machine_t machines[] = {
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.snd_device = NULL,
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.snd_device = NULL,
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.net_device = NULL
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.net_device = NULL
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},
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},
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/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
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/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
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MultiKey/42 (version 1.38) KBC firmware. */
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MultiKey/42 (version 1.38) KBC firmware. */
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{
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{
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@@ -2481,36 +2481,58 @@ pcnet_readl(uint16_t addr, void *priv)
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static void
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static void
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pcnet_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
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pcnet_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
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{
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{
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if (!(addr & 0x10)) {
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pcnet_aprom_writeb((nic_t *) priv, addr, val);
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return;
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}
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pcnet_write((nic_t *) priv, addr, val, 1);
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pcnet_write((nic_t *) priv, addr, val, 1);
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}
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}
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static void
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static void
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pcnet_mmio_writew(uint32_t addr, uint16_t val, void *priv)
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pcnet_mmio_writew(uint32_t addr, uint16_t val, void *priv)
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{
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{
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if (!(addr & 0x10)) {
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pcnet_aprom_writeb((nic_t *) priv, addr, val);
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pcnet_aprom_writeb((nic_t *) priv, addr + 1, val >> 8);
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return;
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}
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pcnet_write((nic_t *) priv, addr, val, 2);
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pcnet_write((nic_t *) priv, addr, val, 2);
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}
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}
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static void
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static void
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pcnet_mmio_writel(uint32_t addr, uint32_t val, void *priv)
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pcnet_mmio_writel(uint32_t addr, uint32_t val, void *priv)
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{
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{
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if (!(addr & 0x10)) {
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pcnet_aprom_writeb((nic_t *) priv, addr, val);
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pcnet_aprom_writeb((nic_t *) priv, addr + 1, val >> 8);
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pcnet_aprom_writeb((nic_t *) priv, addr + 2, val >> 16);
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pcnet_aprom_writeb((nic_t *) priv, addr + 3, val >> 24);
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return;
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}
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pcnet_write((nic_t *) priv, addr, val, 4);
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pcnet_write((nic_t *) priv, addr, val, 4);
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}
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}
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static uint8_t
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static uint8_t
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pcnet_mmio_readb(uint32_t addr, void *priv)
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pcnet_mmio_readb(uint32_t addr, void *priv)
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{
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{
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if (!(addr & 0x10))
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return pcnet_aprom_readb((nic_t *) priv, addr);
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return (pcnet_read((nic_t *) priv, addr, 1));
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return (pcnet_read((nic_t *) priv, addr, 1));
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}
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}
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static uint16_t
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static uint16_t
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pcnet_mmio_readw(uint32_t addr, void *priv)
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pcnet_mmio_readw(uint32_t addr, void *priv)
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{
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{
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if (!(addr & 0x10))
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return pcnet_aprom_readb((nic_t *) priv, addr) | (pcnet_aprom_readb((nic_t *) priv, addr + 1) << 8);
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return (pcnet_read((nic_t *) priv, addr, 2));
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return (pcnet_read((nic_t *) priv, addr, 2));
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}
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}
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static uint32_t
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static uint32_t
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pcnet_mmio_readl(uint32_t addr, void *priv)
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pcnet_mmio_readl(uint32_t addr, void *priv)
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{
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{
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if (!(addr & 0x10))
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return pcnet_aprom_readb((nic_t *) priv, addr) | (pcnet_aprom_readb((nic_t *) priv, addr + 1) << 8) | (pcnet_aprom_readb((nic_t *) priv, addr + 2) << 16) | (pcnet_aprom_readb((nic_t *) priv, addr + 3) << 24);
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return (pcnet_read((nic_t *) priv, addr, 4));
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return (pcnet_read((nic_t *) priv, addr, 4));
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}
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}
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@@ -2607,7 +2629,7 @@ pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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/* Then let's set the PCI regs. */
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/* Then let's set the PCI regs. */
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pcnet_pci_bar[0].addr_regs[addr & 3] = val;
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pcnet_pci_bar[0].addr_regs[addr & 3] = val;
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/* Then let's calculate the new I/O base. */
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/* Then let's calculate the new I/O base. */
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pcnet_pci_bar[0].addr &= 0xff00;
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pcnet_pci_bar[0].addr &= 0xffe0;
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dev->PCIBase = pcnet_pci_bar[0].addr;
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dev->PCIBase = pcnet_pci_bar[0].addr;
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/* Log the new base. */
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/* Log the new base. */
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pcnet_log(4, "%s: New I/O base is %04X\n", dev->name, dev->PCIBase);
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pcnet_log(4, "%s: New I/O base is %04X\n", dev->name, dev->PCIBase);
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@@ -2685,7 +2707,7 @@ pcnet_pci_read(UNUSED(int func), int addr, void *priv)
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case 0x0E:
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case 0x0E:
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return 0; /*Header type */
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return 0; /*Header type */
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case 0x10:
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case 0x10:
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return 1; /*I/O space*/
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return pcnet_pci_bar[0].addr_regs[0] | 1; /*I/O space*/
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case 0x11:
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case 0x11:
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return pcnet_pci_bar[0].addr_regs[1];
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return pcnet_pci_bar[0].addr_regs[1];
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case 0x12:
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case 0x12:
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