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Implemented a PIIX register written to by the ZAPPA that is officially reserved on PIIX (but otherwise exists on PIIX3).

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OBattler
2021-09-17 02:54:19 +02:00
parent 89f1583a34
commit 626e8e58bb
1 changed files with 2 additions and 0 deletions
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2
src/chipset/intel_piix.c
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@@ -528,6 +528,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
case 0xab: case 0xab:
if (dev->type == 3) if (dev->type == 3)
fregs[addr] &= (val & 0x01); fregs[addr] &= (val & 0x01);
else if (dev->type < 3)
fregs[addr] = val;
break; break;
case 0xb0: case 0xb0:
if (dev->type == 4) if (dev->type == 4)