diff --git a/src/VIDEO/vid_s3.c b/src/VIDEO/vid_s3.c
index 5c1ea29cc..c44021f04 100644
--- a/src/VIDEO/vid_s3.c
+++ b/src/VIDEO/vid_s3.c
@@ -155,6 +155,7 @@ typedef struct s3_t
         uint64_t status_time;
 
 	uint8_t subsys_cntl, subsys_stat;
+	uint8_t status_9ae9;
 } s3_t;
 
 #define INT_VSY      (1 << 0)
@@ -444,70 +445,88 @@ static void s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
 
 static void s3_accel_out_fifo_w(s3_t *s3, uint16_t port, uint16_t val)
 {
-        if (s3->accel.cmd & 0x100)
-        {
-                if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80)
-                {
-                        if (s3->accel.cmd & 0x1000)
-                                val = (val >> 8) | (val << 8);
-                        if ((s3->accel.cmd & 0x600) == 0x000)
-                                s3_accel_start(8, 1, val | (val << 16), 0, s3);
-                        else
-                                s3_accel_start(16, 1, val | (val << 16), 0, s3);
-                }
-                else
-                {
-                        if ((s3->accel.cmd & 0x600) == 0x000)
-                                s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3);
-                        else
-                                s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
-                }
-        }
+	if (port & 0x8000)
+	{
+		s3_accel_out_fifo(s3, port,     val);
+		s3_accel_out_fifo(s3, port + 1, val >> 8);
+	}
+	else
+	{
+		if (s3->accel.cmd & 0x100)
+		{
+			if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80)
+			{
+				if (s3->accel.cmd & 0x1000)
+					val = (val >> 8) | (val << 8);
+				if ((s3->accel.cmd & 0x600) == 0x000)
+					s3_accel_start(8, 1, val | (val << 16), 0, s3);
+				else
+					s3_accel_start(16, 1, val | (val << 16), 0, s3);
+			}
+			else
+			{
+				if ((s3->accel.cmd & 0x600) == 0x000)
+					s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3);
+				else
+					s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
+			}
+		}
+	}
 }
 
 static void s3_accel_out_fifo_l(s3_t *s3, uint16_t port, uint32_t val)
 {
-        if (s3->accel.cmd & 0x100)
-        {
-                if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80)
-                {
-                        if (s3->accel.cmd & 0x400)
-                        {
-                                if (s3->accel.cmd & 0x1000)
-                                        val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24);
-                                s3_accel_start(32, 1, val, 0, s3);
-                        }
-                        else if ((s3->accel.cmd & 0x600) == 0x200)
-                        {
-                                if (s3->accel.cmd & 0x1000)
-                                        val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
-                                s3_accel_start(16, 1, val, 0, s3);
-                                s3_accel_start(16, 1, val >> 16, 0, s3);
-                        }
-                        else
-                        {
-                                if (s3->accel.cmd & 0x1000)
-                                        val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
-                                s3_accel_start(8, 1, val, 0, s3);
-                                s3_accel_start(8, 1, val >> 16, 0, s3);
-                        }
-                }
-                else
-                {
-                        if (s3->accel.cmd & 0x400)
-                                s3_accel_start(4, 1, 0xffffffff, val, s3);
-                        else if ((s3->accel.cmd & 0x600) == 0x200)
-                        {
-                                s3_accel_start(2, 1, 0xffffffff, val, s3);
-                                s3_accel_start(2, 1, 0xffffffff, val >> 16, s3);
-                        }
-                        else
-                        {
-                                s3_accel_start(1, 1, 0xffffffff, val, s3);
-                                s3_accel_start(1, 1, 0xffffffff, val >> 16, s3);
-                        }
-                }
-        }
+	if (port & 0x8000)
+	{
+		s3_accel_out_fifo(s3, port,     val);
+		s3_accel_out_fifo(s3, port + 1, val >> 8);
+		s3_accel_out_fifo(s3, port + 2, val >> 16);
+		s3_accel_out_fifo(s3, port + 3, val >> 24);
+	}
+	else
+	{
+		if (s3->accel.cmd & 0x100)
+		{
+			if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80)
+			{
+				if (s3->accel.cmd & 0x400)
+				{
+					if (s3->accel.cmd & 0x1000)
+						val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24);
+					s3_accel_start(32, 1, val, 0, s3);
+				}
+				else if ((s3->accel.cmd & 0x600) == 0x200)
+				{
+					if (s3->accel.cmd & 0x1000)
+						val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
+					s3_accel_start(16, 1, val, 0, s3);
+					s3_accel_start(16, 1, val >> 16, 0, s3);
+				}
+				else
+				{
+					if (s3->accel.cmd & 0x1000)
+						val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
+					s3_accel_start(8, 1, val, 0, s3);
+					s3_accel_start(8, 1, val >> 16, 0, s3);
+				}
+			}
+			else
+			{
+				if (s3->accel.cmd & 0x400)
+					s3_accel_start(4, 1, 0xffffffff, val, s3);
+				else if ((s3->accel.cmd & 0x600) == 0x200)
+				{
+					s3_accel_start(2, 1, 0xffffffff, val, s3);
+					s3_accel_start(2, 1, 0xffffffff, val >> 16, s3);
+				}
+				else
+				{
+					s3_accel_start(1, 1, 0xffffffff, val, s3);
+					s3_accel_start(1, 1, 0xffffffff, val >> 16, s3);
+				}
+			}
+		}
+	}
 }
 
 static void s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val)
@@ -1257,7 +1276,7 @@ uint8_t s3_accel_in(uint16_t port, void *p)
                 if (!FIFO_EMPTY)
                         temp |= 0x02; /*Hardware busy*/
                 else
-                        temp |= 0x04; /*FIFO empty*/
+                        temp |= s3->status_9ae9; /*FIFO empty*/
                 if (FIFO_FULL)
                         temp |= 0xf8; /*FIFO full*/
                 return temp;
@@ -1642,6 +1661,15 @@ void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
                         
                         s3->accel.dest = s3->accel.cy * s3->width;
                 }
+
+		s3->status_9ae9 = 4; /*To avoid the spam from OS/2's drivers*/
+
+		if ((s3->accel.cmd & 0x100) && !cpu_input)
+		{
+			s3->status_9ae9 = 2; /*To avoid the spam from OS/2's drivers*/
+			return; /*Wait for data from CPU*/
+		}
+
                 if ((s3->accel.cmd & 0x100) && !cpu_input) return; /*Wait for data from CPU*/
 
                 frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
diff --git a/src/net_ne2000.c b/src/net_ne2000.c
index f08c3353b..9df7ac7ff 100644
--- a/src/net_ne2000.c
+++ b/src/net_ne2000.c
@@ -1636,6 +1636,7 @@ nic_pci_write(int func, int addr, uint8_t val, void *priv)
 		nic_update_bios(dev);
 		return;
 
+#if 0
 	case 0x3C:			/* PCI_ILR */
 		if (val != 0xFF) {
 			nelog(1, "%s: IRQ now: %i\n", dev->name, val);
@@ -1643,6 +1644,7 @@ nic_pci_write(int func, int addr, uint8_t val, void *priv)
 		}
 		dev->pci_regs[addr] = dev->base_irq;
 		return;
+#endif
     }
 }
 
@@ -2219,7 +2221,6 @@ static device_config_t ne2000_config[] =
 
 static device_config_t rtl8029as_config[] =
 {
-#if 0
 	{
 		"irq", "IRQ", CONFIG_SELECTION, "", 10,
 		{
@@ -2243,7 +2244,6 @@ static device_config_t rtl8029as_config[] =
 			}
 		},
 	},
-#endif
 #if 1
 	/*
 	 * WTF.
diff --git a/src/scsi_buslogic.c b/src/scsi_buslogic.c
index a95a9a569..eaf475044 100644
--- a/src/scsi_buslogic.c
+++ b/src/scsi_buslogic.c
@@ -532,14 +532,16 @@ BuslogicLog(const char *format, ...)
     }
 #endif
 }
-#define pclog	BuslogicLog
+/* #define pclog	BuslogicLog */
 
 
 static void
 BuslogicInterrupt(Buslogic_t *bl, int set)
 {
+#if 0
 	if (bl->chip != CHIP_BUSLOGIC_PCI)
 	{
+#endif
 		if (set)
 		{
 			picint(1 << bl->Irq);
@@ -548,18 +550,20 @@ BuslogicInterrupt(Buslogic_t *bl, int set)
 		{
 			picintc(1 << bl->Irq);
 		}
+#if 0
 	}
 	else
 	{
 	        if (set)
 		{
-        	        pci_set_irq(bl->Card, PCI_INTA);
+        	        pci_set_irq(bl->Card, PCI_INTD);
 		}
 	        else
 		{
-        	        pci_clear_irq(bl->Card, PCI_INTA);
+        	        pci_clear_irq(bl->Card, PCI_INTD);
 		}
 	}
+#endif
 }
 
 
@@ -1254,7 +1258,14 @@ BuslogicWrite(uint16_t Port, uint8_t Val, void *p)
 
 				case 0x0B:
 					bl->DataBuf[0] = (1 << bl->DmaChannel);
-					bl->DataBuf[1] = (1<<(bl->Irq-9));
+					if ((bl->Irq >= 9) && (bl->Irq <= 15))
+					{
+						bl->DataBuf[1] = (1<<(bl->Irq-9));
+					}
+					else
+						bl->DataBuf[1] = 0;
+					{
+					}
 					bl->DataBuf[2] = 7;	/* HOST ID */
 					bl->DataReplyLeft = 3;
 					break;
@@ -2127,7 +2138,7 @@ BuslogicPCIRead(int func, int addr, void *p)
 	case 0x3C:
 		return bl->Irq;
 	case 0x3D:
-		return 1;
+		return 4;
     }
 
     return(0);
@@ -2138,16 +2149,17 @@ static void
 BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
 {
     Buslogic_t *bl = (Buslogic_t *)p;
+    uint8_t valxor;
 
     switch (addr) {
 	case 0x04:
-		io_removehandler(bl->PCIBase, 4,
+		valxor = (val & 0x27) ^ buslogic_pci_regs[addr];
+		if (valxor & PCI_COMMAND_IO) {
+			io_removehandler(bl->PCIBase, 4,
 				 BuslogicRead, BuslogicReadW, BuslogicReadL,
 				 BuslogicWrite, BuslogicWriteW, BuslogicWriteL,
 				 bl);
-		mem_mapping_disable(&bl->mmio_mapping);
-		if (val & PCI_COMMAND_IO) {
-			if (bl->PCIBase != 0) {
+			if ((bl->PCIBase != 0) && (val & PCI_COMMAND_IO)) {
 				io_sethandler(bl->PCIBase, 0x0020,
 					      BuslogicRead, BuslogicReadW,
 					      BuslogicReadL, BuslogicWrite,
@@ -2155,13 +2167,14 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
 					      bl);
 			}
 		}
-		if (val & PCI_COMMAND_MEM) {
-			if (bl->PCIBase != 0) {
+		if (valxor & PCI_COMMAND_MEM) {
+			mem_mapping_disable(&bl->mmio_mapping);
+			if ((bl->MMIOBase != 0) & (val & PCI_COMMAND_MEM)) {
 				mem_mapping_set_addr(&bl->mmio_mapping,
 						     bl->MMIOBase, 0x20);
 			}
 		}
-		buslogic_pci_regs[addr] = val;
+		buslogic_pci_regs[addr] = val & 0x27;
 		break;
 
 	case 0x10:
@@ -2215,6 +2228,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
 		}
 		return;
 
+#if 0
 	case 0x3C:
 		buslogic_pci_regs[addr] = val;
 		if (val != 0xFF) {
@@ -2222,6 +2236,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
 			bl->Irq = val;
 		}
 		return;
+#endif
     }
 }
 
@@ -2291,9 +2306,11 @@ BuslogicInit(int chip)
 
 	buslogic_pci_bar[0].addr_regs[0] = 1;
 	buslogic_pci_bar[1].addr_regs[0] = 0;
-       	buslogic_pci_regs[0x04] = 1;
+       	buslogic_pci_regs[0x04] = 3;
+#if 0
         buslogic_pci_regs[0x05] = 0;
         buslogic_pci_regs[0x07] = 2;
+#endif
 	buslogic_pci_bar[2].addr = 0;
 
 	mem_mapping_add(&bl->mmio_mapping, 0xfffd0000, 0x20,