Chips & Technologies 486 emulation
Some extremely basic 486 chipset. Used by very few motherboards.
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tiseno100
GitHub
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src/chipset/cs4031.c
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src/chipset/cs4031.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Chips & Technologies CS4031 chipset.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2020 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct
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{
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uint8_t index,
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regs[256];
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port_92_t * port_92;
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} cs4031_t;
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#ifdef ENABLE_CS4031_LOG
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int cs4031_do_log = ENABLE_CS4031_LOG;
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static void
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cs4031_log(const char *fmt, ...)
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{
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va_list ap;
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if (cs4031_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define cs4031_log(fmt, ...)
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#endif
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static void cs4031_shadow_recalc(cs4031_t *dev)
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{
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uint32_t romc0000, romc4000, romc8000, romcc000, romd0000, rome0000, romf0000;
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/* Register 18h */
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if(dev->regs[0x18] & 0x01)
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mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(0xa0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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if(dev->regs[0x18] & 0x02)
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mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state_both(0xb0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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/* Register 19h-1ah-1bh*/
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shadowbios = (dev->regs[0x19] & 0x40);
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shadowbios_write = (dev->regs[0x1a] & 0x40);
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/* ROMCS only functions if shadow write is disabled */
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romc0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x01)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romc4000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x02)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romc8000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x04)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romcc000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x08)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romd0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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rome0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x20)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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romf0000 = ((dev->regs[0x1b] & 0x80) && (dev->regs[0x1b] & 0x40)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state_both(0xc0000, 0x4000, ((dev->regs[0x19] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x01) ? MEM_WRITE_INTERNAL : romc0000));
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mem_set_mem_state_both(0xc4000, 0x4000, ((dev->regs[0x19] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x02) ? MEM_WRITE_INTERNAL : romc4000));
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mem_set_mem_state_both(0xc8000, 0x4000, ((dev->regs[0x19] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x04) ? MEM_WRITE_INTERNAL : romc8000));
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mem_set_mem_state_both(0xcc000, 0x4000, ((dev->regs[0x19] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x08) ? MEM_WRITE_INTERNAL : romcc000));
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mem_set_mem_state_both(0xd0000, 0x10000, ((dev->regs[0x19] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x10) ? MEM_WRITE_INTERNAL : romd0000));
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x19] & 0x20) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x20) ? MEM_WRITE_INTERNAL : rome0000));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x19] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & 0x40) ? MEM_WRITE_INTERNAL : romf0000));
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}
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static void
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cs4031_write(uint16_t addr, uint8_t val, void *priv)
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{
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cs4031_t *dev = (cs4031_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
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dev->regs[dev->index] = val;
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switch(dev->index){
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case 0x06:
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cpu_update_waitstates();
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break;
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case 0x18:
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case 0x19:
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case 0x1a:
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case 0x1b:
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cs4031_shadow_recalc(dev);
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break;
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case 0x1c:
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if(dev->regs[0x1c] & 0x20)
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port_92_add(dev->port_92);
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else
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port_92_remove(dev->port_92);
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break;
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}
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break;
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}
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}
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static uint8_t
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cs4031_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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cs4031_t *dev = (cs4031_t *) priv;
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switch (addr) {
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case 0x23:
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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static void
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cs4031_close(void *priv)
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{
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cs4031_t *dev = (cs4031_t *) priv;
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free(dev);
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}
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static void *
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cs4031_init(const device_t *info)
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{
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cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
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memset(dev, 0, sizeof(cs4031_t));
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dev->port_92 = device_add(&port_92_device);
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io_sethandler(0x022, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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io_sethandler(0x023, 0x0001, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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dev->regs[0x05] = 0x05;
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dev->regs[0x18] = 0x00;
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dev->regs[0x19] = 0x00;
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dev->regs[0x1a] = 0x00;
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dev->regs[0x1b] = 0x60;
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cs4031_shadow_recalc(dev);
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return dev;
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}
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const device_t cs4031_device = {
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"Chips & Technogies CS4031",
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0,
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0,
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cs4031_init, cs4031_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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